1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright 2018 Mellanox Technologies, Ltd */
7 #include <rte_malloc.h>
8 #include <rte_eal_paging.h>
11 #include "mlx5_devx_cmds.h"
12 #include "mlx5_common_utils.h"
13 #include "mlx5_malloc.h"
17 * Perform read access to the registers. Reads data from register
18 * and writes ones to the specified buffer.
21 * Context returned from mlx5 open_device() glue function.
23 * Register identifier according to the PRM.
25 * Register access auxiliary parameter according to the PRM.
27 * Pointer to the buffer to store read data.
29 * Buffer size in double words.
32 * 0 on success, a negative value otherwise.
35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
36 uint32_t *data, uint32_t dw_cnt)
38 uint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0};
39 uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
40 MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
43 MLX5_ASSERT(data && dw_cnt);
44 MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
45 if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
46 DRV_LOG(ERR, "Not enough buffer for register read data");
49 MLX5_SET(access_register_in, in, opcode,
50 MLX5_CMD_OP_ACCESS_REGISTER_USER);
51 MLX5_SET(access_register_in, in, op_mod,
52 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
53 MLX5_SET(access_register_in, in, register_id, reg_id);
54 MLX5_SET(access_register_in, in, argument, arg);
55 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
56 MLX5_ST_SZ_DW(access_register_out) *
57 sizeof(uint32_t) + dw_cnt);
60 status = MLX5_GET(access_register_out, out, status);
62 int syndrome = MLX5_GET(access_register_out, out, syndrome);
64 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, "
65 "status %x, syndrome = %x",
66 reg_id, status, syndrome);
69 memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
70 dw_cnt * sizeof(uint32_t));
73 rc = (rc > 0) ? -rc : rc;
78 * Allocate flow counters via devx interface.
81 * Context returned from mlx5 open_device() glue function.
83 * Pointer to counters properties structure to be filled by the routine.
85 * Bulk counter numbers in 128 counters units.
88 * Pointer to counter object on success, a negative value otherwise and
91 struct mlx5_devx_obj *
92 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
94 struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
96 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
97 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
103 MLX5_SET(alloc_flow_counter_in, in, opcode,
104 MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
105 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
106 dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
107 sizeof(in), out, sizeof(out));
109 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
114 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
119 * Query flow counters values.
122 * devx object that was obtained from mlx5_devx_cmd_fc_alloc.
124 * Whether hardware should clear the counters after the query or not.
125 * @param[in] n_counters
126 * 0 in case of 1 counter to read, otherwise the counter number to read.
128 * The number of packets that matched the flow.
130 * The number of bytes that matched the flow.
132 * The mkey key for batch query.
134 * The address in the mkey range for batch query.
136 * The completion object for asynchronous batch query.
138 * The ID to be returned in the asynchronous batch query response.
141 * 0 on success, a negative value otherwise.
144 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
145 int clear, uint32_t n_counters,
146 uint64_t *pkts, uint64_t *bytes,
147 uint32_t mkey, void *addr,
151 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
152 MLX5_ST_SZ_BYTES(traffic_counter);
153 uint32_t out[out_len];
154 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
158 MLX5_SET(query_flow_counter_in, in, opcode,
159 MLX5_CMD_OP_QUERY_FLOW_COUNTER);
160 MLX5_SET(query_flow_counter_in, in, op_mod, 0);
161 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
162 MLX5_SET(query_flow_counter_in, in, clear, !!clear);
165 MLX5_SET(query_flow_counter_in, in, num_of_counters,
167 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
168 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
169 MLX5_SET64(query_flow_counter_in, in, address,
170 (uint64_t)(uintptr_t)addr);
173 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
176 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
180 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
185 stats = MLX5_ADDR_OF(query_flow_counter_out,
186 out, flow_statistics);
187 *pkts = MLX5_GET64(traffic_counter, stats, packets);
188 *bytes = MLX5_GET64(traffic_counter, stats, octets);
197 * Context returned from mlx5 open_device() glue function.
199 * Attributes of the requested mkey.
202 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno
205 struct mlx5_devx_obj *
206 mlx5_devx_cmd_mkey_create(void *ctx,
207 struct mlx5_devx_mkey_attr *attr)
209 struct mlx5_klm *klm_array = attr->klm_array;
210 int klm_num = attr->klm_num;
211 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
212 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
213 uint32_t in[in_size_dw];
214 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
216 struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
219 uint32_t translation_size;
225 memset(in, 0, in_size_dw * 4);
226 pgsize = rte_mem_page_size();
227 if (pgsize == (size_t)-1) {
229 DRV_LOG(ERR, "Failed to get page size");
233 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
234 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
237 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
239 translation_size = RTE_ALIGN(klm_num, 4);
240 for (i = 0; i < klm_num; i++) {
241 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
242 MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
243 MLX5_SET64(klm, klm, address, klm_array[i].address);
244 klm += MLX5_ST_SZ_BYTES(klm);
246 for (; i < (int)translation_size; i++) {
247 MLX5_SET(klm, klm, mkey, 0x0);
248 MLX5_SET64(klm, klm, address, 0x0);
249 klm += MLX5_ST_SZ_BYTES(klm);
251 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
252 MLX5_MKC_ACCESS_MODE_KLM_FBS :
253 MLX5_MKC_ACCESS_MODE_KLM);
254 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
256 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
257 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
258 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
260 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
262 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
263 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
264 MLX5_SET(mkc, mkc, lw, 0x1);
265 MLX5_SET(mkc, mkc, lr, 0x1);
266 MLX5_SET(mkc, mkc, qpn, 0xffffff);
267 MLX5_SET(mkc, mkc, pd, attr->pd);
268 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
269 MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
270 if (attr->relaxed_ordering == 1) {
271 MLX5_SET(mkc, mkc, relaxed_ordering_write, 0x1);
272 MLX5_SET(mkc, mkc, relaxed_ordering_read, 0x1);
274 MLX5_SET64(mkc, mkc, start_addr, attr->addr);
275 MLX5_SET64(mkc, mkc, len, attr->size);
276 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
279 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d\n",
280 klm_num ? "an in" : "a ", errno);
285 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
286 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
291 * Get status of devx command response.
292 * Mainly used for asynchronous commands.
295 * The out response buffer.
298 * 0 on success, non-zero value otherwise.
301 mlx5_devx_get_out_command_status(void *out)
307 status = MLX5_GET(query_flow_counter_out, out, status);
309 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
311 DRV_LOG(ERR, "Bad devX status %x, syndrome = %x", status,
318 * Destroy any object allocated by a Devx API.
321 * Pointer to a general object.
324 * 0 on success, a negative value otherwise.
327 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
333 ret = mlx5_glue->devx_obj_destroy(obj->obj);
339 * Query NIC vport context.
340 * Fills minimal inline attribute.
343 * ibv contexts returned from mlx5dv_open_device.
347 * Attributes device values.
350 * 0 on success, a negative value otherwise.
353 mlx5_devx_cmd_query_nic_vport_context(void *ctx,
355 struct mlx5_hca_attr *attr)
357 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
358 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
360 int status, syndrome, rc;
362 /* Query NIC vport context to determine inline mode. */
363 MLX5_SET(query_nic_vport_context_in, in, opcode,
364 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
365 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
367 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
368 rc = mlx5_glue->devx_general_cmd(ctx,
373 status = MLX5_GET(query_nic_vport_context_out, out, status);
374 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
376 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
377 "status %x, syndrome = %x",
381 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
383 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
384 min_wqe_inline_mode);
387 rc = (rc > 0) ? -rc : rc;
392 * Query NIC vDPA attributes.
395 * Context returned from mlx5 open_device() glue function.
396 * @param[out] vdpa_attr
397 * vDPA Attributes structure to fill.
400 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
401 struct mlx5_hca_vdpa_attr *vdpa_attr)
403 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
404 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
405 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
406 int status, syndrome, rc;
408 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
409 MLX5_SET(query_hca_cap_in, in, op_mod,
410 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
411 MLX5_HCA_CAP_OPMOD_GET_CUR);
412 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
413 status = MLX5_GET(query_hca_cap_out, out, status);
414 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
416 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities,"
417 " status %x, syndrome = %x", status, syndrome);
418 vdpa_attr->valid = 0;
420 vdpa_attr->valid = 1;
421 vdpa_attr->desc_tunnel_offload_type =
422 MLX5_GET(virtio_emulation_cap, hcattr,
423 desc_tunnel_offload_type);
424 vdpa_attr->eth_frame_offload_type =
425 MLX5_GET(virtio_emulation_cap, hcattr,
426 eth_frame_offload_type);
427 vdpa_attr->virtio_version_1_0 =
428 MLX5_GET(virtio_emulation_cap, hcattr,
430 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
432 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
434 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
436 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
438 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
440 vdpa_attr->virtio_queue_type =
441 MLX5_GET(virtio_emulation_cap, hcattr,
443 vdpa_attr->log_doorbell_stride =
444 MLX5_GET(virtio_emulation_cap, hcattr,
445 log_doorbell_stride);
446 vdpa_attr->log_doorbell_bar_size =
447 MLX5_GET(virtio_emulation_cap, hcattr,
448 log_doorbell_bar_size);
449 vdpa_attr->doorbell_bar_offset =
450 MLX5_GET64(virtio_emulation_cap, hcattr,
451 doorbell_bar_offset);
452 vdpa_attr->max_num_virtio_queues =
453 MLX5_GET(virtio_emulation_cap, hcattr,
454 max_num_virtio_queues);
455 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
456 umem_1_buffer_param_a);
457 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
458 umem_1_buffer_param_b);
459 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
460 umem_2_buffer_param_a);
461 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
462 umem_2_buffer_param_b);
463 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
464 umem_3_buffer_param_a);
465 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
466 umem_3_buffer_param_b);
471 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
472 uint32_t ids[], uint32_t num)
474 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
475 uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
476 void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
477 void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
478 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
483 if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
485 DRV_LOG(ERR, "Too many sample IDs to be fetched.");
488 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
489 MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
490 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
491 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
492 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
493 ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
497 DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
501 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
502 void *s_off = (void *)((char *)sample + i *
503 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
506 en = MLX5_GET(parse_graph_flow_match_sample, s_off,
507 flow_match_sample_en);
510 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
511 flow_match_sample_field_id);
515 DRV_LOG(ERR, "Number of sample IDs are not as expected.");
522 struct mlx5_devx_obj *
523 mlx5_devx_cmd_create_flex_parser(void *ctx,
524 struct mlx5_devx_graph_node_attr *data)
526 uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
527 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
528 void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
529 void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
530 void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
531 void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
532 void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
533 struct mlx5_devx_obj *parse_flex_obj = NULL;
536 parse_flex_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0,
538 if (!parse_flex_obj) {
539 DRV_LOG(ERR, "Failed to allocate flex parser data");
544 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
545 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
546 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
547 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
548 MLX5_SET(parse_graph_flex, flex, header_length_mode,
549 data->header_length_mode);
550 MLX5_SET(parse_graph_flex, flex, header_length_base_value,
551 data->header_length_base_value);
552 MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
553 data->header_length_field_offset);
554 MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
555 data->header_length_field_shift);
556 MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
557 data->header_length_field_mask);
558 for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
559 struct mlx5_devx_match_sample_attr *s = &data->sample[i];
560 void *s_off = (void *)((char *)sample + i *
561 MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
563 if (!s->flow_match_sample_en)
565 MLX5_SET(parse_graph_flow_match_sample, s_off,
566 flow_match_sample_en, !!s->flow_match_sample_en);
567 MLX5_SET(parse_graph_flow_match_sample, s_off,
568 flow_match_sample_field_offset,
569 s->flow_match_sample_field_offset);
570 MLX5_SET(parse_graph_flow_match_sample, s_off,
571 flow_match_sample_offset_mode,
572 s->flow_match_sample_offset_mode);
573 MLX5_SET(parse_graph_flow_match_sample, s_off,
574 flow_match_sample_field_offset_mask,
575 s->flow_match_sample_field_offset_mask);
576 MLX5_SET(parse_graph_flow_match_sample, s_off,
577 flow_match_sample_field_offset_shift,
578 s->flow_match_sample_field_offset_shift);
579 MLX5_SET(parse_graph_flow_match_sample, s_off,
580 flow_match_sample_field_base_offset,
581 s->flow_match_sample_field_base_offset);
582 MLX5_SET(parse_graph_flow_match_sample, s_off,
583 flow_match_sample_tunnel_mode,
584 s->flow_match_sample_tunnel_mode);
586 for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
587 struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
588 struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
589 void *in_off = (void *)((char *)in_arc + i *
590 MLX5_ST_SZ_BYTES(parse_graph_arc));
591 void *out_off = (void *)((char *)out_arc + i *
592 MLX5_ST_SZ_BYTES(parse_graph_arc));
594 if (ia->arc_parse_graph_node != 0) {
595 MLX5_SET(parse_graph_arc, in_off,
596 compare_condition_value,
597 ia->compare_condition_value);
598 MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
599 ia->start_inner_tunnel);
600 MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
601 ia->arc_parse_graph_node);
602 MLX5_SET(parse_graph_arc, in_off,
603 parse_graph_node_handle,
604 ia->parse_graph_node_handle);
606 if (oa->arc_parse_graph_node != 0) {
607 MLX5_SET(parse_graph_arc, out_off,
608 compare_condition_value,
609 oa->compare_condition_value);
610 MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
611 oa->start_inner_tunnel);
612 MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
613 oa->arc_parse_graph_node);
614 MLX5_SET(parse_graph_arc, out_off,
615 parse_graph_node_handle,
616 oa->parse_graph_node_handle);
619 parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
621 if (!parse_flex_obj->obj) {
623 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object "
625 mlx5_free(parse_flex_obj);
628 parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
629 return parse_flex_obj;
633 * Query HCA attributes.
634 * Using those attributes we can check on run time if the device
635 * is having the required capabilities.
638 * Context returned from mlx5 open_device() glue function.
640 * Attributes device values.
643 * 0 on success, a negative value otherwise.
646 mlx5_devx_cmd_query_hca_attr(void *ctx,
647 struct mlx5_hca_attr *attr)
649 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
650 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
652 int status, syndrome, rc, i;
654 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
655 MLX5_SET(query_hca_cap_in, in, op_mod,
656 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
657 MLX5_HCA_CAP_OPMOD_GET_CUR);
659 rc = mlx5_glue->devx_general_cmd(ctx,
660 in, sizeof(in), out, sizeof(out));
663 status = MLX5_GET(query_hca_cap_out, out, status);
664 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
666 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
667 "status %x, syndrome = %x",
671 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
672 attr->flow_counter_bulk_alloc_bitmap =
673 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
674 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
676 attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
678 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
679 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
680 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
681 log_max_hairpin_queues);
682 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
683 log_max_hairpin_wq_data_sz);
684 attr->log_max_hairpin_num_packets = MLX5_GET
685 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
686 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
687 attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
688 relaxed_ordering_write);
689 attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
690 relaxed_ordering_read);
691 attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
692 access_register_user);
693 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
695 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
696 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
697 flex_parser_protocols);
698 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
699 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
701 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
702 attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
704 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
705 attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr,
707 MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
708 attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
709 wqe_index_ignore_cap);
710 attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
711 attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
712 attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
713 log_max_static_sq_wq);
714 attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
715 device_frequency_khz);
716 attr->scatter_fcs_w_decap_disable =
717 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
718 attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp);
719 attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
720 regexp_num_of_engines);
722 MLX5_SET(query_hca_cap_in, in, op_mod,
723 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
724 MLX5_HCA_CAP_OPMOD_GET_CUR);
725 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
730 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
731 " status %x, syndrome = %x",
735 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
736 attr->qos.srtcm_sup =
737 MLX5_GET(qos_cap, hcattr, flow_meter_srtcm);
738 attr->qos.log_max_flow_meter =
739 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
740 attr->qos.flow_meter_reg_c_ids =
741 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
742 attr->qos.flow_meter_reg_share =
743 MLX5_GET(qos_cap, hcattr, flow_meter_reg_share);
744 attr->qos.packet_pacing =
745 MLX5_GET(qos_cap, hcattr, packet_pacing);
746 attr->qos.wqe_rate_pp =
747 MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
749 if (attr->vdpa.valid)
750 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
751 if (!attr->eth_net_offloads)
754 /* Query Flow Sampler Capability From FLow Table Properties Layout. */
755 memset(in, 0, sizeof(in));
756 memset(out, 0, sizeof(out));
757 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
758 MLX5_SET(query_hca_cap_in, in, op_mod,
759 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
760 MLX5_HCA_CAP_OPMOD_GET_CUR);
762 rc = mlx5_glue->devx_general_cmd(ctx,
767 status = MLX5_GET(query_hca_cap_out, out, status);
768 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
770 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
771 "status %x, syndrome = %x",
773 attr->log_max_ft_sampler_num = 0;
776 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
777 attr->log_max_ft_sampler_num =
778 MLX5_GET(flow_table_nic_cap,
779 hcattr, flow_table_properties.log_max_ft_sampler_num);
781 /* Query HCA offloads for Ethernet protocol. */
782 memset(in, 0, sizeof(in));
783 memset(out, 0, sizeof(out));
784 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
785 MLX5_SET(query_hca_cap_in, in, op_mod,
786 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
787 MLX5_HCA_CAP_OPMOD_GET_CUR);
789 rc = mlx5_glue->devx_general_cmd(ctx,
793 attr->eth_net_offloads = 0;
796 status = MLX5_GET(query_hca_cap_out, out, status);
797 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
799 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
800 "status %x, syndrome = %x",
802 attr->eth_net_offloads = 0;
805 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
806 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
807 hcattr, wqe_vlan_insert);
808 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
810 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
811 hcattr, tunnel_lro_gre);
812 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
813 hcattr, tunnel_lro_vxlan);
814 attr->lro_max_msg_sz_mode = MLX5_GET
815 (per_protocol_networking_offload_caps,
816 hcattr, lro_max_msg_sz_mode);
817 for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
818 attr->lro_timer_supported_periods[i] =
819 MLX5_GET(per_protocol_networking_offload_caps, hcattr,
820 lro_timer_supported_periods[i]);
822 attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
823 hcattr, lro_min_mss_size);
824 attr->tunnel_stateless_geneve_rx =
825 MLX5_GET(per_protocol_networking_offload_caps,
826 hcattr, tunnel_stateless_geneve_rx);
827 attr->geneve_max_opt_len =
828 MLX5_GET(per_protocol_networking_offload_caps,
829 hcattr, max_geneve_opt_len);
830 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
831 hcattr, wqe_inline_mode);
832 attr->tunnel_stateless_gtp = MLX5_GET
833 (per_protocol_networking_offload_caps,
834 hcattr, tunnel_stateless_gtp);
835 if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
837 if (attr->eth_virt) {
838 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
846 rc = (rc > 0) ? -rc : rc;
851 * Query TIS transport domain from QP verbs object using DevX API.
854 * Pointer to verbs QP returned by ibv_create_qp .
856 * TIS number of TIS to query.
858 * Pointer to TIS transport domain variable, to be set by the routine.
861 * 0 on success, a negative value otherwise.
864 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
867 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
868 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
869 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
873 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
874 MLX5_SET(query_tis_in, in, tisn, tis_num);
875 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
877 DRV_LOG(ERR, "Failed to query QP using DevX");
880 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
881 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
892 * Fill WQ data for DevX API command.
893 * Utility function for use when creating DevX objects containing a WQ.
896 * Pointer to WQ context to fill with data.
897 * @param [in] wq_attr
898 * Pointer to WQ attributes structure to fill in WQ context.
901 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
903 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
904 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
905 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
906 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
907 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
908 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
909 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
910 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
911 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
912 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
913 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
914 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
915 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
916 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
917 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, wq_attr->log_wq_pg_sz);
918 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
919 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
920 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
921 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
922 wq_attr->log_hairpin_num_packets);
923 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
924 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
925 wq_attr->single_wqe_log_num_of_strides);
926 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
927 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
928 wq_attr->single_stride_log_num_of_bytes);
929 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
930 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
931 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
935 * Create RQ using DevX API.
938 * Context returned from mlx5 open_device() glue function.
939 * @param [in] rq_attr
940 * Pointer to create RQ attributes structure.
942 * CPU socket ID for allocations.
945 * The DevX object created, NULL otherwise and rte_errno is set.
947 struct mlx5_devx_obj *
948 mlx5_devx_cmd_create_rq(void *ctx,
949 struct mlx5_devx_create_rq_attr *rq_attr,
952 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
953 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
954 void *rq_ctx, *wq_ctx;
955 struct mlx5_devx_wq_attr *wq_attr;
956 struct mlx5_devx_obj *rq = NULL;
958 rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
960 DRV_LOG(ERR, "Failed to allocate RQ data");
964 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
965 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
966 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
967 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
968 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
969 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
970 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
971 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
972 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
973 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
974 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
975 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
976 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
977 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
978 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
979 wq_attr = &rq_attr->wq_attr;
980 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
981 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
984 DRV_LOG(ERR, "Failed to create RQ using DevX");
989 rq->id = MLX5_GET(create_rq_out, out, rqn);
994 * Modify RQ using DevX API.
997 * Pointer to RQ object structure.
998 * @param [in] rq_attr
999 * Pointer to modify RQ attributes structure.
1002 * 0 on success, a negative errno value otherwise and rte_errno is set.
1005 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1006 struct mlx5_devx_modify_rq_attr *rq_attr)
1008 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1009 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1010 void *rq_ctx, *wq_ctx;
1013 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1014 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1015 MLX5_SET(modify_rq_in, in, rqn, rq->id);
1016 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1017 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1018 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1019 if (rq_attr->modify_bitmask &
1020 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1021 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1022 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1023 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1024 if (rq_attr->modify_bitmask &
1025 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1026 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1027 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1028 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1029 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1030 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1031 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1033 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1036 DRV_LOG(ERR, "Failed to modify RQ using DevX");
1044 * Create TIR using DevX API.
1047 * Context returned from mlx5 open_device() glue function.
1048 * @param [in] tir_attr
1049 * Pointer to TIR attributes structure.
1052 * The DevX object created, NULL otherwise and rte_errno is set.
1054 struct mlx5_devx_obj *
1055 mlx5_devx_cmd_create_tir(void *ctx,
1056 struct mlx5_devx_tir_attr *tir_attr)
1058 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1059 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1060 void *tir_ctx, *outer, *inner, *rss_key;
1061 struct mlx5_devx_obj *tir = NULL;
1063 tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1065 DRV_LOG(ERR, "Failed to allocate TIR data");
1069 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1070 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1071 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1072 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1073 tir_attr->lro_timeout_period_usecs);
1074 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1075 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1076 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1077 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1078 MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1079 tir_attr->tunneled_offload_en);
1080 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1081 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1082 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1083 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1084 rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1085 memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1086 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1087 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1088 tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1089 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1090 tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1091 MLX5_SET(rx_hash_field_select, outer, selected_fields,
1092 tir_attr->rx_hash_field_selector_outer.selected_fields);
1093 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1094 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1095 tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1096 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1097 tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1098 MLX5_SET(rx_hash_field_select, inner, selected_fields,
1099 tir_attr->rx_hash_field_selector_inner.selected_fields);
1100 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1103 DRV_LOG(ERR, "Failed to create TIR using DevX");
1108 tir->id = MLX5_GET(create_tir_out, out, tirn);
1113 * Create RQT using DevX API.
1116 * Context returned from mlx5 open_device() glue function.
1117 * @param [in] rqt_attr
1118 * Pointer to RQT attributes structure.
1121 * The DevX object created, NULL otherwise and rte_errno is set.
1123 struct mlx5_devx_obj *
1124 mlx5_devx_cmd_create_rqt(void *ctx,
1125 struct mlx5_devx_rqt_attr *rqt_attr)
1127 uint32_t *in = NULL;
1128 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1129 rqt_attr->rqt_actual_size * sizeof(uint32_t);
1130 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1132 struct mlx5_devx_obj *rqt = NULL;
1135 in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1137 DRV_LOG(ERR, "Failed to allocate RQT IN data");
1141 rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1143 DRV_LOG(ERR, "Failed to allocate RQT data");
1148 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1149 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1150 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1151 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1152 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1153 for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1154 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1155 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1158 DRV_LOG(ERR, "Failed to create RQT using DevX");
1163 rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1168 * Modify RQT using DevX API.
1171 * Pointer to RQT DevX object structure.
1172 * @param [in] rqt_attr
1173 * Pointer to RQT attributes structure.
1176 * 0 on success, a negative errno value otherwise and rte_errno is set.
1179 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1180 struct mlx5_devx_rqt_attr *rqt_attr)
1182 uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1183 rqt_attr->rqt_actual_size * sizeof(uint32_t);
1184 uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1185 uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1191 DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1195 MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
1196 MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
1197 MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
1198 rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
1199 MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1200 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1201 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1202 for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1203 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1204 ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
1207 DRV_LOG(ERR, "Failed to modify RQT using DevX.");
1215 * Create SQ using DevX API.
1218 * Context returned from mlx5 open_device() glue function.
1219 * @param [in] sq_attr
1220 * Pointer to SQ attributes structure.
1221 * @param [in] socket
1222 * CPU socket ID for allocations.
1225 * The DevX object created, NULL otherwise and rte_errno is set.
1227 struct mlx5_devx_obj *
1228 mlx5_devx_cmd_create_sq(void *ctx,
1229 struct mlx5_devx_create_sq_attr *sq_attr)
1231 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
1232 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
1235 struct mlx5_devx_wq_attr *wq_attr;
1236 struct mlx5_devx_obj *sq = NULL;
1238 sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
1240 DRV_LOG(ERR, "Failed to allocate SQ data");
1244 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
1245 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
1246 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
1247 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
1248 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
1249 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
1250 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
1251 sq_attr->flush_in_error_en);
1252 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
1253 sq_attr->min_wqe_inline_mode);
1254 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1255 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
1256 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
1257 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
1258 MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
1259 MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
1260 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
1261 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
1262 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
1263 sq_attr->packet_pacing_rate_limit_index);
1264 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
1265 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
1266 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
1267 wq_attr = &sq_attr->wq_attr;
1268 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1269 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1272 DRV_LOG(ERR, "Failed to create SQ using DevX");
1277 sq->id = MLX5_GET(create_sq_out, out, sqn);
1282 * Modify SQ using DevX API.
1285 * Pointer to SQ object structure.
1286 * @param [in] sq_attr
1287 * Pointer to SQ attributes structure.
1290 * 0 on success, a negative errno value otherwise and rte_errno is set.
1293 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
1294 struct mlx5_devx_modify_sq_attr *sq_attr)
1296 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
1297 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
1301 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
1302 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
1303 MLX5_SET(modify_sq_in, in, sqn, sq->id);
1304 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1305 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1306 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
1307 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
1308 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
1311 DRV_LOG(ERR, "Failed to modify SQ using DevX");
1319 * Create TIS using DevX API.
1322 * Context returned from mlx5 open_device() glue function.
1323 * @param [in] tis_attr
1324 * Pointer to TIS attributes structure.
1327 * The DevX object created, NULL otherwise and rte_errno is set.
1329 struct mlx5_devx_obj *
1330 mlx5_devx_cmd_create_tis(void *ctx,
1331 struct mlx5_devx_tis_attr *tis_attr)
1333 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1334 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
1335 struct mlx5_devx_obj *tis = NULL;
1338 tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
1340 DRV_LOG(ERR, "Failed to allocate TIS object");
1344 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
1345 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
1346 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1347 tis_attr->strict_lag_tx_port_affinity);
1348 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1349 tis_attr->strict_lag_tx_port_affinity);
1350 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
1351 MLX5_SET(tisc, tis_ctx, transport_domain,
1352 tis_attr->transport_domain);
1353 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1356 DRV_LOG(ERR, "Failed to create TIS using DevX");
1361 tis->id = MLX5_GET(create_tis_out, out, tisn);
1366 * Create transport domain using DevX API.
1369 * Context returned from mlx5 open_device() glue function.
1371 * The DevX object created, NULL otherwise and rte_errno is set.
1373 struct mlx5_devx_obj *
1374 mlx5_devx_cmd_create_td(void *ctx)
1376 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1377 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1378 struct mlx5_devx_obj *td = NULL;
1380 td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
1382 DRV_LOG(ERR, "Failed to allocate TD object");
1386 MLX5_SET(alloc_transport_domain_in, in, opcode,
1387 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1388 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1391 DRV_LOG(ERR, "Failed to create TIS using DevX");
1396 td->id = MLX5_GET(alloc_transport_domain_out, out,
1402 * Dump all flows to file.
1404 * @param[in] fdb_domain
1406 * @param[in] rx_domain
1408 * @param[in] tx_domain
1411 * Pointer to file stream.
1414 * 0 on success, a nagative value otherwise.
1417 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1418 void *rx_domain __rte_unused,
1419 void *tx_domain __rte_unused, FILE *file __rte_unused)
1423 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1425 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1429 MLX5_ASSERT(rx_domain);
1430 ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1433 MLX5_ASSERT(tx_domain);
1434 ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1442 * Create CQ using DevX API.
1445 * Context returned from mlx5 open_device() glue function.
1447 * Pointer to CQ attributes structure.
1450 * The DevX object created, NULL otherwise and rte_errno is set.
1452 struct mlx5_devx_obj *
1453 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
1455 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
1456 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
1457 struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1460 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1463 DRV_LOG(ERR, "Failed to allocate CQ object memory.");
1467 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
1468 if (attr->db_umem_valid) {
1469 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
1470 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
1471 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
1473 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
1475 MLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size);
1476 MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
1477 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
1478 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
1479 MLX5_SET(cqc, cqctx, log_page_size, attr->log_page_size -
1480 MLX5_ADAPTER_PAGE_SHIFT);
1481 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
1482 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
1483 MLX5_SET(cqc, cqctx, cqe_comp_en, attr->cqe_comp_en);
1484 MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
1485 MLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size);
1486 if (attr->q_umem_valid) {
1487 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
1488 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
1489 MLX5_SET64(create_cq_in, in, cq_umem_offset,
1490 attr->q_umem_offset);
1492 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1496 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno);
1500 cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
1505 * Create VIRTQ using DevX API.
1508 * Context returned from mlx5 open_device() glue function.
1510 * Pointer to VIRTQ attributes structure.
1513 * The DevX object created, NULL otherwise and rte_errno is set.
1515 struct mlx5_devx_obj *
1516 mlx5_devx_cmd_create_virtq(void *ctx,
1517 struct mlx5_devx_virtq_attr *attr)
1519 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1520 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1521 struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1524 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1525 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1526 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1529 DRV_LOG(ERR, "Failed to allocate virtq data.");
1533 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1534 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1535 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1536 MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1537 MLX5_SET16(virtio_net_q, virtq, hw_available_index,
1538 attr->hw_available_index);
1539 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
1540 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
1541 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
1542 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
1543 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
1544 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
1545 attr->virtio_version_1_0);
1546 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
1547 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
1548 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
1549 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
1550 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
1551 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1552 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
1553 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
1554 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
1555 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
1556 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
1557 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
1558 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
1559 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
1560 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
1561 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
1562 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
1563 MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
1564 MLX5_SET(virtio_q, virtctx, pd, attr->pd);
1565 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
1566 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1568 if (!virtq_obj->obj) {
1570 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX.");
1571 mlx5_free(virtq_obj);
1574 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1579 * Modify VIRTQ using DevX API.
1581 * @param[in] virtq_obj
1582 * Pointer to virtq object structure.
1584 * Pointer to modify virtq attributes structure.
1587 * 0 on success, a negative errno value otherwise and rte_errno is set.
1590 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
1591 struct mlx5_devx_virtq_attr *attr)
1593 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1594 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1595 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1596 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1597 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1600 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1601 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
1602 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1603 MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1604 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1605 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);
1606 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1607 switch (attr->type) {
1608 case MLX5_VIRTQ_MODIFY_TYPE_STATE:
1609 MLX5_SET16(virtio_net_q, virtq, state, attr->state);
1611 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:
1612 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
1613 attr->dirty_bitmap_mkey);
1614 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
1615 attr->dirty_bitmap_addr);
1616 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
1617 attr->dirty_bitmap_size);
1619 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:
1620 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
1621 attr->dirty_bitmap_dump_enable);
1627 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
1630 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1638 * Query VIRTQ using DevX API.
1640 * @param[in] virtq_obj
1641 * Pointer to virtq object structure.
1642 * @param [in/out] attr
1643 * Pointer to virtq attributes structure.
1646 * 0 on success, a negative errno value otherwise and rte_errno is set.
1649 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
1650 struct mlx5_devx_virtq_attr *attr)
1652 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
1653 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
1654 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
1655 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
1658 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1659 MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
1660 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1661 MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1662 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1663 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
1666 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1670 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
1671 hw_available_index);
1672 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
1677 * Create QP using DevX API.
1680 * Context returned from mlx5 open_device() glue function.
1682 * Pointer to QP attributes structure.
1685 * The DevX object created, NULL otherwise and rte_errno is set.
1687 struct mlx5_devx_obj *
1688 mlx5_devx_cmd_create_qp(void *ctx,
1689 struct mlx5_devx_qp_attr *attr)
1691 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
1692 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
1693 struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
1696 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1699 DRV_LOG(ERR, "Failed to allocate QP data.");
1703 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
1704 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
1705 MLX5_SET(qpc, qpc, pd, attr->pd);
1706 if (attr->uar_index) {
1707 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1708 MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
1709 MLX5_SET(qpc, qpc, log_page_size, attr->log_page_size -
1710 MLX5_ADAPTER_PAGE_SHIFT);
1711 if (attr->sq_size) {
1712 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));
1713 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
1714 MLX5_SET(qpc, qpc, log_sq_size,
1715 rte_log2_u32(attr->sq_size));
1717 MLX5_SET(qpc, qpc, no_sq, 1);
1719 if (attr->rq_size) {
1720 MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size));
1721 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
1722 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
1723 MLX5_LOG_RQ_STRIDE_SHIFT);
1724 MLX5_SET(qpc, qpc, log_rq_size,
1725 rte_log2_u32(attr->rq_size));
1726 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
1728 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1730 if (attr->dbr_umem_valid) {
1731 MLX5_SET(qpc, qpc, dbr_umem_valid,
1732 attr->dbr_umem_valid);
1733 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
1735 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
1736 MLX5_SET64(create_qp_in, in, wq_umem_offset,
1737 attr->wq_umem_offset);
1738 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
1739 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
1741 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
1742 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1743 MLX5_SET(qpc, qpc, no_sq, 1);
1745 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1749 DRV_LOG(ERR, "Failed to create QP Obj using DevX.");
1753 qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
1758 * Modify QP using DevX API.
1759 * Currently supports only force loop-back QP.
1762 * Pointer to QP object structure.
1763 * @param [in] qp_st_mod_op
1764 * The QP state modification operation.
1765 * @param [in] remote_qp_id
1766 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
1769 * 0 on success, a negative errno value otherwise and rte_errno is set.
1772 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
1773 uint32_t remote_qp_id)
1776 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
1777 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
1778 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
1781 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
1782 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
1783 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
1788 unsigned int outlen;
1790 memset(&in, 0, sizeof(in));
1791 memset(&out, 0, sizeof(out));
1792 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
1793 switch (qp_st_mod_op) {
1794 case MLX5_CMD_OP_RST2INIT_QP:
1795 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
1796 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
1797 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
1798 MLX5_SET(qpc, qpc, rre, 1);
1799 MLX5_SET(qpc, qpc, rwe, 1);
1800 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1801 inlen = sizeof(in.rst2init);
1802 outlen = sizeof(out.rst2init);
1804 case MLX5_CMD_OP_INIT2RTR_QP:
1805 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
1806 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
1807 MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
1808 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
1809 MLX5_SET(qpc, qpc, mtu, 1);
1810 MLX5_SET(qpc, qpc, log_msg_max, 30);
1811 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
1812 MLX5_SET(qpc, qpc, min_rnr_nak, 0);
1813 inlen = sizeof(in.init2rtr);
1814 outlen = sizeof(out.init2rtr);
1816 case MLX5_CMD_OP_RTR2RTS_QP:
1817 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
1818 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
1819 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14);
1820 MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
1821 MLX5_SET(qpc, qpc, retry_count, 7);
1822 MLX5_SET(qpc, qpc, rnr_retry, 7);
1823 inlen = sizeof(in.rtr2rts);
1824 outlen = sizeof(out.rtr2rts);
1827 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
1832 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
1834 DRV_LOG(ERR, "Failed to modify QP using DevX.");
1841 struct mlx5_devx_obj *
1842 mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
1844 uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
1845 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1846 struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
1847 sizeof(*couners_obj), 0,
1849 void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
1852 DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
1856 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1857 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1858 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1859 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
1860 couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1862 if (!couners_obj->obj) {
1864 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using"
1866 mlx5_free(couners_obj);
1869 couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1874 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
1875 struct mlx5_devx_virtio_q_couners_attr *attr)
1877 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
1878 uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
1879 void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
1880 void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
1884 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1885 MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
1886 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1887 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
1888 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
1889 ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
1892 DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
1896 attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
1898 attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
1900 attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
1902 attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
1904 attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
1906 attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,