1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright 2018 Mellanox Technologies, Ltd */
7 #include <rte_malloc.h>
10 #include "mlx5_devx_cmds.h"
11 #include "mlx5_common_utils.h"
15 * Allocate flow counters via devx interface.
18 * ibv contexts returned from mlx5dv_open_device.
20 * Pointer to counters properties structure to be filled by the routine.
22 * Bulk counter numbers in 128 counters units.
25 * Pointer to counter object on success, a negative value otherwise and
28 struct mlx5_devx_obj *
29 mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx, uint32_t bulk_n_128)
31 struct mlx5_devx_obj *dcs = rte_zmalloc("dcs", sizeof(*dcs), 0);
32 uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)] = {0};
33 uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
39 MLX5_SET(alloc_flow_counter_in, in, opcode,
40 MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
41 MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
42 dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
43 sizeof(in), out, sizeof(out));
45 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
50 dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
55 * Query flow counters values.
58 * devx object that was obtained from mlx5_devx_cmd_fc_alloc.
60 * Whether hardware should clear the counters after the query or not.
61 * @param[in] n_counters
62 * 0 in case of 1 counter to read, otherwise the counter number to read.
64 * The number of packets that matched the flow.
66 * The number of bytes that matched the flow.
68 * The mkey key for batch query.
70 * The address in the mkey range for batch query.
72 * The completion object for asynchronous batch query.
74 * The ID to be returned in the asynchronous batch query response.
77 * 0 on success, a negative value otherwise.
80 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
81 int clear, uint32_t n_counters,
82 uint64_t *pkts, uint64_t *bytes,
83 uint32_t mkey, void *addr,
84 struct mlx5dv_devx_cmd_comp *cmd_comp,
87 int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
88 MLX5_ST_SZ_BYTES(traffic_counter);
89 uint32_t out[out_len];
90 uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
94 MLX5_SET(query_flow_counter_in, in, opcode,
95 MLX5_CMD_OP_QUERY_FLOW_COUNTER);
96 MLX5_SET(query_flow_counter_in, in, op_mod, 0);
97 MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
98 MLX5_SET(query_flow_counter_in, in, clear, !!clear);
101 MLX5_SET(query_flow_counter_in, in, num_of_counters,
103 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
104 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
105 MLX5_SET64(query_flow_counter_in, in, address,
106 (uint64_t)(uintptr_t)addr);
109 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
112 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
116 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
121 stats = MLX5_ADDR_OF(query_flow_counter_out,
122 out, flow_statistics);
123 *pkts = MLX5_GET64(traffic_counter, stats, packets);
124 *bytes = MLX5_GET64(traffic_counter, stats, octets);
133 * ibv contexts returned from mlx5dv_open_device.
135 * Attributes of the requested mkey.
138 * Pointer to Devx mkey on success, a negative value otherwise and rte_errno
141 struct mlx5_devx_obj *
142 mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
143 struct mlx5_devx_mkey_attr *attr)
145 struct mlx5_klm *klm_array = attr->klm_array;
146 int klm_num = attr->klm_num;
147 int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
148 (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
149 uint32_t in[in_size_dw];
150 uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
152 struct mlx5_devx_obj *mkey = rte_zmalloc("mkey", sizeof(*mkey), 0);
154 uint32_t translation_size;
160 memset(in, 0, in_size_dw * 4);
161 pgsize = sysconf(_SC_PAGESIZE);
162 MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
163 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
166 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
168 translation_size = RTE_ALIGN(klm_num, 4);
169 for (i = 0; i < klm_num; i++) {
170 MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
171 MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
172 MLX5_SET64(klm, klm, address, klm_array[i].address);
173 klm += MLX5_ST_SZ_BYTES(klm);
175 for (; i < (int)translation_size; i++) {
176 MLX5_SET(klm, klm, mkey, 0x0);
177 MLX5_SET64(klm, klm, address, 0x0);
178 klm += MLX5_ST_SZ_BYTES(klm);
180 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
181 MLX5_MKC_ACCESS_MODE_KLM_FBS :
182 MLX5_MKC_ACCESS_MODE_KLM);
183 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
185 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
186 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
187 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
189 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
191 MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
192 MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
193 MLX5_SET(mkc, mkc, lw, 0x1);
194 MLX5_SET(mkc, mkc, lr, 0x1);
195 MLX5_SET(mkc, mkc, qpn, 0xffffff);
196 MLX5_SET(mkc, mkc, pd, attr->pd);
197 MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
198 MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
199 MLX5_SET64(mkc, mkc, start_addr, attr->addr);
200 MLX5_SET64(mkc, mkc, len, attr->size);
201 mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
204 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d\n",
205 klm_num ? "an in" : "a ", errno);
210 mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
211 mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
216 * Get status of devx command response.
217 * Mainly used for asynchronous commands.
220 * The out response buffer.
223 * 0 on success, non-zero value otherwise.
226 mlx5_devx_get_out_command_status(void *out)
232 status = MLX5_GET(query_flow_counter_out, out, status);
234 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
236 DRV_LOG(ERR, "Bad devX status %x, syndrome = %x", status,
243 * Destroy any object allocated by a Devx API.
246 * Pointer to a general object.
249 * 0 on success, a negative value otherwise.
252 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
258 ret = mlx5_glue->devx_obj_destroy(obj->obj);
264 * Query NIC vport context.
265 * Fills minimal inline attribute.
268 * ibv contexts returned from mlx5dv_open_device.
272 * Attributes device values.
275 * 0 on success, a negative value otherwise.
278 mlx5_devx_cmd_query_nic_vport_context(struct ibv_context *ctx,
280 struct mlx5_hca_attr *attr)
282 uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
283 uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
285 int status, syndrome, rc;
287 /* Query NIC vport context to determine inline mode. */
288 MLX5_SET(query_nic_vport_context_in, in, opcode,
289 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
290 MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
292 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
293 rc = mlx5_glue->devx_general_cmd(ctx,
298 status = MLX5_GET(query_nic_vport_context_out, out, status);
299 syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
301 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
302 "status %x, syndrome = %x",
306 vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
308 attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
309 min_wqe_inline_mode);
312 rc = (rc > 0) ? -rc : rc;
317 * Query NIC vDPA attributes.
320 * ibv contexts returned from mlx5dv_open_device.
321 * @param[out] vdpa_attr
322 * vDPA Attributes structure to fill.
325 mlx5_devx_cmd_query_hca_vdpa_attr(struct ibv_context *ctx,
326 struct mlx5_hca_vdpa_attr *vdpa_attr)
328 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
329 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
330 void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
331 int status, syndrome, rc;
333 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
334 MLX5_SET(query_hca_cap_in, in, op_mod,
335 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
336 MLX5_HCA_CAP_OPMOD_GET_CUR);
337 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
338 status = MLX5_GET(query_hca_cap_out, out, status);
339 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
341 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities,"
342 " status %x, syndrome = %x", status, syndrome);
343 vdpa_attr->valid = 0;
345 vdpa_attr->valid = 1;
346 vdpa_attr->desc_tunnel_offload_type =
347 MLX5_GET(virtio_emulation_cap, hcattr,
348 desc_tunnel_offload_type);
349 vdpa_attr->eth_frame_offload_type =
350 MLX5_GET(virtio_emulation_cap, hcattr,
351 eth_frame_offload_type);
352 vdpa_attr->virtio_version_1_0 =
353 MLX5_GET(virtio_emulation_cap, hcattr,
355 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
357 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
359 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
361 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
363 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
365 vdpa_attr->virtio_queue_type =
366 MLX5_GET(virtio_emulation_cap, hcattr,
368 vdpa_attr->log_doorbell_stride =
369 MLX5_GET(virtio_emulation_cap, hcattr,
370 log_doorbell_stride);
371 vdpa_attr->log_doorbell_bar_size =
372 MLX5_GET(virtio_emulation_cap, hcattr,
373 log_doorbell_bar_size);
374 vdpa_attr->doorbell_bar_offset =
375 MLX5_GET64(virtio_emulation_cap, hcattr,
376 doorbell_bar_offset);
377 vdpa_attr->max_num_virtio_queues =
378 MLX5_GET(virtio_emulation_cap, hcattr,
379 max_num_virtio_queues);
380 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
381 umem_1_buffer_param_a);
382 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
383 umem_1_buffer_param_b);
384 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
385 umem_2_buffer_param_a);
386 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
387 umem_2_buffer_param_b);
388 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
389 umem_3_buffer_param_a);
390 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
391 umem_3_buffer_param_b);
396 * Query HCA attributes.
397 * Using those attributes we can check on run time if the device
398 * is having the required capabilities.
401 * ibv contexts returned from mlx5dv_open_device.
403 * Attributes device values.
406 * 0 on success, a negative value otherwise.
409 mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
410 struct mlx5_hca_attr *attr)
412 uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
413 uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
415 int status, syndrome, rc;
417 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
418 MLX5_SET(query_hca_cap_in, in, op_mod,
419 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
420 MLX5_HCA_CAP_OPMOD_GET_CUR);
422 rc = mlx5_glue->devx_general_cmd(ctx,
423 in, sizeof(in), out, sizeof(out));
426 status = MLX5_GET(query_hca_cap_out, out, status);
427 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
429 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
430 "status %x, syndrome = %x",
434 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
435 attr->flow_counter_bulk_alloc_bitmap =
436 MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
437 attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
439 attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
440 attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
441 attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
442 log_max_hairpin_queues);
443 attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
444 log_max_hairpin_wq_data_sz);
445 attr->log_max_hairpin_num_packets = MLX5_GET
446 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
447 attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
448 attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
450 attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
451 attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
452 flex_parser_protocols);
453 attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
454 attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
456 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
458 MLX5_SET(query_hca_cap_in, in, op_mod,
459 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
460 MLX5_HCA_CAP_OPMOD_GET_CUR);
461 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
466 DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
467 " status %x, syndrome = %x",
471 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
472 attr->qos.srtcm_sup =
473 MLX5_GET(qos_cap, hcattr, flow_meter_srtcm);
474 attr->qos.log_max_flow_meter =
475 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
476 attr->qos.flow_meter_reg_c_ids =
477 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
478 attr->qos.flow_meter_reg_share =
479 MLX5_GET(qos_cap, hcattr, flow_meter_reg_share);
481 if (attr->vdpa.valid)
482 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
483 if (!attr->eth_net_offloads)
486 /* Query HCA offloads for Ethernet protocol. */
487 memset(in, 0, sizeof(in));
488 memset(out, 0, sizeof(out));
489 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
490 MLX5_SET(query_hca_cap_in, in, op_mod,
491 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
492 MLX5_HCA_CAP_OPMOD_GET_CUR);
494 rc = mlx5_glue->devx_general_cmd(ctx,
498 attr->eth_net_offloads = 0;
501 status = MLX5_GET(query_hca_cap_out, out, status);
502 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
504 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
505 "status %x, syndrome = %x",
507 attr->eth_net_offloads = 0;
510 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
511 attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
512 hcattr, wqe_vlan_insert);
513 attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
515 attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
516 hcattr, tunnel_lro_gre);
517 attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
518 hcattr, tunnel_lro_vxlan);
519 attr->lro_max_msg_sz_mode = MLX5_GET
520 (per_protocol_networking_offload_caps,
521 hcattr, lro_max_msg_sz_mode);
522 for (int i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
523 attr->lro_timer_supported_periods[i] =
524 MLX5_GET(per_protocol_networking_offload_caps, hcattr,
525 lro_timer_supported_periods[i]);
527 attr->tunnel_stateless_geneve_rx =
528 MLX5_GET(per_protocol_networking_offload_caps,
529 hcattr, tunnel_stateless_geneve_rx);
530 attr->geneve_max_opt_len =
531 MLX5_GET(per_protocol_networking_offload_caps,
532 hcattr, max_geneve_opt_len);
533 attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
534 hcattr, wqe_inline_mode);
535 attr->tunnel_stateless_gtp = MLX5_GET
536 (per_protocol_networking_offload_caps,
537 hcattr, tunnel_stateless_gtp);
538 if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
540 if (attr->eth_virt) {
541 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
549 rc = (rc > 0) ? -rc : rc;
554 * Query TIS transport domain from QP verbs object using DevX API.
557 * Pointer to verbs QP returned by ibv_create_qp .
559 * TIS number of TIS to query.
561 * Pointer to TIS transport domain variable, to be set by the routine.
564 * 0 on success, a negative value otherwise.
567 mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
570 uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
571 uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
575 MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
576 MLX5_SET(query_tis_in, in, tisn, tis_num);
577 rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
579 DRV_LOG(ERR, "Failed to query QP using DevX");
582 tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
583 *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
588 * Fill WQ data for DevX API command.
589 * Utility function for use when creating DevX objects containing a WQ.
592 * Pointer to WQ context to fill with data.
593 * @param [in] wq_attr
594 * Pointer to WQ attributes structure to fill in WQ context.
597 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
599 MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
600 MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
601 MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
602 MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
603 MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
604 MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
605 MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
606 MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
607 MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
608 MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
609 MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
610 MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
611 MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
612 MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
613 MLX5_SET(wq, wq_ctx, log_wq_pg_sz, wq_attr->log_wq_pg_sz);
614 MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
615 MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
616 MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
617 MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
618 wq_attr->log_hairpin_num_packets);
619 MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
620 MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
621 wq_attr->single_wqe_log_num_of_strides);
622 MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
623 MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
624 wq_attr->single_stride_log_num_of_bytes);
625 MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
626 MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
627 MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
631 * Create RQ using DevX API.
634 * ibv_context returned from mlx5dv_open_device.
635 * @param [in] rq_attr
636 * Pointer to create RQ attributes structure.
638 * CPU socket ID for allocations.
641 * The DevX object created, NULL otherwise and rte_errno is set.
643 struct mlx5_devx_obj *
644 mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
645 struct mlx5_devx_create_rq_attr *rq_attr,
648 uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
649 uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
650 void *rq_ctx, *wq_ctx;
651 struct mlx5_devx_wq_attr *wq_attr;
652 struct mlx5_devx_obj *rq = NULL;
654 rq = rte_calloc_socket(__func__, 1, sizeof(*rq), 0, socket);
656 DRV_LOG(ERR, "Failed to allocate RQ data");
660 MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
661 rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
662 MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
663 MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
664 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
665 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
666 MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
667 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
668 MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
669 MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
670 MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
671 MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
672 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
673 MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
674 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
675 wq_attr = &rq_attr->wq_attr;
676 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
677 rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
680 DRV_LOG(ERR, "Failed to create RQ using DevX");
685 rq->id = MLX5_GET(create_rq_out, out, rqn);
690 * Modify RQ using DevX API.
693 * Pointer to RQ object structure.
694 * @param [in] rq_attr
695 * Pointer to modify RQ attributes structure.
698 * 0 on success, a negative errno value otherwise and rte_errno is set.
701 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
702 struct mlx5_devx_modify_rq_attr *rq_attr)
704 uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
705 uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
706 void *rq_ctx, *wq_ctx;
709 MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
710 MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
711 MLX5_SET(modify_rq_in, in, rqn, rq->id);
712 MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
713 rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
714 MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
715 if (rq_attr->modify_bitmask &
716 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
717 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
718 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
719 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
720 if (rq_attr->modify_bitmask &
721 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
722 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
723 MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
724 MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
725 if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
726 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
727 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
729 ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
732 DRV_LOG(ERR, "Failed to modify RQ using DevX");
740 * Create TIR using DevX API.
743 * ibv_context returned from mlx5dv_open_device.
744 * @param [in] tir_attr
745 * Pointer to TIR attributes structure.
748 * The DevX object created, NULL otherwise and rte_errno is set.
750 struct mlx5_devx_obj *
751 mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
752 struct mlx5_devx_tir_attr *tir_attr)
754 uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
755 uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
756 void *tir_ctx, *outer, *inner;
757 struct mlx5_devx_obj *tir = NULL;
760 tir = rte_calloc(__func__, 1, sizeof(*tir), 0);
762 DRV_LOG(ERR, "Failed to allocate TIR data");
766 MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
767 tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
768 MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
769 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
770 tir_attr->lro_timeout_period_usecs);
771 MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
772 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
773 MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
774 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
775 MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
776 tir_attr->tunneled_offload_en);
777 MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
778 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
779 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
780 MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
781 for (i = 0; i < 10; i++) {
782 MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
783 tir_attr->rx_hash_toeplitz_key[i]);
785 outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
786 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
787 tir_attr->rx_hash_field_selector_outer.l3_prot_type);
788 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
789 tir_attr->rx_hash_field_selector_outer.l4_prot_type);
790 MLX5_SET(rx_hash_field_select, outer, selected_fields,
791 tir_attr->rx_hash_field_selector_outer.selected_fields);
792 inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
793 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
794 tir_attr->rx_hash_field_selector_inner.l3_prot_type);
795 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
796 tir_attr->rx_hash_field_selector_inner.l4_prot_type);
797 MLX5_SET(rx_hash_field_select, inner, selected_fields,
798 tir_attr->rx_hash_field_selector_inner.selected_fields);
799 tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
802 DRV_LOG(ERR, "Failed to create TIR using DevX");
807 tir->id = MLX5_GET(create_tir_out, out, tirn);
812 * Create RQT using DevX API.
815 * ibv_context returned from mlx5dv_open_device.
816 * @param [in] rqt_attr
817 * Pointer to RQT attributes structure.
820 * The DevX object created, NULL otherwise and rte_errno is set.
822 struct mlx5_devx_obj *
823 mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
824 struct mlx5_devx_rqt_attr *rqt_attr)
827 uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
828 rqt_attr->rqt_actual_size * sizeof(uint32_t);
829 uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
831 struct mlx5_devx_obj *rqt = NULL;
834 in = rte_calloc(__func__, 1, inlen, 0);
836 DRV_LOG(ERR, "Failed to allocate RQT IN data");
840 rqt = rte_calloc(__func__, 1, sizeof(*rqt), 0);
842 DRV_LOG(ERR, "Failed to allocate RQT data");
847 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
848 rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
849 MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
850 MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
851 for (i = 0; i < rqt_attr->rqt_actual_size; i++)
852 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
853 rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
856 DRV_LOG(ERR, "Failed to create RQT using DevX");
861 rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
866 * Create SQ using DevX API.
869 * ibv_context returned from mlx5dv_open_device.
870 * @param [in] sq_attr
871 * Pointer to SQ attributes structure.
873 * CPU socket ID for allocations.
876 * The DevX object created, NULL otherwise and rte_errno is set.
878 struct mlx5_devx_obj *
879 mlx5_devx_cmd_create_sq(struct ibv_context *ctx,
880 struct mlx5_devx_create_sq_attr *sq_attr)
882 uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
883 uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
886 struct mlx5_devx_wq_attr *wq_attr;
887 struct mlx5_devx_obj *sq = NULL;
889 sq = rte_calloc(__func__, 1, sizeof(*sq), 0);
891 DRV_LOG(ERR, "Failed to allocate SQ data");
895 MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
896 sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
897 MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
898 MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
899 MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
900 MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
901 MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
902 sq_attr->flush_in_error_en);
903 MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
904 sq_attr->min_wqe_inline_mode);
905 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
906 MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
907 MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
908 MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
909 MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
910 MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
911 MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
912 sq_attr->packet_pacing_rate_limit_index);
913 MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
914 MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
915 wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
916 wq_attr = &sq_attr->wq_attr;
917 devx_cmd_fill_wq_data(wq_ctx, wq_attr);
918 sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
921 DRV_LOG(ERR, "Failed to create SQ using DevX");
926 sq->id = MLX5_GET(create_sq_out, out, sqn);
931 * Modify SQ using DevX API.
934 * Pointer to SQ object structure.
935 * @param [in] sq_attr
936 * Pointer to SQ attributes structure.
939 * 0 on success, a negative errno value otherwise and rte_errno is set.
942 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
943 struct mlx5_devx_modify_sq_attr *sq_attr)
945 uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
946 uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
950 MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
951 MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
952 MLX5_SET(modify_sq_in, in, sqn, sq->id);
953 sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
954 MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
955 MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
956 MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
957 ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
960 DRV_LOG(ERR, "Failed to modify SQ using DevX");
968 * Create TIS using DevX API.
971 * ibv_context returned from mlx5dv_open_device.
972 * @param [in] tis_attr
973 * Pointer to TIS attributes structure.
976 * The DevX object created, NULL otherwise and rte_errno is set.
978 struct mlx5_devx_obj *
979 mlx5_devx_cmd_create_tis(struct ibv_context *ctx,
980 struct mlx5_devx_tis_attr *tis_attr)
982 uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
983 uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
984 struct mlx5_devx_obj *tis = NULL;
987 tis = rte_calloc(__func__, 1, sizeof(*tis), 0);
989 DRV_LOG(ERR, "Failed to allocate TIS object");
993 MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
994 tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
995 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
996 tis_attr->strict_lag_tx_port_affinity);
997 MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
998 tis_attr->strict_lag_tx_port_affinity);
999 MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
1000 MLX5_SET(tisc, tis_ctx, transport_domain,
1001 tis_attr->transport_domain);
1002 tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1005 DRV_LOG(ERR, "Failed to create TIS using DevX");
1010 tis->id = MLX5_GET(create_tis_out, out, tisn);
1015 * Create transport domain using DevX API.
1018 * ibv_context returned from mlx5dv_open_device.
1021 * The DevX object created, NULL otherwise and rte_errno is set.
1023 struct mlx5_devx_obj *
1024 mlx5_devx_cmd_create_td(struct ibv_context *ctx)
1026 uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1027 uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1028 struct mlx5_devx_obj *td = NULL;
1030 td = rte_calloc(__func__, 1, sizeof(*td), 0);
1032 DRV_LOG(ERR, "Failed to allocate TD object");
1036 MLX5_SET(alloc_transport_domain_in, in, opcode,
1037 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1038 td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1041 DRV_LOG(ERR, "Failed to create TIS using DevX");
1046 td->id = MLX5_GET(alloc_transport_domain_out, out,
1052 * Dump all flows to file.
1054 * @param[in] fdb_domain
1056 * @param[in] rx_domain
1058 * @param[in] tx_domain
1061 * Pointer to file stream.
1064 * 0 on success, a nagative value otherwise.
1067 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1068 void *rx_domain __rte_unused,
1069 void *tx_domain __rte_unused, FILE *file __rte_unused)
1073 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1075 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1080 ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1084 ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1092 * Create CQ using DevX API.
1095 * ibv_context returned from mlx5dv_open_device.
1097 * Pointer to CQ attributes structure.
1100 * The DevX object created, NULL otherwise and rte_errno is set.
1102 struct mlx5_devx_obj *
1103 mlx5_devx_cmd_create_cq(struct ibv_context *ctx, struct mlx5_devx_cq_attr *attr)
1105 uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
1106 uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
1107 struct mlx5_devx_obj *cq_obj = rte_zmalloc(__func__, sizeof(*cq_obj),
1109 void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1112 DRV_LOG(ERR, "Failed to allocate CQ object memory.");
1116 MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
1117 if (attr->db_umem_valid) {
1118 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
1119 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
1120 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
1122 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
1124 MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
1125 MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
1126 MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
1127 MLX5_SET(cqc, cqctx, log_page_size, attr->log_page_size -
1128 MLX5_ADAPTER_PAGE_SHIFT);
1129 MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
1130 MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
1131 if (attr->q_umem_valid) {
1132 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
1133 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
1134 MLX5_SET64(create_cq_in, in, cq_umem_offset,
1135 attr->q_umem_offset);
1137 cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1141 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno);
1145 cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
1150 * Create VIRTQ using DevX API.
1153 * ibv_context returned from mlx5dv_open_device.
1155 * Pointer to VIRTQ attributes structure.
1158 * The DevX object created, NULL otherwise and rte_errno is set.
1160 struct mlx5_devx_obj *
1161 mlx5_devx_cmd_create_virtq(struct ibv_context *ctx,
1162 struct mlx5_devx_virtq_attr *attr)
1164 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1165 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1166 struct mlx5_devx_obj *virtq_obj = rte_zmalloc(__func__,
1167 sizeof(*virtq_obj), 0);
1168 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1169 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1170 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1173 DRV_LOG(ERR, "Failed to allocate virtq data.");
1177 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1178 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1179 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1180 MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1181 MLX5_SET16(virtio_net_q, virtq, hw_available_index,
1182 attr->hw_available_index);
1183 MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
1184 MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
1185 MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
1186 MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
1187 MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
1188 MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
1189 attr->virtio_version_1_0);
1190 MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
1191 MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
1192 MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
1193 MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
1194 MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
1195 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1196 MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
1197 MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
1198 MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
1199 MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
1200 MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
1201 MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
1202 MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
1203 MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
1204 MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
1205 MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
1206 MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
1207 MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
1208 virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1210 if (!virtq_obj->obj) {
1212 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX.");
1213 rte_free(virtq_obj);
1216 virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1221 * Modify VIRTQ using DevX API.
1223 * @param[in] virtq_obj
1224 * Pointer to virtq object structure.
1226 * Pointer to modify virtq attributes structure.
1229 * 0 on success, a negative errno value otherwise and rte_errno is set.
1232 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
1233 struct mlx5_devx_virtq_attr *attr)
1235 uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1236 uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1237 void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1238 void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1239 void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1242 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1243 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
1244 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1245 MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1246 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1247 MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);
1248 MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1249 switch (attr->type) {
1250 case MLX5_VIRTQ_MODIFY_TYPE_STATE:
1251 MLX5_SET16(virtio_net_q, virtq, state, attr->state);
1253 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:
1254 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
1255 attr->dirty_bitmap_mkey);
1256 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
1257 attr->dirty_bitmap_addr);
1258 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
1259 attr->dirty_bitmap_size);
1261 case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:
1262 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
1263 attr->dirty_bitmap_dump_enable);
1269 ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
1272 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1280 * Query VIRTQ using DevX API.
1282 * @param[in] virtq_obj
1283 * Pointer to virtq object structure.
1284 * @param [in/out] attr
1285 * Pointer to virtq attributes structure.
1288 * 0 on success, a negative errno value otherwise and rte_errno is set.
1291 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
1292 struct mlx5_devx_virtq_attr *attr)
1294 uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
1295 uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
1296 void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
1297 void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
1300 MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1301 MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
1302 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1303 MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1304 MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1305 ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
1308 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1312 attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
1313 hw_available_index);
1314 attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
1319 * Create QP using DevX API.
1322 * ibv_context returned from mlx5dv_open_device.
1324 * Pointer to QP attributes structure.
1327 * The DevX object created, NULL otherwise and rte_errno is set.
1329 struct mlx5_devx_obj *
1330 mlx5_devx_cmd_create_qp(struct ibv_context *ctx,
1331 struct mlx5_devx_qp_attr *attr)
1333 uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
1334 uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
1335 struct mlx5_devx_obj *qp_obj = rte_zmalloc(__func__, sizeof(*qp_obj),
1337 void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1340 DRV_LOG(ERR, "Failed to allocate QP data.");
1344 MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
1345 MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
1346 MLX5_SET(qpc, qpc, pd, attr->pd);
1347 if (attr->uar_index) {
1348 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1349 MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
1350 MLX5_SET(qpc, qpc, log_page_size, attr->log_page_size -
1351 MLX5_ADAPTER_PAGE_SHIFT);
1352 if (attr->sq_size) {
1353 RTE_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));
1354 MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
1355 MLX5_SET(qpc, qpc, log_sq_size,
1356 rte_log2_u32(attr->sq_size));
1358 MLX5_SET(qpc, qpc, no_sq, 1);
1360 if (attr->rq_size) {
1361 RTE_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size));
1362 MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
1363 MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
1364 MLX5_LOG_RQ_STRIDE_SHIFT);
1365 MLX5_SET(qpc, qpc, log_rq_size,
1366 rte_log2_u32(attr->rq_size));
1367 MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
1369 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1371 if (attr->dbr_umem_valid) {
1372 MLX5_SET(qpc, qpc, dbr_umem_valid,
1373 attr->dbr_umem_valid);
1374 MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
1376 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
1377 MLX5_SET64(create_qp_in, in, wq_umem_offset,
1378 attr->wq_umem_offset);
1379 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
1380 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
1382 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
1383 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1384 MLX5_SET(qpc, qpc, no_sq, 1);
1386 qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1390 DRV_LOG(ERR, "Failed to create QP Obj using DevX.");
1394 qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
1399 * Modify QP using DevX API.
1400 * Currently supports only force loop-back QP.
1403 * Pointer to QP object structure.
1404 * @param [in] qp_st_mod_op
1405 * The QP state modification operation.
1406 * @param [in] remote_qp_id
1407 * The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
1410 * 0 on success, a negative errno value otherwise and rte_errno is set.
1413 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
1414 uint32_t remote_qp_id)
1417 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
1418 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
1419 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
1422 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
1423 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
1424 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
1429 unsigned int outlen;
1431 memset(&in, 0, sizeof(in));
1432 memset(&out, 0, sizeof(out));
1433 MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
1434 switch (qp_st_mod_op) {
1435 case MLX5_CMD_OP_RST2INIT_QP:
1436 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
1437 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
1438 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
1439 MLX5_SET(qpc, qpc, rre, 1);
1440 MLX5_SET(qpc, qpc, rwe, 1);
1441 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1442 inlen = sizeof(in.rst2init);
1443 outlen = sizeof(out.rst2init);
1445 case MLX5_CMD_OP_INIT2RTR_QP:
1446 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
1447 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
1448 MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
1449 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
1450 MLX5_SET(qpc, qpc, mtu, 1);
1451 MLX5_SET(qpc, qpc, log_msg_max, 30);
1452 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
1453 MLX5_SET(qpc, qpc, min_rnr_nak, 0);
1454 inlen = sizeof(in.init2rtr);
1455 outlen = sizeof(out.init2rtr);
1457 case MLX5_CMD_OP_RTR2RTS_QP:
1458 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
1459 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
1460 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14);
1461 MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
1462 MLX5_SET(qpc, qpc, retry_count, 7);
1463 MLX5_SET(qpc, qpc, rnr_retry, 7);
1464 inlen = sizeof(in.rtr2rts);
1465 outlen = sizeof(out.rtr2rts);
1468 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
1473 ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
1475 DRV_LOG(ERR, "Failed to modify QP using DevX.");