drivers/common/mlx5/mlx5_devx_cmds.c

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /* Copyright 2018 Mellanox Technologies, Ltd */
   3
   4 #include <unistd.h>
   5
   6 #include <rte_errno.h>
   7 #include <rte_malloc.h>
   8 #include <rte_eal_paging.h>
   9
  10 #include "mlx5_prm.h"
  11 #include "mlx5_devx_cmds.h"
  12 #include "mlx5_common_utils.h"
  13 #include "mlx5_malloc.h"
  14
  15
  16 /**
  17  * Perform read access to the registers. Reads data from register
  18  * and writes ones to the specified buffer.
  19  *
  20  * @param[in] ctx
  21  *   Context returned from mlx5 open_device() glue function.
  22  * @param[in] reg_id
  23  *   Register identifier according to the PRM.
  24  * @param[in] arg
  25  *   Register access auxiliary parameter according to the PRM.
  26  * @param[out] data
  27  *   Pointer to the buffer to store read data.
  28  * @param[in] dw_cnt
  29  *   Buffer size in double words.
  30  *
  31  * @return
  32  *   0 on success, a negative value otherwise.
  33  */
  34 int
  35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
  36                             uint32_t *data, uint32_t dw_cnt)
  37 {
  38         uint32_t in[MLX5_ST_SZ_DW(access_register_in)]   = {0};
  39         uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
  40                      MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
  41         int status, rc;
  42
  43         MLX5_ASSERT(data && dw_cnt);
  44         MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
  45         if (dw_cnt  > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
  46                 DRV_LOG(ERR, "Not enough  buffer for register read data");
  47                 return -1;
  48         }
  49         MLX5_SET(access_register_in, in, opcode,
  50                  MLX5_CMD_OP_ACCESS_REGISTER_USER);
  51         MLX5_SET(access_register_in, in, op_mod,
  52                                         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
  53         MLX5_SET(access_register_in, in, register_id, reg_id);
  54         MLX5_SET(access_register_in, in, argument, arg);
  55         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
  56                                          MLX5_ST_SZ_DW(access_register_out) *
  57                                          sizeof(uint32_t) + dw_cnt);
  58         if (rc)
  59                 goto error;
  60         status = MLX5_GET(access_register_out, out, status);
  61         if (status) {
  62                 int syndrome = MLX5_GET(access_register_out, out, syndrome);
  63
  64                 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, "
  65                                "status %x, syndrome = %x",
  66                                reg_id, status, syndrome);
  67                 return -1;
  68         }
  69         memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
  70                dw_cnt * sizeof(uint32_t));
  71         return 0;
  72 error:
  73         rc = (rc > 0) ? -rc : rc;
  74         return rc;
  75 }
  76
  77 /**
  78  * Allocate flow counters via devx interface.
  79  *
  80  * @param[in] ctx
  81  *   Context returned from mlx5 open_device() glue function.
  82  * @param dcs
  83  *   Pointer to counters properties structure to be filled by the routine.
  84  * @param bulk_n_128
  85  *   Bulk counter numbers in 128 counters units.
  86  *
  87  * @return
  88  *   Pointer to counter object on success, a negative value otherwise and
  89  *   rte_errno is set.
  90  */
  91 struct mlx5_devx_obj *
  92 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
  93 {
  94         struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
  95                                                 0, SOCKET_ID_ANY);
  96         uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)]   = {0};
  97         uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
  98
  99         if (!dcs) {
 100                 rte_errno = ENOMEM;
 101                 return NULL;
 102         }
 103         MLX5_SET(alloc_flow_counter_in, in, opcode,
 104                  MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
 105         MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
 106         dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
 107                                               sizeof(in), out, sizeof(out));
 108         if (!dcs->obj) {
 109                 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
 110                 rte_errno = errno;
 111                 mlx5_free(dcs);
 112                 return NULL;
 113         }
 114         dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
 115         return dcs;
 116 }
 117
 118 /**
 119  * Query flow counters values.
 120  *
 121  * @param[in] dcs
 122  *   devx object that was obtained from mlx5_devx_cmd_fc_alloc.
 123  * @param[in] clear
 124  *   Whether hardware should clear the counters after the query or not.
 125  * @param[in] n_counters
 126  *   0 in case of 1 counter to read, otherwise the counter number to read.
 127  *  @param pkts
 128  *   The number of packets that matched the flow.
 129  *  @param bytes
 130  *    The number of bytes that matched the flow.
 131  *  @param mkey
 132  *   The mkey key for batch query.
 133  *  @param addr
 134  *    The address in the mkey range for batch query.
 135  *  @param cmd_comp
 136  *   The completion object for asynchronous batch query.
 137  *  @param async_id
 138  *    The ID to be returned in the asynchronous batch query response.
 139  *
 140  * @return
 141  *   0 on success, a negative value otherwise.
 142  */
 143 int
 144 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
 145                                  int clear, uint32_t n_counters,
 146                                  uint64_t *pkts, uint64_t *bytes,
 147                                  uint32_t mkey, void *addr,
 148                                  void *cmd_comp,
 149                                  uint64_t async_id)
 150 {
 151         int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
 152                         MLX5_ST_SZ_BYTES(traffic_counter);
 153         uint32_t out[out_len];
 154         uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
 155         void *stats;
 156         int rc;
 157
 158         MLX5_SET(query_flow_counter_in, in, opcode,
 159                  MLX5_CMD_OP_QUERY_FLOW_COUNTER);
 160         MLX5_SET(query_flow_counter_in, in, op_mod, 0);
 161         MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
 162         MLX5_SET(query_flow_counter_in, in, clear, !!clear);
 163
 164         if (n_counters) {
 165                 MLX5_SET(query_flow_counter_in, in, num_of_counters,
 166                          n_counters);
 167                 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
 168                 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
 169                 MLX5_SET64(query_flow_counter_in, in, address,
 170                            (uint64_t)(uintptr_t)addr);
 171         }
 172         if (!cmd_comp)
 173                 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
 174                                                out_len);
 175         else
 176                 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
 177                                                      out_len, async_id,
 178                                                      cmd_comp);
 179         if (rc) {
 180                 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
 181                 rte_errno = rc;
 182                 return -rc;
 183         }
 184         if (!n_counters) {
 185                 stats = MLX5_ADDR_OF(query_flow_counter_out,
 186                                      out, flow_statistics);
 187                 *pkts = MLX5_GET64(traffic_counter, stats, packets);
 188                 *bytes = MLX5_GET64(traffic_counter, stats, octets);
 189         }
 190         return 0;
 191 }
 192
 193 /**
 194  * Create a new mkey.
 195  *
 196  * @param[in] ctx
 197  *   Context returned from mlx5 open_device() glue function.
 198  * @param[in] attr
 199  *   Attributes of the requested mkey.
 200  *
 201  * @return
 202  *   Pointer to Devx mkey on success, a negative value otherwise and rte_errno
 203  *   is set.
 204  */
 205 struct mlx5_devx_obj *
 206 mlx5_devx_cmd_mkey_create(void *ctx,
 207                           struct mlx5_devx_mkey_attr *attr)
 208 {
 209         struct mlx5_klm *klm_array = attr->klm_array;
 210         int klm_num = attr->klm_num;
 211         int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
 212                      (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
 213         uint32_t in[in_size_dw];
 214         uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
 215         void *mkc;
 216         struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
 217                                                  0, SOCKET_ID_ANY);
 218         size_t pgsize;
 219         uint32_t translation_size;
 220
 221         if (!mkey) {
 222                 rte_errno = ENOMEM;
 223                 return NULL;
 224         }
 225         memset(in, 0, in_size_dw * 4);
 226         pgsize = rte_mem_page_size();
 227         if (pgsize == (size_t)-1) {
 228                 mlx5_free(mkey);
 229                 DRV_LOG(ERR, "Failed to get page size");
 230                 rte_errno = ENOMEM;
 231                 return NULL;
 232         }
 233         MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
 234         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 235         if (klm_num > 0) {
 236                 int i;
 237                 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
 238                                                        klm_pas_mtt);
 239                 translation_size = RTE_ALIGN(klm_num, 4);
 240                 for (i = 0; i < klm_num; i++) {
 241                         MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
 242                         MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
 243                         MLX5_SET64(klm, klm, address, klm_array[i].address);
 244                         klm += MLX5_ST_SZ_BYTES(klm);
 245                 }
 246                 for (; i < (int)translation_size; i++) {
 247                         MLX5_SET(klm, klm, mkey, 0x0);
 248                         MLX5_SET64(klm, klm, address, 0x0);
 249                         klm += MLX5_ST_SZ_BYTES(klm);
 250                 }
 251                 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
 252                          MLX5_MKC_ACCESS_MODE_KLM_FBS :
 253                          MLX5_MKC_ACCESS_MODE_KLM);
 254                 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
 255         } else {
 256                 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
 257                 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 258                 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
 259         }
 260         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 261                  translation_size);
 262         MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
 263         MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
 264         MLX5_SET(mkc, mkc, lw, 0x1);
 265         MLX5_SET(mkc, mkc, lr, 0x1);
 266         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 267         MLX5_SET(mkc, mkc, pd, attr->pd);
 268         MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
 269         MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
 270         if (attr->relaxed_ordering == 1) {
 271                 MLX5_SET(mkc, mkc, relaxed_ordering_write, 0x1);
 272                 MLX5_SET(mkc, mkc, relaxed_ordering_read, 0x1);
 273         }
 274         MLX5_SET64(mkc, mkc, start_addr, attr->addr);
 275         MLX5_SET64(mkc, mkc, len, attr->size);
 276         mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
 277                                                sizeof(out));
 278         if (!mkey->obj) {
 279                 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d\n",
 280                         klm_num ? "an in" : "a ", errno);
 281                 rte_errno = errno;
 282                 mlx5_free(mkey);
 283                 return NULL;
 284         }
 285         mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
 286         mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
 287         return mkey;
 288 }
 289
 290 /**
 291  * Get status of devx command response.
 292  * Mainly used for asynchronous commands.
 293  *
 294  * @param[in] out
 295  *   The out response buffer.
 296  *
 297  * @return
 298  *   0 on success, non-zero value otherwise.
 299  */
 300 int
 301 mlx5_devx_get_out_command_status(void *out)
 302 {
 303         int status;
 304
 305         if (!out)
 306                 return -EINVAL;
 307         status = MLX5_GET(query_flow_counter_out, out, status);
 308         if (status) {
 309                 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
 310
 311                 DRV_LOG(ERR, "Bad devX status %x, syndrome = %x", status,
 312                         syndrome);
 313         }
 314         return status;
 315 }
 316
 317 /**
 318  * Destroy any object allocated by a Devx API.
 319  *
 320  * @param[in] obj
 321  *   Pointer to a general object.
 322  *
 323  * @return
 324  *   0 on success, a negative value otherwise.
 325  */
 326 int
 327 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
 328 {
 329         int ret;
 330
 331         if (!obj)
 332                 return 0;
 333         ret =  mlx5_glue->devx_obj_destroy(obj->obj);
 334         mlx5_free(obj);
 335         return ret;
 336 }
 337
 338 /**
 339  * Query NIC vport context.
 340  * Fills minimal inline attribute.
 341  *
 342  * @param[in] ctx
 343  *   ibv contexts returned from mlx5dv_open_device.
 344  * @param[in] vport
 345  *   vport index
 346  * @param[out] attr
 347  *   Attributes device values.
 348  *
 349  * @return
 350  *   0 on success, a negative value otherwise.
 351  */
 352 static int
 353 mlx5_devx_cmd_query_nic_vport_context(void *ctx,
 354                                       unsigned int vport,
 355                                       struct mlx5_hca_attr *attr)
 356 {
 357         uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
 358         uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
 359         void *vctx;
 360         int status, syndrome, rc;
 361
 362         /* Query NIC vport context to determine inline mode. */
 363         MLX5_SET(query_nic_vport_context_in, in, opcode,
 364                  MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
 365         MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
 366         if (vport)
 367                 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
 368         rc = mlx5_glue->devx_general_cmd(ctx,
 369                                          in, sizeof(in),
 370                                          out, sizeof(out));
 371         if (rc)
 372                 goto error;
 373         status = MLX5_GET(query_nic_vport_context_out, out, status);
 374         syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
 375         if (status) {
 376                 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
 377                         "status %x, syndrome = %x",
 378                         status, syndrome);
 379                 return -1;
 380         }
 381         vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
 382                             nic_vport_context);
 383         attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
 384                                            min_wqe_inline_mode);
 385         return 0;
 386 error:
 387         rc = (rc > 0) ? -rc : rc;
 388         return rc;
 389 }
 390
 391 /**
 392  * Query NIC vDPA attributes.
 393  *
 394  * @param[in] ctx
 395  *   Context returned from mlx5 open_device() glue function.
 396  * @param[out] vdpa_attr
 397  *   vDPA Attributes structure to fill.
 398  */
 399 static void
 400 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
 401                                   struct mlx5_hca_vdpa_attr *vdpa_attr)
 402 {
 403         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 404         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 405         void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 406         int status, syndrome, rc;
 407
 408         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 409         MLX5_SET(query_hca_cap_in, in, op_mod,
 410                  MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
 411                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 412         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 413         status = MLX5_GET(query_hca_cap_out, out, status);
 414         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 415         if (rc || status) {
 416                 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities,"
 417                         " status %x, syndrome = %x", status, syndrome);
 418                 vdpa_attr->valid = 0;
 419         } else {
 420                 vdpa_attr->valid = 1;
 421                 vdpa_attr->desc_tunnel_offload_type =
 422                         MLX5_GET(virtio_emulation_cap, hcattr,
 423                                  desc_tunnel_offload_type);
 424                 vdpa_attr->eth_frame_offload_type =
 425                         MLX5_GET(virtio_emulation_cap, hcattr,
 426                                  eth_frame_offload_type);
 427                 vdpa_attr->virtio_version_1_0 =
 428                         MLX5_GET(virtio_emulation_cap, hcattr,
 429                                  virtio_version_1_0);
 430                 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
 431                                                tso_ipv4);
 432                 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
 433                                                tso_ipv6);
 434                 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 435                                               tx_csum);
 436                 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 437                                               rx_csum);
 438                 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
 439                                                  event_mode);
 440                 vdpa_attr->virtio_queue_type =
 441                         MLX5_GET(virtio_emulation_cap, hcattr,
 442                                  virtio_queue_type);
 443                 vdpa_attr->log_doorbell_stride =
 444                         MLX5_GET(virtio_emulation_cap, hcattr,
 445                                  log_doorbell_stride);
 446                 vdpa_attr->log_doorbell_bar_size =
 447                         MLX5_GET(virtio_emulation_cap, hcattr,
 448                                  log_doorbell_bar_size);
 449                 vdpa_attr->doorbell_bar_offset =
 450                         MLX5_GET64(virtio_emulation_cap, hcattr,
 451                                    doorbell_bar_offset);
 452                 vdpa_attr->max_num_virtio_queues =
 453                         MLX5_GET(virtio_emulation_cap, hcattr,
 454                                  max_num_virtio_queues);
 455                 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
 456                                                  umem_1_buffer_param_a);
 457                 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
 458                                                  umem_1_buffer_param_b);
 459                 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
 460                                                  umem_2_buffer_param_a);
 461                 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
 462                                                  umem_2_buffer_param_b);
 463                 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
 464                                                  umem_3_buffer_param_a);
 465                 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
 466                                                  umem_3_buffer_param_b);
 467         }
 468 }
 469
 470 int
 471 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
 472                                   uint32_t ids[], uint32_t num)
 473 {
 474         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
 475         uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
 476         void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
 477         void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
 478         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 479         int ret;
 480         uint32_t idx = 0;
 481         uint32_t i;
 482
 483         if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
 484                 rte_errno = EINVAL;
 485                 DRV_LOG(ERR, "Too many sample IDs to be fetched.");
 486                 return -rte_errno;
 487         }
 488         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 489                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
 490         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 491                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 492         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
 493         ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
 494                                         out, sizeof(out));
 495         if (ret) {
 496                 rte_errno = ret;
 497                 DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
 498                         (void *)flex_obj);
 499                 return -rte_errno;
 500         }
 501         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 502                 void *s_off = (void *)((char *)sample + i *
 503                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 504                 uint32_t en;
 505
 506                 en = MLX5_GET(parse_graph_flow_match_sample, s_off,
 507                               flow_match_sample_en);
 508                 if (!en)
 509                         continue;
 510                 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
 511                                   flow_match_sample_field_id);
 512         }
 513         if (num != idx) {
 514                 rte_errno = EINVAL;
 515                 DRV_LOG(ERR, "Number of sample IDs are not as expected.");
 516                 return -rte_errno;
 517         }
 518         return ret;
 519 }
 520
 521
 522 struct mlx5_devx_obj *
 523 mlx5_devx_cmd_create_flex_parser(void *ctx,
 524                               struct mlx5_devx_graph_node_attr *data)
 525 {
 526         uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
 527         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
 528         void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
 529         void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
 530         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 531         void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
 532         void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
 533         struct mlx5_devx_obj *parse_flex_obj = NULL;
 534         uint32_t i;
 535
 536         parse_flex_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0,
 537                                      SOCKET_ID_ANY);
 538         if (!parse_flex_obj) {
 539                 DRV_LOG(ERR, "Failed to allocate flex parser data");
 540                 rte_errno = ENOMEM;
 541                 mlx5_free(in);
 542                 return NULL;
 543         }
 544         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 545                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
 546         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 547                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 548         MLX5_SET(parse_graph_flex, flex, header_length_mode,
 549                  data->header_length_mode);
 550         MLX5_SET(parse_graph_flex, flex, header_length_base_value,
 551                  data->header_length_base_value);
 552         MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
 553                  data->header_length_field_offset);
 554         MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
 555                  data->header_length_field_shift);
 556         MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
 557                  data->header_length_field_mask);
 558         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 559                 struct mlx5_devx_match_sample_attr *s = &data->sample[i];
 560                 void *s_off = (void *)((char *)sample + i *
 561                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 562
 563                 if (!s->flow_match_sample_en)
 564                         continue;
 565                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 566                          flow_match_sample_en, !!s->flow_match_sample_en);
 567                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 568                          flow_match_sample_field_offset,
 569                          s->flow_match_sample_field_offset);
 570                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 571                          flow_match_sample_offset_mode,
 572                          s->flow_match_sample_offset_mode);
 573                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 574                          flow_match_sample_field_offset_mask,
 575                          s->flow_match_sample_field_offset_mask);
 576                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 577                          flow_match_sample_field_offset_shift,
 578                          s->flow_match_sample_field_offset_shift);
 579                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 580                          flow_match_sample_field_base_offset,
 581                          s->flow_match_sample_field_base_offset);
 582                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 583                          flow_match_sample_tunnel_mode,
 584                          s->flow_match_sample_tunnel_mode);
 585         }
 586         for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
 587                 struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
 588                 struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
 589                 void *in_off = (void *)((char *)in_arc + i *
 590                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 591                 void *out_off = (void *)((char *)out_arc + i *
 592                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 593
 594                 if (ia->arc_parse_graph_node != 0) {
 595                         MLX5_SET(parse_graph_arc, in_off,
 596                                  compare_condition_value,
 597                                  ia->compare_condition_value);
 598                         MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
 599                                  ia->start_inner_tunnel);
 600                         MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
 601                                  ia->arc_parse_graph_node);
 602                         MLX5_SET(parse_graph_arc, in_off,
 603                                  parse_graph_node_handle,
 604                                  ia->parse_graph_node_handle);
 605                 }
 606                 if (oa->arc_parse_graph_node != 0) {
 607                         MLX5_SET(parse_graph_arc, out_off,
 608                                  compare_condition_value,
 609                                  oa->compare_condition_value);
 610                         MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
 611                                  oa->start_inner_tunnel);
 612                         MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
 613                                  oa->arc_parse_graph_node);
 614                         MLX5_SET(parse_graph_arc, out_off,
 615                                  parse_graph_node_handle,
 616                                  oa->parse_graph_node_handle);
 617                 }
 618         }
 619         parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 620                                                          out, sizeof(out));
 621         if (!parse_flex_obj->obj) {
 622                 rte_errno = errno;
 623                 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object "
 624                         "by using DevX.");
 625                 mlx5_free(parse_flex_obj);
 626                 return NULL;
 627         }
 628         parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
 629         return parse_flex_obj;
 630 }
 631
 632 /**
 633  * Query HCA attributes.
 634  * Using those attributes we can check on run time if the device
 635  * is having the required capabilities.
 636  *
 637  * @param[in] ctx
 638  *   Context returned from mlx5 open_device() glue function.
 639  * @param[out] attr
 640  *   Attributes device values.
 641  *
 642  * @return
 643  *   0 on success, a negative value otherwise.
 644  */
 645 int
 646 mlx5_devx_cmd_query_hca_attr(void *ctx,
 647                              struct mlx5_hca_attr *attr)
 648 {
 649         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 650         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 651         void *hcattr;
 652         int status, syndrome, rc, i;
 653
 654         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 655         MLX5_SET(query_hca_cap_in, in, op_mod,
 656                  MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
 657                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 658
 659         rc = mlx5_glue->devx_general_cmd(ctx,
 660                                          in, sizeof(in), out, sizeof(out));
 661         if (rc)
 662                 goto error;
 663         status = MLX5_GET(query_hca_cap_out, out, status);
 664         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 665         if (status) {
 666                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 667                         "status %x, syndrome = %x",
 668                         status, syndrome);
 669                 return -1;
 670         }
 671         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 672         attr->flow_counter_bulk_alloc_bitmap =
 673                         MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
 674         attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
 675                                             flow_counters_dump);
 676         attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
 677                                           log_max_rqt_size);
 678         attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
 679         attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
 680         attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
 681                                                 log_max_hairpin_queues);
 682         attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
 683                                                     log_max_hairpin_wq_data_sz);
 684         attr->log_max_hairpin_num_packets = MLX5_GET
 685                 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
 686         attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
 687         attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
 688                         relaxed_ordering_write);
 689         attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
 690                         relaxed_ordering_read);
 691         attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
 692                         access_register_user);
 693         attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
 694                                           eth_net_offloads);
 695         attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
 696         attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
 697                                                flex_parser_protocols);
 698         attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
 699         attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 700                                          general_obj_types) &
 701                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 702         attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 703                                                         general_obj_types) &
 704                                   MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
 705         attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 706                                          general_obj_types) &
 707                               MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
 708         attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
 709                                           wqe_index_ignore_cap);
 710         attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
 711         attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
 712         attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
 713                                               log_max_static_sq_wq);
 714         attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
 715                                       device_frequency_khz);
 716         attr->scatter_fcs_w_decap_disable =
 717                 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
 718         attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp);
 719         attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
 720                                                regexp_num_of_engines);
 721         if (attr->qos.sup) {
 722                 MLX5_SET(query_hca_cap_in, in, op_mod,
 723                          MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
 724                          MLX5_HCA_CAP_OPMOD_GET_CUR);
 725                 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
 726                                                  out, sizeof(out));
 727                 if (rc)
 728                         goto error;
 729                 if (status) {
 730                         DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
 731                                 " status %x, syndrome = %x",
 732                                 status, syndrome);
 733                         return -1;
 734                 }
 735                 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 736                 attr->qos.srtcm_sup =
 737                                 MLX5_GET(qos_cap, hcattr, flow_meter_srtcm);
 738                 attr->qos.log_max_flow_meter =
 739                                 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
 740                 attr->qos.flow_meter_reg_c_ids =
 741                                 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
 742                 attr->qos.flow_meter_reg_share =
 743                                 MLX5_GET(qos_cap, hcattr, flow_meter_reg_share);
 744                 attr->qos.packet_pacing =
 745                                 MLX5_GET(qos_cap, hcattr, packet_pacing);
 746                 attr->qos.wqe_rate_pp =
 747                                 MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
 748         }
 749         if (attr->vdpa.valid)
 750                 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
 751         if (!attr->eth_net_offloads)
 752                 return 0;
 753
 754         /* Query Flow Sampler Capability From FLow Table Properties Layout. */
 755         memset(in, 0, sizeof(in));
 756         memset(out, 0, sizeof(out));
 757         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 758         MLX5_SET(query_hca_cap_in, in, op_mod,
 759                  MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
 760                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 761
 762         rc = mlx5_glue->devx_general_cmd(ctx,
 763                                          in, sizeof(in),
 764                                          out, sizeof(out));
 765         if (rc)
 766                 goto error;
 767         status = MLX5_GET(query_hca_cap_out, out, status);
 768         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 769         if (status) {
 770                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 771                         "status %x, syndrome = %x",
 772                         status, syndrome);
 773                 attr->log_max_ft_sampler_num = 0;
 774                 return -1;
 775         }
 776         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 777         attr->log_max_ft_sampler_num =
 778                         MLX5_GET(flow_table_nic_cap,
 779                         hcattr, flow_table_properties.log_max_ft_sampler_num);
 780
 781         /* Query HCA offloads for Ethernet protocol. */
 782         memset(in, 0, sizeof(in));
 783         memset(out, 0, sizeof(out));
 784         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 785         MLX5_SET(query_hca_cap_in, in, op_mod,
 786                  MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
 787                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 788
 789         rc = mlx5_glue->devx_general_cmd(ctx,
 790                                          in, sizeof(in),
 791                                          out, sizeof(out));
 792         if (rc) {
 793                 attr->eth_net_offloads = 0;
 794                 goto error;
 795         }
 796         status = MLX5_GET(query_hca_cap_out, out, status);
 797         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 798         if (status) {
 799                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 800                         "status %x, syndrome = %x",
 801                         status, syndrome);
 802                 attr->eth_net_offloads = 0;
 803                 return -1;
 804         }
 805         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 806         attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
 807                                          hcattr, wqe_vlan_insert);
 808         attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 809                                  lro_cap);
 810         attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
 811                                         hcattr, tunnel_lro_gre);
 812         attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
 813                                           hcattr, tunnel_lro_vxlan);
 814         attr->lro_max_msg_sz_mode = MLX5_GET
 815                                         (per_protocol_networking_offload_caps,
 816                                          hcattr, lro_max_msg_sz_mode);
 817         for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
 818                 attr->lro_timer_supported_periods[i] =
 819                         MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 820                                  lro_timer_supported_periods[i]);
 821         }
 822         attr->tunnel_stateless_geneve_rx =
 823                             MLX5_GET(per_protocol_networking_offload_caps,
 824                                      hcattr, tunnel_stateless_geneve_rx);
 825         attr->geneve_max_opt_len =
 826                     MLX5_GET(per_protocol_networking_offload_caps,
 827                              hcattr, max_geneve_opt_len);
 828         attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
 829                                          hcattr, wqe_inline_mode);
 830         attr->tunnel_stateless_gtp = MLX5_GET
 831                                         (per_protocol_networking_offload_caps,
 832                                          hcattr, tunnel_stateless_gtp);
 833         if (attr->wqe_inline_mode != MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
 834                 return 0;
 835         if (attr->eth_virt) {
 836                 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
 837                 if (rc) {
 838                         attr->eth_virt = 0;
 839                         goto error;
 840                 }
 841         }
 842         return 0;
 843 error:
 844         rc = (rc > 0) ? -rc : rc;
 845         return rc;
 846 }
 847
 848 /**
 849  * Query TIS transport domain from QP verbs object using DevX API.
 850  *
 851  * @param[in] qp
 852  *   Pointer to verbs QP returned by ibv_create_qp .
 853  * @param[in] tis_num
 854  *   TIS number of TIS to query.
 855  * @param[out] tis_td
 856  *   Pointer to TIS transport domain variable, to be set by the routine.
 857  *
 858  * @return
 859  *   0 on success, a negative value otherwise.
 860  */
 861 int
 862 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
 863                               uint32_t *tis_td)
 864 {
 865 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 866         uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
 867         uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
 868         int rc;
 869         void *tis_ctx;
 870
 871         MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
 872         MLX5_SET(query_tis_in, in, tisn, tis_num);
 873         rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
 874         if (rc) {
 875                 DRV_LOG(ERR, "Failed to query QP using DevX");
 876                 return -rc;
 877         };
 878         tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
 879         *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
 880         return 0;
 881 #else
 882         (void)qp;
 883         (void)tis_num;
 884         (void)tis_td;
 885         return -ENOTSUP;
 886 #endif
 887 }
 888
 889 /**
 890  * Fill WQ data for DevX API command.
 891  * Utility function for use when creating DevX objects containing a WQ.
 892  *
 893  * @param[in] wq_ctx
 894  *   Pointer to WQ context to fill with data.
 895  * @param [in] wq_attr
 896  *   Pointer to WQ attributes structure to fill in WQ context.
 897  */
 898 static void
 899 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
 900 {
 901         MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
 902         MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
 903         MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
 904         MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
 905         MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
 906         MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
 907         MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
 908         MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
 909         MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
 910         MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
 911         MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
 912         MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
 913         MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
 914         MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
 915         MLX5_SET(wq, wq_ctx, log_wq_pg_sz, wq_attr->log_wq_pg_sz);
 916         MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
 917         MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
 918         MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
 919         MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
 920                  wq_attr->log_hairpin_num_packets);
 921         MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
 922         MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
 923                  wq_attr->single_wqe_log_num_of_strides);
 924         MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
 925         MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
 926                  wq_attr->single_stride_log_num_of_bytes);
 927         MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
 928         MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
 929         MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
 930 }
 931
 932 /**
 933  * Create RQ using DevX API.
 934  *
 935  * @param[in] ctx
 936  *   Context returned from mlx5 open_device() glue function.
 937  * @param [in] rq_attr
 938  *   Pointer to create RQ attributes structure.
 939  * @param [in] socket
 940  *   CPU socket ID for allocations.
 941  *
 942  * @return
 943  *   The DevX object created, NULL otherwise and rte_errno is set.
 944  */
 945 struct mlx5_devx_obj *
 946 mlx5_devx_cmd_create_rq(void *ctx,
 947                         struct mlx5_devx_create_rq_attr *rq_attr,
 948                         int socket)
 949 {
 950         uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
 951         uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
 952         void *rq_ctx, *wq_ctx;
 953         struct mlx5_devx_wq_attr *wq_attr;
 954         struct mlx5_devx_obj *rq = NULL;
 955
 956         rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
 957         if (!rq) {
 958                 DRV_LOG(ERR, "Failed to allocate RQ data");
 959                 rte_errno = ENOMEM;
 960                 return NULL;
 961         }
 962         MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
 963         rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
 964         MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
 965         MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
 966         MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
 967         MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
 968         MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
 969         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
 970         MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
 971         MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
 972         MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
 973         MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
 974         MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
 975         MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
 976         wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
 977         wq_attr = &rq_attr->wq_attr;
 978         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
 979         rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 980                                                   out, sizeof(out));
 981         if (!rq->obj) {
 982                 DRV_LOG(ERR, "Failed to create RQ using DevX");
 983                 rte_errno = errno;
 984                 mlx5_free(rq);
 985                 return NULL;
 986         }
 987         rq->id = MLX5_GET(create_rq_out, out, rqn);
 988         return rq;
 989 }
 990
 991 /**
 992  * Modify RQ using DevX API.
 993  *
 994  * @param[in] rq
 995  *   Pointer to RQ object structure.
 996  * @param [in] rq_attr
 997  *   Pointer to modify RQ attributes structure.
 998  *
 999  * @return
1000  *   0 on success, a negative errno value otherwise and rte_errno is set.
1001  */
1002 int
1003 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1004                         struct mlx5_devx_modify_rq_attr *rq_attr)
1005 {
1006         uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1007         uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1008         void *rq_ctx, *wq_ctx;
1009         int ret;
1010
1011         MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1012         MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1013         MLX5_SET(modify_rq_in, in, rqn, rq->id);
1014         MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1015         rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1016         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1017         if (rq_attr->modify_bitmask &
1018                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1019                 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1020         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1021                 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1022         if (rq_attr->modify_bitmask &
1023                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1024                 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1025         MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1026         MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1027         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1028                 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1029                 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1030         }
1031         ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1032                                          out, sizeof(out));
1033         if (ret) {
1034                 DRV_LOG(ERR, "Failed to modify RQ using DevX");
1035                 rte_errno = errno;
1036                 return -errno;
1037         }
1038         return ret;
1039 }
1040
1041 /**
1042  * Create TIR using DevX API.
1043  *
1044  * @param[in] ctx
1045  *  Context returned from mlx5 open_device() glue function.
1046  * @param [in] tir_attr
1047  *   Pointer to TIR attributes structure.
1048  *
1049  * @return
1050  *   The DevX object created, NULL otherwise and rte_errno is set.
1051  */
1052 struct mlx5_devx_obj *
1053 mlx5_devx_cmd_create_tir(void *ctx,
1054                          struct mlx5_devx_tir_attr *tir_attr)
1055 {
1056         uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1057         uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1058         void *tir_ctx, *outer, *inner, *rss_key;
1059         struct mlx5_devx_obj *tir = NULL;
1060
1061         tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1062         if (!tir) {
1063                 DRV_LOG(ERR, "Failed to allocate TIR data");
1064                 rte_errno = ENOMEM;
1065                 return NULL;
1066         }
1067         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1068         tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1069         MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1070         MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1071                  tir_attr->lro_timeout_period_usecs);
1072         MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1073         MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1074         MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1075         MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1076         MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1077                  tir_attr->tunneled_offload_en);
1078         MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1079         MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1080         MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1081         MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1082         rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1083         memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1084         outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1085         MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1086                  tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1087         MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1088                  tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1089         MLX5_SET(rx_hash_field_select, outer, selected_fields,
1090                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1091         inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1092         MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1093                  tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1094         MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1095                  tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1096         MLX5_SET(rx_hash_field_select, inner, selected_fields,
1097                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1098         tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1099                                                    out, sizeof(out));
1100         if (!tir->obj) {
1101                 DRV_LOG(ERR, "Failed to create TIR using DevX");
1102                 rte_errno = errno;
1103                 mlx5_free(tir);
1104                 return NULL;
1105         }
1106         tir->id = MLX5_GET(create_tir_out, out, tirn);
1107         return tir;
1108 }
1109
1110 /**
1111  * Create RQT using DevX API.
1112  *
1113  * @param[in] ctx
1114  *   Context returned from mlx5 open_device() glue function.
1115  * @param [in] rqt_attr
1116  *   Pointer to RQT attributes structure.
1117  *
1118  * @return
1119  *   The DevX object created, NULL otherwise and rte_errno is set.
1120  */
1121 struct mlx5_devx_obj *
1122 mlx5_devx_cmd_create_rqt(void *ctx,
1123                          struct mlx5_devx_rqt_attr *rqt_attr)
1124 {
1125         uint32_t *in = NULL;
1126         uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1127                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1128         uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1129         void *rqt_ctx;
1130         struct mlx5_devx_obj *rqt = NULL;
1131         int i;
1132
1133         in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1134         if (!in) {
1135                 DRV_LOG(ERR, "Failed to allocate RQT IN data");
1136                 rte_errno = ENOMEM;
1137                 return NULL;
1138         }
1139         rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1140         if (!rqt) {
1141                 DRV_LOG(ERR, "Failed to allocate RQT data");
1142                 rte_errno = ENOMEM;
1143                 mlx5_free(in);
1144                 return NULL;
1145         }
1146         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1147         rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1148         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1149         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1150         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1151         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1152                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1153         rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1154         mlx5_free(in);
1155         if (!rqt->obj) {
1156                 DRV_LOG(ERR, "Failed to create RQT using DevX");
1157                 rte_errno = errno;
1158                 mlx5_free(rqt);
1159                 return NULL;
1160         }
1161         rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1162         return rqt;
1163 }
1164
1165 /**
1166  * Modify RQT using DevX API.
1167  *
1168  * @param[in] rqt
1169  *   Pointer to RQT DevX object structure.
1170  * @param [in] rqt_attr
1171  *   Pointer to RQT attributes structure.
1172  *
1173  * @return
1174  *   0 on success, a negative errno value otherwise and rte_errno is set.
1175  */
1176 int
1177 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1178                          struct mlx5_devx_rqt_attr *rqt_attr)
1179 {
1180         uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1181                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1182         uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1183         uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1184         void *rqt_ctx;
1185         int i;
1186         int ret;
1187
1188         if (!in) {
1189                 DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1190                 rte_errno = ENOMEM;
1191                 return -ENOMEM;
1192         }
1193         MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
1194         MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
1195         MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
1196         rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
1197         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1198         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1199         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1200         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1201                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1202         ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
1203         mlx5_free(in);
1204         if (ret) {
1205                 DRV_LOG(ERR, "Failed to modify RQT using DevX.");
1206                 rte_errno = errno;
1207                 return -rte_errno;
1208         }
1209         return ret;
1210 }
1211
1212 /**
1213  * Create SQ using DevX API.
1214  *
1215  * @param[in] ctx
1216  *   Context returned from mlx5 open_device() glue function.
1217  * @param [in] sq_attr
1218  *   Pointer to SQ attributes structure.
1219  * @param [in] socket
1220  *   CPU socket ID for allocations.
1221  *
1222  * @return
1223  *   The DevX object created, NULL otherwise and rte_errno is set.
1224  **/
1225 struct mlx5_devx_obj *
1226 mlx5_devx_cmd_create_sq(void *ctx,
1227                         struct mlx5_devx_create_sq_attr *sq_attr)
1228 {
1229         uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
1230         uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
1231         void *sq_ctx;
1232         void *wq_ctx;
1233         struct mlx5_devx_wq_attr *wq_attr;
1234         struct mlx5_devx_obj *sq = NULL;
1235
1236         sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
1237         if (!sq) {
1238                 DRV_LOG(ERR, "Failed to allocate SQ data");
1239                 rte_errno = ENOMEM;
1240                 return NULL;
1241         }
1242         MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
1243         sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
1244         MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
1245         MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
1246         MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
1247         MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
1248         MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
1249                  sq_attr->flush_in_error_en);
1250         MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
1251                  sq_attr->min_wqe_inline_mode);
1252         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1253         MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
1254         MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
1255         MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
1256         MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
1257         MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
1258         MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
1259         MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
1260         MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
1261                  sq_attr->packet_pacing_rate_limit_index);
1262         MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
1263         MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
1264         wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
1265         wq_attr = &sq_attr->wq_attr;
1266         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1267         sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1268                                              out, sizeof(out));
1269         if (!sq->obj) {
1270                 DRV_LOG(ERR, "Failed to create SQ using DevX");
1271                 rte_errno = errno;
1272                 mlx5_free(sq);
1273                 return NULL;
1274         }
1275         sq->id = MLX5_GET(create_sq_out, out, sqn);
1276         return sq;
1277 }
1278
1279 /**
1280  * Modify SQ using DevX API.
1281  *
1282  * @param[in] sq
1283  *   Pointer to SQ object structure.
1284  * @param [in] sq_attr
1285  *   Pointer to SQ attributes structure.
1286  *
1287  * @return
1288  *   0 on success, a negative errno value otherwise and rte_errno is set.
1289  */
1290 int
1291 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
1292                         struct mlx5_devx_modify_sq_attr *sq_attr)
1293 {
1294         uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
1295         uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
1296         void *sq_ctx;
1297         int ret;
1298
1299         MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
1300         MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
1301         MLX5_SET(modify_sq_in, in, sqn, sq->id);
1302         sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1303         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1304         MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
1305         MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
1306         ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
1307                                          out, sizeof(out));
1308         if (ret) {
1309                 DRV_LOG(ERR, "Failed to modify SQ using DevX");
1310                 rte_errno = errno;
1311                 return -rte_errno;
1312         }
1313         return ret;
1314 }
1315
1316 /**
1317  * Create TIS using DevX API.
1318  *
1319  * @param[in] ctx
1320  *   Context returned from mlx5 open_device() glue function.
1321  * @param [in] tis_attr
1322  *   Pointer to TIS attributes structure.
1323  *
1324  * @return
1325  *   The DevX object created, NULL otherwise and rte_errno is set.
1326  */
1327 struct mlx5_devx_obj *
1328 mlx5_devx_cmd_create_tis(void *ctx,
1329                          struct mlx5_devx_tis_attr *tis_attr)
1330 {
1331         uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1332         uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
1333         struct mlx5_devx_obj *tis = NULL;
1334         void *tis_ctx;
1335
1336         tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
1337         if (!tis) {
1338                 DRV_LOG(ERR, "Failed to allocate TIS object");
1339                 rte_errno = ENOMEM;
1340                 return NULL;
1341         }
1342         MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
1343         tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
1344         MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1345                  tis_attr->strict_lag_tx_port_affinity);
1346         MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1347                  tis_attr->strict_lag_tx_port_affinity);
1348         MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
1349         MLX5_SET(tisc, tis_ctx, transport_domain,
1350                  tis_attr->transport_domain);
1351         tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1352                                               out, sizeof(out));
1353         if (!tis->obj) {
1354                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1355                 rte_errno = errno;
1356                 mlx5_free(tis);
1357                 return NULL;
1358         }
1359         tis->id = MLX5_GET(create_tis_out, out, tisn);
1360         return tis;
1361 }
1362
1363 /**
1364  * Create transport domain using DevX API.
1365  *
1366  * @param[in] ctx
1367  *   Context returned from mlx5 open_device() glue function.
1368  * @return
1369  *   The DevX object created, NULL otherwise and rte_errno is set.
1370  */
1371 struct mlx5_devx_obj *
1372 mlx5_devx_cmd_create_td(void *ctx)
1373 {
1374         uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1375         uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1376         struct mlx5_devx_obj *td = NULL;
1377
1378         td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
1379         if (!td) {
1380                 DRV_LOG(ERR, "Failed to allocate TD object");
1381                 rte_errno = ENOMEM;
1382                 return NULL;
1383         }
1384         MLX5_SET(alloc_transport_domain_in, in, opcode,
1385                  MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1386         td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1387                                              out, sizeof(out));
1388         if (!td->obj) {
1389                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1390                 rte_errno = errno;
1391                 mlx5_free(td);
1392                 return NULL;
1393         }
1394         td->id = MLX5_GET(alloc_transport_domain_out, out,
1395                            transport_domain);
1396         return td;
1397 }
1398
1399 /**
1400  * Dump all flows to file.
1401  *
1402  * @param[in] fdb_domain
1403  *   FDB domain.
1404  * @param[in] rx_domain
1405  *   RX domain.
1406  * @param[in] tx_domain
1407  *   TX domain.
1408  * @param[out] file
1409  *   Pointer to file stream.
1410  *
1411  * @return
1412  *   0 on success, a nagative value otherwise.
1413  */
1414 int
1415 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1416                         void *rx_domain __rte_unused,
1417                         void *tx_domain __rte_unused, FILE *file __rte_unused)
1418 {
1419         int ret = 0;
1420
1421 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1422         if (fdb_domain) {
1423                 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1424                 if (ret)
1425                         return ret;
1426         }
1427         MLX5_ASSERT(rx_domain);
1428         ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1429         if (ret)
1430                 return ret;
1431         MLX5_ASSERT(tx_domain);
1432         ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1433 #else
1434         ret = ENOTSUP;
1435 #endif
1436         return -ret;
1437 }
1438
1439 /*
1440  * Create CQ using DevX API.
1441  *
1442  * @param[in] ctx
1443  *   Context returned from mlx5 open_device() glue function.
1444  * @param [in] attr
1445  *   Pointer to CQ attributes structure.
1446  *
1447  * @return
1448  *   The DevX object created, NULL otherwise and rte_errno is set.
1449  */
1450 struct mlx5_devx_obj *
1451 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
1452 {
1453         uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
1454         uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
1455         struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1456                                                    sizeof(*cq_obj),
1457                                                    0, SOCKET_ID_ANY);
1458         void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1459
1460         if (!cq_obj) {
1461                 DRV_LOG(ERR, "Failed to allocate CQ object memory.");
1462                 rte_errno = ENOMEM;
1463                 return NULL;
1464         }
1465         MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
1466         if (attr->db_umem_valid) {
1467                 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
1468                 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
1469                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
1470         } else {
1471                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
1472         }
1473         MLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size);
1474         MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
1475         MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
1476         MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
1477         MLX5_SET(cqc, cqctx, log_page_size, attr->log_page_size -
1478                  MLX5_ADAPTER_PAGE_SHIFT);
1479         MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
1480         MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
1481         MLX5_SET(cqc, cqctx, cqe_comp_en, attr->cqe_comp_en);
1482         MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
1483         MLX5_SET(cqc, cqctx, cqe_sz, attr->cqe_size);
1484         if (attr->q_umem_valid) {
1485                 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
1486                 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
1487                 MLX5_SET64(create_cq_in, in, cq_umem_offset,
1488                            attr->q_umem_offset);
1489         }
1490         cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1491                                                  sizeof(out));
1492         if (!cq_obj->obj) {
1493                 rte_errno = errno;
1494                 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno);
1495                 mlx5_free(cq_obj);
1496                 return NULL;
1497         }
1498         cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
1499         return cq_obj;
1500 }
1501
1502 /**
1503  * Create VIRTQ using DevX API.
1504  *
1505  * @param[in] ctx
1506  *   Context returned from mlx5 open_device() glue function.
1507  * @param [in] attr
1508  *   Pointer to VIRTQ attributes structure.
1509  *
1510  * @return
1511  *   The DevX object created, NULL otherwise and rte_errno is set.
1512  */
1513 struct mlx5_devx_obj *
1514 mlx5_devx_cmd_create_virtq(void *ctx,
1515                            struct mlx5_devx_virtq_attr *attr)
1516 {
1517         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1518         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1519         struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1520                                                      sizeof(*virtq_obj),
1521                                                      0, SOCKET_ID_ANY);
1522         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1523         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1524         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1525
1526         if (!virtq_obj) {
1527                 DRV_LOG(ERR, "Failed to allocate virtq data.");
1528                 rte_errno = ENOMEM;
1529                 return NULL;
1530         }
1531         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1532                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1533         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1534                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1535         MLX5_SET16(virtio_net_q, virtq, hw_available_index,
1536                    attr->hw_available_index);
1537         MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
1538         MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
1539         MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
1540         MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
1541         MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
1542         MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
1543                    attr->virtio_version_1_0);
1544         MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
1545         MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
1546         MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
1547         MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
1548         MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
1549         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1550         MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
1551         MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
1552         MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
1553         MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
1554         MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
1555         MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
1556         MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
1557         MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
1558         MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
1559         MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
1560         MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
1561         MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
1562         MLX5_SET(virtio_q, virtctx, pd, attr->pd);
1563         MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
1564         virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1565                                                     sizeof(out));
1566         if (!virtq_obj->obj) {
1567                 rte_errno = errno;
1568                 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX.");
1569                 mlx5_free(virtq_obj);
1570                 return NULL;
1571         }
1572         virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1573         return virtq_obj;
1574 }
1575
1576 /**
1577  * Modify VIRTQ using DevX API.
1578  *
1579  * @param[in] virtq_obj
1580  *   Pointer to virtq object structure.
1581  * @param [in] attr
1582  *   Pointer to modify virtq attributes structure.
1583  *
1584  * @return
1585  *   0 on success, a negative errno value otherwise and rte_errno is set.
1586  */
1587 int
1588 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
1589                            struct mlx5_devx_virtq_attr *attr)
1590 {
1591         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1592         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1593         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1594         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1595         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1596         int ret;
1597
1598         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1599                  MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
1600         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1601                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1602         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1603         MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);
1604         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1605         switch (attr->type) {
1606         case MLX5_VIRTQ_MODIFY_TYPE_STATE:
1607                 MLX5_SET16(virtio_net_q, virtq, state, attr->state);
1608                 break;
1609         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:
1610                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
1611                          attr->dirty_bitmap_mkey);
1612                 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
1613                          attr->dirty_bitmap_addr);
1614                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
1615                          attr->dirty_bitmap_size);
1616                 break;
1617         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:
1618                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
1619                          attr->dirty_bitmap_dump_enable);
1620                 break;
1621         default:
1622                 rte_errno = EINVAL;
1623                 return -rte_errno;
1624         }
1625         ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
1626                                          out, sizeof(out));
1627         if (ret) {
1628                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1629                 rte_errno = errno;
1630                 return -rte_errno;
1631         }
1632         return ret;
1633 }
1634
1635 /**
1636  * Query VIRTQ using DevX API.
1637  *
1638  * @param[in] virtq_obj
1639  *   Pointer to virtq object structure.
1640  * @param [in/out] attr
1641  *   Pointer to virtq attributes structure.
1642  *
1643  * @return
1644  *   0 on success, a negative errno value otherwise and rte_errno is set.
1645  */
1646 int
1647 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
1648                            struct mlx5_devx_virtq_attr *attr)
1649 {
1650         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
1651         uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
1652         void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
1653         void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
1654         int ret;
1655
1656         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1657                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
1658         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1659                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1660         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1661         ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
1662                                          out, sizeof(out));
1663         if (ret) {
1664                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1665                 rte_errno = errno;
1666                 return -errno;
1667         }
1668         attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
1669                                               hw_available_index);
1670         attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
1671         return ret;
1672 }
1673
1674 /**
1675  * Create QP using DevX API.
1676  *
1677  * @param[in] ctx
1678  *   Context returned from mlx5 open_device() glue function.
1679  * @param [in] attr
1680  *   Pointer to QP attributes structure.
1681  *
1682  * @return
1683  *   The DevX object created, NULL otherwise and rte_errno is set.
1684  */
1685 struct mlx5_devx_obj *
1686 mlx5_devx_cmd_create_qp(void *ctx,
1687                         struct mlx5_devx_qp_attr *attr)
1688 {
1689         uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
1690         uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
1691         struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
1692                                                    sizeof(*qp_obj),
1693                                                    0, SOCKET_ID_ANY);
1694         void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1695
1696         if (!qp_obj) {
1697                 DRV_LOG(ERR, "Failed to allocate QP data.");
1698                 rte_errno = ENOMEM;
1699                 return NULL;
1700         }
1701         MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
1702         MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
1703         MLX5_SET(qpc, qpc, pd, attr->pd);
1704         if (attr->uar_index) {
1705                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1706                 MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
1707                 MLX5_SET(qpc, qpc, log_page_size, attr->log_page_size -
1708                          MLX5_ADAPTER_PAGE_SHIFT);
1709                 if (attr->sq_size) {
1710                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));
1711                         MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
1712                         MLX5_SET(qpc, qpc, log_sq_size,
1713                                  rte_log2_u32(attr->sq_size));
1714                 } else {
1715                         MLX5_SET(qpc, qpc, no_sq, 1);
1716                 }
1717                 if (attr->rq_size) {
1718                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size));
1719                         MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
1720                         MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
1721                                  MLX5_LOG_RQ_STRIDE_SHIFT);
1722                         MLX5_SET(qpc, qpc, log_rq_size,
1723                                  rte_log2_u32(attr->rq_size));
1724                         MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
1725                 } else {
1726                         MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1727                 }
1728                 if (attr->dbr_umem_valid) {
1729                         MLX5_SET(qpc, qpc, dbr_umem_valid,
1730                                  attr->dbr_umem_valid);
1731                         MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
1732                 }
1733                 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
1734                 MLX5_SET64(create_qp_in, in, wq_umem_offset,
1735                            attr->wq_umem_offset);
1736                 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
1737                 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
1738         } else {
1739                 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
1740                 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1741                 MLX5_SET(qpc, qpc, no_sq, 1);
1742         }
1743         qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1744                                                  sizeof(out));
1745         if (!qp_obj->obj) {
1746                 rte_errno = errno;
1747                 DRV_LOG(ERR, "Failed to create QP Obj using DevX.");
1748                 mlx5_free(qp_obj);
1749                 return NULL;
1750         }
1751         qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
1752         return qp_obj;
1753 }
1754
1755 /**
1756  * Modify QP using DevX API.
1757  * Currently supports only force loop-back QP.
1758  *
1759  * @param[in] qp
1760  *   Pointer to QP object structure.
1761  * @param [in] qp_st_mod_op
1762  *   The QP state modification operation.
1763  * @param [in] remote_qp_id
1764  *   The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
1765  *
1766  * @return
1767  *   0 on success, a negative errno value otherwise and rte_errno is set.
1768  */
1769 int
1770 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
1771                               uint32_t remote_qp_id)
1772 {
1773         union {
1774                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
1775                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
1776                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
1777         } in;
1778         union {
1779                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
1780                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
1781                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
1782         } out;
1783         void *qpc;
1784         int ret;
1785         unsigned int inlen;
1786         unsigned int outlen;
1787
1788         memset(&in, 0, sizeof(in));
1789         memset(&out, 0, sizeof(out));
1790         MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
1791         switch (qp_st_mod_op) {
1792         case MLX5_CMD_OP_RST2INIT_QP:
1793                 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
1794                 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
1795                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
1796                 MLX5_SET(qpc, qpc, rre, 1);
1797                 MLX5_SET(qpc, qpc, rwe, 1);
1798                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1799                 inlen = sizeof(in.rst2init);
1800                 outlen = sizeof(out.rst2init);
1801                 break;
1802         case MLX5_CMD_OP_INIT2RTR_QP:
1803                 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
1804                 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
1805                 MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
1806                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
1807                 MLX5_SET(qpc, qpc, mtu, 1);
1808                 MLX5_SET(qpc, qpc, log_msg_max, 30);
1809                 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
1810                 MLX5_SET(qpc, qpc, min_rnr_nak, 0);
1811                 inlen = sizeof(in.init2rtr);
1812                 outlen = sizeof(out.init2rtr);
1813                 break;
1814         case MLX5_CMD_OP_RTR2RTS_QP:
1815                 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
1816                 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
1817                 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14);
1818                 MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
1819                 MLX5_SET(qpc, qpc, retry_count, 7);
1820                 MLX5_SET(qpc, qpc, rnr_retry, 7);
1821                 inlen = sizeof(in.rtr2rts);
1822                 outlen = sizeof(out.rtr2rts);
1823                 break;
1824         default:
1825                 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
1826                         qp_st_mod_op);
1827                 rte_errno = EINVAL;
1828                 return -rte_errno;
1829         }
1830         ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
1831         if (ret) {
1832                 DRV_LOG(ERR, "Failed to modify QP using DevX.");
1833                 rte_errno = errno;
1834                 return -rte_errno;
1835         }
1836         return ret;
1837 }
1838
1839 struct mlx5_devx_obj *
1840 mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
1841 {
1842         uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
1843         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1844         struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
1845                                                        sizeof(*couners_obj), 0,
1846                                                        SOCKET_ID_ANY);
1847         void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
1848
1849         if (!couners_obj) {
1850                 DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
1851                 rte_errno = ENOMEM;
1852                 return NULL;
1853         }
1854         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1855                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1856         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1857                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
1858         couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1859                                                       sizeof(out));
1860         if (!couners_obj->obj) {
1861                 rte_errno = errno;
1862                 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using"
1863                         " DevX.");
1864                 mlx5_free(couners_obj);
1865                 return NULL;
1866         }
1867         couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1868         return couners_obj;
1869 }
1870
1871 int
1872 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
1873                                    struct mlx5_devx_virtio_q_couners_attr *attr)
1874 {
1875         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
1876         uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
1877         void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
1878         void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
1879                                                virtio_q_counters);
1880         int ret;
1881
1882         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1883                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
1884         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1885                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
1886         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
1887         ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
1888                                         sizeof(out));
1889         if (ret) {
1890                 DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
1891                 rte_errno = errno;
1892                 return -errno;
1893         }
1894         attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
1895                                          received_desc);
1896         attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
1897                                           completed_desc);
1898         attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
1899                                     error_cqes);
1900         attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
1901                                          bad_desc_errors);
1902         attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
1903                                           exceed_max_chain);
1904         attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
1905                                         invalid_buffer);
1906         return ret;
1907 }