drivers/common/mlx5/mlx5_devx_cmds.c

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /* Copyright 2018 Mellanox Technologies, Ltd */
   3
   4 #include <unistd.h>
   5
   6 #include <rte_errno.h>
   7 #include <rte_malloc.h>
   8 #include <rte_eal_paging.h>
   9
  10 #include "mlx5_prm.h"
  11 #include "mlx5_devx_cmds.h"
  12 #include "mlx5_common_utils.h"
  13 #include "mlx5_malloc.h"
  14
  15
  16 /**
  17  * Perform read access to the registers. Reads data from register
  18  * and writes ones to the specified buffer.
  19  *
  20  * @param[in] ctx
  21  *   Context returned from mlx5 open_device() glue function.
  22  * @param[in] reg_id
  23  *   Register identifier according to the PRM.
  24  * @param[in] arg
  25  *   Register access auxiliary parameter according to the PRM.
  26  * @param[out] data
  27  *   Pointer to the buffer to store read data.
  28  * @param[in] dw_cnt
  29  *   Buffer size in double words.
  30  *
  31  * @return
  32  *   0 on success, a negative value otherwise.
  33  */
  34 int
  35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
  36                             uint32_t *data, uint32_t dw_cnt)
  37 {
  38         uint32_t in[MLX5_ST_SZ_DW(access_register_in)]   = {0};
  39         uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
  40                      MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
  41         int status, rc;
  42
  43         MLX5_ASSERT(data && dw_cnt);
  44         MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
  45         if (dw_cnt  > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
  46                 DRV_LOG(ERR, "Not enough  buffer for register read data");
  47                 return -1;
  48         }
  49         MLX5_SET(access_register_in, in, opcode,
  50                  MLX5_CMD_OP_ACCESS_REGISTER_USER);
  51         MLX5_SET(access_register_in, in, op_mod,
  52                                         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
  53         MLX5_SET(access_register_in, in, register_id, reg_id);
  54         MLX5_SET(access_register_in, in, argument, arg);
  55         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
  56                                          MLX5_ST_SZ_BYTES(access_register_out) +
  57                                          sizeof(uint32_t) * dw_cnt);
  58         if (rc)
  59                 goto error;
  60         status = MLX5_GET(access_register_out, out, status);
  61         if (status) {
  62                 int syndrome = MLX5_GET(access_register_out, out, syndrome);
  63
  64                 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, "
  65                                "status %x, syndrome = %x",
  66                                reg_id, status, syndrome);
  67                 return -1;
  68         }
  69         memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
  70                dw_cnt * sizeof(uint32_t));
  71         return 0;
  72 error:
  73         rc = (rc > 0) ? -rc : rc;
  74         return rc;
  75 }
  76
  77 /**
  78  * Allocate flow counters via devx interface.
  79  *
  80  * @param[in] ctx
  81  *   Context returned from mlx5 open_device() glue function.
  82  * @param dcs
  83  *   Pointer to counters properties structure to be filled by the routine.
  84  * @param bulk_n_128
  85  *   Bulk counter numbers in 128 counters units.
  86  *
  87  * @return
  88  *   Pointer to counter object on success, a negative value otherwise and
  89  *   rte_errno is set.
  90  */
  91 struct mlx5_devx_obj *
  92 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
  93 {
  94         struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
  95                                                 0, SOCKET_ID_ANY);
  96         uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)]   = {0};
  97         uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
  98
  99         if (!dcs) {
 100                 rte_errno = ENOMEM;
 101                 return NULL;
 102         }
 103         MLX5_SET(alloc_flow_counter_in, in, opcode,
 104                  MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
 105         MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
 106         dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
 107                                               sizeof(in), out, sizeof(out));
 108         if (!dcs->obj) {
 109                 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
 110                 rte_errno = errno;
 111                 mlx5_free(dcs);
 112                 return NULL;
 113         }
 114         dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
 115         return dcs;
 116 }
 117
 118 /**
 119  * Query flow counters values.
 120  *
 121  * @param[in] dcs
 122  *   devx object that was obtained from mlx5_devx_cmd_fc_alloc.
 123  * @param[in] clear
 124  *   Whether hardware should clear the counters after the query or not.
 125  * @param[in] n_counters
 126  *   0 in case of 1 counter to read, otherwise the counter number to read.
 127  *  @param pkts
 128  *   The number of packets that matched the flow.
 129  *  @param bytes
 130  *    The number of bytes that matched the flow.
 131  *  @param mkey
 132  *   The mkey key for batch query.
 133  *  @param addr
 134  *    The address in the mkey range for batch query.
 135  *  @param cmd_comp
 136  *   The completion object for asynchronous batch query.
 137  *  @param async_id
 138  *    The ID to be returned in the asynchronous batch query response.
 139  *
 140  * @return
 141  *   0 on success, a negative value otherwise.
 142  */
 143 int
 144 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
 145                                  int clear, uint32_t n_counters,
 146                                  uint64_t *pkts, uint64_t *bytes,
 147                                  uint32_t mkey, void *addr,
 148                                  void *cmd_comp,
 149                                  uint64_t async_id)
 150 {
 151         int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
 152                         MLX5_ST_SZ_BYTES(traffic_counter);
 153         uint32_t out[out_len];
 154         uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
 155         void *stats;
 156         int rc;
 157
 158         MLX5_SET(query_flow_counter_in, in, opcode,
 159                  MLX5_CMD_OP_QUERY_FLOW_COUNTER);
 160         MLX5_SET(query_flow_counter_in, in, op_mod, 0);
 161         MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
 162         MLX5_SET(query_flow_counter_in, in, clear, !!clear);
 163
 164         if (n_counters) {
 165                 MLX5_SET(query_flow_counter_in, in, num_of_counters,
 166                          n_counters);
 167                 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
 168                 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
 169                 MLX5_SET64(query_flow_counter_in, in, address,
 170                            (uint64_t)(uintptr_t)addr);
 171         }
 172         if (!cmd_comp)
 173                 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
 174                                                out_len);
 175         else
 176                 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
 177                                                      out_len, async_id,
 178                                                      cmd_comp);
 179         if (rc) {
 180                 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
 181                 rte_errno = rc;
 182                 return -rc;
 183         }
 184         if (!n_counters) {
 185                 stats = MLX5_ADDR_OF(query_flow_counter_out,
 186                                      out, flow_statistics);
 187                 *pkts = MLX5_GET64(traffic_counter, stats, packets);
 188                 *bytes = MLX5_GET64(traffic_counter, stats, octets);
 189         }
 190         return 0;
 191 }
 192
 193 /**
 194  * Create a new mkey.
 195  *
 196  * @param[in] ctx
 197  *   Context returned from mlx5 open_device() glue function.
 198  * @param[in] attr
 199  *   Attributes of the requested mkey.
 200  *
 201  * @return
 202  *   Pointer to Devx mkey on success, a negative value otherwise and rte_errno
 203  *   is set.
 204  */
 205 struct mlx5_devx_obj *
 206 mlx5_devx_cmd_mkey_create(void *ctx,
 207                           struct mlx5_devx_mkey_attr *attr)
 208 {
 209         struct mlx5_klm *klm_array = attr->klm_array;
 210         int klm_num = attr->klm_num;
 211         int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
 212                      (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
 213         uint32_t in[in_size_dw];
 214         uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
 215         void *mkc;
 216         struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
 217                                                  0, SOCKET_ID_ANY);
 218         size_t pgsize;
 219         uint32_t translation_size;
 220
 221         if (!mkey) {
 222                 rte_errno = ENOMEM;
 223                 return NULL;
 224         }
 225         memset(in, 0, in_size_dw * 4);
 226         pgsize = rte_mem_page_size();
 227         if (pgsize == (size_t)-1) {
 228                 mlx5_free(mkey);
 229                 DRV_LOG(ERR, "Failed to get page size");
 230                 rte_errno = ENOMEM;
 231                 return NULL;
 232         }
 233         MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
 234         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 235         if (klm_num > 0) {
 236                 int i;
 237                 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
 238                                                        klm_pas_mtt);
 239                 translation_size = RTE_ALIGN(klm_num, 4);
 240                 for (i = 0; i < klm_num; i++) {
 241                         MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
 242                         MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
 243                         MLX5_SET64(klm, klm, address, klm_array[i].address);
 244                         klm += MLX5_ST_SZ_BYTES(klm);
 245                 }
 246                 for (; i < (int)translation_size; i++) {
 247                         MLX5_SET(klm, klm, mkey, 0x0);
 248                         MLX5_SET64(klm, klm, address, 0x0);
 249                         klm += MLX5_ST_SZ_BYTES(klm);
 250                 }
 251                 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
 252                          MLX5_MKC_ACCESS_MODE_KLM_FBS :
 253                          MLX5_MKC_ACCESS_MODE_KLM);
 254                 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
 255         } else {
 256                 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
 257                 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 258                 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
 259         }
 260         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 261                  translation_size);
 262         MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
 263         MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
 264         MLX5_SET(mkc, mkc, lw, 0x1);
 265         MLX5_SET(mkc, mkc, lr, 0x1);
 266         if (attr->set_remote_rw) {
 267                 MLX5_SET(mkc, mkc, rw, 0x1);
 268                 MLX5_SET(mkc, mkc, rr, 0x1);
 269         }
 270         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 271         MLX5_SET(mkc, mkc, pd, attr->pd);
 272         MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
 273         MLX5_SET(mkc, mkc, umr_en, attr->umr_en);
 274         MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
 275         MLX5_SET(mkc, mkc, relaxed_ordering_write,
 276                  attr->relaxed_ordering_write);
 277         MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read);
 278         MLX5_SET64(mkc, mkc, start_addr, attr->addr);
 279         MLX5_SET64(mkc, mkc, len, attr->size);
 280         MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en);
 281         if (attr->crypto_en) {
 282                 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en);
 283                 MLX5_SET(mkc, mkc, bsf_octword_size, 4);
 284         }
 285         mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
 286                                                sizeof(out));
 287         if (!mkey->obj) {
 288                 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d",
 289                         klm_num ? "an in" : "a ", errno);
 290                 rte_errno = errno;
 291                 mlx5_free(mkey);
 292                 return NULL;
 293         }
 294         mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
 295         mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
 296         return mkey;
 297 }
 298
 299 /**
 300  * Get status of devx command response.
 301  * Mainly used for asynchronous commands.
 302  *
 303  * @param[in] out
 304  *   The out response buffer.
 305  *
 306  * @return
 307  *   0 on success, non-zero value otherwise.
 308  */
 309 int
 310 mlx5_devx_get_out_command_status(void *out)
 311 {
 312         int status;
 313
 314         if (!out)
 315                 return -EINVAL;
 316         status = MLX5_GET(query_flow_counter_out, out, status);
 317         if (status) {
 318                 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
 319
 320                 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status,
 321                         syndrome);
 322         }
 323         return status;
 324 }
 325
 326 /**
 327  * Destroy any object allocated by a Devx API.
 328  *
 329  * @param[in] obj
 330  *   Pointer to a general object.
 331  *
 332  * @return
 333  *   0 on success, a negative value otherwise.
 334  */
 335 int
 336 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
 337 {
 338         int ret;
 339
 340         if (!obj)
 341                 return 0;
 342         ret =  mlx5_glue->devx_obj_destroy(obj->obj);
 343         mlx5_free(obj);
 344         return ret;
 345 }
 346
 347 /**
 348  * Query NIC vport context.
 349  * Fills minimal inline attribute.
 350  *
 351  * @param[in] ctx
 352  *   ibv contexts returned from mlx5dv_open_device.
 353  * @param[in] vport
 354  *   vport index
 355  * @param[out] attr
 356  *   Attributes device values.
 357  *
 358  * @return
 359  *   0 on success, a negative value otherwise.
 360  */
 361 static int
 362 mlx5_devx_cmd_query_nic_vport_context(void *ctx,
 363                                       unsigned int vport,
 364                                       struct mlx5_hca_attr *attr)
 365 {
 366         uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
 367         uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
 368         void *vctx;
 369         int status, syndrome, rc;
 370
 371         /* Query NIC vport context to determine inline mode. */
 372         MLX5_SET(query_nic_vport_context_in, in, opcode,
 373                  MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
 374         MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
 375         if (vport)
 376                 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
 377         rc = mlx5_glue->devx_general_cmd(ctx,
 378                                          in, sizeof(in),
 379                                          out, sizeof(out));
 380         if (rc)
 381                 goto error;
 382         status = MLX5_GET(query_nic_vport_context_out, out, status);
 383         syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
 384         if (status) {
 385                 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
 386                         "status %x, syndrome = %x", status, syndrome);
 387                 return -1;
 388         }
 389         vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
 390                             nic_vport_context);
 391         attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
 392                                            min_wqe_inline_mode);
 393         return 0;
 394 error:
 395         rc = (rc > 0) ? -rc : rc;
 396         return rc;
 397 }
 398
 399 /**
 400  * Query NIC vDPA attributes.
 401  *
 402  * @param[in] ctx
 403  *   Context returned from mlx5 open_device() glue function.
 404  * @param[out] vdpa_attr
 405  *   vDPA Attributes structure to fill.
 406  */
 407 static void
 408 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
 409                                   struct mlx5_hca_vdpa_attr *vdpa_attr)
 410 {
 411         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 412         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 413         void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 414         int status, syndrome, rc;
 415
 416         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 417         MLX5_SET(query_hca_cap_in, in, op_mod,
 418                  MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
 419                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 420         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 421         status = MLX5_GET(query_hca_cap_out, out, status);
 422         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 423         if (rc || status) {
 424                 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities,"
 425                         " status %x, syndrome = %x", status, syndrome);
 426                 vdpa_attr->valid = 0;
 427         } else {
 428                 vdpa_attr->valid = 1;
 429                 vdpa_attr->desc_tunnel_offload_type =
 430                         MLX5_GET(virtio_emulation_cap, hcattr,
 431                                  desc_tunnel_offload_type);
 432                 vdpa_attr->eth_frame_offload_type =
 433                         MLX5_GET(virtio_emulation_cap, hcattr,
 434                                  eth_frame_offload_type);
 435                 vdpa_attr->virtio_version_1_0 =
 436                         MLX5_GET(virtio_emulation_cap, hcattr,
 437                                  virtio_version_1_0);
 438                 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
 439                                                tso_ipv4);
 440                 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
 441                                                tso_ipv6);
 442                 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 443                                               tx_csum);
 444                 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 445                                               rx_csum);
 446                 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
 447                                                  event_mode);
 448                 vdpa_attr->virtio_queue_type =
 449                         MLX5_GET(virtio_emulation_cap, hcattr,
 450                                  virtio_queue_type);
 451                 vdpa_attr->log_doorbell_stride =
 452                         MLX5_GET(virtio_emulation_cap, hcattr,
 453                                  log_doorbell_stride);
 454                 vdpa_attr->log_doorbell_bar_size =
 455                         MLX5_GET(virtio_emulation_cap, hcattr,
 456                                  log_doorbell_bar_size);
 457                 vdpa_attr->doorbell_bar_offset =
 458                         MLX5_GET64(virtio_emulation_cap, hcattr,
 459                                    doorbell_bar_offset);
 460                 vdpa_attr->max_num_virtio_queues =
 461                         MLX5_GET(virtio_emulation_cap, hcattr,
 462                                  max_num_virtio_queues);
 463                 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
 464                                                  umem_1_buffer_param_a);
 465                 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
 466                                                  umem_1_buffer_param_b);
 467                 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
 468                                                  umem_2_buffer_param_a);
 469                 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
 470                                                  umem_2_buffer_param_b);
 471                 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
 472                                                  umem_3_buffer_param_a);
 473                 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
 474                                                  umem_3_buffer_param_b);
 475         }
 476 }
 477
 478 int
 479 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
 480                                   uint32_t ids[], uint32_t num)
 481 {
 482         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
 483         uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
 484         void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
 485         void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
 486         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 487         int ret;
 488         uint32_t idx = 0;
 489         uint32_t i;
 490
 491         if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
 492                 rte_errno = EINVAL;
 493                 DRV_LOG(ERR, "Too many sample IDs to be fetched.");
 494                 return -rte_errno;
 495         }
 496         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 497                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
 498         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 499                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 500         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
 501         ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
 502                                         out, sizeof(out));
 503         if (ret) {
 504                 rte_errno = ret;
 505                 DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
 506                         (void *)flex_obj);
 507                 return -rte_errno;
 508         }
 509         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 510                 void *s_off = (void *)((char *)sample + i *
 511                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 512                 uint32_t en;
 513
 514                 en = MLX5_GET(parse_graph_flow_match_sample, s_off,
 515                               flow_match_sample_en);
 516                 if (!en)
 517                         continue;
 518                 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
 519                                   flow_match_sample_field_id);
 520         }
 521         if (num != idx) {
 522                 rte_errno = EINVAL;
 523                 DRV_LOG(ERR, "Number of sample IDs are not as expected.");
 524                 return -rte_errno;
 525         }
 526         return ret;
 527 }
 528
 529
 530 struct mlx5_devx_obj *
 531 mlx5_devx_cmd_create_flex_parser(void *ctx,
 532                               struct mlx5_devx_graph_node_attr *data)
 533 {
 534         uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
 535         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
 536         void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
 537         void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
 538         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 539         void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
 540         void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
 541         struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc
 542                      (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY);
 543         uint32_t i;
 544
 545         if (!parse_flex_obj) {
 546                 DRV_LOG(ERR, "Failed to allocate flex parser data.");
 547                 rte_errno = ENOMEM;
 548                 return NULL;
 549         }
 550         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 551                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
 552         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 553                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 554         MLX5_SET(parse_graph_flex, flex, header_length_mode,
 555                  data->header_length_mode);
 556         MLX5_SET(parse_graph_flex, flex, header_length_base_value,
 557                  data->header_length_base_value);
 558         MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
 559                  data->header_length_field_offset);
 560         MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
 561                  data->header_length_field_shift);
 562         MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
 563                  data->header_length_field_mask);
 564         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 565                 struct mlx5_devx_match_sample_attr *s = &data->sample[i];
 566                 void *s_off = (void *)((char *)sample + i *
 567                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 568
 569                 if (!s->flow_match_sample_en)
 570                         continue;
 571                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 572                          flow_match_sample_en, !!s->flow_match_sample_en);
 573                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 574                          flow_match_sample_field_offset,
 575                          s->flow_match_sample_field_offset);
 576                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 577                          flow_match_sample_offset_mode,
 578                          s->flow_match_sample_offset_mode);
 579                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 580                          flow_match_sample_field_offset_mask,
 581                          s->flow_match_sample_field_offset_mask);
 582                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 583                          flow_match_sample_field_offset_shift,
 584                          s->flow_match_sample_field_offset_shift);
 585                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 586                          flow_match_sample_field_base_offset,
 587                          s->flow_match_sample_field_base_offset);
 588                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 589                          flow_match_sample_tunnel_mode,
 590                          s->flow_match_sample_tunnel_mode);
 591         }
 592         for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
 593                 struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
 594                 struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
 595                 void *in_off = (void *)((char *)in_arc + i *
 596                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 597                 void *out_off = (void *)((char *)out_arc + i *
 598                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 599
 600                 if (ia->arc_parse_graph_node != 0) {
 601                         MLX5_SET(parse_graph_arc, in_off,
 602                                  compare_condition_value,
 603                                  ia->compare_condition_value);
 604                         MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
 605                                  ia->start_inner_tunnel);
 606                         MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
 607                                  ia->arc_parse_graph_node);
 608                         MLX5_SET(parse_graph_arc, in_off,
 609                                  parse_graph_node_handle,
 610                                  ia->parse_graph_node_handle);
 611                 }
 612                 if (oa->arc_parse_graph_node != 0) {
 613                         MLX5_SET(parse_graph_arc, out_off,
 614                                  compare_condition_value,
 615                                  oa->compare_condition_value);
 616                         MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
 617                                  oa->start_inner_tunnel);
 618                         MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
 619                                  oa->arc_parse_graph_node);
 620                         MLX5_SET(parse_graph_arc, out_off,
 621                                  parse_graph_node_handle,
 622                                  oa->parse_graph_node_handle);
 623                 }
 624         }
 625         parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 626                                                          out, sizeof(out));
 627         if (!parse_flex_obj->obj) {
 628                 rte_errno = errno;
 629                 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object "
 630                         "by using DevX.");
 631                 mlx5_free(parse_flex_obj);
 632                 return NULL;
 633         }
 634         parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
 635         return parse_flex_obj;
 636 }
 637
 638 /**
 639  * Query HCA attributes.
 640  * Using those attributes we can check on run time if the device
 641  * is having the required capabilities.
 642  *
 643  * @param[in] ctx
 644  *   Context returned from mlx5 open_device() glue function.
 645  * @param[out] attr
 646  *   Attributes device values.
 647  *
 648  * @return
 649  *   0 on success, a negative value otherwise.
 650  */
 651 int
 652 mlx5_devx_cmd_query_hca_attr(void *ctx,
 653                              struct mlx5_hca_attr *attr)
 654 {
 655         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 656         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 657         void *hcattr;
 658         int status, syndrome, rc, i;
 659         uint64_t general_obj_types_supported = 0;
 660
 661         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 662         MLX5_SET(query_hca_cap_in, in, op_mod,
 663                  MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
 664                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 665
 666         rc = mlx5_glue->devx_general_cmd(ctx,
 667                                          in, sizeof(in), out, sizeof(out));
 668         if (rc)
 669                 goto error;
 670         status = MLX5_GET(query_hca_cap_out, out, status);
 671         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 672         if (status) {
 673                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 674                         "status %x, syndrome = %x", status, syndrome);
 675                 return -1;
 676         }
 677         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 678         attr->flow_counter_bulk_alloc_bitmap =
 679                         MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
 680         attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
 681                                             flow_counters_dump);
 682         attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
 683                                           log_max_rqt_size);
 684         attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
 685         attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
 686         attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
 687                                                 log_max_hairpin_queues);
 688         attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
 689                                                     log_max_hairpin_wq_data_sz);
 690         attr->log_max_hairpin_num_packets = MLX5_GET
 691                 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
 692         attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
 693         attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
 694                                                 relaxed_ordering_write);
 695         attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
 696                                                relaxed_ordering_read);
 697         attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
 698                                               access_register_user);
 699         attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
 700                                           eth_net_offloads);
 701         attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
 702         attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
 703                                                flex_parser_protocols);
 704         attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr,
 705                         max_geneve_tlv_options);
 706         attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,
 707                         max_geneve_tlv_option_data_len);
 708         attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
 709         attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 710                                          general_obj_types) &
 711                               MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO);
 712         attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 713                                          general_obj_types) &
 714                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 715         attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 716                                                         general_obj_types) &
 717                                   MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
 718         attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 719                                          general_obj_types) &
 720                               MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
 721         attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
 722                                           wqe_index_ignore_cap);
 723         attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
 724         attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
 725         attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
 726                                               log_max_static_sq_wq);
 727         attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);
 728         attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
 729                                       device_frequency_khz);
 730         attr->scatter_fcs_w_decap_disable =
 731                 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
 732         attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce);
 733         attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format);
 734         attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);
 735         attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp);
 736         attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
 737                                                regexp_num_of_engines);
 738         /* Read the general_obj_types bitmap and extract the relevant bits. */
 739         general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr,
 740                                                  general_obj_types);
 741         attr->vdpa.valid = !!(general_obj_types_supported &
 742                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 743         attr->vdpa.queue_counters_valid =
 744                         !!(general_obj_types_supported &
 745                            MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
 746         attr->parse_graph_flex_node =
 747                         !!(general_obj_types_supported &
 748                            MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
 749         attr->flow_hit_aso = !!(general_obj_types_supported &
 750                                 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
 751         attr->geneve_tlv_opt = !!(general_obj_types_supported &
 752                                   MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);
 753         attr->dek = !!(general_obj_types_supported &
 754                        MLX5_GENERAL_OBJ_TYPES_CAP_DEK);
 755         /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */
 756         attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);
 757         attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);
 758         attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);
 759         attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);
 760         attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);
 761         attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
 762         attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
 763         attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
 764         attr->reg_c_preserve =
 765                 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);
 766         attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo);
 767         attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress);
 768         attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress);
 769         attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
 770                                                  compress_min_block_size);
 771         attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
 772         attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
 773                                               log_compress_mmo_size);
 774         attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
 775                                                 log_decompress_mmo_size);
 776         attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
 777         attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
 778                                                 mini_cqe_resp_flow_tag);
 779         attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
 780                                                  mini_cqe_resp_l3_l4_tag);
 781         attr->umr_indirect_mkey_disabled =
 782                 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
 783         attr->umr_modify_entity_size_disabled =
 784                 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);
 785         attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto);
 786         if (attr->crypto)
 787                 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts);
 788         if (attr->qos.sup) {
 789                 MLX5_SET(query_hca_cap_in, in, op_mod,
 790                          MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
 791                          MLX5_HCA_CAP_OPMOD_GET_CUR);
 792                 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
 793                                                  out, sizeof(out));
 794                 if (rc)
 795                         goto error;
 796                 if (status) {
 797                         DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
 798                                 " status %x, syndrome = %x", status, syndrome);
 799                         return -1;
 800                 }
 801                 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 802                 attr->qos.flow_meter_old =
 803                                 MLX5_GET(qos_cap, hcattr, flow_meter_old);
 804                 attr->qos.log_max_flow_meter =
 805                                 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
 806                 attr->qos.flow_meter_reg_c_ids =
 807                                 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
 808                 attr->qos.flow_meter =
 809                                 MLX5_GET(qos_cap, hcattr, flow_meter);
 810                 attr->qos.packet_pacing =
 811                                 MLX5_GET(qos_cap, hcattr, packet_pacing);
 812                 attr->qos.wqe_rate_pp =
 813                                 MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
 814                 if (attr->qos.flow_meter_aso_sup) {
 815                         attr->qos.log_meter_aso_granularity =
 816                                 MLX5_GET(qos_cap, hcattr,
 817                                         log_meter_aso_granularity);
 818                         attr->qos.log_meter_aso_max_alloc =
 819                                 MLX5_GET(qos_cap, hcattr,
 820                                         log_meter_aso_max_alloc);
 821                         attr->qos.log_max_num_meter_aso =
 822                                 MLX5_GET(qos_cap, hcattr,
 823                                         log_max_num_meter_aso);
 824                 }
 825         }
 826         if (attr->vdpa.valid)
 827                 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
 828         if (!attr->eth_net_offloads)
 829                 return 0;
 830
 831         /* Query Flow Sampler Capability From FLow Table Properties Layout. */
 832         memset(in, 0, sizeof(in));
 833         memset(out, 0, sizeof(out));
 834         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 835         MLX5_SET(query_hca_cap_in, in, op_mod,
 836                  MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
 837                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 838
 839         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 840         if (rc)
 841                 goto error;
 842         status = MLX5_GET(query_hca_cap_out, out, status);
 843         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 844         if (status) {
 845                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 846                         "status %x, syndrome = %x", status, syndrome);
 847                 attr->log_max_ft_sampler_num = 0;
 848                 return -1;
 849         }
 850         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 851         attr->log_max_ft_sampler_num =
 852                         MLX5_GET(flow_table_nic_cap,
 853                         hcattr, flow_table_properties.log_max_ft_sampler_num);
 854
 855         /* Query HCA offloads for Ethernet protocol. */
 856         memset(in, 0, sizeof(in));
 857         memset(out, 0, sizeof(out));
 858         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 859         MLX5_SET(query_hca_cap_in, in, op_mod,
 860                  MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
 861                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 862
 863         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 864         if (rc) {
 865                 attr->eth_net_offloads = 0;
 866                 goto error;
 867         }
 868         status = MLX5_GET(query_hca_cap_out, out, status);
 869         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 870         if (status) {
 871                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 872                         "status %x, syndrome = %x", status, syndrome);
 873                 attr->eth_net_offloads = 0;
 874                 return -1;
 875         }
 876         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 877         attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
 878                                          hcattr, wqe_vlan_insert);
 879         attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 880                                  lro_cap);
 881         attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
 882                                         hcattr, tunnel_lro_gre);
 883         attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
 884                                           hcattr, tunnel_lro_vxlan);
 885         attr->lro_max_msg_sz_mode = MLX5_GET
 886                                         (per_protocol_networking_offload_caps,
 887                                          hcattr, lro_max_msg_sz_mode);
 888         for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
 889                 attr->lro_timer_supported_periods[i] =
 890                         MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 891                                  lro_timer_supported_periods[i]);
 892         }
 893         attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
 894                                           hcattr, lro_min_mss_size);
 895         attr->tunnel_stateless_geneve_rx =
 896                             MLX5_GET(per_protocol_networking_offload_caps,
 897                                      hcattr, tunnel_stateless_geneve_rx);
 898         attr->geneve_max_opt_len =
 899                     MLX5_GET(per_protocol_networking_offload_caps,
 900                              hcattr, max_geneve_opt_len);
 901         attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
 902                                          hcattr, wqe_inline_mode);
 903         attr->tunnel_stateless_gtp = MLX5_GET
 904                                         (per_protocol_networking_offload_caps,
 905                                          hcattr, tunnel_stateless_gtp);
 906         attr->rss_ind_tbl_cap = MLX5_GET
 907                                         (per_protocol_networking_offload_caps,
 908                                          hcattr, rss_ind_tbl_cap);
 909         /* Query HCA attribute for ROCE. */
 910         if (attr->roce) {
 911                 memset(in, 0, sizeof(in));
 912                 memset(out, 0, sizeof(out));
 913                 MLX5_SET(query_hca_cap_in, in, opcode,
 914                          MLX5_CMD_OP_QUERY_HCA_CAP);
 915                 MLX5_SET(query_hca_cap_in, in, op_mod,
 916                          MLX5_GET_HCA_CAP_OP_MOD_ROCE |
 917                          MLX5_HCA_CAP_OPMOD_GET_CUR);
 918                 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
 919                                                  out, sizeof(out));
 920                 if (rc)
 921                         goto error;
 922                 status = MLX5_GET(query_hca_cap_out, out, status);
 923                 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 924                 if (status) {
 925                         DRV_LOG(DEBUG,
 926                                 "Failed to query devx HCA ROCE capabilities, "
 927                                 "status %x, syndrome = %x", status, syndrome);
 928                         return -1;
 929                 }
 930                 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 931                 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format);
 932         }
 933         if (attr->eth_virt &&
 934             attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) {
 935                 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
 936                 if (rc) {
 937                         attr->eth_virt = 0;
 938                         goto error;
 939                 }
 940         }
 941         return 0;
 942 error:
 943         rc = (rc > 0) ? -rc : rc;
 944         return rc;
 945 }
 946
 947 /**
 948  * Query TIS transport domain from QP verbs object using DevX API.
 949  *
 950  * @param[in] qp
 951  *   Pointer to verbs QP returned by ibv_create_qp .
 952  * @param[in] tis_num
 953  *   TIS number of TIS to query.
 954  * @param[out] tis_td
 955  *   Pointer to TIS transport domain variable, to be set by the routine.
 956  *
 957  * @return
 958  *   0 on success, a negative value otherwise.
 959  */
 960 int
 961 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
 962                               uint32_t *tis_td)
 963 {
 964 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 965         uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
 966         uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
 967         int rc;
 968         void *tis_ctx;
 969
 970         MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
 971         MLX5_SET(query_tis_in, in, tisn, tis_num);
 972         rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
 973         if (rc) {
 974                 DRV_LOG(ERR, "Failed to query QP using DevX");
 975                 return -rc;
 976         };
 977         tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
 978         *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
 979         return 0;
 980 #else
 981         (void)qp;
 982         (void)tis_num;
 983         (void)tis_td;
 984         return -ENOTSUP;
 985 #endif
 986 }
 987
 988 /**
 989  * Fill WQ data for DevX API command.
 990  * Utility function for use when creating DevX objects containing a WQ.
 991  *
 992  * @param[in] wq_ctx
 993  *   Pointer to WQ context to fill with data.
 994  * @param [in] wq_attr
 995  *   Pointer to WQ attributes structure to fill in WQ context.
 996  */
 997 static void
 998 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
 999 {
1000         MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
1001         MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
1002         MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
1003         MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
1004         MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
1005         MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
1006         MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
1007         MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
1008         MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
1009         MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
1010         MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
1011         MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
1012         MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
1013         MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
1014         if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT)
1015                 MLX5_SET(wq, wq_ctx, log_wq_pg_sz,
1016                          wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT);
1017         MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
1018         MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
1019         MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
1020         MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
1021                  wq_attr->log_hairpin_num_packets);
1022         MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
1023         MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
1024                  wq_attr->single_wqe_log_num_of_strides);
1025         MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
1026         MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
1027                  wq_attr->single_stride_log_num_of_bytes);
1028         MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
1029         MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
1030         MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
1031 }
1032
1033 /**
1034  * Create RQ using DevX API.
1035  *
1036  * @param[in] ctx
1037  *   Context returned from mlx5 open_device() glue function.
1038  * @param [in] rq_attr
1039  *   Pointer to create RQ attributes structure.
1040  * @param [in] socket
1041  *   CPU socket ID for allocations.
1042  *
1043  * @return
1044  *   The DevX object created, NULL otherwise and rte_errno is set.
1045  */
1046 struct mlx5_devx_obj *
1047 mlx5_devx_cmd_create_rq(void *ctx,
1048                         struct mlx5_devx_create_rq_attr *rq_attr,
1049                         int socket)
1050 {
1051         uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
1052         uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
1053         void *rq_ctx, *wq_ctx;
1054         struct mlx5_devx_wq_attr *wq_attr;
1055         struct mlx5_devx_obj *rq = NULL;
1056
1057         rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
1058         if (!rq) {
1059                 DRV_LOG(ERR, "Failed to allocate RQ data");
1060                 rte_errno = ENOMEM;
1061                 return NULL;
1062         }
1063         MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
1064         rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
1065         MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
1066         MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
1067         MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1068         MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1069         MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
1070         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1071         MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
1072         MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
1073         MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
1074         MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
1075         MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1076         MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
1077         MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format);
1078         wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1079         wq_attr = &rq_attr->wq_attr;
1080         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1081         rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1082                                                   out, sizeof(out));
1083         if (!rq->obj) {
1084                 DRV_LOG(ERR, "Failed to create RQ using DevX");
1085                 rte_errno = errno;
1086                 mlx5_free(rq);
1087                 return NULL;
1088         }
1089         rq->id = MLX5_GET(create_rq_out, out, rqn);
1090         return rq;
1091 }
1092
1093 /**
1094  * Modify RQ using DevX API.
1095  *
1096  * @param[in] rq
1097  *   Pointer to RQ object structure.
1098  * @param [in] rq_attr
1099  *   Pointer to modify RQ attributes structure.
1100  *
1101  * @return
1102  *   0 on success, a negative errno value otherwise and rte_errno is set.
1103  */
1104 int
1105 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1106                         struct mlx5_devx_modify_rq_attr *rq_attr)
1107 {
1108         uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1109         uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1110         void *rq_ctx, *wq_ctx;
1111         int ret;
1112
1113         MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1114         MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1115         MLX5_SET(modify_rq_in, in, rqn, rq->id);
1116         MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1117         rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1118         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1119         if (rq_attr->modify_bitmask &
1120                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1121                 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1122         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1123                 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1124         if (rq_attr->modify_bitmask &
1125                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1126                 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1127         MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1128         MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1129         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1130                 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1131                 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1132         }
1133         ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1134                                          out, sizeof(out));
1135         if (ret) {
1136                 DRV_LOG(ERR, "Failed to modify RQ using DevX");
1137                 rte_errno = errno;
1138                 return -errno;
1139         }
1140         return ret;
1141 }
1142
1143 /**
1144  * Create TIR using DevX API.
1145  *
1146  * @param[in] ctx
1147  *  Context returned from mlx5 open_device() glue function.
1148  * @param [in] tir_attr
1149  *   Pointer to TIR attributes structure.
1150  *
1151  * @return
1152  *   The DevX object created, NULL otherwise and rte_errno is set.
1153  */
1154 struct mlx5_devx_obj *
1155 mlx5_devx_cmd_create_tir(void *ctx,
1156                          struct mlx5_devx_tir_attr *tir_attr)
1157 {
1158         uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1159         uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1160         void *tir_ctx, *outer, *inner, *rss_key;
1161         struct mlx5_devx_obj *tir = NULL;
1162
1163         tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1164         if (!tir) {
1165                 DRV_LOG(ERR, "Failed to allocate TIR data");
1166                 rte_errno = ENOMEM;
1167                 return NULL;
1168         }
1169         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1170         tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1171         MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1172         MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1173                  tir_attr->lro_timeout_period_usecs);
1174         MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1175         MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1176         MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1177         MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1178         MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1179                  tir_attr->tunneled_offload_en);
1180         MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1181         MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1182         MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1183         MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1184         rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1185         memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1186         outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1187         MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1188                  tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1189         MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1190                  tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1191         MLX5_SET(rx_hash_field_select, outer, selected_fields,
1192                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1193         inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1194         MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1195                  tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1196         MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1197                  tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1198         MLX5_SET(rx_hash_field_select, inner, selected_fields,
1199                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1200         tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1201                                                    out, sizeof(out));
1202         if (!tir->obj) {
1203                 DRV_LOG(ERR, "Failed to create TIR using DevX");
1204                 rte_errno = errno;
1205                 mlx5_free(tir);
1206                 return NULL;
1207         }
1208         tir->id = MLX5_GET(create_tir_out, out, tirn);
1209         return tir;
1210 }
1211
1212 /**
1213  * Modify TIR using DevX API.
1214  *
1215  * @param[in] tir
1216  *   Pointer to TIR DevX object structure.
1217  * @param [in] modify_tir_attr
1218  *   Pointer to TIR modification attributes structure.
1219  *
1220  * @return
1221  *   0 on success, a negative errno value otherwise and rte_errno is set.
1222  */
1223 int
1224 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
1225                          struct mlx5_devx_modify_tir_attr *modify_tir_attr)
1226 {
1227         struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
1228         uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
1229         uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
1230         void *tir_ctx;
1231         int ret;
1232
1233         MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
1234         MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
1235         MLX5_SET64(modify_tir_in, in, modify_bitmask,
1236                    modify_tir_attr->modify_bitmask);
1237         tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1238         if (modify_tir_attr->modify_bitmask &
1239                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
1240                 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1241                          tir_attr->lro_timeout_period_usecs);
1242                 MLX5_SET(tirc, tir_ctx, lro_enable_mask,
1243                          tir_attr->lro_enable_mask);
1244                 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
1245                          tir_attr->lro_max_msg_sz);
1246         }
1247         if (modify_tir_attr->modify_bitmask &
1248                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
1249                 MLX5_SET(tirc, tir_ctx, indirect_table,
1250                          tir_attr->indirect_table);
1251         if (modify_tir_attr->modify_bitmask &
1252                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
1253                 int i;
1254                 void *outer, *inner;
1255
1256                 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
1257                          tir_attr->rx_hash_symmetric);
1258                 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1259                 for (i = 0; i < 10; i++) {
1260                         MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
1261                                  tir_attr->rx_hash_toeplitz_key[i]);
1262                 }
1263                 outer = MLX5_ADDR_OF(tirc, tir_ctx,
1264                                      rx_hash_field_selector_outer);
1265                 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1266                          tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1267                 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1268                          tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1269                 MLX5_SET
1270                 (rx_hash_field_select, outer, selected_fields,
1271                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1272                 inner = MLX5_ADDR_OF(tirc, tir_ctx,
1273                                      rx_hash_field_selector_inner);
1274                 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1275                          tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1276                 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1277                          tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1278                 MLX5_SET
1279                 (rx_hash_field_select, inner, selected_fields,
1280                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1281         }
1282         if (modify_tir_attr->modify_bitmask &
1283             MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
1284                 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1285         }
1286         ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
1287                                          out, sizeof(out));
1288         if (ret) {
1289                 DRV_LOG(ERR, "Failed to modify TIR using DevX");
1290                 rte_errno = errno;
1291                 return -errno;
1292         }
1293         return ret;
1294 }
1295
1296 /**
1297  * Create RQT using DevX API.
1298  *
1299  * @param[in] ctx
1300  *   Context returned from mlx5 open_device() glue function.
1301  * @param [in] rqt_attr
1302  *   Pointer to RQT attributes structure.
1303  *
1304  * @return
1305  *   The DevX object created, NULL otherwise and rte_errno is set.
1306  */
1307 struct mlx5_devx_obj *
1308 mlx5_devx_cmd_create_rqt(void *ctx,
1309                          struct mlx5_devx_rqt_attr *rqt_attr)
1310 {
1311         uint32_t *in = NULL;
1312         uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1313                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1314         uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1315         void *rqt_ctx;
1316         struct mlx5_devx_obj *rqt = NULL;
1317         int i;
1318
1319         in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1320         if (!in) {
1321                 DRV_LOG(ERR, "Failed to allocate RQT IN data");
1322                 rte_errno = ENOMEM;
1323                 return NULL;
1324         }
1325         rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1326         if (!rqt) {
1327                 DRV_LOG(ERR, "Failed to allocate RQT data");
1328                 rte_errno = ENOMEM;
1329                 mlx5_free(in);
1330                 return NULL;
1331         }
1332         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1333         rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1334         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1335         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1336         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1337         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1338                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1339         rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1340         mlx5_free(in);
1341         if (!rqt->obj) {
1342                 DRV_LOG(ERR, "Failed to create RQT using DevX");
1343                 rte_errno = errno;
1344                 mlx5_free(rqt);
1345                 return NULL;
1346         }
1347         rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1348         return rqt;
1349 }
1350
1351 /**
1352  * Modify RQT using DevX API.
1353  *
1354  * @param[in] rqt
1355  *   Pointer to RQT DevX object structure.
1356  * @param [in] rqt_attr
1357  *   Pointer to RQT attributes structure.
1358  *
1359  * @return
1360  *   0 on success, a negative errno value otherwise and rte_errno is set.
1361  */
1362 int
1363 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1364                          struct mlx5_devx_rqt_attr *rqt_attr)
1365 {
1366         uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1367                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1368         uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1369         uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1370         void *rqt_ctx;
1371         int i;
1372         int ret;
1373
1374         if (!in) {
1375                 DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1376                 rte_errno = ENOMEM;
1377                 return -ENOMEM;
1378         }
1379         MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
1380         MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
1381         MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
1382         rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
1383         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1384         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1385         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1386         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1387                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1388         ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
1389         mlx5_free(in);
1390         if (ret) {
1391                 DRV_LOG(ERR, "Failed to modify RQT using DevX.");
1392                 rte_errno = errno;
1393                 return -rte_errno;
1394         }
1395         return ret;
1396 }
1397
1398 /**
1399  * Create SQ using DevX API.
1400  *
1401  * @param[in] ctx
1402  *   Context returned from mlx5 open_device() glue function.
1403  * @param [in] sq_attr
1404  *   Pointer to SQ attributes structure.
1405  * @param [in] socket
1406  *   CPU socket ID for allocations.
1407  *
1408  * @return
1409  *   The DevX object created, NULL otherwise and rte_errno is set.
1410  **/
1411 struct mlx5_devx_obj *
1412 mlx5_devx_cmd_create_sq(void *ctx,
1413                         struct mlx5_devx_create_sq_attr *sq_attr)
1414 {
1415         uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
1416         uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
1417         void *sq_ctx;
1418         void *wq_ctx;
1419         struct mlx5_devx_wq_attr *wq_attr;
1420         struct mlx5_devx_obj *sq = NULL;
1421
1422         sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
1423         if (!sq) {
1424                 DRV_LOG(ERR, "Failed to allocate SQ data");
1425                 rte_errno = ENOMEM;
1426                 return NULL;
1427         }
1428         MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
1429         sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
1430         MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
1431         MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
1432         MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
1433         MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
1434         MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
1435                  sq_attr->allow_multi_pkt_send_wqe);
1436         MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
1437                  sq_attr->min_wqe_inline_mode);
1438         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1439         MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
1440         MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
1441         MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
1442         MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
1443         MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
1444         MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
1445         MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
1446         MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
1447                  sq_attr->packet_pacing_rate_limit_index);
1448         MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
1449         MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
1450         MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format);
1451         wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
1452         wq_attr = &sq_attr->wq_attr;
1453         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1454         sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1455                                              out, sizeof(out));
1456         if (!sq->obj) {
1457                 DRV_LOG(ERR, "Failed to create SQ using DevX");
1458                 rte_errno = errno;
1459                 mlx5_free(sq);
1460                 return NULL;
1461         }
1462         sq->id = MLX5_GET(create_sq_out, out, sqn);
1463         return sq;
1464 }
1465
1466 /**
1467  * Modify SQ using DevX API.
1468  *
1469  * @param[in] sq
1470  *   Pointer to SQ object structure.
1471  * @param [in] sq_attr
1472  *   Pointer to SQ attributes structure.
1473  *
1474  * @return
1475  *   0 on success, a negative errno value otherwise and rte_errno is set.
1476  */
1477 int
1478 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
1479                         struct mlx5_devx_modify_sq_attr *sq_attr)
1480 {
1481         uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
1482         uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
1483         void *sq_ctx;
1484         int ret;
1485
1486         MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
1487         MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
1488         MLX5_SET(modify_sq_in, in, sqn, sq->id);
1489         sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1490         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1491         MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
1492         MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
1493         ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
1494                                          out, sizeof(out));
1495         if (ret) {
1496                 DRV_LOG(ERR, "Failed to modify SQ using DevX");
1497                 rte_errno = errno;
1498                 return -rte_errno;
1499         }
1500         return ret;
1501 }
1502
1503 /**
1504  * Create TIS using DevX API.
1505  *
1506  * @param[in] ctx
1507  *   Context returned from mlx5 open_device() glue function.
1508  * @param [in] tis_attr
1509  *   Pointer to TIS attributes structure.
1510  *
1511  * @return
1512  *   The DevX object created, NULL otherwise and rte_errno is set.
1513  */
1514 struct mlx5_devx_obj *
1515 mlx5_devx_cmd_create_tis(void *ctx,
1516                          struct mlx5_devx_tis_attr *tis_attr)
1517 {
1518         uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1519         uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
1520         struct mlx5_devx_obj *tis = NULL;
1521         void *tis_ctx;
1522
1523         tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
1524         if (!tis) {
1525                 DRV_LOG(ERR, "Failed to allocate TIS object");
1526                 rte_errno = ENOMEM;
1527                 return NULL;
1528         }
1529         MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
1530         tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
1531         MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1532                  tis_attr->strict_lag_tx_port_affinity);
1533         MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,
1534                  tis_attr->lag_tx_port_affinity);
1535         MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
1536         MLX5_SET(tisc, tis_ctx, transport_domain,
1537                  tis_attr->transport_domain);
1538         tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1539                                               out, sizeof(out));
1540         if (!tis->obj) {
1541                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1542                 rte_errno = errno;
1543                 mlx5_free(tis);
1544                 return NULL;
1545         }
1546         tis->id = MLX5_GET(create_tis_out, out, tisn);
1547         return tis;
1548 }
1549
1550 /**
1551  * Create transport domain using DevX API.
1552  *
1553  * @param[in] ctx
1554  *   Context returned from mlx5 open_device() glue function.
1555  * @return
1556  *   The DevX object created, NULL otherwise and rte_errno is set.
1557  */
1558 struct mlx5_devx_obj *
1559 mlx5_devx_cmd_create_td(void *ctx)
1560 {
1561         uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1562         uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1563         struct mlx5_devx_obj *td = NULL;
1564
1565         td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
1566         if (!td) {
1567                 DRV_LOG(ERR, "Failed to allocate TD object");
1568                 rte_errno = ENOMEM;
1569                 return NULL;
1570         }
1571         MLX5_SET(alloc_transport_domain_in, in, opcode,
1572                  MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1573         td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1574                                              out, sizeof(out));
1575         if (!td->obj) {
1576                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1577                 rte_errno = errno;
1578                 mlx5_free(td);
1579                 return NULL;
1580         }
1581         td->id = MLX5_GET(alloc_transport_domain_out, out,
1582                            transport_domain);
1583         return td;
1584 }
1585
1586 /**
1587  * Dump all flows to file.
1588  *
1589  * @param[in] fdb_domain
1590  *   FDB domain.
1591  * @param[in] rx_domain
1592  *   RX domain.
1593  * @param[in] tx_domain
1594  *   TX domain.
1595  * @param[out] file
1596  *   Pointer to file stream.
1597  *
1598  * @return
1599  *   0 on success, a nagative value otherwise.
1600  */
1601 int
1602 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1603                         void *rx_domain __rte_unused,
1604                         void *tx_domain __rte_unused, FILE *file __rte_unused)
1605 {
1606         int ret = 0;
1607
1608 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1609         if (fdb_domain) {
1610                 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1611                 if (ret)
1612                         return ret;
1613         }
1614         MLX5_ASSERT(rx_domain);
1615         ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1616         if (ret)
1617                 return ret;
1618         MLX5_ASSERT(tx_domain);
1619         ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1620 #else
1621         ret = ENOTSUP;
1622 #endif
1623         return -ret;
1624 }
1625
1626 int
1627 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused,
1628                         FILE *file __rte_unused)
1629 {
1630         int ret = 0;
1631 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE
1632         if (rule_info)
1633                 ret = mlx5_glue->dr_dump_rule(file, rule_info);
1634 #else
1635         ret = ENOTSUP;
1636 #endif
1637         return -ret;
1638 }
1639
1640 /*
1641  * Create CQ using DevX API.
1642  *
1643  * @param[in] ctx
1644  *   Context returned from mlx5 open_device() glue function.
1645  * @param [in] attr
1646  *   Pointer to CQ attributes structure.
1647  *
1648  * @return
1649  *   The DevX object created, NULL otherwise and rte_errno is set.
1650  */
1651 struct mlx5_devx_obj *
1652 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
1653 {
1654         uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
1655         uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
1656         struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1657                                                    sizeof(*cq_obj),
1658                                                    0, SOCKET_ID_ANY);
1659         void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1660
1661         if (!cq_obj) {
1662                 DRV_LOG(ERR, "Failed to allocate CQ object memory.");
1663                 rte_errno = ENOMEM;
1664                 return NULL;
1665         }
1666         MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
1667         if (attr->db_umem_valid) {
1668                 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
1669                 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
1670                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
1671         } else {
1672                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
1673         }
1674         MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ?
1675                                      MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B);
1676         MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
1677         MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
1678         MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
1679         if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
1680                 MLX5_SET(cqc, cqctx, log_page_size,
1681                          attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
1682         MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
1683         MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
1684         MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
1685         MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
1686         MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
1687                  attr->mini_cqe_res_format_ext);
1688         if (attr->q_umem_valid) {
1689                 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
1690                 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
1691                 MLX5_SET64(create_cq_in, in, cq_umem_offset,
1692                            attr->q_umem_offset);
1693         }
1694         cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1695                                                  sizeof(out));
1696         if (!cq_obj->obj) {
1697                 rte_errno = errno;
1698                 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno);
1699                 mlx5_free(cq_obj);
1700                 return NULL;
1701         }
1702         cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
1703         return cq_obj;
1704 }
1705
1706 /**
1707  * Create VIRTQ using DevX API.
1708  *
1709  * @param[in] ctx
1710  *   Context returned from mlx5 open_device() glue function.
1711  * @param [in] attr
1712  *   Pointer to VIRTQ attributes structure.
1713  *
1714  * @return
1715  *   The DevX object created, NULL otherwise and rte_errno is set.
1716  */
1717 struct mlx5_devx_obj *
1718 mlx5_devx_cmd_create_virtq(void *ctx,
1719                            struct mlx5_devx_virtq_attr *attr)
1720 {
1721         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1722         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1723         struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1724                                                      sizeof(*virtq_obj),
1725                                                      0, SOCKET_ID_ANY);
1726         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1727         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1728         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1729
1730         if (!virtq_obj) {
1731                 DRV_LOG(ERR, "Failed to allocate virtq data.");
1732                 rte_errno = ENOMEM;
1733                 return NULL;
1734         }
1735         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1736                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1737         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1738                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1739         MLX5_SET16(virtio_net_q, virtq, hw_available_index,
1740                    attr->hw_available_index);
1741         MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
1742         MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
1743         MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
1744         MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
1745         MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
1746         MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
1747                    attr->virtio_version_1_0);
1748         MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
1749         MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
1750         MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
1751         MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
1752         MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
1753         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1754         MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
1755         MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
1756         MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
1757         MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
1758         MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
1759         MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
1760         MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
1761         MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
1762         MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
1763         MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
1764         MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
1765         MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
1766         MLX5_SET(virtio_q, virtctx, pd, attr->pd);
1767         MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode);
1768         MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us);
1769         MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp);
1770         MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
1771         virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1772                                                     sizeof(out));
1773         if (!virtq_obj->obj) {
1774                 rte_errno = errno;
1775                 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX.");
1776                 mlx5_free(virtq_obj);
1777                 return NULL;
1778         }
1779         virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1780         return virtq_obj;
1781 }
1782
1783 /**
1784  * Modify VIRTQ using DevX API.
1785  *
1786  * @param[in] virtq_obj
1787  *   Pointer to virtq object structure.
1788  * @param [in] attr
1789  *   Pointer to modify virtq attributes structure.
1790  *
1791  * @return
1792  *   0 on success, a negative errno value otherwise and rte_errno is set.
1793  */
1794 int
1795 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
1796                            struct mlx5_devx_virtq_attr *attr)
1797 {
1798         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1799         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1800         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1801         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1802         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1803         int ret;
1804
1805         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1806                  MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
1807         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1808                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1809         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1810         MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);
1811         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1812         switch (attr->type) {
1813         case MLX5_VIRTQ_MODIFY_TYPE_STATE:
1814                 MLX5_SET16(virtio_net_q, virtq, state, attr->state);
1815                 break;
1816         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:
1817                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
1818                          attr->dirty_bitmap_mkey);
1819                 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
1820                          attr->dirty_bitmap_addr);
1821                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
1822                          attr->dirty_bitmap_size);
1823                 break;
1824         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:
1825                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
1826                          attr->dirty_bitmap_dump_enable);
1827                 break;
1828         default:
1829                 rte_errno = EINVAL;
1830                 return -rte_errno;
1831         }
1832         ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
1833                                          out, sizeof(out));
1834         if (ret) {
1835                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1836                 rte_errno = errno;
1837                 return -rte_errno;
1838         }
1839         return ret;
1840 }
1841
1842 /**
1843  * Query VIRTQ using DevX API.
1844  *
1845  * @param[in] virtq_obj
1846  *   Pointer to virtq object structure.
1847  * @param [in/out] attr
1848  *   Pointer to virtq attributes structure.
1849  *
1850  * @return
1851  *   0 on success, a negative errno value otherwise and rte_errno is set.
1852  */
1853 int
1854 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
1855                            struct mlx5_devx_virtq_attr *attr)
1856 {
1857         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
1858         uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
1859         void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
1860         void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
1861         int ret;
1862
1863         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1864                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
1865         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1866                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1867         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1868         ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
1869                                          out, sizeof(out));
1870         if (ret) {
1871                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1872                 rte_errno = errno;
1873                 return -errno;
1874         }
1875         attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
1876                                               hw_available_index);
1877         attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
1878         attr->state = MLX5_GET16(virtio_net_q, virtq, state);
1879         attr->error_type = MLX5_GET16(virtio_net_q, virtq,
1880                                       virtio_q_context.error_type);
1881         return ret;
1882 }
1883
1884 /**
1885  * Create QP using DevX API.
1886  *
1887  * @param[in] ctx
1888  *   Context returned from mlx5 open_device() glue function.
1889  * @param [in] attr
1890  *   Pointer to QP attributes structure.
1891  *
1892  * @return
1893  *   The DevX object created, NULL otherwise and rte_errno is set.
1894  */
1895 struct mlx5_devx_obj *
1896 mlx5_devx_cmd_create_qp(void *ctx,
1897                         struct mlx5_devx_qp_attr *attr)
1898 {
1899         uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
1900         uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
1901         struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
1902                                                    sizeof(*qp_obj),
1903                                                    0, SOCKET_ID_ANY);
1904         void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1905
1906         if (!qp_obj) {
1907                 DRV_LOG(ERR, "Failed to allocate QP data.");
1908                 rte_errno = ENOMEM;
1909                 return NULL;
1910         }
1911         MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
1912         MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
1913         MLX5_SET(qpc, qpc, pd, attr->pd);
1914         MLX5_SET(qpc, qpc, ts_format, attr->ts_format);
1915         if (attr->uar_index) {
1916                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1917                 MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
1918                 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
1919                         MLX5_SET(qpc, qpc, log_page_size,
1920                                  attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
1921                 if (attr->sq_size) {
1922                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));
1923                         MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
1924                         MLX5_SET(qpc, qpc, log_sq_size,
1925                                  rte_log2_u32(attr->sq_size));
1926                 } else {
1927                         MLX5_SET(qpc, qpc, no_sq, 1);
1928                 }
1929                 if (attr->rq_size) {
1930                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size));
1931                         MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
1932                         MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
1933                                  MLX5_LOG_RQ_STRIDE_SHIFT);
1934                         MLX5_SET(qpc, qpc, log_rq_size,
1935                                  rte_log2_u32(attr->rq_size));
1936                         MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
1937                 } else {
1938                         MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1939                 }
1940                 if (attr->dbr_umem_valid) {
1941                         MLX5_SET(qpc, qpc, dbr_umem_valid,
1942                                  attr->dbr_umem_valid);
1943                         MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
1944                 }
1945                 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
1946                 MLX5_SET64(create_qp_in, in, wq_umem_offset,
1947                            attr->wq_umem_offset);
1948                 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
1949                 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
1950         } else {
1951                 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
1952                 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1953                 MLX5_SET(qpc, qpc, no_sq, 1);
1954         }
1955         qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1956                                                  sizeof(out));
1957         if (!qp_obj->obj) {
1958                 rte_errno = errno;
1959                 DRV_LOG(ERR, "Failed to create QP Obj using DevX.");
1960                 mlx5_free(qp_obj);
1961                 return NULL;
1962         }
1963         qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
1964         return qp_obj;
1965 }
1966
1967 /**
1968  * Modify QP using DevX API.
1969  * Currently supports only force loop-back QP.
1970  *
1971  * @param[in] qp
1972  *   Pointer to QP object structure.
1973  * @param [in] qp_st_mod_op
1974  *   The QP state modification operation.
1975  * @param [in] remote_qp_id
1976  *   The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
1977  *
1978  * @return
1979  *   0 on success, a negative errno value otherwise and rte_errno is set.
1980  */
1981 int
1982 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
1983                               uint32_t remote_qp_id)
1984 {
1985         union {
1986                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
1987                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
1988                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
1989         } in;
1990         union {
1991                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
1992                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
1993                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
1994         } out;
1995         void *qpc;
1996         int ret;
1997         unsigned int inlen;
1998         unsigned int outlen;
1999
2000         memset(&in, 0, sizeof(in));
2001         memset(&out, 0, sizeof(out));
2002         MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
2003         switch (qp_st_mod_op) {
2004         case MLX5_CMD_OP_RST2INIT_QP:
2005                 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
2006                 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
2007                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2008                 MLX5_SET(qpc, qpc, rre, 1);
2009                 MLX5_SET(qpc, qpc, rwe, 1);
2010                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2011                 inlen = sizeof(in.rst2init);
2012                 outlen = sizeof(out.rst2init);
2013                 break;
2014         case MLX5_CMD_OP_INIT2RTR_QP:
2015                 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
2016                 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
2017                 MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
2018                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2019                 MLX5_SET(qpc, qpc, mtu, 1);
2020                 MLX5_SET(qpc, qpc, log_msg_max, 30);
2021                 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
2022                 MLX5_SET(qpc, qpc, min_rnr_nak, 0);
2023                 inlen = sizeof(in.init2rtr);
2024                 outlen = sizeof(out.init2rtr);
2025                 break;
2026         case MLX5_CMD_OP_RTR2RTS_QP:
2027                 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
2028                 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
2029                 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14);
2030                 MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
2031                 MLX5_SET(qpc, qpc, retry_count, 7);
2032                 MLX5_SET(qpc, qpc, rnr_retry, 7);
2033                 inlen = sizeof(in.rtr2rts);
2034                 outlen = sizeof(out.rtr2rts);
2035                 break;
2036         default:
2037                 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
2038                         qp_st_mod_op);
2039                 rte_errno = EINVAL;
2040                 return -rte_errno;
2041         }
2042         ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
2043         if (ret) {
2044                 DRV_LOG(ERR, "Failed to modify QP using DevX.");
2045                 rte_errno = errno;
2046                 return -rte_errno;
2047         }
2048         return ret;
2049 }
2050
2051 struct mlx5_devx_obj *
2052 mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
2053 {
2054         uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
2055         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2056         struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
2057                                                        sizeof(*couners_obj), 0,
2058                                                        SOCKET_ID_ANY);
2059         void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
2060
2061         if (!couners_obj) {
2062                 DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
2063                 rte_errno = ENOMEM;
2064                 return NULL;
2065         }
2066         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2067                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2068         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2069                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2070         couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2071                                                       sizeof(out));
2072         if (!couners_obj->obj) {
2073                 rte_errno = errno;
2074                 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using"
2075                         " DevX.");
2076                 mlx5_free(couners_obj);
2077                 return NULL;
2078         }
2079         couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2080         return couners_obj;
2081 }
2082
2083 int
2084 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
2085                                    struct mlx5_devx_virtio_q_couners_attr *attr)
2086 {
2087         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2088         uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
2089         void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
2090         void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
2091                                                virtio_q_counters);
2092         int ret;
2093
2094         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2095                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2096         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2097                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2098         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
2099         ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
2100                                         sizeof(out));
2101         if (ret) {
2102                 DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
2103                 rte_errno = errno;
2104                 return -errno;
2105         }
2106         attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2107                                          received_desc);
2108         attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2109                                           completed_desc);
2110         attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
2111                                     error_cqes);
2112         attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
2113                                          bad_desc_errors);
2114         attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
2115                                           exceed_max_chain);
2116         attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
2117                                         invalid_buffer);
2118         return ret;
2119 }
2120
2121 /**
2122  * Create general object of type FLOW_HIT_ASO using DevX API.
2123  *
2124  * @param[in] ctx
2125  *   Context returned from mlx5 open_device() glue function.
2126  * @param [in] pd
2127  *   PD value to associate the FLOW_HIT_ASO object with.
2128  *
2129  * @return
2130  *   The DevX object created, NULL otherwise and rte_errno is set.
2131  */
2132 struct mlx5_devx_obj *
2133 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd)
2134 {
2135         uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0};
2136         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2137         struct mlx5_devx_obj *flow_hit_aso_obj = NULL;
2138         void *ptr = NULL;
2139
2140         flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj),
2141                                        0, SOCKET_ID_ANY);
2142         if (!flow_hit_aso_obj) {
2143                 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data");
2144                 rte_errno = ENOMEM;
2145                 return NULL;
2146         }
2147         ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr);
2148         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2149                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2150         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2151                  MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO);
2152         ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso);
2153         MLX5_SET(flow_hit_aso, ptr, access_pd, pd);
2154         flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2155                                                            out, sizeof(out));
2156         if (!flow_hit_aso_obj->obj) {
2157                 rte_errno = errno;
2158                 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX.");
2159                 mlx5_free(flow_hit_aso_obj);
2160                 return NULL;
2161         }
2162         flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2163         return flow_hit_aso_obj;
2164 }
2165
2166 /*
2167  * Create PD using DevX API.
2168  *
2169  * @param[in] ctx
2170  *   Context returned from mlx5 open_device() glue function.
2171  *
2172  * @return
2173  *   The DevX object created, NULL otherwise and rte_errno is set.
2174  */
2175 struct mlx5_devx_obj *
2176 mlx5_devx_cmd_alloc_pd(void *ctx)
2177 {
2178         struct mlx5_devx_obj *ppd =
2179                 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY);
2180         u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
2181         u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
2182
2183         if (!ppd) {
2184                 DRV_LOG(ERR, "Failed to allocate PD data.");
2185                 rte_errno = ENOMEM;
2186                 return NULL;
2187         }
2188         MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2189         ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2190                                 out, sizeof(out));
2191         if (!ppd->obj) {
2192                 mlx5_free(ppd);
2193                 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX.");
2194                 rte_errno = errno;
2195                 return NULL;
2196         }
2197         ppd->id = MLX5_GET(alloc_pd_out, out, pd);
2198         return ppd;
2199 }
2200
2201 /**
2202  * Create general object of type FLOW_METER_ASO using DevX API.
2203  *
2204  * @param[in] ctx
2205  *   Context returned from mlx5 open_device() glue function.
2206  * @param [in] pd
2207  *   PD value to associate the FLOW_METER_ASO object with.
2208  * @param [in] log_obj_size
2209  *   log_obj_size define to allocate number of 2 * meters
2210  *   in one FLOW_METER_ASO object.
2211  *
2212  * @return
2213  *   The DevX object created, NULL otherwise and rte_errno is set.
2214  */
2215 struct mlx5_devx_obj *
2216 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd,
2217                                                 uint32_t log_obj_size)
2218 {
2219         uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0};
2220         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2221         struct mlx5_devx_obj *flow_meter_aso_obj;
2222         void *ptr;
2223
2224         flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO,
2225                                                 sizeof(*flow_meter_aso_obj),
2226                                                 0, SOCKET_ID_ANY);
2227         if (!flow_meter_aso_obj) {
2228                 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data");
2229                 rte_errno = ENOMEM;
2230                 return NULL;
2231         }
2232         ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr);
2233         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2234                 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2235         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2236                 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO);
2237         MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range,
2238                 log_obj_size);
2239         ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso);
2240         MLX5_SET(flow_meter_aso, ptr, access_pd, pd);
2241         flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create(
2242                                                         ctx, in, sizeof(in),
2243                                                         out, sizeof(out));
2244         if (!flow_meter_aso_obj->obj) {
2245                 rte_errno = errno;
2246                 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX.");
2247                 mlx5_free(flow_meter_aso_obj);
2248                 return NULL;
2249         }
2250         flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr,
2251                                                                 out, obj_id);
2252         return flow_meter_aso_obj;
2253 }
2254
2255 /**
2256  * Create general object of type GENEVE TLV option using DevX API.
2257  *
2258  * @param[in] ctx
2259  *   Context returned from mlx5 open_device() glue function.
2260  * @param [in] class
2261  *   TLV option variable value of class
2262  * @param [in] type
2263  *   TLV option variable value of type
2264  * @param [in] len
2265  *   TLV option variable value of len
2266  *
2267  * @return
2268  *   The DevX object created, NULL otherwise and rte_errno is set.
2269  */
2270 struct mlx5_devx_obj *
2271 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
2272                 uint16_t class, uint8_t type, uint8_t len)
2273 {
2274         uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0};
2275         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2276         struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO,
2277                                                    sizeof(*geneve_tlv_opt_obj),
2278                                                    0, SOCKET_ID_ANY);
2279
2280         if (!geneve_tlv_opt_obj) {
2281                 DRV_LOG(ERR, "Failed to allocate geneve tlv option object.");
2282                 rte_errno = ENOMEM;
2283                 return NULL;
2284         }
2285         void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr);
2286         void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in,
2287                         geneve_tlv_opt);
2288         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2289                         MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2290         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2291                  MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
2292         MLX5_SET(geneve_tlv_option, opt, option_class,
2293                         rte_be_to_cpu_16(class));
2294         MLX5_SET(geneve_tlv_option, opt, option_type, type);
2295         MLX5_SET(geneve_tlv_option, opt, option_data_length, len);
2296         geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,
2297                                         sizeof(in), out, sizeof(out));
2298         if (!geneve_tlv_opt_obj->obj) {
2299                 rte_errno = errno;
2300                 DRV_LOG(ERR, "Failed to create Geneve tlv option "
2301                                 "Obj using DevX.");
2302                 mlx5_free(geneve_tlv_opt_obj);
2303                 return NULL;
2304         }
2305         geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2306         return geneve_tlv_opt_obj;
2307 }
2308
2309 int
2310 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)
2311 {
2312 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2313         uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
2314         uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0};
2315         int rc;
2316         void *rq_ctx;
2317
2318         MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
2319         MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num);
2320         rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out));
2321         if (rc) {
2322                 rte_errno = errno;
2323                 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - "
2324                         "rc = %d, errno = %d.", rc, errno);
2325                 return -rc;
2326         };
2327         rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context);
2328         *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id);
2329         return 0;
2330 #else
2331         (void)wq;
2332         (void)counter_set_id;
2333         return -ENOTSUP;
2334 #endif
2335 }
2336
2337 /*
2338  * Allocate queue counters via devx interface.
2339  *
2340  * @param[in] ctx
2341  *   Context returned from mlx5 open_device() glue function.
2342  *
2343  * @return
2344  *   Pointer to counter object on success, a NULL value otherwise and
2345  *   rte_errno is set.
2346  */
2347 struct mlx5_devx_obj *
2348 mlx5_devx_cmd_queue_counter_alloc(void *ctx)
2349 {
2350         struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0,
2351                                                 SOCKET_ID_ANY);
2352         uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)]   = {0};
2353         uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
2354
2355         if (!dcs) {
2356                 rte_errno = ENOMEM;
2357                 return NULL;
2358         }
2359         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
2360         dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2361                                               sizeof(out));
2362         if (!dcs->obj) {
2363                 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error "
2364                         "%d.", errno);
2365                 rte_errno = errno;
2366                 mlx5_free(dcs);
2367                 return NULL;
2368         }
2369         dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id);
2370         return dcs;
2371 }
2372
2373 /**
2374  * Query queue counters values.
2375  *
2376  * @param[in] dcs
2377  *   devx object of the queue counter set.
2378  * @param[in] clear
2379  *   Whether hardware should clear the counters after the query or not.
2380  *  @param[out] out_of_buffers
2381  *   Number of dropped occurred due to lack of WQE for the associated QPs/RQs.
2382  *
2383  * @return
2384  *   0 on success, a negative value otherwise.
2385  */
2386 int
2387 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
2388                                   uint32_t *out_of_buffers)
2389 {
2390         uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0};
2391         uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0};
2392         int rc;
2393
2394         MLX5_SET(query_q_counter_in, in, opcode,
2395                  MLX5_CMD_OP_QUERY_Q_COUNTER);
2396         MLX5_SET(query_q_counter_in, in, op_mod, 0);
2397         MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id);
2398         MLX5_SET(query_q_counter_in, in, clear, !!clear);
2399         rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
2400                                        sizeof(out));
2401         if (rc) {
2402                 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc);
2403                 rte_errno = rc;
2404                 return -rc;
2405         }
2406         *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer);
2407         return 0;
2408 }
2409
2410 /**
2411  * Create general object of type DEK using DevX API.
2412  *
2413  * @param[in] ctx
2414  *   Context returned from mlx5 open_device() glue function.
2415  * @param [in] attr
2416  *   Pointer to DEK attributes structure.
2417  *
2418  * @return
2419  *   The DevX object created, NULL otherwise and rte_errno is set.
2420  */
2421 struct mlx5_devx_obj *
2422 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr)
2423 {
2424         uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0};
2425         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2426         struct mlx5_devx_obj *dek_obj = NULL;
2427         void *ptr = NULL, *key_addr = NULL;
2428
2429         dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj),
2430                               0, SOCKET_ID_ANY);
2431         if (dek_obj == NULL) {
2432                 DRV_LOG(ERR, "Failed to allocate DEK object data");
2433                 rte_errno = ENOMEM;
2434                 return NULL;
2435         }
2436         ptr = MLX5_ADDR_OF(create_dek_in, in, hdr);
2437         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2438                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2439         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2440                  MLX5_GENERAL_OBJ_TYPE_DEK);
2441         ptr = MLX5_ADDR_OF(create_dek_in, in, dek);
2442         MLX5_SET(dek, ptr, key_size, attr->key_size);
2443         MLX5_SET(dek, ptr, has_keytag, attr->has_keytag);
2444         MLX5_SET(dek, ptr, key_purpose, attr->key_purpose);
2445         MLX5_SET(dek, ptr, pd, attr->pd);
2446         MLX5_SET64(dek, ptr, opaque, attr->opaque);
2447         key_addr = MLX5_ADDR_OF(dek, ptr, key);
2448         memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
2449         dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2450                                                   out, sizeof(out));
2451         if (dek_obj->obj == NULL) {
2452                 rte_errno = errno;
2453                 DRV_LOG(ERR, "Failed to create DEK obj using DevX.");
2454                 mlx5_free(dek_obj);
2455                 return NULL;
2456         }
2457         dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2458         return dek_obj;
2459 }