drivers/common/mlx5/mlx5_devx_cmds.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2018 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <unistd.h>
   6
   7 #include <rte_errno.h>
   8 #include <rte_malloc.h>
   9 #include <rte_eal_paging.h>
  10
  11 #include "mlx5_prm.h"
  12 #include "mlx5_devx_cmds.h"
  13 #include "mlx5_common_log.h"
  14 #include "mlx5_malloc.h"
  15
  16 /**
  17  * Perform read access to the registers. Reads data from register
  18  * and writes ones to the specified buffer.
  19  *
  20  * @param[in] ctx
  21  *   Context returned from mlx5 open_device() glue function.
  22  * @param[in] reg_id
  23  *   Register identifier according to the PRM.
  24  * @param[in] arg
  25  *   Register access auxiliary parameter according to the PRM.
  26  * @param[out] data
  27  *   Pointer to the buffer to store read data.
  28  * @param[in] dw_cnt
  29  *   Buffer size in double words.
  30  *
  31  * @return
  32  *   0 on success, a negative value otherwise.
  33  */
  34 int
  35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
  36                             uint32_t *data, uint32_t dw_cnt)
  37 {
  38         uint32_t in[MLX5_ST_SZ_DW(access_register_in)]   = {0};
  39         uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
  40                      MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
  41         int status, rc;
  42
  43         MLX5_ASSERT(data && dw_cnt);
  44         MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
  45         if (dw_cnt  > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
  46                 DRV_LOG(ERR, "Not enough  buffer for register read data");
  47                 return -1;
  48         }
  49         MLX5_SET(access_register_in, in, opcode,
  50                  MLX5_CMD_OP_ACCESS_REGISTER_USER);
  51         MLX5_SET(access_register_in, in, op_mod,
  52                                         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
  53         MLX5_SET(access_register_in, in, register_id, reg_id);
  54         MLX5_SET(access_register_in, in, argument, arg);
  55         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
  56                                          MLX5_ST_SZ_BYTES(access_register_out) +
  57                                          sizeof(uint32_t) * dw_cnt);
  58         if (rc)
  59                 goto error;
  60         status = MLX5_GET(access_register_out, out, status);
  61         if (status) {
  62                 int syndrome = MLX5_GET(access_register_out, out, syndrome);
  63
  64                 DRV_LOG(DEBUG, "Failed to read access NIC register 0x%X, "
  65                                "status %x, syndrome = %x",
  66                                reg_id, status, syndrome);
  67                 return -1;
  68         }
  69         memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
  70                dw_cnt * sizeof(uint32_t));
  71         return 0;
  72 error:
  73         rc = (rc > 0) ? -rc : rc;
  74         return rc;
  75 }
  76
  77 /**
  78  * Perform write access to the registers.
  79  *
  80  * @param[in] ctx
  81  *   Context returned from mlx5 open_device() glue function.
  82  * @param[in] reg_id
  83  *   Register identifier according to the PRM.
  84  * @param[in] arg
  85  *   Register access auxiliary parameter according to the PRM.
  86  * @param[out] data
  87  *   Pointer to the buffer containing data to write.
  88  * @param[in] dw_cnt
  89  *   Buffer size in double words (32bit units).
  90  *
  91  * @return
  92  *   0 on success, a negative value otherwise.
  93  */
  94 int
  95 mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg,
  96                              uint32_t *data, uint32_t dw_cnt)
  97 {
  98         uint32_t in[MLX5_ST_SZ_DW(access_register_in) +
  99                     MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
 100         uint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0};
 101         int status, rc;
 102         void *ptr;
 103
 104         MLX5_ASSERT(data && dw_cnt);
 105         MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
 106         if (dw_cnt > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
 107                 DRV_LOG(ERR, "Data to write exceeds max size");
 108                 return -1;
 109         }
 110         MLX5_SET(access_register_in, in, opcode,
 111                  MLX5_CMD_OP_ACCESS_REGISTER_USER);
 112         MLX5_SET(access_register_in, in, op_mod,
 113                  MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE);
 114         MLX5_SET(access_register_in, in, register_id, reg_id);
 115         MLX5_SET(access_register_in, in, argument, arg);
 116         ptr = MLX5_ADDR_OF(access_register_in, in, register_data);
 117         memcpy(ptr, data, dw_cnt * sizeof(uint32_t));
 118         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 119
 120         rc = mlx5_glue->devx_general_cmd(ctx, in,
 121                                          MLX5_ST_SZ_BYTES(access_register_in) +
 122                                          dw_cnt * sizeof(uint32_t),
 123                                          out, sizeof(out));
 124         if (rc)
 125                 goto error;
 126         status = MLX5_GET(access_register_out, out, status);
 127         if (status) {
 128                 int syndrome = MLX5_GET(access_register_out, out, syndrome);
 129
 130                 DRV_LOG(DEBUG, "Failed to write access NIC register 0x%X, "
 131                                "status %x, syndrome = %x",
 132                                reg_id, status, syndrome);
 133                 return -1;
 134         }
 135         return 0;
 136 error:
 137         rc = (rc > 0) ? -rc : rc;
 138         return rc;
 139 }
 140
 141 /**
 142  * Allocate flow counters via devx interface.
 143  *
 144  * @param[in] ctx
 145  *   Context returned from mlx5 open_device() glue function.
 146  * @param dcs
 147  *   Pointer to counters properties structure to be filled by the routine.
 148  * @param bulk_n_128
 149  *   Bulk counter numbers in 128 counters units.
 150  *
 151  * @return
 152  *   Pointer to counter object on success, a negative value otherwise and
 153  *   rte_errno is set.
 154  */
 155 struct mlx5_devx_obj *
 156 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
 157 {
 158         struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
 159                                                 0, SOCKET_ID_ANY);
 160         uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)]   = {0};
 161         uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
 162
 163         if (!dcs) {
 164                 rte_errno = ENOMEM;
 165                 return NULL;
 166         }
 167         MLX5_SET(alloc_flow_counter_in, in, opcode,
 168                  MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
 169         MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
 170         dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
 171                                               sizeof(in), out, sizeof(out));
 172         if (!dcs->obj) {
 173                 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
 174                 rte_errno = errno;
 175                 mlx5_free(dcs);
 176                 return NULL;
 177         }
 178         dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
 179         return dcs;
 180 }
 181
 182 /**
 183  * Query flow counters values.
 184  *
 185  * @param[in] dcs
 186  *   devx object that was obtained from mlx5_devx_cmd_fc_alloc.
 187  * @param[in] clear
 188  *   Whether hardware should clear the counters after the query or not.
 189  * @param[in] n_counters
 190  *   0 in case of 1 counter to read, otherwise the counter number to read.
 191  *  @param pkts
 192  *   The number of packets that matched the flow.
 193  *  @param bytes
 194  *    The number of bytes that matched the flow.
 195  *  @param mkey
 196  *   The mkey key for batch query.
 197  *  @param addr
 198  *    The address in the mkey range for batch query.
 199  *  @param cmd_comp
 200  *   The completion object for asynchronous batch query.
 201  *  @param async_id
 202  *    The ID to be returned in the asynchronous batch query response.
 203  *
 204  * @return
 205  *   0 on success, a negative value otherwise.
 206  */
 207 int
 208 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
 209                                  int clear, uint32_t n_counters,
 210                                  uint64_t *pkts, uint64_t *bytes,
 211                                  uint32_t mkey, void *addr,
 212                                  void *cmd_comp,
 213                                  uint64_t async_id)
 214 {
 215         int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
 216                         MLX5_ST_SZ_BYTES(traffic_counter);
 217         uint32_t out[out_len];
 218         uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
 219         void *stats;
 220         int rc;
 221
 222         MLX5_SET(query_flow_counter_in, in, opcode,
 223                  MLX5_CMD_OP_QUERY_FLOW_COUNTER);
 224         MLX5_SET(query_flow_counter_in, in, op_mod, 0);
 225         MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
 226         MLX5_SET(query_flow_counter_in, in, clear, !!clear);
 227
 228         if (n_counters) {
 229                 MLX5_SET(query_flow_counter_in, in, num_of_counters,
 230                          n_counters);
 231                 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
 232                 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
 233                 MLX5_SET64(query_flow_counter_in, in, address,
 234                            (uint64_t)(uintptr_t)addr);
 235         }
 236         if (!cmd_comp)
 237                 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
 238                                                out_len);
 239         else
 240                 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
 241                                                      out_len, async_id,
 242                                                      cmd_comp);
 243         if (rc) {
 244                 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
 245                 rte_errno = rc;
 246                 return -rc;
 247         }
 248         if (!n_counters) {
 249                 stats = MLX5_ADDR_OF(query_flow_counter_out,
 250                                      out, flow_statistics);
 251                 *pkts = MLX5_GET64(traffic_counter, stats, packets);
 252                 *bytes = MLX5_GET64(traffic_counter, stats, octets);
 253         }
 254         return 0;
 255 }
 256
 257 /**
 258  * Create a new mkey.
 259  *
 260  * @param[in] ctx
 261  *   Context returned from mlx5 open_device() glue function.
 262  * @param[in] attr
 263  *   Attributes of the requested mkey.
 264  *
 265  * @return
 266  *   Pointer to Devx mkey on success, a negative value otherwise and rte_errno
 267  *   is set.
 268  */
 269 struct mlx5_devx_obj *
 270 mlx5_devx_cmd_mkey_create(void *ctx,
 271                           struct mlx5_devx_mkey_attr *attr)
 272 {
 273         struct mlx5_klm *klm_array = attr->klm_array;
 274         int klm_num = attr->klm_num;
 275         int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
 276                      (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
 277         uint32_t in[in_size_dw];
 278         uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
 279         void *mkc;
 280         struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
 281                                                  0, SOCKET_ID_ANY);
 282         size_t pgsize;
 283         uint32_t translation_size;
 284
 285         if (!mkey) {
 286                 rte_errno = ENOMEM;
 287                 return NULL;
 288         }
 289         memset(in, 0, in_size_dw * 4);
 290         pgsize = rte_mem_page_size();
 291         if (pgsize == (size_t)-1) {
 292                 mlx5_free(mkey);
 293                 DRV_LOG(ERR, "Failed to get page size");
 294                 rte_errno = ENOMEM;
 295                 return NULL;
 296         }
 297         MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
 298         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 299         if (klm_num > 0) {
 300                 int i;
 301                 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
 302                                                        klm_pas_mtt);
 303                 translation_size = RTE_ALIGN(klm_num, 4);
 304                 for (i = 0; i < klm_num; i++) {
 305                         MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
 306                         MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
 307                         MLX5_SET64(klm, klm, address, klm_array[i].address);
 308                         klm += MLX5_ST_SZ_BYTES(klm);
 309                 }
 310                 for (; i < (int)translation_size; i++) {
 311                         MLX5_SET(klm, klm, mkey, 0x0);
 312                         MLX5_SET64(klm, klm, address, 0x0);
 313                         klm += MLX5_ST_SZ_BYTES(klm);
 314                 }
 315                 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
 316                          MLX5_MKC_ACCESS_MODE_KLM_FBS :
 317                          MLX5_MKC_ACCESS_MODE_KLM);
 318                 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
 319         } else {
 320                 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
 321                 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 322                 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
 323         }
 324         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 325                  translation_size);
 326         MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
 327         MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
 328         MLX5_SET(mkc, mkc, lw, 0x1);
 329         MLX5_SET(mkc, mkc, lr, 0x1);
 330         if (attr->set_remote_rw) {
 331                 MLX5_SET(mkc, mkc, rw, 0x1);
 332                 MLX5_SET(mkc, mkc, rr, 0x1);
 333         }
 334         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 335         MLX5_SET(mkc, mkc, pd, attr->pd);
 336         MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
 337         MLX5_SET(mkc, mkc, umr_en, attr->umr_en);
 338         MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
 339         MLX5_SET(mkc, mkc, relaxed_ordering_write,
 340                  attr->relaxed_ordering_write);
 341         MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read);
 342         MLX5_SET64(mkc, mkc, start_addr, attr->addr);
 343         MLX5_SET64(mkc, mkc, len, attr->size);
 344         MLX5_SET(mkc, mkc, crypto_en, attr->crypto_en);
 345         if (attr->crypto_en) {
 346                 MLX5_SET(mkc, mkc, bsf_en, attr->crypto_en);
 347                 MLX5_SET(mkc, mkc, bsf_octword_size, 4);
 348         }
 349         mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
 350                                                sizeof(out));
 351         if (!mkey->obj) {
 352                 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d",
 353                         klm_num ? "an in" : "a ", errno);
 354                 rte_errno = errno;
 355                 mlx5_free(mkey);
 356                 return NULL;
 357         }
 358         mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
 359         mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
 360         return mkey;
 361 }
 362
 363 /**
 364  * Get status of devx command response.
 365  * Mainly used for asynchronous commands.
 366  *
 367  * @param[in] out
 368  *   The out response buffer.
 369  *
 370  * @return
 371  *   0 on success, non-zero value otherwise.
 372  */
 373 int
 374 mlx5_devx_get_out_command_status(void *out)
 375 {
 376         int status;
 377
 378         if (!out)
 379                 return -EINVAL;
 380         status = MLX5_GET(query_flow_counter_out, out, status);
 381         if (status) {
 382                 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
 383
 384                 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status,
 385                         syndrome);
 386         }
 387         return status;
 388 }
 389
 390 /**
 391  * Destroy any object allocated by a Devx API.
 392  *
 393  * @param[in] obj
 394  *   Pointer to a general object.
 395  *
 396  * @return
 397  *   0 on success, a negative value otherwise.
 398  */
 399 int
 400 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
 401 {
 402         int ret;
 403
 404         if (!obj)
 405                 return 0;
 406         ret =  mlx5_glue->devx_obj_destroy(obj->obj);
 407         mlx5_free(obj);
 408         return ret;
 409 }
 410
 411 /**
 412  * Query NIC vport context.
 413  * Fills minimal inline attribute.
 414  *
 415  * @param[in] ctx
 416  *   ibv contexts returned from mlx5dv_open_device.
 417  * @param[in] vport
 418  *   vport index
 419  * @param[out] attr
 420  *   Attributes device values.
 421  *
 422  * @return
 423  *   0 on success, a negative value otherwise.
 424  */
 425 static int
 426 mlx5_devx_cmd_query_nic_vport_context(void *ctx,
 427                                       unsigned int vport,
 428                                       struct mlx5_hca_attr *attr)
 429 {
 430         uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
 431         uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
 432         void *vctx;
 433         int status, syndrome, rc;
 434
 435         /* Query NIC vport context to determine inline mode. */
 436         MLX5_SET(query_nic_vport_context_in, in, opcode,
 437                  MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
 438         MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
 439         if (vport)
 440                 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
 441         rc = mlx5_glue->devx_general_cmd(ctx,
 442                                          in, sizeof(in),
 443                                          out, sizeof(out));
 444         if (rc)
 445                 goto error;
 446         status = MLX5_GET(query_nic_vport_context_out, out, status);
 447         syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
 448         if (status) {
 449                 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
 450                         "status %x, syndrome = %x", status, syndrome);
 451                 return -1;
 452         }
 453         vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
 454                             nic_vport_context);
 455         attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
 456                                            min_wqe_inline_mode);
 457         return 0;
 458 error:
 459         rc = (rc > 0) ? -rc : rc;
 460         return rc;
 461 }
 462
 463 /**
 464  * Query NIC vDPA attributes.
 465  *
 466  * @param[in] ctx
 467  *   Context returned from mlx5 open_device() glue function.
 468  * @param[out] vdpa_attr
 469  *   vDPA Attributes structure to fill.
 470  */
 471 static void
 472 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
 473                                   struct mlx5_hca_vdpa_attr *vdpa_attr)
 474 {
 475         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 476         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 477         void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 478         int status, syndrome, rc;
 479
 480         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 481         MLX5_SET(query_hca_cap_in, in, op_mod,
 482                  MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
 483                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 484         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 485         status = MLX5_GET(query_hca_cap_out, out, status);
 486         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 487         if (rc || status) {
 488                 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities,"
 489                         " status %x, syndrome = %x", status, syndrome);
 490                 vdpa_attr->valid = 0;
 491         } else {
 492                 vdpa_attr->valid = 1;
 493                 vdpa_attr->desc_tunnel_offload_type =
 494                         MLX5_GET(virtio_emulation_cap, hcattr,
 495                                  desc_tunnel_offload_type);
 496                 vdpa_attr->eth_frame_offload_type =
 497                         MLX5_GET(virtio_emulation_cap, hcattr,
 498                                  eth_frame_offload_type);
 499                 vdpa_attr->virtio_version_1_0 =
 500                         MLX5_GET(virtio_emulation_cap, hcattr,
 501                                  virtio_version_1_0);
 502                 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
 503                                                tso_ipv4);
 504                 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
 505                                                tso_ipv6);
 506                 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 507                                               tx_csum);
 508                 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 509                                               rx_csum);
 510                 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
 511                                                  event_mode);
 512                 vdpa_attr->virtio_queue_type =
 513                         MLX5_GET(virtio_emulation_cap, hcattr,
 514                                  virtio_queue_type);
 515                 vdpa_attr->log_doorbell_stride =
 516                         MLX5_GET(virtio_emulation_cap, hcattr,
 517                                  log_doorbell_stride);
 518                 vdpa_attr->log_doorbell_bar_size =
 519                         MLX5_GET(virtio_emulation_cap, hcattr,
 520                                  log_doorbell_bar_size);
 521                 vdpa_attr->doorbell_bar_offset =
 522                         MLX5_GET64(virtio_emulation_cap, hcattr,
 523                                    doorbell_bar_offset);
 524                 vdpa_attr->max_num_virtio_queues =
 525                         MLX5_GET(virtio_emulation_cap, hcattr,
 526                                  max_num_virtio_queues);
 527                 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
 528                                                  umem_1_buffer_param_a);
 529                 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
 530                                                  umem_1_buffer_param_b);
 531                 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
 532                                                  umem_2_buffer_param_a);
 533                 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
 534                                                  umem_2_buffer_param_b);
 535                 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
 536                                                  umem_3_buffer_param_a);
 537                 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
 538                                                  umem_3_buffer_param_b);
 539         }
 540 }
 541
 542 int
 543 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
 544                                   uint32_t ids[], uint32_t num)
 545 {
 546         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
 547         uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
 548         void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
 549         void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
 550         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 551         int ret;
 552         uint32_t idx = 0;
 553         uint32_t i;
 554
 555         if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
 556                 rte_errno = EINVAL;
 557                 DRV_LOG(ERR, "Too many sample IDs to be fetched.");
 558                 return -rte_errno;
 559         }
 560         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 561                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
 562         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 563                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 564         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
 565         ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
 566                                         out, sizeof(out));
 567         if (ret) {
 568                 rte_errno = ret;
 569                 DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
 570                         (void *)flex_obj);
 571                 return -rte_errno;
 572         }
 573         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 574                 void *s_off = (void *)((char *)sample + i *
 575                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 576                 uint32_t en;
 577
 578                 en = MLX5_GET(parse_graph_flow_match_sample, s_off,
 579                               flow_match_sample_en);
 580                 if (!en)
 581                         continue;
 582                 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
 583                                   flow_match_sample_field_id);
 584         }
 585         if (num != idx) {
 586                 rte_errno = EINVAL;
 587                 DRV_LOG(ERR, "Number of sample IDs are not as expected.");
 588                 return -rte_errno;
 589         }
 590         return ret;
 591 }
 592
 593
 594 struct mlx5_devx_obj *
 595 mlx5_devx_cmd_create_flex_parser(void *ctx,
 596                               struct mlx5_devx_graph_node_attr *data)
 597 {
 598         uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
 599         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
 600         void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
 601         void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
 602         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 603         void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
 604         void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
 605         struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc
 606                      (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY);
 607         uint32_t i;
 608
 609         if (!parse_flex_obj) {
 610                 DRV_LOG(ERR, "Failed to allocate flex parser data.");
 611                 rte_errno = ENOMEM;
 612                 return NULL;
 613         }
 614         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 615                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
 616         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 617                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 618         MLX5_SET(parse_graph_flex, flex, header_length_mode,
 619                  data->header_length_mode);
 620         MLX5_SET(parse_graph_flex, flex, header_length_base_value,
 621                  data->header_length_base_value);
 622         MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
 623                  data->header_length_field_offset);
 624         MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
 625                  data->header_length_field_shift);
 626         MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
 627                  data->header_length_field_mask);
 628         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 629                 struct mlx5_devx_match_sample_attr *s = &data->sample[i];
 630                 void *s_off = (void *)((char *)sample + i *
 631                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 632
 633                 if (!s->flow_match_sample_en)
 634                         continue;
 635                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 636                          flow_match_sample_en, !!s->flow_match_sample_en);
 637                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 638                          flow_match_sample_field_offset,
 639                          s->flow_match_sample_field_offset);
 640                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 641                          flow_match_sample_offset_mode,
 642                          s->flow_match_sample_offset_mode);
 643                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 644                          flow_match_sample_field_offset_mask,
 645                          s->flow_match_sample_field_offset_mask);
 646                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 647                          flow_match_sample_field_offset_shift,
 648                          s->flow_match_sample_field_offset_shift);
 649                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 650                          flow_match_sample_field_base_offset,
 651                          s->flow_match_sample_field_base_offset);
 652                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 653                          flow_match_sample_tunnel_mode,
 654                          s->flow_match_sample_tunnel_mode);
 655         }
 656         for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
 657                 struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
 658                 struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
 659                 void *in_off = (void *)((char *)in_arc + i *
 660                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 661                 void *out_off = (void *)((char *)out_arc + i *
 662                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 663
 664                 if (ia->arc_parse_graph_node != 0) {
 665                         MLX5_SET(parse_graph_arc, in_off,
 666                                  compare_condition_value,
 667                                  ia->compare_condition_value);
 668                         MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
 669                                  ia->start_inner_tunnel);
 670                         MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
 671                                  ia->arc_parse_graph_node);
 672                         MLX5_SET(parse_graph_arc, in_off,
 673                                  parse_graph_node_handle,
 674                                  ia->parse_graph_node_handle);
 675                 }
 676                 if (oa->arc_parse_graph_node != 0) {
 677                         MLX5_SET(parse_graph_arc, out_off,
 678                                  compare_condition_value,
 679                                  oa->compare_condition_value);
 680                         MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
 681                                  oa->start_inner_tunnel);
 682                         MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
 683                                  oa->arc_parse_graph_node);
 684                         MLX5_SET(parse_graph_arc, out_off,
 685                                  parse_graph_node_handle,
 686                                  oa->parse_graph_node_handle);
 687                 }
 688         }
 689         parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 690                                                          out, sizeof(out));
 691         if (!parse_flex_obj->obj) {
 692                 rte_errno = errno;
 693                 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object "
 694                         "by using DevX.");
 695                 mlx5_free(parse_flex_obj);
 696                 return NULL;
 697         }
 698         parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
 699         return parse_flex_obj;
 700 }
 701
 702 static int
 703 mlx5_devx_query_pkt_integrity_match(void *hcattr)
 704 {
 705         return MLX5_GET(flow_table_nic_cap, hcattr,
 706                         ft_field_support_2_nic_receive.inner_l3_ok) &&
 707                MLX5_GET(flow_table_nic_cap, hcattr,
 708                         ft_field_support_2_nic_receive.inner_l4_ok) &&
 709                MLX5_GET(flow_table_nic_cap, hcattr,
 710                         ft_field_support_2_nic_receive.outer_l3_ok) &&
 711                MLX5_GET(flow_table_nic_cap, hcattr,
 712                         ft_field_support_2_nic_receive.outer_l4_ok) &&
 713                MLX5_GET(flow_table_nic_cap, hcattr,
 714                         ft_field_support_2_nic_receive
 715                                 .inner_ipv4_checksum_ok) &&
 716                MLX5_GET(flow_table_nic_cap, hcattr,
 717                         ft_field_support_2_nic_receive.inner_l4_checksum_ok) &&
 718                MLX5_GET(flow_table_nic_cap, hcattr,
 719                         ft_field_support_2_nic_receive
 720                                 .outer_ipv4_checksum_ok) &&
 721                MLX5_GET(flow_table_nic_cap, hcattr,
 722                         ft_field_support_2_nic_receive.outer_l4_checksum_ok);
 723 }
 724
 725 /**
 726  * Query HCA attributes.
 727  * Using those attributes we can check on run time if the device
 728  * is having the required capabilities.
 729  *
 730  * @param[in] ctx
 731  *   Context returned from mlx5 open_device() glue function.
 732  * @param[out] attr
 733  *   Attributes device values.
 734  *
 735  * @return
 736  *   0 on success, a negative value otherwise.
 737  */
 738 int
 739 mlx5_devx_cmd_query_hca_attr(void *ctx,
 740                              struct mlx5_hca_attr *attr)
 741 {
 742         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 743         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 744         void *hcattr;
 745         int status, syndrome, rc, i;
 746         uint64_t general_obj_types_supported = 0;
 747
 748         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 749         MLX5_SET(query_hca_cap_in, in, op_mod,
 750                  MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
 751                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 752
 753         rc = mlx5_glue->devx_general_cmd(ctx,
 754                                          in, sizeof(in), out, sizeof(out));
 755         if (rc)
 756                 goto error;
 757         status = MLX5_GET(query_hca_cap_out, out, status);
 758         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 759         if (status) {
 760                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 761                         "status %x, syndrome = %x", status, syndrome);
 762                 return -1;
 763         }
 764         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 765         attr->flow_counter_bulk_alloc_bitmap =
 766                         MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
 767         attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
 768                                             flow_counters_dump);
 769         attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
 770                                           log_max_rqt_size);
 771         attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
 772         attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
 773         attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
 774                                                 log_max_hairpin_queues);
 775         attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
 776                                                     log_max_hairpin_wq_data_sz);
 777         attr->log_max_hairpin_num_packets = MLX5_GET
 778                 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
 779         attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
 780         attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
 781                                                 relaxed_ordering_write);
 782         attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
 783                                                relaxed_ordering_read);
 784         attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
 785                                               access_register_user);
 786         attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
 787                                           eth_net_offloads);
 788         attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
 789         attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
 790                                                flex_parser_protocols);
 791         attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr,
 792                         max_geneve_tlv_options);
 793         attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,
 794                         max_geneve_tlv_option_data_len);
 795         attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
 796         attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 797                                          general_obj_types) &
 798                               MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO);
 799         attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 800                                          general_obj_types) &
 801                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 802         attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 803                                                         general_obj_types) &
 804                                   MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
 805         attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 806                                          general_obj_types) &
 807                               MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
 808         attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
 809                                           wqe_index_ignore_cap);
 810         attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
 811         attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
 812         attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
 813                                               log_max_static_sq_wq);
 814         attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);
 815         attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
 816                                       device_frequency_khz);
 817         attr->scatter_fcs_w_decap_disable =
 818                 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
 819         attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce);
 820         attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format);
 821         attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);
 822         attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp);
 823         attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
 824                                                regexp_num_of_engines);
 825         /* Read the general_obj_types bitmap and extract the relevant bits. */
 826         general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr,
 827                                                  general_obj_types);
 828         attr->vdpa.valid = !!(general_obj_types_supported &
 829                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 830         attr->vdpa.queue_counters_valid =
 831                         !!(general_obj_types_supported &
 832                            MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
 833         attr->parse_graph_flex_node =
 834                         !!(general_obj_types_supported &
 835                            MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
 836         attr->flow_hit_aso = !!(general_obj_types_supported &
 837                                 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
 838         attr->geneve_tlv_opt = !!(general_obj_types_supported &
 839                                   MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);
 840         attr->dek = !!(general_obj_types_supported &
 841                        MLX5_GENERAL_OBJ_TYPES_CAP_DEK);
 842         attr->import_kek = !!(general_obj_types_supported &
 843                               MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK);
 844         attr->credential = !!(general_obj_types_supported &
 845                               MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL);
 846         attr->crypto_login = !!(general_obj_types_supported &
 847                                 MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN);
 848         /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */
 849         attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);
 850         attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);
 851         attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);
 852         attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);
 853         attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);
 854         attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
 855         attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
 856         attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
 857         attr->reg_c_preserve =
 858                 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);
 859         attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo);
 860         attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress);
 861         attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress);
 862         attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
 863                                                  compress_min_block_size);
 864         attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
 865         attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
 866                                               log_compress_mmo_size);
 867         attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
 868                                                 log_decompress_mmo_size);
 869         attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
 870         attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
 871                                                 mini_cqe_resp_flow_tag);
 872         attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
 873                                                  mini_cqe_resp_l3_l4_tag);
 874         attr->umr_indirect_mkey_disabled =
 875                 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
 876         attr->umr_modify_entity_size_disabled =
 877                 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);
 878         attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto);
 879         if (attr->crypto)
 880                 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts);
 881         attr->ct_offload = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 882                                          general_obj_types) &
 883                               MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD);
 884         if (attr->qos.sup) {
 885                 MLX5_SET(query_hca_cap_in, in, op_mod,
 886                          MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
 887                          MLX5_HCA_CAP_OPMOD_GET_CUR);
 888                 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
 889                                                  out, sizeof(out));
 890                 if (rc)
 891                         goto error;
 892                 if (status) {
 893                         DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
 894                                 " status %x, syndrome = %x", status, syndrome);
 895                         return -1;
 896                 }
 897                 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 898                 attr->qos.flow_meter_old =
 899                                 MLX5_GET(qos_cap, hcattr, flow_meter_old);
 900                 attr->qos.log_max_flow_meter =
 901                                 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
 902                 attr->qos.flow_meter_reg_c_ids =
 903                                 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
 904                 attr->qos.flow_meter =
 905                                 MLX5_GET(qos_cap, hcattr, flow_meter);
 906                 attr->qos.packet_pacing =
 907                                 MLX5_GET(qos_cap, hcattr, packet_pacing);
 908                 attr->qos.wqe_rate_pp =
 909                                 MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
 910                 if (attr->qos.flow_meter_aso_sup) {
 911                         attr->qos.log_meter_aso_granularity =
 912                                 MLX5_GET(qos_cap, hcattr,
 913                                         log_meter_aso_granularity);
 914                         attr->qos.log_meter_aso_max_alloc =
 915                                 MLX5_GET(qos_cap, hcattr,
 916                                         log_meter_aso_max_alloc);
 917                         attr->qos.log_max_num_meter_aso =
 918                                 MLX5_GET(qos_cap, hcattr,
 919                                         log_max_num_meter_aso);
 920                 }
 921         }
 922         if (attr->vdpa.valid)
 923                 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
 924         if (!attr->eth_net_offloads)
 925                 return 0;
 926
 927         /* Query Flow Sampler Capability From FLow Table Properties Layout. */
 928         memset(in, 0, sizeof(in));
 929         memset(out, 0, sizeof(out));
 930         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 931         MLX5_SET(query_hca_cap_in, in, op_mod,
 932                  MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
 933                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 934
 935         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 936         if (rc)
 937                 goto error;
 938         status = MLX5_GET(query_hca_cap_out, out, status);
 939         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 940         if (status) {
 941                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 942                         "status %x, syndrome = %x", status, syndrome);
 943                 attr->log_max_ft_sampler_num = 0;
 944                 return -1;
 945         }
 946         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 947         attr->log_max_ft_sampler_num = MLX5_GET
 948                 (flow_table_nic_cap, hcattr,
 949                  flow_table_properties_nic_receive.log_max_ft_sampler_num);
 950         attr->pkt_integrity_match = mlx5_devx_query_pkt_integrity_match(hcattr);
 951         /* Query HCA offloads for Ethernet protocol. */
 952         memset(in, 0, sizeof(in));
 953         memset(out, 0, sizeof(out));
 954         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 955         MLX5_SET(query_hca_cap_in, in, op_mod,
 956                  MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
 957                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 958
 959         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 960         if (rc) {
 961                 attr->eth_net_offloads = 0;
 962                 goto error;
 963         }
 964         status = MLX5_GET(query_hca_cap_out, out, status);
 965         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 966         if (status) {
 967                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 968                         "status %x, syndrome = %x", status, syndrome);
 969                 attr->eth_net_offloads = 0;
 970                 return -1;
 971         }
 972         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 973         attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
 974                                          hcattr, wqe_vlan_insert);
 975         attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps,
 976                                          hcattr, csum_cap);
 977         attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 978                                  lro_cap);
 979         attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
 980                                         hcattr, tunnel_lro_gre);
 981         attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
 982                                           hcattr, tunnel_lro_vxlan);
 983         attr->lro_max_msg_sz_mode = MLX5_GET
 984                                         (per_protocol_networking_offload_caps,
 985                                          hcattr, lro_max_msg_sz_mode);
 986         for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
 987                 attr->lro_timer_supported_periods[i] =
 988                         MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 989                                  lro_timer_supported_periods[i]);
 990         }
 991         attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
 992                                           hcattr, lro_min_mss_size);
 993         attr->tunnel_stateless_geneve_rx =
 994                             MLX5_GET(per_protocol_networking_offload_caps,
 995                                      hcattr, tunnel_stateless_geneve_rx);
 996         attr->geneve_max_opt_len =
 997                     MLX5_GET(per_protocol_networking_offload_caps,
 998                              hcattr, max_geneve_opt_len);
 999         attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
1000                                          hcattr, wqe_inline_mode);
1001         attr->tunnel_stateless_gtp = MLX5_GET
1002                                         (per_protocol_networking_offload_caps,
1003                                          hcattr, tunnel_stateless_gtp);
1004         attr->rss_ind_tbl_cap = MLX5_GET
1005                                         (per_protocol_networking_offload_caps,
1006                                          hcattr, rss_ind_tbl_cap);
1007         /* Query HCA attribute for ROCE. */
1008         if (attr->roce) {
1009                 memset(in, 0, sizeof(in));
1010                 memset(out, 0, sizeof(out));
1011                 MLX5_SET(query_hca_cap_in, in, opcode,
1012                          MLX5_CMD_OP_QUERY_HCA_CAP);
1013                 MLX5_SET(query_hca_cap_in, in, op_mod,
1014                          MLX5_GET_HCA_CAP_OP_MOD_ROCE |
1015                          MLX5_HCA_CAP_OPMOD_GET_CUR);
1016                 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
1017                                                  out, sizeof(out));
1018                 if (rc)
1019                         goto error;
1020                 status = MLX5_GET(query_hca_cap_out, out, status);
1021                 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
1022                 if (status) {
1023                         DRV_LOG(DEBUG,
1024                                 "Failed to query devx HCA ROCE capabilities, "
1025                                 "status %x, syndrome = %x", status, syndrome);
1026                         return -1;
1027                 }
1028                 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
1029                 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format);
1030         }
1031         if (attr->eth_virt &&
1032             attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) {
1033                 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
1034                 if (rc) {
1035                         attr->eth_virt = 0;
1036                         goto error;
1037                 }
1038         }
1039         return 0;
1040 error:
1041         rc = (rc > 0) ? -rc : rc;
1042         return rc;
1043 }
1044
1045 /**
1046  * Query TIS transport domain from QP verbs object using DevX API.
1047  *
1048  * @param[in] qp
1049  *   Pointer to verbs QP returned by ibv_create_qp .
1050  * @param[in] tis_num
1051  *   TIS number of TIS to query.
1052  * @param[out] tis_td
1053  *   Pointer to TIS transport domain variable, to be set by the routine.
1054  *
1055  * @return
1056  *   0 on success, a negative value otherwise.
1057  */
1058 int
1059 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
1060                               uint32_t *tis_td)
1061 {
1062 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
1063         uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
1064         uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
1065         int rc;
1066         void *tis_ctx;
1067
1068         MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
1069         MLX5_SET(query_tis_in, in, tisn, tis_num);
1070         rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
1071         if (rc) {
1072                 DRV_LOG(ERR, "Failed to query QP using DevX");
1073                 return -rc;
1074         };
1075         tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
1076         *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
1077         return 0;
1078 #else
1079         (void)qp;
1080         (void)tis_num;
1081         (void)tis_td;
1082         return -ENOTSUP;
1083 #endif
1084 }
1085
1086 /**
1087  * Fill WQ data for DevX API command.
1088  * Utility function for use when creating DevX objects containing a WQ.
1089  *
1090  * @param[in] wq_ctx
1091  *   Pointer to WQ context to fill with data.
1092  * @param [in] wq_attr
1093  *   Pointer to WQ attributes structure to fill in WQ context.
1094  */
1095 static void
1096 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
1097 {
1098         MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
1099         MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
1100         MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
1101         MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
1102         MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
1103         MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
1104         MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
1105         MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
1106         MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
1107         MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
1108         MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
1109         MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
1110         MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
1111         MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
1112         if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT)
1113                 MLX5_SET(wq, wq_ctx, log_wq_pg_sz,
1114                          wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT);
1115         MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
1116         MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
1117         MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
1118         MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
1119                  wq_attr->log_hairpin_num_packets);
1120         MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
1121         MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
1122                  wq_attr->single_wqe_log_num_of_strides);
1123         MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
1124         MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
1125                  wq_attr->single_stride_log_num_of_bytes);
1126         MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
1127         MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
1128         MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
1129 }
1130
1131 /**
1132  * Create RQ using DevX API.
1133  *
1134  * @param[in] ctx
1135  *   Context returned from mlx5 open_device() glue function.
1136  * @param [in] rq_attr
1137  *   Pointer to create RQ attributes structure.
1138  * @param [in] socket
1139  *   CPU socket ID for allocations.
1140  *
1141  * @return
1142  *   The DevX object created, NULL otherwise and rte_errno is set.
1143  */
1144 struct mlx5_devx_obj *
1145 mlx5_devx_cmd_create_rq(void *ctx,
1146                         struct mlx5_devx_create_rq_attr *rq_attr,
1147                         int socket)
1148 {
1149         uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
1150         uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
1151         void *rq_ctx, *wq_ctx;
1152         struct mlx5_devx_wq_attr *wq_attr;
1153         struct mlx5_devx_obj *rq = NULL;
1154
1155         rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
1156         if (!rq) {
1157                 DRV_LOG(ERR, "Failed to allocate RQ data");
1158                 rte_errno = ENOMEM;
1159                 return NULL;
1160         }
1161         MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
1162         rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
1163         MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
1164         MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
1165         MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1166         MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1167         MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
1168         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1169         MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
1170         MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
1171         MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
1172         MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
1173         MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1174         MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
1175         MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format);
1176         wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1177         wq_attr = &rq_attr->wq_attr;
1178         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1179         rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1180                                                   out, sizeof(out));
1181         if (!rq->obj) {
1182                 DRV_LOG(ERR, "Failed to create RQ using DevX");
1183                 rte_errno = errno;
1184                 mlx5_free(rq);
1185                 return NULL;
1186         }
1187         rq->id = MLX5_GET(create_rq_out, out, rqn);
1188         return rq;
1189 }
1190
1191 /**
1192  * Modify RQ using DevX API.
1193  *
1194  * @param[in] rq
1195  *   Pointer to RQ object structure.
1196  * @param [in] rq_attr
1197  *   Pointer to modify RQ attributes structure.
1198  *
1199  * @return
1200  *   0 on success, a negative errno value otherwise and rte_errno is set.
1201  */
1202 int
1203 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1204                         struct mlx5_devx_modify_rq_attr *rq_attr)
1205 {
1206         uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1207         uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1208         void *rq_ctx, *wq_ctx;
1209         int ret;
1210
1211         MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1212         MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1213         MLX5_SET(modify_rq_in, in, rqn, rq->id);
1214         MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1215         rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1216         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1217         if (rq_attr->modify_bitmask &
1218                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1219                 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1220         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1221                 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1222         if (rq_attr->modify_bitmask &
1223                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1224                 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1225         MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1226         MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1227         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1228                 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1229                 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1230         }
1231         ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1232                                          out, sizeof(out));
1233         if (ret) {
1234                 DRV_LOG(ERR, "Failed to modify RQ using DevX");
1235                 rte_errno = errno;
1236                 return -errno;
1237         }
1238         return ret;
1239 }
1240
1241 /**
1242  * Create TIR using DevX API.
1243  *
1244  * @param[in] ctx
1245  *  Context returned from mlx5 open_device() glue function.
1246  * @param [in] tir_attr
1247  *   Pointer to TIR attributes structure.
1248  *
1249  * @return
1250  *   The DevX object created, NULL otherwise and rte_errno is set.
1251  */
1252 struct mlx5_devx_obj *
1253 mlx5_devx_cmd_create_tir(void *ctx,
1254                          struct mlx5_devx_tir_attr *tir_attr)
1255 {
1256         uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1257         uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1258         void *tir_ctx, *outer, *inner, *rss_key;
1259         struct mlx5_devx_obj *tir = NULL;
1260
1261         tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1262         if (!tir) {
1263                 DRV_LOG(ERR, "Failed to allocate TIR data");
1264                 rte_errno = ENOMEM;
1265                 return NULL;
1266         }
1267         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1268         tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1269         MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1270         MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1271                  tir_attr->lro_timeout_period_usecs);
1272         MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1273         MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1274         MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1275         MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1276         MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1277                  tir_attr->tunneled_offload_en);
1278         MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1279         MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1280         MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1281         MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1282         rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1283         memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1284         outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1285         MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1286                  tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1287         MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1288                  tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1289         MLX5_SET(rx_hash_field_select, outer, selected_fields,
1290                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1291         inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1292         MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1293                  tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1294         MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1295                  tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1296         MLX5_SET(rx_hash_field_select, inner, selected_fields,
1297                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1298         tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1299                                                    out, sizeof(out));
1300         if (!tir->obj) {
1301                 DRV_LOG(ERR, "Failed to create TIR using DevX");
1302                 rte_errno = errno;
1303                 mlx5_free(tir);
1304                 return NULL;
1305         }
1306         tir->id = MLX5_GET(create_tir_out, out, tirn);
1307         return tir;
1308 }
1309
1310 /**
1311  * Modify TIR using DevX API.
1312  *
1313  * @param[in] tir
1314  *   Pointer to TIR DevX object structure.
1315  * @param [in] modify_tir_attr
1316  *   Pointer to TIR modification attributes structure.
1317  *
1318  * @return
1319  *   0 on success, a negative errno value otherwise and rte_errno is set.
1320  */
1321 int
1322 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
1323                          struct mlx5_devx_modify_tir_attr *modify_tir_attr)
1324 {
1325         struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
1326         uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
1327         uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
1328         void *tir_ctx;
1329         int ret;
1330
1331         MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
1332         MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
1333         MLX5_SET64(modify_tir_in, in, modify_bitmask,
1334                    modify_tir_attr->modify_bitmask);
1335         tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1336         if (modify_tir_attr->modify_bitmask &
1337                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
1338                 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1339                          tir_attr->lro_timeout_period_usecs);
1340                 MLX5_SET(tirc, tir_ctx, lro_enable_mask,
1341                          tir_attr->lro_enable_mask);
1342                 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
1343                          tir_attr->lro_max_msg_sz);
1344         }
1345         if (modify_tir_attr->modify_bitmask &
1346                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
1347                 MLX5_SET(tirc, tir_ctx, indirect_table,
1348                          tir_attr->indirect_table);
1349         if (modify_tir_attr->modify_bitmask &
1350                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
1351                 int i;
1352                 void *outer, *inner;
1353
1354                 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
1355                          tir_attr->rx_hash_symmetric);
1356                 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1357                 for (i = 0; i < 10; i++) {
1358                         MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
1359                                  tir_attr->rx_hash_toeplitz_key[i]);
1360                 }
1361                 outer = MLX5_ADDR_OF(tirc, tir_ctx,
1362                                      rx_hash_field_selector_outer);
1363                 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1364                          tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1365                 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1366                          tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1367                 MLX5_SET
1368                 (rx_hash_field_select, outer, selected_fields,
1369                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1370                 inner = MLX5_ADDR_OF(tirc, tir_ctx,
1371                                      rx_hash_field_selector_inner);
1372                 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1373                          tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1374                 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1375                          tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1376                 MLX5_SET
1377                 (rx_hash_field_select, inner, selected_fields,
1378                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1379         }
1380         if (modify_tir_attr->modify_bitmask &
1381             MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
1382                 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1383         }
1384         ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
1385                                          out, sizeof(out));
1386         if (ret) {
1387                 DRV_LOG(ERR, "Failed to modify TIR using DevX");
1388                 rte_errno = errno;
1389                 return -errno;
1390         }
1391         return ret;
1392 }
1393
1394 /**
1395  * Create RQT using DevX API.
1396  *
1397  * @param[in] ctx
1398  *   Context returned from mlx5 open_device() glue function.
1399  * @param [in] rqt_attr
1400  *   Pointer to RQT attributes structure.
1401  *
1402  * @return
1403  *   The DevX object created, NULL otherwise and rte_errno is set.
1404  */
1405 struct mlx5_devx_obj *
1406 mlx5_devx_cmd_create_rqt(void *ctx,
1407                          struct mlx5_devx_rqt_attr *rqt_attr)
1408 {
1409         uint32_t *in = NULL;
1410         uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1411                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1412         uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1413         void *rqt_ctx;
1414         struct mlx5_devx_obj *rqt = NULL;
1415         int i;
1416
1417         in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1418         if (!in) {
1419                 DRV_LOG(ERR, "Failed to allocate RQT IN data");
1420                 rte_errno = ENOMEM;
1421                 return NULL;
1422         }
1423         rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1424         if (!rqt) {
1425                 DRV_LOG(ERR, "Failed to allocate RQT data");
1426                 rte_errno = ENOMEM;
1427                 mlx5_free(in);
1428                 return NULL;
1429         }
1430         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1431         rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1432         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1433         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1434         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1435         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1436                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1437         rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1438         mlx5_free(in);
1439         if (!rqt->obj) {
1440                 DRV_LOG(ERR, "Failed to create RQT using DevX");
1441                 rte_errno = errno;
1442                 mlx5_free(rqt);
1443                 return NULL;
1444         }
1445         rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1446         return rqt;
1447 }
1448
1449 /**
1450  * Modify RQT using DevX API.
1451  *
1452  * @param[in] rqt
1453  *   Pointer to RQT DevX object structure.
1454  * @param [in] rqt_attr
1455  *   Pointer to RQT attributes structure.
1456  *
1457  * @return
1458  *   0 on success, a negative errno value otherwise and rte_errno is set.
1459  */
1460 int
1461 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1462                          struct mlx5_devx_rqt_attr *rqt_attr)
1463 {
1464         uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1465                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1466         uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1467         uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1468         void *rqt_ctx;
1469         int i;
1470         int ret;
1471
1472         if (!in) {
1473                 DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1474                 rte_errno = ENOMEM;
1475                 return -ENOMEM;
1476         }
1477         MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
1478         MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
1479         MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
1480         rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
1481         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1482         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1483         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1484         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1485                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1486         ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
1487         mlx5_free(in);
1488         if (ret) {
1489                 DRV_LOG(ERR, "Failed to modify RQT using DevX.");
1490                 rte_errno = errno;
1491                 return -rte_errno;
1492         }
1493         return ret;
1494 }
1495
1496 /**
1497  * Create SQ using DevX API.
1498  *
1499  * @param[in] ctx
1500  *   Context returned from mlx5 open_device() glue function.
1501  * @param [in] sq_attr
1502  *   Pointer to SQ attributes structure.
1503  * @param [in] socket
1504  *   CPU socket ID for allocations.
1505  *
1506  * @return
1507  *   The DevX object created, NULL otherwise and rte_errno is set.
1508  **/
1509 struct mlx5_devx_obj *
1510 mlx5_devx_cmd_create_sq(void *ctx,
1511                         struct mlx5_devx_create_sq_attr *sq_attr)
1512 {
1513         uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
1514         uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
1515         void *sq_ctx;
1516         void *wq_ctx;
1517         struct mlx5_devx_wq_attr *wq_attr;
1518         struct mlx5_devx_obj *sq = NULL;
1519
1520         sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
1521         if (!sq) {
1522                 DRV_LOG(ERR, "Failed to allocate SQ data");
1523                 rte_errno = ENOMEM;
1524                 return NULL;
1525         }
1526         MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
1527         sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
1528         MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
1529         MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
1530         MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
1531         MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
1532         MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
1533                  sq_attr->allow_multi_pkt_send_wqe);
1534         MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
1535                  sq_attr->min_wqe_inline_mode);
1536         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1537         MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
1538         MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
1539         MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
1540         MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
1541         MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
1542         MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
1543         MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
1544         MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
1545                  sq_attr->packet_pacing_rate_limit_index);
1546         MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
1547         MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
1548         MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format);
1549         wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
1550         wq_attr = &sq_attr->wq_attr;
1551         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1552         sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1553                                              out, sizeof(out));
1554         if (!sq->obj) {
1555                 DRV_LOG(ERR, "Failed to create SQ using DevX");
1556                 rte_errno = errno;
1557                 mlx5_free(sq);
1558                 return NULL;
1559         }
1560         sq->id = MLX5_GET(create_sq_out, out, sqn);
1561         return sq;
1562 }
1563
1564 /**
1565  * Modify SQ using DevX API.
1566  *
1567  * @param[in] sq
1568  *   Pointer to SQ object structure.
1569  * @param [in] sq_attr
1570  *   Pointer to SQ attributes structure.
1571  *
1572  * @return
1573  *   0 on success, a negative errno value otherwise and rte_errno is set.
1574  */
1575 int
1576 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
1577                         struct mlx5_devx_modify_sq_attr *sq_attr)
1578 {
1579         uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
1580         uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
1581         void *sq_ctx;
1582         int ret;
1583
1584         MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
1585         MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
1586         MLX5_SET(modify_sq_in, in, sqn, sq->id);
1587         sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1588         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1589         MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
1590         MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
1591         ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
1592                                          out, sizeof(out));
1593         if (ret) {
1594                 DRV_LOG(ERR, "Failed to modify SQ using DevX");
1595                 rte_errno = errno;
1596                 return -rte_errno;
1597         }
1598         return ret;
1599 }
1600
1601 /**
1602  * Create TIS using DevX API.
1603  *
1604  * @param[in] ctx
1605  *   Context returned from mlx5 open_device() glue function.
1606  * @param [in] tis_attr
1607  *   Pointer to TIS attributes structure.
1608  *
1609  * @return
1610  *   The DevX object created, NULL otherwise and rte_errno is set.
1611  */
1612 struct mlx5_devx_obj *
1613 mlx5_devx_cmd_create_tis(void *ctx,
1614                          struct mlx5_devx_tis_attr *tis_attr)
1615 {
1616         uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1617         uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
1618         struct mlx5_devx_obj *tis = NULL;
1619         void *tis_ctx;
1620
1621         tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
1622         if (!tis) {
1623                 DRV_LOG(ERR, "Failed to allocate TIS object");
1624                 rte_errno = ENOMEM;
1625                 return NULL;
1626         }
1627         MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
1628         tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
1629         MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1630                  tis_attr->strict_lag_tx_port_affinity);
1631         MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,
1632                  tis_attr->lag_tx_port_affinity);
1633         MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
1634         MLX5_SET(tisc, tis_ctx, transport_domain,
1635                  tis_attr->transport_domain);
1636         tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1637                                               out, sizeof(out));
1638         if (!tis->obj) {
1639                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1640                 rte_errno = errno;
1641                 mlx5_free(tis);
1642                 return NULL;
1643         }
1644         tis->id = MLX5_GET(create_tis_out, out, tisn);
1645         return tis;
1646 }
1647
1648 /**
1649  * Create transport domain using DevX API.
1650  *
1651  * @param[in] ctx
1652  *   Context returned from mlx5 open_device() glue function.
1653  * @return
1654  *   The DevX object created, NULL otherwise and rte_errno is set.
1655  */
1656 struct mlx5_devx_obj *
1657 mlx5_devx_cmd_create_td(void *ctx)
1658 {
1659         uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1660         uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1661         struct mlx5_devx_obj *td = NULL;
1662
1663         td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
1664         if (!td) {
1665                 DRV_LOG(ERR, "Failed to allocate TD object");
1666                 rte_errno = ENOMEM;
1667                 return NULL;
1668         }
1669         MLX5_SET(alloc_transport_domain_in, in, opcode,
1670                  MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1671         td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1672                                              out, sizeof(out));
1673         if (!td->obj) {
1674                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1675                 rte_errno = errno;
1676                 mlx5_free(td);
1677                 return NULL;
1678         }
1679         td->id = MLX5_GET(alloc_transport_domain_out, out,
1680                            transport_domain);
1681         return td;
1682 }
1683
1684 /**
1685  * Dump all flows to file.
1686  *
1687  * @param[in] fdb_domain
1688  *   FDB domain.
1689  * @param[in] rx_domain
1690  *   RX domain.
1691  * @param[in] tx_domain
1692  *   TX domain.
1693  * @param[out] file
1694  *   Pointer to file stream.
1695  *
1696  * @return
1697  *   0 on success, a nagative value otherwise.
1698  */
1699 int
1700 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1701                         void *rx_domain __rte_unused,
1702                         void *tx_domain __rte_unused, FILE *file __rte_unused)
1703 {
1704         int ret = 0;
1705
1706 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1707         if (fdb_domain) {
1708                 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1709                 if (ret)
1710                         return ret;
1711         }
1712         MLX5_ASSERT(rx_domain);
1713         ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1714         if (ret)
1715                 return ret;
1716         MLX5_ASSERT(tx_domain);
1717         ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1718 #else
1719         ret = ENOTSUP;
1720 #endif
1721         return -ret;
1722 }
1723
1724 int
1725 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused,
1726                         FILE *file __rte_unused)
1727 {
1728         int ret = 0;
1729 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE
1730         if (rule_info)
1731                 ret = mlx5_glue->dr_dump_rule(file, rule_info);
1732 #else
1733         ret = ENOTSUP;
1734 #endif
1735         return -ret;
1736 }
1737
1738 /*
1739  * Create CQ using DevX API.
1740  *
1741  * @param[in] ctx
1742  *   Context returned from mlx5 open_device() glue function.
1743  * @param [in] attr
1744  *   Pointer to CQ attributes structure.
1745  *
1746  * @return
1747  *   The DevX object created, NULL otherwise and rte_errno is set.
1748  */
1749 struct mlx5_devx_obj *
1750 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
1751 {
1752         uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
1753         uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
1754         struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1755                                                    sizeof(*cq_obj),
1756                                                    0, SOCKET_ID_ANY);
1757         void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1758
1759         if (!cq_obj) {
1760                 DRV_LOG(ERR, "Failed to allocate CQ object memory.");
1761                 rte_errno = ENOMEM;
1762                 return NULL;
1763         }
1764         MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
1765         if (attr->db_umem_valid) {
1766                 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
1767                 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
1768                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
1769         } else {
1770                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
1771         }
1772         MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ?
1773                                      MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B);
1774         MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
1775         MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
1776         MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
1777         if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
1778                 MLX5_SET(cqc, cqctx, log_page_size,
1779                          attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
1780         MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
1781         MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
1782         MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
1783         MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
1784         MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
1785                  attr->mini_cqe_res_format_ext);
1786         if (attr->q_umem_valid) {
1787                 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
1788                 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
1789                 MLX5_SET64(create_cq_in, in, cq_umem_offset,
1790                            attr->q_umem_offset);
1791         }
1792         cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1793                                                  sizeof(out));
1794         if (!cq_obj->obj) {
1795                 rte_errno = errno;
1796                 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno);
1797                 mlx5_free(cq_obj);
1798                 return NULL;
1799         }
1800         cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
1801         return cq_obj;
1802 }
1803
1804 /**
1805  * Create VIRTQ using DevX API.
1806  *
1807  * @param[in] ctx
1808  *   Context returned from mlx5 open_device() glue function.
1809  * @param [in] attr
1810  *   Pointer to VIRTQ attributes structure.
1811  *
1812  * @return
1813  *   The DevX object created, NULL otherwise and rte_errno is set.
1814  */
1815 struct mlx5_devx_obj *
1816 mlx5_devx_cmd_create_virtq(void *ctx,
1817                            struct mlx5_devx_virtq_attr *attr)
1818 {
1819         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1820         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1821         struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1822                                                      sizeof(*virtq_obj),
1823                                                      0, SOCKET_ID_ANY);
1824         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1825         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1826         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1827
1828         if (!virtq_obj) {
1829                 DRV_LOG(ERR, "Failed to allocate virtq data.");
1830                 rte_errno = ENOMEM;
1831                 return NULL;
1832         }
1833         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1834                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1835         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1836                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1837         MLX5_SET16(virtio_net_q, virtq, hw_available_index,
1838                    attr->hw_available_index);
1839         MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
1840         MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
1841         MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
1842         MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
1843         MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
1844         MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
1845                    attr->virtio_version_1_0);
1846         MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
1847         MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
1848         MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
1849         MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
1850         MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
1851         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1852         MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
1853         MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
1854         MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
1855         MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
1856         MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
1857         MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
1858         MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
1859         MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
1860         MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
1861         MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
1862         MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
1863         MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
1864         MLX5_SET(virtio_q, virtctx, pd, attr->pd);
1865         MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode);
1866         MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us);
1867         MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp);
1868         MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
1869         virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1870                                                     sizeof(out));
1871         if (!virtq_obj->obj) {
1872                 rte_errno = errno;
1873                 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX.");
1874                 mlx5_free(virtq_obj);
1875                 return NULL;
1876         }
1877         virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1878         return virtq_obj;
1879 }
1880
1881 /**
1882  * Modify VIRTQ using DevX API.
1883  *
1884  * @param[in] virtq_obj
1885  *   Pointer to virtq object structure.
1886  * @param [in] attr
1887  *   Pointer to modify virtq attributes structure.
1888  *
1889  * @return
1890  *   0 on success, a negative errno value otherwise and rte_errno is set.
1891  */
1892 int
1893 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
1894                            struct mlx5_devx_virtq_attr *attr)
1895 {
1896         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1897         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1898         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1899         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1900         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1901         int ret;
1902
1903         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1904                  MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
1905         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1906                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1907         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1908         MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);
1909         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1910         switch (attr->type) {
1911         case MLX5_VIRTQ_MODIFY_TYPE_STATE:
1912                 MLX5_SET16(virtio_net_q, virtq, state, attr->state);
1913                 break;
1914         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:
1915                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
1916                          attr->dirty_bitmap_mkey);
1917                 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
1918                          attr->dirty_bitmap_addr);
1919                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
1920                          attr->dirty_bitmap_size);
1921                 break;
1922         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:
1923                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
1924                          attr->dirty_bitmap_dump_enable);
1925                 break;
1926         default:
1927                 rte_errno = EINVAL;
1928                 return -rte_errno;
1929         }
1930         ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
1931                                          out, sizeof(out));
1932         if (ret) {
1933                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1934                 rte_errno = errno;
1935                 return -rte_errno;
1936         }
1937         return ret;
1938 }
1939
1940 /**
1941  * Query VIRTQ using DevX API.
1942  *
1943  * @param[in] virtq_obj
1944  *   Pointer to virtq object structure.
1945  * @param [in/out] attr
1946  *   Pointer to virtq attributes structure.
1947  *
1948  * @return
1949  *   0 on success, a negative errno value otherwise and rte_errno is set.
1950  */
1951 int
1952 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
1953                            struct mlx5_devx_virtq_attr *attr)
1954 {
1955         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
1956         uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
1957         void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
1958         void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
1959         int ret;
1960
1961         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1962                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
1963         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1964                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1965         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1966         ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
1967                                          out, sizeof(out));
1968         if (ret) {
1969                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1970                 rte_errno = errno;
1971                 return -errno;
1972         }
1973         attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
1974                                               hw_available_index);
1975         attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
1976         attr->state = MLX5_GET16(virtio_net_q, virtq, state);
1977         attr->error_type = MLX5_GET16(virtio_net_q, virtq,
1978                                       virtio_q_context.error_type);
1979         return ret;
1980 }
1981
1982 /**
1983  * Create QP using DevX API.
1984  *
1985  * @param[in] ctx
1986  *   Context returned from mlx5 open_device() glue function.
1987  * @param [in] attr
1988  *   Pointer to QP attributes structure.
1989  *
1990  * @return
1991  *   The DevX object created, NULL otherwise and rte_errno is set.
1992  */
1993 struct mlx5_devx_obj *
1994 mlx5_devx_cmd_create_qp(void *ctx,
1995                         struct mlx5_devx_qp_attr *attr)
1996 {
1997         uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
1998         uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
1999         struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
2000                                                    sizeof(*qp_obj),
2001                                                    0, SOCKET_ID_ANY);
2002         void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
2003
2004         if (!qp_obj) {
2005                 DRV_LOG(ERR, "Failed to allocate QP data.");
2006                 rte_errno = ENOMEM;
2007                 return NULL;
2008         }
2009         MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
2010         MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
2011         MLX5_SET(qpc, qpc, pd, attr->pd);
2012         MLX5_SET(qpc, qpc, ts_format, attr->ts_format);
2013         if (attr->uar_index) {
2014                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2015                 MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
2016                 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
2017                         MLX5_SET(qpc, qpc, log_page_size,
2018                                  attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
2019                 if (attr->sq_size) {
2020                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));
2021                         MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
2022                         MLX5_SET(qpc, qpc, log_sq_size,
2023                                  rte_log2_u32(attr->sq_size));
2024                 } else {
2025                         MLX5_SET(qpc, qpc, no_sq, 1);
2026                 }
2027                 if (attr->rq_size) {
2028                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size));
2029                         MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
2030                         MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
2031                                  MLX5_LOG_RQ_STRIDE_SHIFT);
2032                         MLX5_SET(qpc, qpc, log_rq_size,
2033                                  rte_log2_u32(attr->rq_size));
2034                         MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
2035                 } else {
2036                         MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2037                 }
2038                 if (attr->dbr_umem_valid) {
2039                         MLX5_SET(qpc, qpc, dbr_umem_valid,
2040                                  attr->dbr_umem_valid);
2041                         MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
2042                 }
2043                 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
2044                 MLX5_SET64(create_qp_in, in, wq_umem_offset,
2045                            attr->wq_umem_offset);
2046                 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
2047                 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
2048         } else {
2049                 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
2050                 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
2051                 MLX5_SET(qpc, qpc, no_sq, 1);
2052         }
2053         qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2054                                                  sizeof(out));
2055         if (!qp_obj->obj) {
2056                 rte_errno = errno;
2057                 DRV_LOG(ERR, "Failed to create QP Obj using DevX.");
2058                 mlx5_free(qp_obj);
2059                 return NULL;
2060         }
2061         qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
2062         return qp_obj;
2063 }
2064
2065 /**
2066  * Modify QP using DevX API.
2067  * Currently supports only force loop-back QP.
2068  *
2069  * @param[in] qp
2070  *   Pointer to QP object structure.
2071  * @param [in] qp_st_mod_op
2072  *   The QP state modification operation.
2073  * @param [in] remote_qp_id
2074  *   The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
2075  *
2076  * @return
2077  *   0 on success, a negative errno value otherwise and rte_errno is set.
2078  */
2079 int
2080 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
2081                               uint32_t remote_qp_id)
2082 {
2083         union {
2084                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
2085                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
2086                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
2087         } in;
2088         union {
2089                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
2090                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
2091                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
2092         } out;
2093         void *qpc;
2094         int ret;
2095         unsigned int inlen;
2096         unsigned int outlen;
2097
2098         memset(&in, 0, sizeof(in));
2099         memset(&out, 0, sizeof(out));
2100         MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
2101         switch (qp_st_mod_op) {
2102         case MLX5_CMD_OP_RST2INIT_QP:
2103                 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
2104                 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
2105                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2106                 MLX5_SET(qpc, qpc, rre, 1);
2107                 MLX5_SET(qpc, qpc, rwe, 1);
2108                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2109                 inlen = sizeof(in.rst2init);
2110                 outlen = sizeof(out.rst2init);
2111                 break;
2112         case MLX5_CMD_OP_INIT2RTR_QP:
2113                 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
2114                 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
2115                 MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
2116                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2117                 MLX5_SET(qpc, qpc, mtu, 1);
2118                 MLX5_SET(qpc, qpc, log_msg_max, 30);
2119                 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
2120                 MLX5_SET(qpc, qpc, min_rnr_nak, 0);
2121                 inlen = sizeof(in.init2rtr);
2122                 outlen = sizeof(out.init2rtr);
2123                 break;
2124         case MLX5_CMD_OP_RTR2RTS_QP:
2125                 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
2126                 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
2127                 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14);
2128                 MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
2129                 MLX5_SET(qpc, qpc, retry_count, 7);
2130                 MLX5_SET(qpc, qpc, rnr_retry, 7);
2131                 inlen = sizeof(in.rtr2rts);
2132                 outlen = sizeof(out.rtr2rts);
2133                 break;
2134         default:
2135                 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
2136                         qp_st_mod_op);
2137                 rte_errno = EINVAL;
2138                 return -rte_errno;
2139         }
2140         ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
2141         if (ret) {
2142                 DRV_LOG(ERR, "Failed to modify QP using DevX.");
2143                 rte_errno = errno;
2144                 return -rte_errno;
2145         }
2146         return ret;
2147 }
2148
2149 struct mlx5_devx_obj *
2150 mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
2151 {
2152         uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
2153         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2154         struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
2155                                                        sizeof(*couners_obj), 0,
2156                                                        SOCKET_ID_ANY);
2157         void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
2158
2159         if (!couners_obj) {
2160                 DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
2161                 rte_errno = ENOMEM;
2162                 return NULL;
2163         }
2164         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2165                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2166         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2167                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2168         couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2169                                                       sizeof(out));
2170         if (!couners_obj->obj) {
2171                 rte_errno = errno;
2172                 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using"
2173                         " DevX.");
2174                 mlx5_free(couners_obj);
2175                 return NULL;
2176         }
2177         couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2178         return couners_obj;
2179 }
2180
2181 int
2182 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
2183                                    struct mlx5_devx_virtio_q_couners_attr *attr)
2184 {
2185         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2186         uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
2187         void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
2188         void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
2189                                                virtio_q_counters);
2190         int ret;
2191
2192         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2193                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2194         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2195                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2196         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
2197         ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
2198                                         sizeof(out));
2199         if (ret) {
2200                 DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
2201                 rte_errno = errno;
2202                 return -errno;
2203         }
2204         attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2205                                          received_desc);
2206         attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2207                                           completed_desc);
2208         attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
2209                                     error_cqes);
2210         attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
2211                                          bad_desc_errors);
2212         attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
2213                                           exceed_max_chain);
2214         attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
2215                                         invalid_buffer);
2216         return ret;
2217 }
2218
2219 /**
2220  * Create general object of type FLOW_HIT_ASO using DevX API.
2221  *
2222  * @param[in] ctx
2223  *   Context returned from mlx5 open_device() glue function.
2224  * @param [in] pd
2225  *   PD value to associate the FLOW_HIT_ASO object with.
2226  *
2227  * @return
2228  *   The DevX object created, NULL otherwise and rte_errno is set.
2229  */
2230 struct mlx5_devx_obj *
2231 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd)
2232 {
2233         uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0};
2234         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2235         struct mlx5_devx_obj *flow_hit_aso_obj = NULL;
2236         void *ptr = NULL;
2237
2238         flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj),
2239                                        0, SOCKET_ID_ANY);
2240         if (!flow_hit_aso_obj) {
2241                 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data");
2242                 rte_errno = ENOMEM;
2243                 return NULL;
2244         }
2245         ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr);
2246         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2247                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2248         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2249                  MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO);
2250         ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso);
2251         MLX5_SET(flow_hit_aso, ptr, access_pd, pd);
2252         flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2253                                                            out, sizeof(out));
2254         if (!flow_hit_aso_obj->obj) {
2255                 rte_errno = errno;
2256                 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX.");
2257                 mlx5_free(flow_hit_aso_obj);
2258                 return NULL;
2259         }
2260         flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2261         return flow_hit_aso_obj;
2262 }
2263
2264 /*
2265  * Create PD using DevX API.
2266  *
2267  * @param[in] ctx
2268  *   Context returned from mlx5 open_device() glue function.
2269  *
2270  * @return
2271  *   The DevX object created, NULL otherwise and rte_errno is set.
2272  */
2273 struct mlx5_devx_obj *
2274 mlx5_devx_cmd_alloc_pd(void *ctx)
2275 {
2276         struct mlx5_devx_obj *ppd =
2277                 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY);
2278         u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
2279         u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
2280
2281         if (!ppd) {
2282                 DRV_LOG(ERR, "Failed to allocate PD data.");
2283                 rte_errno = ENOMEM;
2284                 return NULL;
2285         }
2286         MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2287         ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2288                                 out, sizeof(out));
2289         if (!ppd->obj) {
2290                 mlx5_free(ppd);
2291                 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX.");
2292                 rte_errno = errno;
2293                 return NULL;
2294         }
2295         ppd->id = MLX5_GET(alloc_pd_out, out, pd);
2296         return ppd;
2297 }
2298
2299 /**
2300  * Create general object of type FLOW_METER_ASO using DevX API.
2301  *
2302  * @param[in] ctx
2303  *   Context returned from mlx5 open_device() glue function.
2304  * @param [in] pd
2305  *   PD value to associate the FLOW_METER_ASO object with.
2306  * @param [in] log_obj_size
2307  *   log_obj_size define to allocate number of 2 * meters
2308  *   in one FLOW_METER_ASO object.
2309  *
2310  * @return
2311  *   The DevX object created, NULL otherwise and rte_errno is set.
2312  */
2313 struct mlx5_devx_obj *
2314 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd,
2315                                                 uint32_t log_obj_size)
2316 {
2317         uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0};
2318         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2319         struct mlx5_devx_obj *flow_meter_aso_obj;
2320         void *ptr;
2321
2322         flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO,
2323                                                 sizeof(*flow_meter_aso_obj),
2324                                                 0, SOCKET_ID_ANY);
2325         if (!flow_meter_aso_obj) {
2326                 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data");
2327                 rte_errno = ENOMEM;
2328                 return NULL;
2329         }
2330         ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr);
2331         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2332                 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2333         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2334                 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO);
2335         MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range,
2336                 log_obj_size);
2337         ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso);
2338         MLX5_SET(flow_meter_aso, ptr, access_pd, pd);
2339         flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create(
2340                                                         ctx, in, sizeof(in),
2341                                                         out, sizeof(out));
2342         if (!flow_meter_aso_obj->obj) {
2343                 rte_errno = errno;
2344                 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX.");
2345                 mlx5_free(flow_meter_aso_obj);
2346                 return NULL;
2347         }
2348         flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr,
2349                                                                 out, obj_id);
2350         return flow_meter_aso_obj;
2351 }
2352
2353 /**
2354  * Create general object of type GENEVE TLV option using DevX API.
2355  *
2356  * @param[in] ctx
2357  *   Context returned from mlx5 open_device() glue function.
2358  * @param [in] class
2359  *   TLV option variable value of class
2360  * @param [in] type
2361  *   TLV option variable value of type
2362  * @param [in] len
2363  *   TLV option variable value of len
2364  *
2365  * @return
2366  *   The DevX object created, NULL otherwise and rte_errno is set.
2367  */
2368 struct mlx5_devx_obj *
2369 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
2370                 uint16_t class, uint8_t type, uint8_t len)
2371 {
2372         uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0};
2373         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2374         struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO,
2375                                                    sizeof(*geneve_tlv_opt_obj),
2376                                                    0, SOCKET_ID_ANY);
2377
2378         if (!geneve_tlv_opt_obj) {
2379                 DRV_LOG(ERR, "Failed to allocate geneve tlv option object.");
2380                 rte_errno = ENOMEM;
2381                 return NULL;
2382         }
2383         void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr);
2384         void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in,
2385                         geneve_tlv_opt);
2386         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2387                         MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2388         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2389                  MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
2390         MLX5_SET(geneve_tlv_option, opt, option_class,
2391                         rte_be_to_cpu_16(class));
2392         MLX5_SET(geneve_tlv_option, opt, option_type, type);
2393         MLX5_SET(geneve_tlv_option, opt, option_data_length, len);
2394         geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,
2395                                         sizeof(in), out, sizeof(out));
2396         if (!geneve_tlv_opt_obj->obj) {
2397                 rte_errno = errno;
2398                 DRV_LOG(ERR, "Failed to create Geneve tlv option "
2399                                 "Obj using DevX.");
2400                 mlx5_free(geneve_tlv_opt_obj);
2401                 return NULL;
2402         }
2403         geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2404         return geneve_tlv_opt_obj;
2405 }
2406
2407 int
2408 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)
2409 {
2410 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2411         uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
2412         uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0};
2413         int rc;
2414         void *rq_ctx;
2415
2416         MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
2417         MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num);
2418         rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out));
2419         if (rc) {
2420                 rte_errno = errno;
2421                 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - "
2422                         "rc = %d, errno = %d.", rc, errno);
2423                 return -rc;
2424         };
2425         rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context);
2426         *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id);
2427         return 0;
2428 #else
2429         (void)wq;
2430         (void)counter_set_id;
2431         return -ENOTSUP;
2432 #endif
2433 }
2434
2435 /*
2436  * Allocate queue counters via devx interface.
2437  *
2438  * @param[in] ctx
2439  *   Context returned from mlx5 open_device() glue function.
2440  *
2441  * @return
2442  *   Pointer to counter object on success, a NULL value otherwise and
2443  *   rte_errno is set.
2444  */
2445 struct mlx5_devx_obj *
2446 mlx5_devx_cmd_queue_counter_alloc(void *ctx)
2447 {
2448         struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0,
2449                                                 SOCKET_ID_ANY);
2450         uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)]   = {0};
2451         uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
2452
2453         if (!dcs) {
2454                 rte_errno = ENOMEM;
2455                 return NULL;
2456         }
2457         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
2458         dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2459                                               sizeof(out));
2460         if (!dcs->obj) {
2461                 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error "
2462                         "%d.", errno);
2463                 rte_errno = errno;
2464                 mlx5_free(dcs);
2465                 return NULL;
2466         }
2467         dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id);
2468         return dcs;
2469 }
2470
2471 /**
2472  * Query queue counters values.
2473  *
2474  * @param[in] dcs
2475  *   devx object of the queue counter set.
2476  * @param[in] clear
2477  *   Whether hardware should clear the counters after the query or not.
2478  *  @param[out] out_of_buffers
2479  *   Number of dropped occurred due to lack of WQE for the associated QPs/RQs.
2480  *
2481  * @return
2482  *   0 on success, a negative value otherwise.
2483  */
2484 int
2485 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
2486                                   uint32_t *out_of_buffers)
2487 {
2488         uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0};
2489         uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0};
2490         int rc;
2491
2492         MLX5_SET(query_q_counter_in, in, opcode,
2493                  MLX5_CMD_OP_QUERY_Q_COUNTER);
2494         MLX5_SET(query_q_counter_in, in, op_mod, 0);
2495         MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id);
2496         MLX5_SET(query_q_counter_in, in, clear, !!clear);
2497         rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
2498                                        sizeof(out));
2499         if (rc) {
2500                 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc);
2501                 rte_errno = rc;
2502                 return -rc;
2503         }
2504         *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer);
2505         return 0;
2506 }
2507
2508 /**
2509  * Create general object of type DEK using DevX API.
2510  *
2511  * @param[in] ctx
2512  *   Context returned from mlx5 open_device() glue function.
2513  * @param [in] attr
2514  *   Pointer to DEK attributes structure.
2515  *
2516  * @return
2517  *   The DevX object created, NULL otherwise and rte_errno is set.
2518  */
2519 struct mlx5_devx_obj *
2520 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr)
2521 {
2522         uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0};
2523         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2524         struct mlx5_devx_obj *dek_obj = NULL;
2525         void *ptr = NULL, *key_addr = NULL;
2526
2527         dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj),
2528                               0, SOCKET_ID_ANY);
2529         if (dek_obj == NULL) {
2530                 DRV_LOG(ERR, "Failed to allocate DEK object data");
2531                 rte_errno = ENOMEM;
2532                 return NULL;
2533         }
2534         ptr = MLX5_ADDR_OF(create_dek_in, in, hdr);
2535         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2536                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2537         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2538                  MLX5_GENERAL_OBJ_TYPE_DEK);
2539         ptr = MLX5_ADDR_OF(create_dek_in, in, dek);
2540         MLX5_SET(dek, ptr, key_size, attr->key_size);
2541         MLX5_SET(dek, ptr, has_keytag, attr->has_keytag);
2542         MLX5_SET(dek, ptr, key_purpose, attr->key_purpose);
2543         MLX5_SET(dek, ptr, pd, attr->pd);
2544         MLX5_SET64(dek, ptr, opaque, attr->opaque);
2545         key_addr = MLX5_ADDR_OF(dek, ptr, key);
2546         memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
2547         dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2548                                                   out, sizeof(out));
2549         if (dek_obj->obj == NULL) {
2550                 rte_errno = errno;
2551                 DRV_LOG(ERR, "Failed to create DEK obj using DevX.");
2552                 mlx5_free(dek_obj);
2553                 return NULL;
2554         }
2555         dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2556         return dek_obj;
2557 }
2558
2559 /**
2560  * Create general object of type IMPORT_KEK using DevX API.
2561  *
2562  * @param[in] ctx
2563  *   Context returned from mlx5 open_device() glue function.
2564  * @param [in] attr
2565  *   Pointer to IMPORT_KEK attributes structure.
2566  *
2567  * @return
2568  *   The DevX object created, NULL otherwise and rte_errno is set.
2569  */
2570 struct mlx5_devx_obj *
2571 mlx5_devx_cmd_create_import_kek_obj(void *ctx,
2572                                     struct mlx5_devx_import_kek_attr *attr)
2573 {
2574         uint32_t in[MLX5_ST_SZ_DW(create_import_kek_in)] = {0};
2575         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2576         struct mlx5_devx_obj *import_kek_obj = NULL;
2577         void *ptr = NULL, *key_addr = NULL;
2578
2579         import_kek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*import_kek_obj),
2580                                      0, SOCKET_ID_ANY);
2581         if (import_kek_obj == NULL) {
2582                 DRV_LOG(ERR, "Failed to allocate IMPORT_KEK object data");
2583                 rte_errno = ENOMEM;
2584                 return NULL;
2585         }
2586         ptr = MLX5_ADDR_OF(create_import_kek_in, in, hdr);
2587         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2588                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2589         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2590                  MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK);
2591         ptr = MLX5_ADDR_OF(create_import_kek_in, in, import_kek);
2592         MLX5_SET(import_kek, ptr, key_size, attr->key_size);
2593         key_addr = MLX5_ADDR_OF(import_kek, ptr, key);
2594         memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
2595         import_kek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2596                                                          out, sizeof(out));
2597         if (import_kek_obj->obj == NULL) {
2598                 rte_errno = errno;
2599                 DRV_LOG(ERR, "Failed to create IMPORT_KEK object using DevX.");
2600                 mlx5_free(import_kek_obj);
2601                 return NULL;
2602         }
2603         import_kek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2604         return import_kek_obj;
2605 }
2606
2607 /**
2608  * Create general object of type CREDENTIAL using DevX API.
2609  *
2610  * @param[in] ctx
2611  *   Context returned from mlx5 open_device() glue function.
2612  * @param [in] attr
2613  *   Pointer to CREDENTIAL attributes structure.
2614  *
2615  * @return
2616  *   The DevX object created, NULL otherwise and rte_errno is set.
2617  */
2618 struct mlx5_devx_obj *
2619 mlx5_devx_cmd_create_credential_obj(void *ctx,
2620                                     struct mlx5_devx_credential_attr *attr)
2621 {
2622         uint32_t in[MLX5_ST_SZ_DW(create_credential_in)] = {0};
2623         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2624         struct mlx5_devx_obj *credential_obj = NULL;
2625         void *ptr = NULL, *credential_addr = NULL;
2626
2627         credential_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*credential_obj),
2628                                      0, SOCKET_ID_ANY);
2629         if (credential_obj == NULL) {
2630                 DRV_LOG(ERR, "Failed to allocate CREDENTIAL object data");
2631                 rte_errno = ENOMEM;
2632                 return NULL;
2633         }
2634         ptr = MLX5_ADDR_OF(create_credential_in, in, hdr);
2635         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2636                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2637         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2638                  MLX5_GENERAL_OBJ_TYPE_CREDENTIAL);
2639         ptr = MLX5_ADDR_OF(create_credential_in, in, credential);
2640         MLX5_SET(credential, ptr, credential_role, attr->credential_role);
2641         credential_addr = MLX5_ADDR_OF(credential, ptr, credential);
2642         memcpy(credential_addr, (void *)(attr->credential),
2643                MLX5_CRYPTO_CREDENTIAL_SIZE);
2644         credential_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2645                                                          out, sizeof(out));
2646         if (credential_obj->obj == NULL) {
2647                 rte_errno = errno;
2648                 DRV_LOG(ERR, "Failed to create CREDENTIAL object using DevX.");
2649                 mlx5_free(credential_obj);
2650                 return NULL;
2651         }
2652         credential_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2653         return credential_obj;
2654 }
2655
2656 /**
2657  * Create general object of type CRYPTO_LOGIN using DevX API.
2658  *
2659  * @param[in] ctx
2660  *   Context returned from mlx5 open_device() glue function.
2661  * @param [in] attr
2662  *   Pointer to CRYPTO_LOGIN attributes structure.
2663  *
2664  * @return
2665  *   The DevX object created, NULL otherwise and rte_errno is set.
2666  */
2667 struct mlx5_devx_obj *
2668 mlx5_devx_cmd_create_crypto_login_obj(void *ctx,
2669                                       struct mlx5_devx_crypto_login_attr *attr)
2670 {
2671         uint32_t in[MLX5_ST_SZ_DW(create_crypto_login_in)] = {0};
2672         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2673         struct mlx5_devx_obj *crypto_login_obj = NULL;
2674         void *ptr = NULL, *credential_addr = NULL;
2675
2676         crypto_login_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*crypto_login_obj),
2677                                        0, SOCKET_ID_ANY);
2678         if (crypto_login_obj == NULL) {
2679                 DRV_LOG(ERR, "Failed to allocate CRYPTO_LOGIN object data");
2680                 rte_errno = ENOMEM;
2681                 return NULL;
2682         }
2683         ptr = MLX5_ADDR_OF(create_crypto_login_in, in, hdr);
2684         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2685                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2686         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2687                  MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN);
2688         ptr = MLX5_ADDR_OF(create_crypto_login_in, in, crypto_login);
2689         MLX5_SET(crypto_login, ptr, credential_pointer,
2690                  attr->credential_pointer);
2691         MLX5_SET(crypto_login, ptr, session_import_kek_ptr,
2692                  attr->session_import_kek_ptr);
2693         credential_addr = MLX5_ADDR_OF(crypto_login, ptr, credential);
2694         memcpy(credential_addr, (void *)(attr->credential),
2695                MLX5_CRYPTO_CREDENTIAL_SIZE);
2696         crypto_login_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2697                                                            out, sizeof(out));
2698         if (crypto_login_obj->obj == NULL) {
2699                 rte_errno = errno;
2700                 DRV_LOG(ERR, "Failed to create CRYPTO_LOGIN obj using DevX.");
2701                 mlx5_free(crypto_login_obj);
2702                 return NULL;
2703         }
2704         crypto_login_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2705         return crypto_login_obj;
2706 }