drivers/common/mlx5/mlx5_devx_cmds.c

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /* Copyright 2018 Mellanox Technologies, Ltd */
   3
   4 #include <unistd.h>
   5
   6 #include <rte_errno.h>
   7 #include <rte_malloc.h>
   8 #include <rte_eal_paging.h>
   9
  10 #include "mlx5_prm.h"
  11 #include "mlx5_devx_cmds.h"
  12 #include "mlx5_common_utils.h"
  13 #include "mlx5_malloc.h"
  14
  15
  16 /**
  17  * Perform read access to the registers. Reads data from register
  18  * and writes ones to the specified buffer.
  19  *
  20  * @param[in] ctx
  21  *   Context returned from mlx5 open_device() glue function.
  22  * @param[in] reg_id
  23  *   Register identifier according to the PRM.
  24  * @param[in] arg
  25  *   Register access auxiliary parameter according to the PRM.
  26  * @param[out] data
  27  *   Pointer to the buffer to store read data.
  28  * @param[in] dw_cnt
  29  *   Buffer size in double words.
  30  *
  31  * @return
  32  *   0 on success, a negative value otherwise.
  33  */
  34 int
  35 mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,
  36                             uint32_t *data, uint32_t dw_cnt)
  37 {
  38         uint32_t in[MLX5_ST_SZ_DW(access_register_in)]   = {0};
  39         uint32_t out[MLX5_ST_SZ_DW(access_register_out) +
  40                      MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};
  41         int status, rc;
  42
  43         MLX5_ASSERT(data && dw_cnt);
  44         MLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);
  45         if (dw_cnt  > MLX5_ACCESS_REGISTER_DATA_DWORD_MAX) {
  46                 DRV_LOG(ERR, "Not enough  buffer for register read data");
  47                 return -1;
  48         }
  49         MLX5_SET(access_register_in, in, opcode,
  50                  MLX5_CMD_OP_ACCESS_REGISTER_USER);
  51         MLX5_SET(access_register_in, in, op_mod,
  52                                         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ);
  53         MLX5_SET(access_register_in, in, register_id, reg_id);
  54         MLX5_SET(access_register_in, in, argument, arg);
  55         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
  56                                          MLX5_ST_SZ_BYTES(access_register_out) +
  57                                          sizeof(uint32_t) * dw_cnt);
  58         if (rc)
  59                 goto error;
  60         status = MLX5_GET(access_register_out, out, status);
  61         if (status) {
  62                 int syndrome = MLX5_GET(access_register_out, out, syndrome);
  63
  64                 DRV_LOG(DEBUG, "Failed to access NIC register 0x%X, "
  65                                "status %x, syndrome = %x",
  66                                reg_id, status, syndrome);
  67                 return -1;
  68         }
  69         memcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],
  70                dw_cnt * sizeof(uint32_t));
  71         return 0;
  72 error:
  73         rc = (rc > 0) ? -rc : rc;
  74         return rc;
  75 }
  76
  77 /**
  78  * Allocate flow counters via devx interface.
  79  *
  80  * @param[in] ctx
  81  *   Context returned from mlx5 open_device() glue function.
  82  * @param dcs
  83  *   Pointer to counters properties structure to be filled by the routine.
  84  * @param bulk_n_128
  85  *   Bulk counter numbers in 128 counters units.
  86  *
  87  * @return
  88  *   Pointer to counter object on success, a negative value otherwise and
  89  *   rte_errno is set.
  90  */
  91 struct mlx5_devx_obj *
  92 mlx5_devx_cmd_flow_counter_alloc(void *ctx, uint32_t bulk_n_128)
  93 {
  94         struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs),
  95                                                 0, SOCKET_ID_ANY);
  96         uint32_t in[MLX5_ST_SZ_DW(alloc_flow_counter_in)]   = {0};
  97         uint32_t out[MLX5_ST_SZ_DW(alloc_flow_counter_out)] = {0};
  98
  99         if (!dcs) {
 100                 rte_errno = ENOMEM;
 101                 return NULL;
 102         }
 103         MLX5_SET(alloc_flow_counter_in, in, opcode,
 104                  MLX5_CMD_OP_ALLOC_FLOW_COUNTER);
 105         MLX5_SET(alloc_flow_counter_in, in, flow_counter_bulk, bulk_n_128);
 106         dcs->obj = mlx5_glue->devx_obj_create(ctx, in,
 107                                               sizeof(in), out, sizeof(out));
 108         if (!dcs->obj) {
 109                 DRV_LOG(ERR, "Can't allocate counters - error %d", errno);
 110                 rte_errno = errno;
 111                 mlx5_free(dcs);
 112                 return NULL;
 113         }
 114         dcs->id = MLX5_GET(alloc_flow_counter_out, out, flow_counter_id);
 115         return dcs;
 116 }
 117
 118 /**
 119  * Query flow counters values.
 120  *
 121  * @param[in] dcs
 122  *   devx object that was obtained from mlx5_devx_cmd_fc_alloc.
 123  * @param[in] clear
 124  *   Whether hardware should clear the counters after the query or not.
 125  * @param[in] n_counters
 126  *   0 in case of 1 counter to read, otherwise the counter number to read.
 127  *  @param pkts
 128  *   The number of packets that matched the flow.
 129  *  @param bytes
 130  *    The number of bytes that matched the flow.
 131  *  @param mkey
 132  *   The mkey key for batch query.
 133  *  @param addr
 134  *    The address in the mkey range for batch query.
 135  *  @param cmd_comp
 136  *   The completion object for asynchronous batch query.
 137  *  @param async_id
 138  *    The ID to be returned in the asynchronous batch query response.
 139  *
 140  * @return
 141  *   0 on success, a negative value otherwise.
 142  */
 143 int
 144 mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
 145                                  int clear, uint32_t n_counters,
 146                                  uint64_t *pkts, uint64_t *bytes,
 147                                  uint32_t mkey, void *addr,
 148                                  void *cmd_comp,
 149                                  uint64_t async_id)
 150 {
 151         int out_len = MLX5_ST_SZ_BYTES(query_flow_counter_out) +
 152                         MLX5_ST_SZ_BYTES(traffic_counter);
 153         uint32_t out[out_len];
 154         uint32_t in[MLX5_ST_SZ_DW(query_flow_counter_in)] = {0};
 155         void *stats;
 156         int rc;
 157
 158         MLX5_SET(query_flow_counter_in, in, opcode,
 159                  MLX5_CMD_OP_QUERY_FLOW_COUNTER);
 160         MLX5_SET(query_flow_counter_in, in, op_mod, 0);
 161         MLX5_SET(query_flow_counter_in, in, flow_counter_id, dcs->id);
 162         MLX5_SET(query_flow_counter_in, in, clear, !!clear);
 163
 164         if (n_counters) {
 165                 MLX5_SET(query_flow_counter_in, in, num_of_counters,
 166                          n_counters);
 167                 MLX5_SET(query_flow_counter_in, in, dump_to_memory, 1);
 168                 MLX5_SET(query_flow_counter_in, in, mkey, mkey);
 169                 MLX5_SET64(query_flow_counter_in, in, address,
 170                            (uint64_t)(uintptr_t)addr);
 171         }
 172         if (!cmd_comp)
 173                 rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
 174                                                out_len);
 175         else
 176                 rc = mlx5_glue->devx_obj_query_async(dcs->obj, in, sizeof(in),
 177                                                      out_len, async_id,
 178                                                      cmd_comp);
 179         if (rc) {
 180                 DRV_LOG(ERR, "Failed to query devx counters with rc %d", rc);
 181                 rte_errno = rc;
 182                 return -rc;
 183         }
 184         if (!n_counters) {
 185                 stats = MLX5_ADDR_OF(query_flow_counter_out,
 186                                      out, flow_statistics);
 187                 *pkts = MLX5_GET64(traffic_counter, stats, packets);
 188                 *bytes = MLX5_GET64(traffic_counter, stats, octets);
 189         }
 190         return 0;
 191 }
 192
 193 /**
 194  * Create a new mkey.
 195  *
 196  * @param[in] ctx
 197  *   Context returned from mlx5 open_device() glue function.
 198  * @param[in] attr
 199  *   Attributes of the requested mkey.
 200  *
 201  * @return
 202  *   Pointer to Devx mkey on success, a negative value otherwise and rte_errno
 203  *   is set.
 204  */
 205 struct mlx5_devx_obj *
 206 mlx5_devx_cmd_mkey_create(void *ctx,
 207                           struct mlx5_devx_mkey_attr *attr)
 208 {
 209         struct mlx5_klm *klm_array = attr->klm_array;
 210         int klm_num = attr->klm_num;
 211         int in_size_dw = MLX5_ST_SZ_DW(create_mkey_in) +
 212                      (klm_num ? RTE_ALIGN(klm_num, 4) : 0) * MLX5_ST_SZ_DW(klm);
 213         uint32_t in[in_size_dw];
 214         uint32_t out[MLX5_ST_SZ_DW(create_mkey_out)] = {0};
 215         void *mkc;
 216         struct mlx5_devx_obj *mkey = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*mkey),
 217                                                  0, SOCKET_ID_ANY);
 218         size_t pgsize;
 219         uint32_t translation_size;
 220
 221         if (!mkey) {
 222                 rte_errno = ENOMEM;
 223                 return NULL;
 224         }
 225         memset(in, 0, in_size_dw * 4);
 226         pgsize = rte_mem_page_size();
 227         if (pgsize == (size_t)-1) {
 228                 mlx5_free(mkey);
 229                 DRV_LOG(ERR, "Failed to get page size");
 230                 rte_errno = ENOMEM;
 231                 return NULL;
 232         }
 233         MLX5_SET(create_mkey_in, in, opcode, MLX5_CMD_OP_CREATE_MKEY);
 234         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
 235         if (klm_num > 0) {
 236                 int i;
 237                 uint8_t *klm = (uint8_t *)MLX5_ADDR_OF(create_mkey_in, in,
 238                                                        klm_pas_mtt);
 239                 translation_size = RTE_ALIGN(klm_num, 4);
 240                 for (i = 0; i < klm_num; i++) {
 241                         MLX5_SET(klm, klm, byte_count, klm_array[i].byte_count);
 242                         MLX5_SET(klm, klm, mkey, klm_array[i].mkey);
 243                         MLX5_SET64(klm, klm, address, klm_array[i].address);
 244                         klm += MLX5_ST_SZ_BYTES(klm);
 245                 }
 246                 for (; i < (int)translation_size; i++) {
 247                         MLX5_SET(klm, klm, mkey, 0x0);
 248                         MLX5_SET64(klm, klm, address, 0x0);
 249                         klm += MLX5_ST_SZ_BYTES(klm);
 250                 }
 251                 MLX5_SET(mkc, mkc, access_mode_1_0, attr->log_entity_size ?
 252                          MLX5_MKC_ACCESS_MODE_KLM_FBS :
 253                          MLX5_MKC_ACCESS_MODE_KLM);
 254                 MLX5_SET(mkc, mkc, log_page_size, attr->log_entity_size);
 255         } else {
 256                 translation_size = (RTE_ALIGN(attr->size, pgsize) * 8) / 16;
 257                 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
 258                 MLX5_SET(mkc, mkc, log_page_size, rte_log2_u32(pgsize));
 259         }
 260         MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
 261                  translation_size);
 262         MLX5_SET(create_mkey_in, in, mkey_umem_id, attr->umem_id);
 263         MLX5_SET(create_mkey_in, in, pg_access, attr->pg_access);
 264         MLX5_SET(mkc, mkc, lw, 0x1);
 265         MLX5_SET(mkc, mkc, lr, 0x1);
 266         MLX5_SET(mkc, mkc, qpn, 0xffffff);
 267         MLX5_SET(mkc, mkc, pd, attr->pd);
 268         MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
 269         MLX5_SET(mkc, mkc, umr_en, attr->umr_en);
 270         MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
 271         MLX5_SET(mkc, mkc, relaxed_ordering_write,
 272                  attr->relaxed_ordering_write);
 273         MLX5_SET(mkc, mkc, relaxed_ordering_read, attr->relaxed_ordering_read);
 274         MLX5_SET64(mkc, mkc, start_addr, attr->addr);
 275         MLX5_SET64(mkc, mkc, len, attr->size);
 276         mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
 277                                                sizeof(out));
 278         if (!mkey->obj) {
 279                 DRV_LOG(ERR, "Can't create %sdirect mkey - error %d",
 280                         klm_num ? "an in" : "a ", errno);
 281                 rte_errno = errno;
 282                 mlx5_free(mkey);
 283                 return NULL;
 284         }
 285         mkey->id = MLX5_GET(create_mkey_out, out, mkey_index);
 286         mkey->id = (mkey->id << 8) | (attr->umem_id & 0xFF);
 287         return mkey;
 288 }
 289
 290 /**
 291  * Get status of devx command response.
 292  * Mainly used for asynchronous commands.
 293  *
 294  * @param[in] out
 295  *   The out response buffer.
 296  *
 297  * @return
 298  *   0 on success, non-zero value otherwise.
 299  */
 300 int
 301 mlx5_devx_get_out_command_status(void *out)
 302 {
 303         int status;
 304
 305         if (!out)
 306                 return -EINVAL;
 307         status = MLX5_GET(query_flow_counter_out, out, status);
 308         if (status) {
 309                 int syndrome = MLX5_GET(query_flow_counter_out, out, syndrome);
 310
 311                 DRV_LOG(ERR, "Bad DevX status %x, syndrome = %x", status,
 312                         syndrome);
 313         }
 314         return status;
 315 }
 316
 317 /**
 318  * Destroy any object allocated by a Devx API.
 319  *
 320  * @param[in] obj
 321  *   Pointer to a general object.
 322  *
 323  * @return
 324  *   0 on success, a negative value otherwise.
 325  */
 326 int
 327 mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj)
 328 {
 329         int ret;
 330
 331         if (!obj)
 332                 return 0;
 333         ret =  mlx5_glue->devx_obj_destroy(obj->obj);
 334         mlx5_free(obj);
 335         return ret;
 336 }
 337
 338 /**
 339  * Query NIC vport context.
 340  * Fills minimal inline attribute.
 341  *
 342  * @param[in] ctx
 343  *   ibv contexts returned from mlx5dv_open_device.
 344  * @param[in] vport
 345  *   vport index
 346  * @param[out] attr
 347  *   Attributes device values.
 348  *
 349  * @return
 350  *   0 on success, a negative value otherwise.
 351  */
 352 static int
 353 mlx5_devx_cmd_query_nic_vport_context(void *ctx,
 354                                       unsigned int vport,
 355                                       struct mlx5_hca_attr *attr)
 356 {
 357         uint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};
 358         uint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};
 359         void *vctx;
 360         int status, syndrome, rc;
 361
 362         /* Query NIC vport context to determine inline mode. */
 363         MLX5_SET(query_nic_vport_context_in, in, opcode,
 364                  MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT);
 365         MLX5_SET(query_nic_vport_context_in, in, vport_number, vport);
 366         if (vport)
 367                 MLX5_SET(query_nic_vport_context_in, in, other_vport, 1);
 368         rc = mlx5_glue->devx_general_cmd(ctx,
 369                                          in, sizeof(in),
 370                                          out, sizeof(out));
 371         if (rc)
 372                 goto error;
 373         status = MLX5_GET(query_nic_vport_context_out, out, status);
 374         syndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);
 375         if (status) {
 376                 DRV_LOG(DEBUG, "Failed to query NIC vport context, "
 377                         "status %x, syndrome = %x", status, syndrome);
 378                 return -1;
 379         }
 380         vctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,
 381                             nic_vport_context);
 382         attr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,
 383                                            min_wqe_inline_mode);
 384         return 0;
 385 error:
 386         rc = (rc > 0) ? -rc : rc;
 387         return rc;
 388 }
 389
 390 /**
 391  * Query NIC vDPA attributes.
 392  *
 393  * @param[in] ctx
 394  *   Context returned from mlx5 open_device() glue function.
 395  * @param[out] vdpa_attr
 396  *   vDPA Attributes structure to fill.
 397  */
 398 static void
 399 mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,
 400                                   struct mlx5_hca_vdpa_attr *vdpa_attr)
 401 {
 402         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 403         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 404         void *hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 405         int status, syndrome, rc;
 406
 407         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 408         MLX5_SET(query_hca_cap_in, in, op_mod,
 409                  MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION |
 410                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 411         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 412         status = MLX5_GET(query_hca_cap_out, out, status);
 413         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 414         if (rc || status) {
 415                 RTE_LOG(DEBUG, PMD, "Failed to query devx VDPA capabilities,"
 416                         " status %x, syndrome = %x", status, syndrome);
 417                 vdpa_attr->valid = 0;
 418         } else {
 419                 vdpa_attr->valid = 1;
 420                 vdpa_attr->desc_tunnel_offload_type =
 421                         MLX5_GET(virtio_emulation_cap, hcattr,
 422                                  desc_tunnel_offload_type);
 423                 vdpa_attr->eth_frame_offload_type =
 424                         MLX5_GET(virtio_emulation_cap, hcattr,
 425                                  eth_frame_offload_type);
 426                 vdpa_attr->virtio_version_1_0 =
 427                         MLX5_GET(virtio_emulation_cap, hcattr,
 428                                  virtio_version_1_0);
 429                 vdpa_attr->tso_ipv4 = MLX5_GET(virtio_emulation_cap, hcattr,
 430                                                tso_ipv4);
 431                 vdpa_attr->tso_ipv6 = MLX5_GET(virtio_emulation_cap, hcattr,
 432                                                tso_ipv6);
 433                 vdpa_attr->tx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 434                                               tx_csum);
 435                 vdpa_attr->rx_csum = MLX5_GET(virtio_emulation_cap, hcattr,
 436                                               rx_csum);
 437                 vdpa_attr->event_mode = MLX5_GET(virtio_emulation_cap, hcattr,
 438                                                  event_mode);
 439                 vdpa_attr->virtio_queue_type =
 440                         MLX5_GET(virtio_emulation_cap, hcattr,
 441                                  virtio_queue_type);
 442                 vdpa_attr->log_doorbell_stride =
 443                         MLX5_GET(virtio_emulation_cap, hcattr,
 444                                  log_doorbell_stride);
 445                 vdpa_attr->log_doorbell_bar_size =
 446                         MLX5_GET(virtio_emulation_cap, hcattr,
 447                                  log_doorbell_bar_size);
 448                 vdpa_attr->doorbell_bar_offset =
 449                         MLX5_GET64(virtio_emulation_cap, hcattr,
 450                                    doorbell_bar_offset);
 451                 vdpa_attr->max_num_virtio_queues =
 452                         MLX5_GET(virtio_emulation_cap, hcattr,
 453                                  max_num_virtio_queues);
 454                 vdpa_attr->umems[0].a = MLX5_GET(virtio_emulation_cap, hcattr,
 455                                                  umem_1_buffer_param_a);
 456                 vdpa_attr->umems[0].b = MLX5_GET(virtio_emulation_cap, hcattr,
 457                                                  umem_1_buffer_param_b);
 458                 vdpa_attr->umems[1].a = MLX5_GET(virtio_emulation_cap, hcattr,
 459                                                  umem_2_buffer_param_a);
 460                 vdpa_attr->umems[1].b = MLX5_GET(virtio_emulation_cap, hcattr,
 461                                                  umem_2_buffer_param_b);
 462                 vdpa_attr->umems[2].a = MLX5_GET(virtio_emulation_cap, hcattr,
 463                                                  umem_3_buffer_param_a);
 464                 vdpa_attr->umems[2].b = MLX5_GET(virtio_emulation_cap, hcattr,
 465                                                  umem_3_buffer_param_b);
 466         }
 467 }
 468
 469 int
 470 mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
 471                                   uint32_t ids[], uint32_t num)
 472 {
 473         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
 474         uint32_t out[MLX5_ST_SZ_DW(create_flex_parser_out)] = {0};
 475         void *hdr = MLX5_ADDR_OF(create_flex_parser_out, in, hdr);
 476         void *flex = MLX5_ADDR_OF(create_flex_parser_out, out, flex);
 477         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 478         int ret;
 479         uint32_t idx = 0;
 480         uint32_t i;
 481
 482         if (num > MLX5_GRAPH_NODE_SAMPLE_NUM) {
 483                 rte_errno = EINVAL;
 484                 DRV_LOG(ERR, "Too many sample IDs to be fetched.");
 485                 return -rte_errno;
 486         }
 487         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 488                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
 489         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 490                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 491         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, flex_obj->id);
 492         ret = mlx5_glue->devx_obj_query(flex_obj->obj, in, sizeof(in),
 493                                         out, sizeof(out));
 494         if (ret) {
 495                 rte_errno = ret;
 496                 DRV_LOG(ERR, "Failed to query sample IDs with object %p.",
 497                         (void *)flex_obj);
 498                 return -rte_errno;
 499         }
 500         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 501                 void *s_off = (void *)((char *)sample + i *
 502                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 503                 uint32_t en;
 504
 505                 en = MLX5_GET(parse_graph_flow_match_sample, s_off,
 506                               flow_match_sample_en);
 507                 if (!en)
 508                         continue;
 509                 ids[idx++] = MLX5_GET(parse_graph_flow_match_sample, s_off,
 510                                   flow_match_sample_field_id);
 511         }
 512         if (num != idx) {
 513                 rte_errno = EINVAL;
 514                 DRV_LOG(ERR, "Number of sample IDs are not as expected.");
 515                 return -rte_errno;
 516         }
 517         return ret;
 518 }
 519
 520
 521 struct mlx5_devx_obj *
 522 mlx5_devx_cmd_create_flex_parser(void *ctx,
 523                               struct mlx5_devx_graph_node_attr *data)
 524 {
 525         uint32_t in[MLX5_ST_SZ_DW(create_flex_parser_in)] = {0};
 526         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
 527         void *hdr = MLX5_ADDR_OF(create_flex_parser_in, in, hdr);
 528         void *flex = MLX5_ADDR_OF(create_flex_parser_in, in, flex);
 529         void *sample = MLX5_ADDR_OF(parse_graph_flex, flex, sample_table);
 530         void *in_arc = MLX5_ADDR_OF(parse_graph_flex, flex, input_arc);
 531         void *out_arc = MLX5_ADDR_OF(parse_graph_flex, flex, output_arc);
 532         struct mlx5_devx_obj *parse_flex_obj = mlx5_malloc
 533                      (MLX5_MEM_ZERO, sizeof(*parse_flex_obj), 0, SOCKET_ID_ANY);
 534         uint32_t i;
 535
 536         if (!parse_flex_obj) {
 537                 DRV_LOG(ERR, "Failed to allocate flex parser data.");
 538                 rte_errno = ENOMEM;
 539                 return NULL;
 540         }
 541         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
 542                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
 543         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
 544                  MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH);
 545         MLX5_SET(parse_graph_flex, flex, header_length_mode,
 546                  data->header_length_mode);
 547         MLX5_SET(parse_graph_flex, flex, header_length_base_value,
 548                  data->header_length_base_value);
 549         MLX5_SET(parse_graph_flex, flex, header_length_field_offset,
 550                  data->header_length_field_offset);
 551         MLX5_SET(parse_graph_flex, flex, header_length_field_shift,
 552                  data->header_length_field_shift);
 553         MLX5_SET(parse_graph_flex, flex, header_length_field_mask,
 554                  data->header_length_field_mask);
 555         for (i = 0; i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {
 556                 struct mlx5_devx_match_sample_attr *s = &data->sample[i];
 557                 void *s_off = (void *)((char *)sample + i *
 558                               MLX5_ST_SZ_BYTES(parse_graph_flow_match_sample));
 559
 560                 if (!s->flow_match_sample_en)
 561                         continue;
 562                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 563                          flow_match_sample_en, !!s->flow_match_sample_en);
 564                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 565                          flow_match_sample_field_offset,
 566                          s->flow_match_sample_field_offset);
 567                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 568                          flow_match_sample_offset_mode,
 569                          s->flow_match_sample_offset_mode);
 570                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 571                          flow_match_sample_field_offset_mask,
 572                          s->flow_match_sample_field_offset_mask);
 573                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 574                          flow_match_sample_field_offset_shift,
 575                          s->flow_match_sample_field_offset_shift);
 576                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 577                          flow_match_sample_field_base_offset,
 578                          s->flow_match_sample_field_base_offset);
 579                 MLX5_SET(parse_graph_flow_match_sample, s_off,
 580                          flow_match_sample_tunnel_mode,
 581                          s->flow_match_sample_tunnel_mode);
 582         }
 583         for (i = 0; i < MLX5_GRAPH_NODE_ARC_NUM; i++) {
 584                 struct mlx5_devx_graph_arc_attr *ia = &data->in[i];
 585                 struct mlx5_devx_graph_arc_attr *oa = &data->out[i];
 586                 void *in_off = (void *)((char *)in_arc + i *
 587                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 588                 void *out_off = (void *)((char *)out_arc + i *
 589                               MLX5_ST_SZ_BYTES(parse_graph_arc));
 590
 591                 if (ia->arc_parse_graph_node != 0) {
 592                         MLX5_SET(parse_graph_arc, in_off,
 593                                  compare_condition_value,
 594                                  ia->compare_condition_value);
 595                         MLX5_SET(parse_graph_arc, in_off, start_inner_tunnel,
 596                                  ia->start_inner_tunnel);
 597                         MLX5_SET(parse_graph_arc, in_off, arc_parse_graph_node,
 598                                  ia->arc_parse_graph_node);
 599                         MLX5_SET(parse_graph_arc, in_off,
 600                                  parse_graph_node_handle,
 601                                  ia->parse_graph_node_handle);
 602                 }
 603                 if (oa->arc_parse_graph_node != 0) {
 604                         MLX5_SET(parse_graph_arc, out_off,
 605                                  compare_condition_value,
 606                                  oa->compare_condition_value);
 607                         MLX5_SET(parse_graph_arc, out_off, start_inner_tunnel,
 608                                  oa->start_inner_tunnel);
 609                         MLX5_SET(parse_graph_arc, out_off, arc_parse_graph_node,
 610                                  oa->arc_parse_graph_node);
 611                         MLX5_SET(parse_graph_arc, out_off,
 612                                  parse_graph_node_handle,
 613                                  oa->parse_graph_node_handle);
 614                 }
 615         }
 616         parse_flex_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
 617                                                          out, sizeof(out));
 618         if (!parse_flex_obj->obj) {
 619                 rte_errno = errno;
 620                 DRV_LOG(ERR, "Failed to create FLEX PARSE GRAPH object "
 621                         "by using DevX.");
 622                 mlx5_free(parse_flex_obj);
 623                 return NULL;
 624         }
 625         parse_flex_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
 626         return parse_flex_obj;
 627 }
 628
 629 /**
 630  * Query HCA attributes.
 631  * Using those attributes we can check on run time if the device
 632  * is having the required capabilities.
 633  *
 634  * @param[in] ctx
 635  *   Context returned from mlx5 open_device() glue function.
 636  * @param[out] attr
 637  *   Attributes device values.
 638  *
 639  * @return
 640  *   0 on success, a negative value otherwise.
 641  */
 642 int
 643 mlx5_devx_cmd_query_hca_attr(void *ctx,
 644                              struct mlx5_hca_attr *attr)
 645 {
 646         uint32_t in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {0};
 647         uint32_t out[MLX5_ST_SZ_DW(query_hca_cap_out)] = {0};
 648         void *hcattr;
 649         int status, syndrome, rc, i;
 650         uint64_t general_obj_types_supported = 0;
 651
 652         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 653         MLX5_SET(query_hca_cap_in, in, op_mod,
 654                  MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE |
 655                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 656
 657         rc = mlx5_glue->devx_general_cmd(ctx,
 658                                          in, sizeof(in), out, sizeof(out));
 659         if (rc)
 660                 goto error;
 661         status = MLX5_GET(query_hca_cap_out, out, status);
 662         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 663         if (status) {
 664                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 665                         "status %x, syndrome = %x", status, syndrome);
 666                 return -1;
 667         }
 668         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 669         attr->flow_counter_bulk_alloc_bitmap =
 670                         MLX5_GET(cmd_hca_cap, hcattr, flow_counter_bulk_alloc);
 671         attr->flow_counters_dump = MLX5_GET(cmd_hca_cap, hcattr,
 672                                             flow_counters_dump);
 673         attr->log_max_rqt_size = MLX5_GET(cmd_hca_cap, hcattr,
 674                                           log_max_rqt_size);
 675         attr->eswitch_manager = MLX5_GET(cmd_hca_cap, hcattr, eswitch_manager);
 676         attr->hairpin = MLX5_GET(cmd_hca_cap, hcattr, hairpin);
 677         attr->log_max_hairpin_queues = MLX5_GET(cmd_hca_cap, hcattr,
 678                                                 log_max_hairpin_queues);
 679         attr->log_max_hairpin_wq_data_sz = MLX5_GET(cmd_hca_cap, hcattr,
 680                                                     log_max_hairpin_wq_data_sz);
 681         attr->log_max_hairpin_num_packets = MLX5_GET
 682                 (cmd_hca_cap, hcattr, log_min_hairpin_wq_data_sz);
 683         attr->vhca_id = MLX5_GET(cmd_hca_cap, hcattr, vhca_id);
 684         attr->relaxed_ordering_write = MLX5_GET(cmd_hca_cap, hcattr,
 685                                                 relaxed_ordering_write);
 686         attr->relaxed_ordering_read = MLX5_GET(cmd_hca_cap, hcattr,
 687                                                relaxed_ordering_read);
 688         attr->access_register_user = MLX5_GET(cmd_hca_cap, hcattr,
 689                                               access_register_user);
 690         attr->eth_net_offloads = MLX5_GET(cmd_hca_cap, hcattr,
 691                                           eth_net_offloads);
 692         attr->eth_virt = MLX5_GET(cmd_hca_cap, hcattr, eth_virt);
 693         attr->flex_parser_protocols = MLX5_GET(cmd_hca_cap, hcattr,
 694                                                flex_parser_protocols);
 695         attr->max_geneve_tlv_options = MLX5_GET(cmd_hca_cap, hcattr,
 696                         max_geneve_tlv_options);
 697         attr->max_geneve_tlv_option_data_len = MLX5_GET(cmd_hca_cap, hcattr,
 698                         max_geneve_tlv_option_data_len);
 699         attr->qos.sup = MLX5_GET(cmd_hca_cap, hcattr, qos);
 700         attr->qos.flow_meter_aso_sup = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 701                                          general_obj_types) &
 702                               MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO);
 703         attr->vdpa.valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 704                                          general_obj_types) &
 705                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 706         attr->vdpa.queue_counters_valid = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 707                                                         general_obj_types) &
 708                                   MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
 709         attr->parse_graph_flex_node = !!(MLX5_GET64(cmd_hca_cap, hcattr,
 710                                          general_obj_types) &
 711                               MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
 712         attr->wqe_index_ignore = MLX5_GET(cmd_hca_cap, hcattr,
 713                                           wqe_index_ignore_cap);
 714         attr->cross_channel = MLX5_GET(cmd_hca_cap, hcattr, cd);
 715         attr->non_wire_sq = MLX5_GET(cmd_hca_cap, hcattr, non_wire_sq);
 716         attr->log_max_static_sq_wq = MLX5_GET(cmd_hca_cap, hcattr,
 717                                               log_max_static_sq_wq);
 718         attr->num_lag_ports = MLX5_GET(cmd_hca_cap, hcattr, num_lag_ports);
 719         attr->dev_freq_khz = MLX5_GET(cmd_hca_cap, hcattr,
 720                                       device_frequency_khz);
 721         attr->scatter_fcs_w_decap_disable =
 722                 MLX5_GET(cmd_hca_cap, hcattr, scatter_fcs_w_decap_disable);
 723         attr->roce = MLX5_GET(cmd_hca_cap, hcattr, roce);
 724         attr->rq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, rq_ts_format);
 725         attr->sq_ts_format = MLX5_GET(cmd_hca_cap, hcattr, sq_ts_format);
 726         attr->regex = MLX5_GET(cmd_hca_cap, hcattr, regexp);
 727         attr->regexp_num_of_engines = MLX5_GET(cmd_hca_cap, hcattr,
 728                                                regexp_num_of_engines);
 729         /* Read the general_obj_types bitmap and extract the relevant bits. */
 730         general_obj_types_supported = MLX5_GET64(cmd_hca_cap, hcattr,
 731                                                  general_obj_types);
 732         attr->vdpa.valid = !!(general_obj_types_supported &
 733                               MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q);
 734         attr->vdpa.queue_counters_valid =
 735                         !!(general_obj_types_supported &
 736                            MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS);
 737         attr->parse_graph_flex_node =
 738                         !!(general_obj_types_supported &
 739                            MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE);
 740         attr->flow_hit_aso = !!(general_obj_types_supported &
 741                                 MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO);
 742         attr->geneve_tlv_opt = !!(general_obj_types_supported &
 743                                   MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT);
 744         attr->dek = !!(general_obj_types_supported &
 745                        MLX5_GENERAL_OBJ_TYPES_CAP_DEK);
 746         /* Add reading of other GENERAL_OBJ_TYPES_CAP bits above this line. */
 747         attr->log_max_cq = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq);
 748         attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp);
 749         attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz);
 750         attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz);
 751         attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz);
 752         attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd);
 753         attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq);
 754         attr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);
 755         attr->reg_c_preserve =
 756                 MLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);
 757         attr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo);
 758         attr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress);
 759         attr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress);
 760         attr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,
 761                                                  compress_min_block_size);
 762         attr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);
 763         attr->log_max_mmo_compress = MLX5_GET(cmd_hca_cap, hcattr,
 764                                               log_compress_mmo_size);
 765         attr->log_max_mmo_decompress = MLX5_GET(cmd_hca_cap, hcattr,
 766                                                 log_decompress_mmo_size);
 767         attr->cqe_compression = MLX5_GET(cmd_hca_cap, hcattr, cqe_compression);
 768         attr->mini_cqe_resp_flow_tag = MLX5_GET(cmd_hca_cap, hcattr,
 769                                                 mini_cqe_resp_flow_tag);
 770         attr->mini_cqe_resp_l3_l4_tag = MLX5_GET(cmd_hca_cap, hcattr,
 771                                                  mini_cqe_resp_l3_l4_tag);
 772         attr->umr_indirect_mkey_disabled =
 773                 MLX5_GET(cmd_hca_cap, hcattr, umr_indirect_mkey_disabled);
 774         attr->umr_modify_entity_size_disabled =
 775                 MLX5_GET(cmd_hca_cap, hcattr, umr_modify_entity_size_disabled);
 776         attr->crypto = MLX5_GET(cmd_hca_cap, hcattr, crypto);
 777         if (attr->crypto)
 778                 attr->aes_xts = MLX5_GET(cmd_hca_cap, hcattr, aes_xts);
 779         if (attr->qos.sup) {
 780                 MLX5_SET(query_hca_cap_in, in, op_mod,
 781                          MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP |
 782                          MLX5_HCA_CAP_OPMOD_GET_CUR);
 783                 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
 784                                                  out, sizeof(out));
 785                 if (rc)
 786                         goto error;
 787                 if (status) {
 788                         DRV_LOG(DEBUG, "Failed to query devx QOS capabilities,"
 789                                 " status %x, syndrome = %x", status, syndrome);
 790                         return -1;
 791                 }
 792                 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 793                 attr->qos.flow_meter_old =
 794                                 MLX5_GET(qos_cap, hcattr, flow_meter_old);
 795                 attr->qos.log_max_flow_meter =
 796                                 MLX5_GET(qos_cap, hcattr, log_max_flow_meter);
 797                 attr->qos.flow_meter_reg_c_ids =
 798                                 MLX5_GET(qos_cap, hcattr, flow_meter_reg_id);
 799                 attr->qos.flow_meter =
 800                                 MLX5_GET(qos_cap, hcattr, flow_meter);
 801                 attr->qos.packet_pacing =
 802                                 MLX5_GET(qos_cap, hcattr, packet_pacing);
 803                 attr->qos.wqe_rate_pp =
 804                                 MLX5_GET(qos_cap, hcattr, wqe_rate_pp);
 805                 if (attr->qos.flow_meter_aso_sup) {
 806                         attr->qos.log_meter_aso_granularity =
 807                                 MLX5_GET(qos_cap, hcattr,
 808                                         log_meter_aso_granularity);
 809                         attr->qos.log_meter_aso_max_alloc =
 810                                 MLX5_GET(qos_cap, hcattr,
 811                                         log_meter_aso_max_alloc);
 812                         attr->qos.log_max_num_meter_aso =
 813                                 MLX5_GET(qos_cap, hcattr,
 814                                         log_max_num_meter_aso);
 815                 }
 816         }
 817         if (attr->vdpa.valid)
 818                 mlx5_devx_cmd_query_hca_vdpa_attr(ctx, &attr->vdpa);
 819         if (!attr->eth_net_offloads)
 820                 return 0;
 821
 822         /* Query Flow Sampler Capability From FLow Table Properties Layout. */
 823         memset(in, 0, sizeof(in));
 824         memset(out, 0, sizeof(out));
 825         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 826         MLX5_SET(query_hca_cap_in, in, op_mod,
 827                  MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE |
 828                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 829
 830         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 831         if (rc)
 832                 goto error;
 833         status = MLX5_GET(query_hca_cap_out, out, status);
 834         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 835         if (status) {
 836                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 837                         "status %x, syndrome = %x", status, syndrome);
 838                 attr->log_max_ft_sampler_num = 0;
 839                 return -1;
 840         }
 841         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 842         attr->log_max_ft_sampler_num =
 843                         MLX5_GET(flow_table_nic_cap,
 844                         hcattr, flow_table_properties.log_max_ft_sampler_num);
 845
 846         /* Query HCA offloads for Ethernet protocol. */
 847         memset(in, 0, sizeof(in));
 848         memset(out, 0, sizeof(out));
 849         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 850         MLX5_SET(query_hca_cap_in, in, op_mod,
 851                  MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS |
 852                  MLX5_HCA_CAP_OPMOD_GET_CUR);
 853
 854         rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));
 855         if (rc) {
 856                 attr->eth_net_offloads = 0;
 857                 goto error;
 858         }
 859         status = MLX5_GET(query_hca_cap_out, out, status);
 860         syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 861         if (status) {
 862                 DRV_LOG(DEBUG, "Failed to query devx HCA capabilities, "
 863                         "status %x, syndrome = %x", status, syndrome);
 864                 attr->eth_net_offloads = 0;
 865                 return -1;
 866         }
 867         hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 868         attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
 869                                          hcattr, wqe_vlan_insert);
 870         attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 871                                  lro_cap);
 872         attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
 873                                         hcattr, tunnel_lro_gre);
 874         attr->tunnel_lro_vxlan = MLX5_GET(per_protocol_networking_offload_caps,
 875                                           hcattr, tunnel_lro_vxlan);
 876         attr->lro_max_msg_sz_mode = MLX5_GET
 877                                         (per_protocol_networking_offload_caps,
 878                                          hcattr, lro_max_msg_sz_mode);
 879         for (i = 0 ; i < MLX5_LRO_NUM_SUPP_PERIODS ; i++) {
 880                 attr->lro_timer_supported_periods[i] =
 881                         MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 882                                  lro_timer_supported_periods[i]);
 883         }
 884         attr->lro_min_mss_size = MLX5_GET(per_protocol_networking_offload_caps,
 885                                           hcattr, lro_min_mss_size);
 886         attr->tunnel_stateless_geneve_rx =
 887                             MLX5_GET(per_protocol_networking_offload_caps,
 888                                      hcattr, tunnel_stateless_geneve_rx);
 889         attr->geneve_max_opt_len =
 890                     MLX5_GET(per_protocol_networking_offload_caps,
 891                              hcattr, max_geneve_opt_len);
 892         attr->wqe_inline_mode = MLX5_GET(per_protocol_networking_offload_caps,
 893                                          hcattr, wqe_inline_mode);
 894         attr->tunnel_stateless_gtp = MLX5_GET
 895                                         (per_protocol_networking_offload_caps,
 896                                          hcattr, tunnel_stateless_gtp);
 897         attr->rss_ind_tbl_cap = MLX5_GET
 898                                         (per_protocol_networking_offload_caps,
 899                                          hcattr, rss_ind_tbl_cap);
 900         /* Query HCA attribute for ROCE. */
 901         if (attr->roce) {
 902                 memset(in, 0, sizeof(in));
 903                 memset(out, 0, sizeof(out));
 904                 MLX5_SET(query_hca_cap_in, in, opcode,
 905                          MLX5_CMD_OP_QUERY_HCA_CAP);
 906                 MLX5_SET(query_hca_cap_in, in, op_mod,
 907                          MLX5_GET_HCA_CAP_OP_MOD_ROCE |
 908                          MLX5_HCA_CAP_OPMOD_GET_CUR);
 909                 rc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in),
 910                                                  out, sizeof(out));
 911                 if (rc)
 912                         goto error;
 913                 status = MLX5_GET(query_hca_cap_out, out, status);
 914                 syndrome = MLX5_GET(query_hca_cap_out, out, syndrome);
 915                 if (status) {
 916                         DRV_LOG(DEBUG,
 917                                 "Failed to query devx HCA ROCE capabilities, "
 918                                 "status %x, syndrome = %x", status, syndrome);
 919                         return -1;
 920                 }
 921                 hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 922                 attr->qp_ts_format = MLX5_GET(roce_caps, hcattr, qp_ts_format);
 923         }
 924         if (attr->eth_virt &&
 925             attr->wqe_inline_mode == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT) {
 926                 rc = mlx5_devx_cmd_query_nic_vport_context(ctx, 0, attr);
 927                 if (rc) {
 928                         attr->eth_virt = 0;
 929                         goto error;
 930                 }
 931         }
 932         return 0;
 933 error:
 934         rc = (rc > 0) ? -rc : rc;
 935         return rc;
 936 }
 937
 938 /**
 939  * Query TIS transport domain from QP verbs object using DevX API.
 940  *
 941  * @param[in] qp
 942  *   Pointer to verbs QP returned by ibv_create_qp .
 943  * @param[in] tis_num
 944  *   TIS number of TIS to query.
 945  * @param[out] tis_td
 946  *   Pointer to TIS transport domain variable, to be set by the routine.
 947  *
 948  * @return
 949  *   0 on success, a negative value otherwise.
 950  */
 951 int
 952 mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
 953                               uint32_t *tis_td)
 954 {
 955 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 956         uint32_t in[MLX5_ST_SZ_DW(query_tis_in)] = {0};
 957         uint32_t out[MLX5_ST_SZ_DW(query_tis_out)] = {0};
 958         int rc;
 959         void *tis_ctx;
 960
 961         MLX5_SET(query_tis_in, in, opcode, MLX5_CMD_OP_QUERY_TIS);
 962         MLX5_SET(query_tis_in, in, tisn, tis_num);
 963         rc = mlx5_glue->devx_qp_query(qp, in, sizeof(in), out, sizeof(out));
 964         if (rc) {
 965                 DRV_LOG(ERR, "Failed to query QP using DevX");
 966                 return -rc;
 967         };
 968         tis_ctx = MLX5_ADDR_OF(query_tis_out, out, tis_context);
 969         *tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);
 970         return 0;
 971 #else
 972         (void)qp;
 973         (void)tis_num;
 974         (void)tis_td;
 975         return -ENOTSUP;
 976 #endif
 977 }
 978
 979 /**
 980  * Fill WQ data for DevX API command.
 981  * Utility function for use when creating DevX objects containing a WQ.
 982  *
 983  * @param[in] wq_ctx
 984  *   Pointer to WQ context to fill with data.
 985  * @param [in] wq_attr
 986  *   Pointer to WQ attributes structure to fill in WQ context.
 987  */
 988 static void
 989 devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)
 990 {
 991         MLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);
 992         MLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);
 993         MLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);
 994         MLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);
 995         MLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);
 996         MLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);
 997         MLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);
 998         MLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);
 999         MLX5_SET(wq, wq_ctx, pd, wq_attr->pd);
1000         MLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);
1001         MLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);
1002         MLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);
1003         MLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);
1004         MLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);
1005         if (wq_attr->log_wq_pg_sz > MLX5_ADAPTER_PAGE_SHIFT)
1006                 MLX5_SET(wq, wq_ctx, log_wq_pg_sz,
1007                          wq_attr->log_wq_pg_sz - MLX5_ADAPTER_PAGE_SHIFT);
1008         MLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);
1009         MLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);
1010         MLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);
1011         MLX5_SET(wq, wq_ctx, log_hairpin_num_packets,
1012                  wq_attr->log_hairpin_num_packets);
1013         MLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);
1014         MLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,
1015                  wq_attr->single_wqe_log_num_of_strides);
1016         MLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);
1017         MLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,
1018                  wq_attr->single_stride_log_num_of_bytes);
1019         MLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);
1020         MLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);
1021         MLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);
1022 }
1023
1024 /**
1025  * Create RQ using DevX API.
1026  *
1027  * @param[in] ctx
1028  *   Context returned from mlx5 open_device() glue function.
1029  * @param [in] rq_attr
1030  *   Pointer to create RQ attributes structure.
1031  * @param [in] socket
1032  *   CPU socket ID for allocations.
1033  *
1034  * @return
1035  *   The DevX object created, NULL otherwise and rte_errno is set.
1036  */
1037 struct mlx5_devx_obj *
1038 mlx5_devx_cmd_create_rq(void *ctx,
1039                         struct mlx5_devx_create_rq_attr *rq_attr,
1040                         int socket)
1041 {
1042         uint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};
1043         uint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};
1044         void *rq_ctx, *wq_ctx;
1045         struct mlx5_devx_wq_attr *wq_attr;
1046         struct mlx5_devx_obj *rq = NULL;
1047
1048         rq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rq), 0, socket);
1049         if (!rq) {
1050                 DRV_LOG(ERR, "Failed to allocate RQ data");
1051                 rte_errno = ENOMEM;
1052                 return NULL;
1053         }
1054         MLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);
1055         rq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);
1056         MLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);
1057         MLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);
1058         MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1059         MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1060         MLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);
1061         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1062         MLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);
1063         MLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);
1064         MLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);
1065         MLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);
1066         MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1067         MLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);
1068         MLX5_SET(sqc, rq_ctx, ts_format, rq_attr->ts_format);
1069         wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1070         wq_attr = &rq_attr->wq_attr;
1071         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1072         rq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1073                                                   out, sizeof(out));
1074         if (!rq->obj) {
1075                 DRV_LOG(ERR, "Failed to create RQ using DevX");
1076                 rte_errno = errno;
1077                 mlx5_free(rq);
1078                 return NULL;
1079         }
1080         rq->id = MLX5_GET(create_rq_out, out, rqn);
1081         return rq;
1082 }
1083
1084 /**
1085  * Modify RQ using DevX API.
1086  *
1087  * @param[in] rq
1088  *   Pointer to RQ object structure.
1089  * @param [in] rq_attr
1090  *   Pointer to modify RQ attributes structure.
1091  *
1092  * @return
1093  *   0 on success, a negative errno value otherwise and rte_errno is set.
1094  */
1095 int
1096 mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
1097                         struct mlx5_devx_modify_rq_attr *rq_attr)
1098 {
1099         uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
1100         uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
1101         void *rq_ctx, *wq_ctx;
1102         int ret;
1103
1104         MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
1105         MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
1106         MLX5_SET(modify_rq_in, in, rqn, rq->id);
1107         MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
1108         rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1109         MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
1110         if (rq_attr->modify_bitmask &
1111                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
1112                 MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
1113         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
1114                 MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
1115         if (rq_attr->modify_bitmask &
1116                         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
1117                 MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
1118         MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
1119         MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
1120         if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
1121                 wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
1122                 MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
1123         }
1124         ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
1125                                          out, sizeof(out));
1126         if (ret) {
1127                 DRV_LOG(ERR, "Failed to modify RQ using DevX");
1128                 rte_errno = errno;
1129                 return -errno;
1130         }
1131         return ret;
1132 }
1133
1134 /**
1135  * Create TIR using DevX API.
1136  *
1137  * @param[in] ctx
1138  *  Context returned from mlx5 open_device() glue function.
1139  * @param [in] tir_attr
1140  *   Pointer to TIR attributes structure.
1141  *
1142  * @return
1143  *   The DevX object created, NULL otherwise and rte_errno is set.
1144  */
1145 struct mlx5_devx_obj *
1146 mlx5_devx_cmd_create_tir(void *ctx,
1147                          struct mlx5_devx_tir_attr *tir_attr)
1148 {
1149         uint32_t in[MLX5_ST_SZ_DW(create_tir_in)] = {0};
1150         uint32_t out[MLX5_ST_SZ_DW(create_tir_out)] = {0};
1151         void *tir_ctx, *outer, *inner, *rss_key;
1152         struct mlx5_devx_obj *tir = NULL;
1153
1154         tir = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tir), 0, SOCKET_ID_ANY);
1155         if (!tir) {
1156                 DRV_LOG(ERR, "Failed to allocate TIR data");
1157                 rte_errno = ENOMEM;
1158                 return NULL;
1159         }
1160         MLX5_SET(create_tir_in, in, opcode, MLX5_CMD_OP_CREATE_TIR);
1161         tir_ctx = MLX5_ADDR_OF(create_tir_in, in, ctx);
1162         MLX5_SET(tirc, tir_ctx, disp_type, tir_attr->disp_type);
1163         MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1164                  tir_attr->lro_timeout_period_usecs);
1165         MLX5_SET(tirc, tir_ctx, lro_enable_mask, tir_attr->lro_enable_mask);
1166         MLX5_SET(tirc, tir_ctx, lro_max_msg_sz, tir_attr->lro_max_msg_sz);
1167         MLX5_SET(tirc, tir_ctx, inline_rqn, tir_attr->inline_rqn);
1168         MLX5_SET(tirc, tir_ctx, rx_hash_symmetric, tir_attr->rx_hash_symmetric);
1169         MLX5_SET(tirc, tir_ctx, tunneled_offload_en,
1170                  tir_attr->tunneled_offload_en);
1171         MLX5_SET(tirc, tir_ctx, indirect_table, tir_attr->indirect_table);
1172         MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1173         MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1174         MLX5_SET(tirc, tir_ctx, transport_domain, tir_attr->transport_domain);
1175         rss_key = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_toeplitz_key);
1176         memcpy(rss_key, tir_attr->rx_hash_toeplitz_key, MLX5_RSS_HASH_KEY_LEN);
1177         outer = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_outer);
1178         MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1179                  tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1180         MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1181                  tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1182         MLX5_SET(rx_hash_field_select, outer, selected_fields,
1183                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1184         inner = MLX5_ADDR_OF(tirc, tir_ctx, rx_hash_field_selector_inner);
1185         MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1186                  tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1187         MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1188                  tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1189         MLX5_SET(rx_hash_field_select, inner, selected_fields,
1190                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1191         tir->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1192                                                    out, sizeof(out));
1193         if (!tir->obj) {
1194                 DRV_LOG(ERR, "Failed to create TIR using DevX");
1195                 rte_errno = errno;
1196                 mlx5_free(tir);
1197                 return NULL;
1198         }
1199         tir->id = MLX5_GET(create_tir_out, out, tirn);
1200         return tir;
1201 }
1202
1203 /**
1204  * Modify TIR using DevX API.
1205  *
1206  * @param[in] tir
1207  *   Pointer to TIR DevX object structure.
1208  * @param [in] modify_tir_attr
1209  *   Pointer to TIR modification attributes structure.
1210  *
1211  * @return
1212  *   0 on success, a negative errno value otherwise and rte_errno is set.
1213  */
1214 int
1215 mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
1216                          struct mlx5_devx_modify_tir_attr *modify_tir_attr)
1217 {
1218         struct mlx5_devx_tir_attr *tir_attr = &modify_tir_attr->tir;
1219         uint32_t in[MLX5_ST_SZ_DW(modify_tir_in)] = {0};
1220         uint32_t out[MLX5_ST_SZ_DW(modify_tir_out)] = {0};
1221         void *tir_ctx;
1222         int ret;
1223
1224         MLX5_SET(modify_tir_in, in, opcode, MLX5_CMD_OP_MODIFY_TIR);
1225         MLX5_SET(modify_tir_in, in, tirn, modify_tir_attr->tirn);
1226         MLX5_SET64(modify_tir_in, in, modify_bitmask,
1227                    modify_tir_attr->modify_bitmask);
1228         tir_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1229         if (modify_tir_attr->modify_bitmask &
1230                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO) {
1231                 MLX5_SET(tirc, tir_ctx, lro_timeout_period_usecs,
1232                          tir_attr->lro_timeout_period_usecs);
1233                 MLX5_SET(tirc, tir_ctx, lro_enable_mask,
1234                          tir_attr->lro_enable_mask);
1235                 MLX5_SET(tirc, tir_ctx, lro_max_msg_sz,
1236                          tir_attr->lro_max_msg_sz);
1237         }
1238         if (modify_tir_attr->modify_bitmask &
1239                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE)
1240                 MLX5_SET(tirc, tir_ctx, indirect_table,
1241                          tir_attr->indirect_table);
1242         if (modify_tir_attr->modify_bitmask &
1243                         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH) {
1244                 int i;
1245                 void *outer, *inner;
1246
1247                 MLX5_SET(tirc, tir_ctx, rx_hash_symmetric,
1248                          tir_attr->rx_hash_symmetric);
1249                 MLX5_SET(tirc, tir_ctx, rx_hash_fn, tir_attr->rx_hash_fn);
1250                 for (i = 0; i < 10; i++) {
1251                         MLX5_SET(tirc, tir_ctx, rx_hash_toeplitz_key[i],
1252                                  tir_attr->rx_hash_toeplitz_key[i]);
1253                 }
1254                 outer = MLX5_ADDR_OF(tirc, tir_ctx,
1255                                      rx_hash_field_selector_outer);
1256                 MLX5_SET(rx_hash_field_select, outer, l3_prot_type,
1257                          tir_attr->rx_hash_field_selector_outer.l3_prot_type);
1258                 MLX5_SET(rx_hash_field_select, outer, l4_prot_type,
1259                          tir_attr->rx_hash_field_selector_outer.l4_prot_type);
1260                 MLX5_SET
1261                 (rx_hash_field_select, outer, selected_fields,
1262                  tir_attr->rx_hash_field_selector_outer.selected_fields);
1263                 inner = MLX5_ADDR_OF(tirc, tir_ctx,
1264                                      rx_hash_field_selector_inner);
1265                 MLX5_SET(rx_hash_field_select, inner, l3_prot_type,
1266                          tir_attr->rx_hash_field_selector_inner.l3_prot_type);
1267                 MLX5_SET(rx_hash_field_select, inner, l4_prot_type,
1268                          tir_attr->rx_hash_field_selector_inner.l4_prot_type);
1269                 MLX5_SET
1270                 (rx_hash_field_select, inner, selected_fields,
1271                  tir_attr->rx_hash_field_selector_inner.selected_fields);
1272         }
1273         if (modify_tir_attr->modify_bitmask &
1274             MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN) {
1275                 MLX5_SET(tirc, tir_ctx, self_lb_block, tir_attr->self_lb_block);
1276         }
1277         ret = mlx5_glue->devx_obj_modify(tir->obj, in, sizeof(in),
1278                                          out, sizeof(out));
1279         if (ret) {
1280                 DRV_LOG(ERR, "Failed to modify TIR using DevX");
1281                 rte_errno = errno;
1282                 return -errno;
1283         }
1284         return ret;
1285 }
1286
1287 /**
1288  * Create RQT using DevX API.
1289  *
1290  * @param[in] ctx
1291  *   Context returned from mlx5 open_device() glue function.
1292  * @param [in] rqt_attr
1293  *   Pointer to RQT attributes structure.
1294  *
1295  * @return
1296  *   The DevX object created, NULL otherwise and rte_errno is set.
1297  */
1298 struct mlx5_devx_obj *
1299 mlx5_devx_cmd_create_rqt(void *ctx,
1300                          struct mlx5_devx_rqt_attr *rqt_attr)
1301 {
1302         uint32_t *in = NULL;
1303         uint32_t inlen = MLX5_ST_SZ_BYTES(create_rqt_in) +
1304                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1305         uint32_t out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
1306         void *rqt_ctx;
1307         struct mlx5_devx_obj *rqt = NULL;
1308         int i;
1309
1310         in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1311         if (!in) {
1312                 DRV_LOG(ERR, "Failed to allocate RQT IN data");
1313                 rte_errno = ENOMEM;
1314                 return NULL;
1315         }
1316         rqt = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*rqt), 0, SOCKET_ID_ANY);
1317         if (!rqt) {
1318                 DRV_LOG(ERR, "Failed to allocate RQT data");
1319                 rte_errno = ENOMEM;
1320                 mlx5_free(in);
1321                 return NULL;
1322         }
1323         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1324         rqt_ctx = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1325         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1326         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1327         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1328         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1329                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1330         rqt->obj = mlx5_glue->devx_obj_create(ctx, in, inlen, out, sizeof(out));
1331         mlx5_free(in);
1332         if (!rqt->obj) {
1333                 DRV_LOG(ERR, "Failed to create RQT using DevX");
1334                 rte_errno = errno;
1335                 mlx5_free(rqt);
1336                 return NULL;
1337         }
1338         rqt->id = MLX5_GET(create_rqt_out, out, rqtn);
1339         return rqt;
1340 }
1341
1342 /**
1343  * Modify RQT using DevX API.
1344  *
1345  * @param[in] rqt
1346  *   Pointer to RQT DevX object structure.
1347  * @param [in] rqt_attr
1348  *   Pointer to RQT attributes structure.
1349  *
1350  * @return
1351  *   0 on success, a negative errno value otherwise and rte_errno is set.
1352  */
1353 int
1354 mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
1355                          struct mlx5_devx_rqt_attr *rqt_attr)
1356 {
1357         uint32_t inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) +
1358                          rqt_attr->rqt_actual_size * sizeof(uint32_t);
1359         uint32_t out[MLX5_ST_SZ_DW(modify_rqt_out)] = {0};
1360         uint32_t *in = mlx5_malloc(MLX5_MEM_ZERO, inlen, 0, SOCKET_ID_ANY);
1361         void *rqt_ctx;
1362         int i;
1363         int ret;
1364
1365         if (!in) {
1366                 DRV_LOG(ERR, "Failed to allocate RQT modify IN data.");
1367                 rte_errno = ENOMEM;
1368                 return -ENOMEM;
1369         }
1370         MLX5_SET(modify_rqt_in, in, opcode, MLX5_CMD_OP_MODIFY_RQT);
1371         MLX5_SET(modify_rqt_in, in, rqtn, rqt->id);
1372         MLX5_SET64(modify_rqt_in, in, modify_bitmask, 0x1);
1373         rqt_ctx = MLX5_ADDR_OF(modify_rqt_in, in, rqt_context);
1374         MLX5_SET(rqtc, rqt_ctx, list_q_type, rqt_attr->rq_type);
1375         MLX5_SET(rqtc, rqt_ctx, rqt_max_size, rqt_attr->rqt_max_size);
1376         MLX5_SET(rqtc, rqt_ctx, rqt_actual_size, rqt_attr->rqt_actual_size);
1377         for (i = 0; i < rqt_attr->rqt_actual_size; i++)
1378                 MLX5_SET(rqtc, rqt_ctx, rq_num[i], rqt_attr->rq_list[i]);
1379         ret = mlx5_glue->devx_obj_modify(rqt->obj, in, inlen, out, sizeof(out));
1380         mlx5_free(in);
1381         if (ret) {
1382                 DRV_LOG(ERR, "Failed to modify RQT using DevX.");
1383                 rte_errno = errno;
1384                 return -rte_errno;
1385         }
1386         return ret;
1387 }
1388
1389 /**
1390  * Create SQ using DevX API.
1391  *
1392  * @param[in] ctx
1393  *   Context returned from mlx5 open_device() glue function.
1394  * @param [in] sq_attr
1395  *   Pointer to SQ attributes structure.
1396  * @param [in] socket
1397  *   CPU socket ID for allocations.
1398  *
1399  * @return
1400  *   The DevX object created, NULL otherwise and rte_errno is set.
1401  **/
1402 struct mlx5_devx_obj *
1403 mlx5_devx_cmd_create_sq(void *ctx,
1404                         struct mlx5_devx_create_sq_attr *sq_attr)
1405 {
1406         uint32_t in[MLX5_ST_SZ_DW(create_sq_in)] = {0};
1407         uint32_t out[MLX5_ST_SZ_DW(create_sq_out)] = {0};
1408         void *sq_ctx;
1409         void *wq_ctx;
1410         struct mlx5_devx_wq_attr *wq_attr;
1411         struct mlx5_devx_obj *sq = NULL;
1412
1413         sq = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sq), 0, SOCKET_ID_ANY);
1414         if (!sq) {
1415                 DRV_LOG(ERR, "Failed to allocate SQ data");
1416                 rte_errno = ENOMEM;
1417                 return NULL;
1418         }
1419         MLX5_SET(create_sq_in, in, opcode, MLX5_CMD_OP_CREATE_SQ);
1420         sq_ctx = MLX5_ADDR_OF(create_sq_in, in, ctx);
1421         MLX5_SET(sqc, sq_ctx, rlky, sq_attr->rlky);
1422         MLX5_SET(sqc, sq_ctx, cd_master, sq_attr->cd_master);
1423         MLX5_SET(sqc, sq_ctx, fre, sq_attr->fre);
1424         MLX5_SET(sqc, sq_ctx, flush_in_error_en, sq_attr->flush_in_error_en);
1425         MLX5_SET(sqc, sq_ctx, allow_multi_pkt_send_wqe,
1426                  sq_attr->allow_multi_pkt_send_wqe);
1427         MLX5_SET(sqc, sq_ctx, min_wqe_inline_mode,
1428                  sq_attr->min_wqe_inline_mode);
1429         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1430         MLX5_SET(sqc, sq_ctx, reg_umr, sq_attr->reg_umr);
1431         MLX5_SET(sqc, sq_ctx, allow_swp, sq_attr->allow_swp);
1432         MLX5_SET(sqc, sq_ctx, hairpin, sq_attr->hairpin);
1433         MLX5_SET(sqc, sq_ctx, non_wire, sq_attr->non_wire);
1434         MLX5_SET(sqc, sq_ctx, static_sq_wq, sq_attr->static_sq_wq);
1435         MLX5_SET(sqc, sq_ctx, user_index, sq_attr->user_index);
1436         MLX5_SET(sqc, sq_ctx, cqn, sq_attr->cqn);
1437         MLX5_SET(sqc, sq_ctx, packet_pacing_rate_limit_index,
1438                  sq_attr->packet_pacing_rate_limit_index);
1439         MLX5_SET(sqc, sq_ctx, tis_lst_sz, sq_attr->tis_lst_sz);
1440         MLX5_SET(sqc, sq_ctx, tis_num_0, sq_attr->tis_num);
1441         MLX5_SET(sqc, sq_ctx, ts_format, sq_attr->ts_format);
1442         wq_ctx = MLX5_ADDR_OF(sqc, sq_ctx, wq);
1443         wq_attr = &sq_attr->wq_attr;
1444         devx_cmd_fill_wq_data(wq_ctx, wq_attr);
1445         sq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1446                                              out, sizeof(out));
1447         if (!sq->obj) {
1448                 DRV_LOG(ERR, "Failed to create SQ using DevX");
1449                 rte_errno = errno;
1450                 mlx5_free(sq);
1451                 return NULL;
1452         }
1453         sq->id = MLX5_GET(create_sq_out, out, sqn);
1454         return sq;
1455 }
1456
1457 /**
1458  * Modify SQ using DevX API.
1459  *
1460  * @param[in] sq
1461  *   Pointer to SQ object structure.
1462  * @param [in] sq_attr
1463  *   Pointer to SQ attributes structure.
1464  *
1465  * @return
1466  *   0 on success, a negative errno value otherwise and rte_errno is set.
1467  */
1468 int
1469 mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
1470                         struct mlx5_devx_modify_sq_attr *sq_attr)
1471 {
1472         uint32_t in[MLX5_ST_SZ_DW(modify_sq_in)] = {0};
1473         uint32_t out[MLX5_ST_SZ_DW(modify_sq_out)] = {0};
1474         void *sq_ctx;
1475         int ret;
1476
1477         MLX5_SET(modify_sq_in, in, opcode, MLX5_CMD_OP_MODIFY_SQ);
1478         MLX5_SET(modify_sq_in, in, sq_state, sq_attr->sq_state);
1479         MLX5_SET(modify_sq_in, in, sqn, sq->id);
1480         sq_ctx = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1481         MLX5_SET(sqc, sq_ctx, state, sq_attr->state);
1482         MLX5_SET(sqc, sq_ctx, hairpin_peer_rq, sq_attr->hairpin_peer_rq);
1483         MLX5_SET(sqc, sq_ctx, hairpin_peer_vhca, sq_attr->hairpin_peer_vhca);
1484         ret = mlx5_glue->devx_obj_modify(sq->obj, in, sizeof(in),
1485                                          out, sizeof(out));
1486         if (ret) {
1487                 DRV_LOG(ERR, "Failed to modify SQ using DevX");
1488                 rte_errno = errno;
1489                 return -rte_errno;
1490         }
1491         return ret;
1492 }
1493
1494 /**
1495  * Create TIS using DevX API.
1496  *
1497  * @param[in] ctx
1498  *   Context returned from mlx5 open_device() glue function.
1499  * @param [in] tis_attr
1500  *   Pointer to TIS attributes structure.
1501  *
1502  * @return
1503  *   The DevX object created, NULL otherwise and rte_errno is set.
1504  */
1505 struct mlx5_devx_obj *
1506 mlx5_devx_cmd_create_tis(void *ctx,
1507                          struct mlx5_devx_tis_attr *tis_attr)
1508 {
1509         uint32_t in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1510         uint32_t out[MLX5_ST_SZ_DW(create_tis_out)] = {0};
1511         struct mlx5_devx_obj *tis = NULL;
1512         void *tis_ctx;
1513
1514         tis = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*tis), 0, SOCKET_ID_ANY);
1515         if (!tis) {
1516                 DRV_LOG(ERR, "Failed to allocate TIS object");
1517                 rte_errno = ENOMEM;
1518                 return NULL;
1519         }
1520         MLX5_SET(create_tis_in, in, opcode, MLX5_CMD_OP_CREATE_TIS);
1521         tis_ctx = MLX5_ADDR_OF(create_tis_in, in, ctx);
1522         MLX5_SET(tisc, tis_ctx, strict_lag_tx_port_affinity,
1523                  tis_attr->strict_lag_tx_port_affinity);
1524         MLX5_SET(tisc, tis_ctx, lag_tx_port_affinity,
1525                  tis_attr->lag_tx_port_affinity);
1526         MLX5_SET(tisc, tis_ctx, prio, tis_attr->prio);
1527         MLX5_SET(tisc, tis_ctx, transport_domain,
1528                  tis_attr->transport_domain);
1529         tis->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1530                                               out, sizeof(out));
1531         if (!tis->obj) {
1532                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1533                 rte_errno = errno;
1534                 mlx5_free(tis);
1535                 return NULL;
1536         }
1537         tis->id = MLX5_GET(create_tis_out, out, tisn);
1538         return tis;
1539 }
1540
1541 /**
1542  * Create transport domain using DevX API.
1543  *
1544  * @param[in] ctx
1545  *   Context returned from mlx5 open_device() glue function.
1546  * @return
1547  *   The DevX object created, NULL otherwise and rte_errno is set.
1548  */
1549 struct mlx5_devx_obj *
1550 mlx5_devx_cmd_create_td(void *ctx)
1551 {
1552         uint32_t in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0};
1553         uint32_t out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0};
1554         struct mlx5_devx_obj *td = NULL;
1555
1556         td = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*td), 0, SOCKET_ID_ANY);
1557         if (!td) {
1558                 DRV_LOG(ERR, "Failed to allocate TD object");
1559                 rte_errno = ENOMEM;
1560                 return NULL;
1561         }
1562         MLX5_SET(alloc_transport_domain_in, in, opcode,
1563                  MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN);
1564         td->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
1565                                              out, sizeof(out));
1566         if (!td->obj) {
1567                 DRV_LOG(ERR, "Failed to create TIS using DevX");
1568                 rte_errno = errno;
1569                 mlx5_free(td);
1570                 return NULL;
1571         }
1572         td->id = MLX5_GET(alloc_transport_domain_out, out,
1573                            transport_domain);
1574         return td;
1575 }
1576
1577 /**
1578  * Dump all flows to file.
1579  *
1580  * @param[in] fdb_domain
1581  *   FDB domain.
1582  * @param[in] rx_domain
1583  *   RX domain.
1584  * @param[in] tx_domain
1585  *   TX domain.
1586  * @param[out] file
1587  *   Pointer to file stream.
1588  *
1589  * @return
1590  *   0 on success, a nagative value otherwise.
1591  */
1592 int
1593 mlx5_devx_cmd_flow_dump(void *fdb_domain __rte_unused,
1594                         void *rx_domain __rte_unused,
1595                         void *tx_domain __rte_unused, FILE *file __rte_unused)
1596 {
1597         int ret = 0;
1598
1599 #ifdef HAVE_MLX5_DR_FLOW_DUMP
1600         if (fdb_domain) {
1601                 ret = mlx5_glue->dr_dump_domain(file, fdb_domain);
1602                 if (ret)
1603                         return ret;
1604         }
1605         MLX5_ASSERT(rx_domain);
1606         ret = mlx5_glue->dr_dump_domain(file, rx_domain);
1607         if (ret)
1608                 return ret;
1609         MLX5_ASSERT(tx_domain);
1610         ret = mlx5_glue->dr_dump_domain(file, tx_domain);
1611 #else
1612         ret = ENOTSUP;
1613 #endif
1614         return -ret;
1615 }
1616
1617 int
1618 mlx5_devx_cmd_flow_single_dump(void *rule_info __rte_unused,
1619                         FILE *file __rte_unused)
1620 {
1621         int ret = 0;
1622 #ifdef HAVE_MLX5_DR_FLOW_DUMP_RULE
1623         if (rule_info)
1624                 ret = mlx5_glue->dr_dump_rule(file, rule_info);
1625 #else
1626         ret = ENOTSUP;
1627 #endif
1628         return -ret;
1629 }
1630
1631 /*
1632  * Create CQ using DevX API.
1633  *
1634  * @param[in] ctx
1635  *   Context returned from mlx5 open_device() glue function.
1636  * @param [in] attr
1637  *   Pointer to CQ attributes structure.
1638  *
1639  * @return
1640  *   The DevX object created, NULL otherwise and rte_errno is set.
1641  */
1642 struct mlx5_devx_obj *
1643 mlx5_devx_cmd_create_cq(void *ctx, struct mlx5_devx_cq_attr *attr)
1644 {
1645         uint32_t in[MLX5_ST_SZ_DW(create_cq_in)] = {0};
1646         uint32_t out[MLX5_ST_SZ_DW(create_cq_out)] = {0};
1647         struct mlx5_devx_obj *cq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1648                                                    sizeof(*cq_obj),
1649                                                    0, SOCKET_ID_ANY);
1650         void *cqctx = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1651
1652         if (!cq_obj) {
1653                 DRV_LOG(ERR, "Failed to allocate CQ object memory.");
1654                 rte_errno = ENOMEM;
1655                 return NULL;
1656         }
1657         MLX5_SET(create_cq_in, in, opcode, MLX5_CMD_OP_CREATE_CQ);
1658         if (attr->db_umem_valid) {
1659                 MLX5_SET(cqc, cqctx, dbr_umem_valid, attr->db_umem_valid);
1660                 MLX5_SET(cqc, cqctx, dbr_umem_id, attr->db_umem_id);
1661                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_umem_offset);
1662         } else {
1663                 MLX5_SET64(cqc, cqctx, dbr_addr, attr->db_addr);
1664         }
1665         MLX5_SET(cqc, cqctx, cqe_sz, (RTE_CACHE_LINE_SIZE == 128) ?
1666                                      MLX5_CQE_SIZE_128B : MLX5_CQE_SIZE_64B);
1667         MLX5_SET(cqc, cqctx, cc, attr->use_first_only);
1668         MLX5_SET(cqc, cqctx, oi, attr->overrun_ignore);
1669         MLX5_SET(cqc, cqctx, log_cq_size, attr->log_cq_size);
1670         if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
1671                 MLX5_SET(cqc, cqctx, log_page_size,
1672                          attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
1673         MLX5_SET(cqc, cqctx, c_eqn, attr->eqn);
1674         MLX5_SET(cqc, cqctx, uar_page, attr->uar_page_id);
1675         MLX5_SET(cqc, cqctx, cqe_comp_en, !!attr->cqe_comp_en);
1676         MLX5_SET(cqc, cqctx, mini_cqe_res_format, attr->mini_cqe_res_format);
1677         MLX5_SET(cqc, cqctx, mini_cqe_res_format_ext,
1678                  attr->mini_cqe_res_format_ext);
1679         if (attr->q_umem_valid) {
1680                 MLX5_SET(create_cq_in, in, cq_umem_valid, attr->q_umem_valid);
1681                 MLX5_SET(create_cq_in, in, cq_umem_id, attr->q_umem_id);
1682                 MLX5_SET64(create_cq_in, in, cq_umem_offset,
1683                            attr->q_umem_offset);
1684         }
1685         cq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1686                                                  sizeof(out));
1687         if (!cq_obj->obj) {
1688                 rte_errno = errno;
1689                 DRV_LOG(ERR, "Failed to create CQ using DevX errno=%d.", errno);
1690                 mlx5_free(cq_obj);
1691                 return NULL;
1692         }
1693         cq_obj->id = MLX5_GET(create_cq_out, out, cqn);
1694         return cq_obj;
1695 }
1696
1697 /**
1698  * Create VIRTQ using DevX API.
1699  *
1700  * @param[in] ctx
1701  *   Context returned from mlx5 open_device() glue function.
1702  * @param [in] attr
1703  *   Pointer to VIRTQ attributes structure.
1704  *
1705  * @return
1706  *   The DevX object created, NULL otherwise and rte_errno is set.
1707  */
1708 struct mlx5_devx_obj *
1709 mlx5_devx_cmd_create_virtq(void *ctx,
1710                            struct mlx5_devx_virtq_attr *attr)
1711 {
1712         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1713         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1714         struct mlx5_devx_obj *virtq_obj = mlx5_malloc(MLX5_MEM_ZERO,
1715                                                      sizeof(*virtq_obj),
1716                                                      0, SOCKET_ID_ANY);
1717         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1718         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1719         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1720
1721         if (!virtq_obj) {
1722                 DRV_LOG(ERR, "Failed to allocate virtq data.");
1723                 rte_errno = ENOMEM;
1724                 return NULL;
1725         }
1726         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1727                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
1728         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1729                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1730         MLX5_SET16(virtio_net_q, virtq, hw_available_index,
1731                    attr->hw_available_index);
1732         MLX5_SET16(virtio_net_q, virtq, hw_used_index, attr->hw_used_index);
1733         MLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);
1734         MLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);
1735         MLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);
1736         MLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);
1737         MLX5_SET16(virtio_q, virtctx, virtio_version_1_0,
1738                    attr->virtio_version_1_0);
1739         MLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);
1740         MLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);
1741         MLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);
1742         MLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);
1743         MLX5_SET64(virtio_q, virtctx, available_addr, attr->available_addr);
1744         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1745         MLX5_SET16(virtio_q, virtctx, queue_size, attr->q_size);
1746         MLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);
1747         MLX5_SET(virtio_q, virtctx, umem_1_id, attr->umems[0].id);
1748         MLX5_SET(virtio_q, virtctx, umem_1_size, attr->umems[0].size);
1749         MLX5_SET64(virtio_q, virtctx, umem_1_offset, attr->umems[0].offset);
1750         MLX5_SET(virtio_q, virtctx, umem_2_id, attr->umems[1].id);
1751         MLX5_SET(virtio_q, virtctx, umem_2_size, attr->umems[1].size);
1752         MLX5_SET64(virtio_q, virtctx, umem_2_offset, attr->umems[1].offset);
1753         MLX5_SET(virtio_q, virtctx, umem_3_id, attr->umems[2].id);
1754         MLX5_SET(virtio_q, virtctx, umem_3_size, attr->umems[2].size);
1755         MLX5_SET64(virtio_q, virtctx, umem_3_offset, attr->umems[2].offset);
1756         MLX5_SET(virtio_q, virtctx, counter_set_id, attr->counters_obj_id);
1757         MLX5_SET(virtio_q, virtctx, pd, attr->pd);
1758         MLX5_SET(virtio_q, virtctx, queue_period_mode, attr->hw_latency_mode);
1759         MLX5_SET(virtio_q, virtctx, queue_period_us, attr->hw_max_latency_us);
1760         MLX5_SET(virtio_q, virtctx, queue_max_count, attr->hw_max_pending_comp);
1761         MLX5_SET(virtio_net_q, virtq, tisn_or_qpn, attr->tis_id);
1762         virtq_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1763                                                     sizeof(out));
1764         if (!virtq_obj->obj) {
1765                 rte_errno = errno;
1766                 DRV_LOG(ERR, "Failed to create VIRTQ Obj using DevX.");
1767                 mlx5_free(virtq_obj);
1768                 return NULL;
1769         }
1770         virtq_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
1771         return virtq_obj;
1772 }
1773
1774 /**
1775  * Modify VIRTQ using DevX API.
1776  *
1777  * @param[in] virtq_obj
1778  *   Pointer to virtq object structure.
1779  * @param [in] attr
1780  *   Pointer to modify virtq attributes structure.
1781  *
1782  * @return
1783  *   0 on success, a negative errno value otherwise and rte_errno is set.
1784  */
1785 int
1786 mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
1787                            struct mlx5_devx_virtq_attr *attr)
1788 {
1789         uint32_t in[MLX5_ST_SZ_DW(create_virtq_in)] = {0};
1790         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
1791         void *virtq = MLX5_ADDR_OF(create_virtq_in, in, virtq);
1792         void *hdr = MLX5_ADDR_OF(create_virtq_in, in, hdr);
1793         void *virtctx = MLX5_ADDR_OF(virtio_net_q, virtq, virtio_q_context);
1794         int ret;
1795
1796         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1797                  MLX5_CMD_OP_MODIFY_GENERAL_OBJECT);
1798         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1799                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1800         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1801         MLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);
1802         MLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);
1803         switch (attr->type) {
1804         case MLX5_VIRTQ_MODIFY_TYPE_STATE:
1805                 MLX5_SET16(virtio_net_q, virtq, state, attr->state);
1806                 break;
1807         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:
1808                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,
1809                          attr->dirty_bitmap_mkey);
1810                 MLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,
1811                          attr->dirty_bitmap_addr);
1812                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,
1813                          attr->dirty_bitmap_size);
1814                 break;
1815         case MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:
1816                 MLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,
1817                          attr->dirty_bitmap_dump_enable);
1818                 break;
1819         default:
1820                 rte_errno = EINVAL;
1821                 return -rte_errno;
1822         }
1823         ret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),
1824                                          out, sizeof(out));
1825         if (ret) {
1826                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1827                 rte_errno = errno;
1828                 return -rte_errno;
1829         }
1830         return ret;
1831 }
1832
1833 /**
1834  * Query VIRTQ using DevX API.
1835  *
1836  * @param[in] virtq_obj
1837  *   Pointer to virtq object structure.
1838  * @param [in/out] attr
1839  *   Pointer to virtq attributes structure.
1840  *
1841  * @return
1842  *   0 on success, a negative errno value otherwise and rte_errno is set.
1843  */
1844 int
1845 mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
1846                            struct mlx5_devx_virtq_attr *attr)
1847 {
1848         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
1849         uint32_t out[MLX5_ST_SZ_DW(query_virtq_out)] = {0};
1850         void *hdr = MLX5_ADDR_OF(query_virtq_out, in, hdr);
1851         void *virtq = MLX5_ADDR_OF(query_virtq_out, out, virtq);
1852         int ret;
1853
1854         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
1855                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
1856         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
1857                  MLX5_GENERAL_OBJ_TYPE_VIRTQ);
1858         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);
1859         ret = mlx5_glue->devx_obj_query(virtq_obj->obj, in, sizeof(in),
1860                                          out, sizeof(out));
1861         if (ret) {
1862                 DRV_LOG(ERR, "Failed to modify VIRTQ using DevX.");
1863                 rte_errno = errno;
1864                 return -errno;
1865         }
1866         attr->hw_available_index = MLX5_GET16(virtio_net_q, virtq,
1867                                               hw_available_index);
1868         attr->hw_used_index = MLX5_GET16(virtio_net_q, virtq, hw_used_index);
1869         attr->state = MLX5_GET16(virtio_net_q, virtq, state);
1870         attr->error_type = MLX5_GET16(virtio_net_q, virtq,
1871                                       virtio_q_context.error_type);
1872         return ret;
1873 }
1874
1875 /**
1876  * Create QP using DevX API.
1877  *
1878  * @param[in] ctx
1879  *   Context returned from mlx5 open_device() glue function.
1880  * @param [in] attr
1881  *   Pointer to QP attributes structure.
1882  *
1883  * @return
1884  *   The DevX object created, NULL otherwise and rte_errno is set.
1885  */
1886 struct mlx5_devx_obj *
1887 mlx5_devx_cmd_create_qp(void *ctx,
1888                         struct mlx5_devx_qp_attr *attr)
1889 {
1890         uint32_t in[MLX5_ST_SZ_DW(create_qp_in)] = {0};
1891         uint32_t out[MLX5_ST_SZ_DW(create_qp_out)] = {0};
1892         struct mlx5_devx_obj *qp_obj = mlx5_malloc(MLX5_MEM_ZERO,
1893                                                    sizeof(*qp_obj),
1894                                                    0, SOCKET_ID_ANY);
1895         void *qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1896
1897         if (!qp_obj) {
1898                 DRV_LOG(ERR, "Failed to allocate QP data.");
1899                 rte_errno = ENOMEM;
1900                 return NULL;
1901         }
1902         MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
1903         MLX5_SET(qpc, qpc, st, MLX5_QP_ST_RC);
1904         MLX5_SET(qpc, qpc, pd, attr->pd);
1905         MLX5_SET(qpc, qpc, ts_format, attr->ts_format);
1906         if (attr->uar_index) {
1907                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1908                 MLX5_SET(qpc, qpc, uar_page, attr->uar_index);
1909                 if (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)
1910                         MLX5_SET(qpc, qpc, log_page_size,
1911                                  attr->log_page_size - MLX5_ADAPTER_PAGE_SHIFT);
1912                 if (attr->sq_size) {
1913                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->sq_size));
1914                         MLX5_SET(qpc, qpc, cqn_snd, attr->cqn);
1915                         MLX5_SET(qpc, qpc, log_sq_size,
1916                                  rte_log2_u32(attr->sq_size));
1917                 } else {
1918                         MLX5_SET(qpc, qpc, no_sq, 1);
1919                 }
1920                 if (attr->rq_size) {
1921                         MLX5_ASSERT(RTE_IS_POWER_OF_2(attr->rq_size));
1922                         MLX5_SET(qpc, qpc, cqn_rcv, attr->cqn);
1923                         MLX5_SET(qpc, qpc, log_rq_stride, attr->log_rq_stride -
1924                                  MLX5_LOG_RQ_STRIDE_SHIFT);
1925                         MLX5_SET(qpc, qpc, log_rq_size,
1926                                  rte_log2_u32(attr->rq_size));
1927                         MLX5_SET(qpc, qpc, rq_type, MLX5_NON_ZERO_RQ);
1928                 } else {
1929                         MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1930                 }
1931                 if (attr->dbr_umem_valid) {
1932                         MLX5_SET(qpc, qpc, dbr_umem_valid,
1933                                  attr->dbr_umem_valid);
1934                         MLX5_SET(qpc, qpc, dbr_umem_id, attr->dbr_umem_id);
1935                 }
1936                 MLX5_SET64(qpc, qpc, dbr_addr, attr->dbr_address);
1937                 MLX5_SET64(create_qp_in, in, wq_umem_offset,
1938                            attr->wq_umem_offset);
1939                 MLX5_SET(create_qp_in, in, wq_umem_id, attr->wq_umem_id);
1940                 MLX5_SET(create_qp_in, in, wq_umem_valid, 1);
1941         } else {
1942                 /* Special QP to be managed by FW - no SQ\RQ\CQ\UAR\DB rec. */
1943                 MLX5_SET(qpc, qpc, rq_type, MLX5_ZERO_LEN_RQ);
1944                 MLX5_SET(qpc, qpc, no_sq, 1);
1945         }
1946         qp_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
1947                                                  sizeof(out));
1948         if (!qp_obj->obj) {
1949                 rte_errno = errno;
1950                 DRV_LOG(ERR, "Failed to create QP Obj using DevX.");
1951                 mlx5_free(qp_obj);
1952                 return NULL;
1953         }
1954         qp_obj->id = MLX5_GET(create_qp_out, out, qpn);
1955         return qp_obj;
1956 }
1957
1958 /**
1959  * Modify QP using DevX API.
1960  * Currently supports only force loop-back QP.
1961  *
1962  * @param[in] qp
1963  *   Pointer to QP object structure.
1964  * @param [in] qp_st_mod_op
1965  *   The QP state modification operation.
1966  * @param [in] remote_qp_id
1967  *   The remote QP ID for MLX5_CMD_OP_INIT2RTR_QP operation.
1968  *
1969  * @return
1970  *   0 on success, a negative errno value otherwise and rte_errno is set.
1971  */
1972 int
1973 mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp, uint32_t qp_st_mod_op,
1974                               uint32_t remote_qp_id)
1975 {
1976         union {
1977                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_in)];
1978                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_in)];
1979                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_in)];
1980         } in;
1981         union {
1982                 uint32_t rst2init[MLX5_ST_SZ_DW(rst2init_qp_out)];
1983                 uint32_t init2rtr[MLX5_ST_SZ_DW(init2rtr_qp_out)];
1984                 uint32_t rtr2rts[MLX5_ST_SZ_DW(rtr2rts_qp_out)];
1985         } out;
1986         void *qpc;
1987         int ret;
1988         unsigned int inlen;
1989         unsigned int outlen;
1990
1991         memset(&in, 0, sizeof(in));
1992         memset(&out, 0, sizeof(out));
1993         MLX5_SET(rst2init_qp_in, &in, opcode, qp_st_mod_op);
1994         switch (qp_st_mod_op) {
1995         case MLX5_CMD_OP_RST2INIT_QP:
1996                 MLX5_SET(rst2init_qp_in, &in, qpn, qp->id);
1997                 qpc = MLX5_ADDR_OF(rst2init_qp_in, &in, qpc);
1998                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
1999                 MLX5_SET(qpc, qpc, rre, 1);
2000                 MLX5_SET(qpc, qpc, rwe, 1);
2001                 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
2002                 inlen = sizeof(in.rst2init);
2003                 outlen = sizeof(out.rst2init);
2004                 break;
2005         case MLX5_CMD_OP_INIT2RTR_QP:
2006                 MLX5_SET(init2rtr_qp_in, &in, qpn, qp->id);
2007                 qpc = MLX5_ADDR_OF(init2rtr_qp_in, &in, qpc);
2008                 MLX5_SET(qpc, qpc, primary_address_path.fl, 1);
2009                 MLX5_SET(qpc, qpc, primary_address_path.vhca_port_num, 1);
2010                 MLX5_SET(qpc, qpc, mtu, 1);
2011                 MLX5_SET(qpc, qpc, log_msg_max, 30);
2012                 MLX5_SET(qpc, qpc, remote_qpn, remote_qp_id);
2013                 MLX5_SET(qpc, qpc, min_rnr_nak, 0);
2014                 inlen = sizeof(in.init2rtr);
2015                 outlen = sizeof(out.init2rtr);
2016                 break;
2017         case MLX5_CMD_OP_RTR2RTS_QP:
2018                 qpc = MLX5_ADDR_OF(rtr2rts_qp_in, &in, qpc);
2019                 MLX5_SET(rtr2rts_qp_in, &in, qpn, qp->id);
2020                 MLX5_SET(qpc, qpc, primary_address_path.ack_timeout, 14);
2021                 MLX5_SET(qpc, qpc, log_ack_req_freq, 0);
2022                 MLX5_SET(qpc, qpc, retry_count, 7);
2023                 MLX5_SET(qpc, qpc, rnr_retry, 7);
2024                 inlen = sizeof(in.rtr2rts);
2025                 outlen = sizeof(out.rtr2rts);
2026                 break;
2027         default:
2028                 DRV_LOG(ERR, "Invalid or unsupported QP modify op %u.",
2029                         qp_st_mod_op);
2030                 rte_errno = EINVAL;
2031                 return -rte_errno;
2032         }
2033         ret = mlx5_glue->devx_obj_modify(qp->obj, &in, inlen, &out, outlen);
2034         if (ret) {
2035                 DRV_LOG(ERR, "Failed to modify QP using DevX.");
2036                 rte_errno = errno;
2037                 return -rte_errno;
2038         }
2039         return ret;
2040 }
2041
2042 struct mlx5_devx_obj *
2043 mlx5_devx_cmd_create_virtio_q_counters(void *ctx)
2044 {
2045         uint32_t in[MLX5_ST_SZ_DW(create_virtio_q_counters_in)] = {0};
2046         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2047         struct mlx5_devx_obj *couners_obj = mlx5_malloc(MLX5_MEM_ZERO,
2048                                                        sizeof(*couners_obj), 0,
2049                                                        SOCKET_ID_ANY);
2050         void *hdr = MLX5_ADDR_OF(create_virtio_q_counters_in, in, hdr);
2051
2052         if (!couners_obj) {
2053                 DRV_LOG(ERR, "Failed to allocate virtio queue counters data.");
2054                 rte_errno = ENOMEM;
2055                 return NULL;
2056         }
2057         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2058                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2059         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2060                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2061         couners_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2062                                                       sizeof(out));
2063         if (!couners_obj->obj) {
2064                 rte_errno = errno;
2065                 DRV_LOG(ERR, "Failed to create virtio queue counters Obj using"
2066                         " DevX.");
2067                 mlx5_free(couners_obj);
2068                 return NULL;
2069         }
2070         couners_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2071         return couners_obj;
2072 }
2073
2074 int
2075 mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
2076                                    struct mlx5_devx_virtio_q_couners_attr *attr)
2077 {
2078         uint32_t in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {0};
2079         uint32_t out[MLX5_ST_SZ_DW(query_virtio_q_counters_out)] = {0};
2080         void *hdr = MLX5_ADDR_OF(query_virtio_q_counters_out, in, hdr);
2081         void *virtio_q_counters = MLX5_ADDR_OF(query_virtio_q_counters_out, out,
2082                                                virtio_q_counters);
2083         int ret;
2084
2085         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2086                  MLX5_CMD_OP_QUERY_GENERAL_OBJECT);
2087         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2088                  MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS);
2089         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, couners_obj->id);
2090         ret = mlx5_glue->devx_obj_query(couners_obj->obj, in, sizeof(in), out,
2091                                         sizeof(out));
2092         if (ret) {
2093                 DRV_LOG(ERR, "Failed to query virtio q counters using DevX.");
2094                 rte_errno = errno;
2095                 return -errno;
2096         }
2097         attr->received_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2098                                          received_desc);
2099         attr->completed_desc = MLX5_GET64(virtio_q_counters, virtio_q_counters,
2100                                           completed_desc);
2101         attr->error_cqes = MLX5_GET(virtio_q_counters, virtio_q_counters,
2102                                     error_cqes);
2103         attr->bad_desc_errors = MLX5_GET(virtio_q_counters, virtio_q_counters,
2104                                          bad_desc_errors);
2105         attr->exceed_max_chain = MLX5_GET(virtio_q_counters, virtio_q_counters,
2106                                           exceed_max_chain);
2107         attr->invalid_buffer = MLX5_GET(virtio_q_counters, virtio_q_counters,
2108                                         invalid_buffer);
2109         return ret;
2110 }
2111
2112 /**
2113  * Create general object of type FLOW_HIT_ASO using DevX API.
2114  *
2115  * @param[in] ctx
2116  *   Context returned from mlx5 open_device() glue function.
2117  * @param [in] pd
2118  *   PD value to associate the FLOW_HIT_ASO object with.
2119  *
2120  * @return
2121  *   The DevX object created, NULL otherwise and rte_errno is set.
2122  */
2123 struct mlx5_devx_obj *
2124 mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx, uint32_t pd)
2125 {
2126         uint32_t in[MLX5_ST_SZ_DW(create_flow_hit_aso_in)] = {0};
2127         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2128         struct mlx5_devx_obj *flow_hit_aso_obj = NULL;
2129         void *ptr = NULL;
2130
2131         flow_hit_aso_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_hit_aso_obj),
2132                                        0, SOCKET_ID_ANY);
2133         if (!flow_hit_aso_obj) {
2134                 DRV_LOG(ERR, "Failed to allocate FLOW_HIT_ASO object data");
2135                 rte_errno = ENOMEM;
2136                 return NULL;
2137         }
2138         ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, hdr);
2139         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2140                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2141         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2142                  MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO);
2143         ptr = MLX5_ADDR_OF(create_flow_hit_aso_in, in, flow_hit_aso);
2144         MLX5_SET(flow_hit_aso, ptr, access_pd, pd);
2145         flow_hit_aso_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2146                                                            out, sizeof(out));
2147         if (!flow_hit_aso_obj->obj) {
2148                 rte_errno = errno;
2149                 DRV_LOG(ERR, "Failed to create FLOW_HIT_ASO obj using DevX.");
2150                 mlx5_free(flow_hit_aso_obj);
2151                 return NULL;
2152         }
2153         flow_hit_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2154         return flow_hit_aso_obj;
2155 }
2156
2157 /*
2158  * Create PD using DevX API.
2159  *
2160  * @param[in] ctx
2161  *   Context returned from mlx5 open_device() glue function.
2162  *
2163  * @return
2164  *   The DevX object created, NULL otherwise and rte_errno is set.
2165  */
2166 struct mlx5_devx_obj *
2167 mlx5_devx_cmd_alloc_pd(void *ctx)
2168 {
2169         struct mlx5_devx_obj *ppd =
2170                 mlx5_malloc(MLX5_MEM_ZERO, sizeof(*ppd), 0, SOCKET_ID_ANY);
2171         u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0};
2172         u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0};
2173
2174         if (!ppd) {
2175                 DRV_LOG(ERR, "Failed to allocate PD data.");
2176                 rte_errno = ENOMEM;
2177                 return NULL;
2178         }
2179         MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2180         ppd->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2181                                 out, sizeof(out));
2182         if (!ppd->obj) {
2183                 mlx5_free(ppd);
2184                 DRV_LOG(ERR, "Failed to allocate PD Obj using DevX.");
2185                 rte_errno = errno;
2186                 return NULL;
2187         }
2188         ppd->id = MLX5_GET(alloc_pd_out, out, pd);
2189         return ppd;
2190 }
2191
2192 /**
2193  * Create general object of type FLOW_METER_ASO using DevX API.
2194  *
2195  * @param[in] ctx
2196  *   Context returned from mlx5 open_device() glue function.
2197  * @param [in] pd
2198  *   PD value to associate the FLOW_METER_ASO object with.
2199  * @param [in] log_obj_size
2200  *   log_obj_size define to allocate number of 2 * meters
2201  *   in one FLOW_METER_ASO object.
2202  *
2203  * @return
2204  *   The DevX object created, NULL otherwise and rte_errno is set.
2205  */
2206 struct mlx5_devx_obj *
2207 mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx, uint32_t pd,
2208                                                 uint32_t log_obj_size)
2209 {
2210         uint32_t in[MLX5_ST_SZ_DW(create_flow_meter_aso_in)] = {0};
2211         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)];
2212         struct mlx5_devx_obj *flow_meter_aso_obj;
2213         void *ptr;
2214
2215         flow_meter_aso_obj = mlx5_malloc(MLX5_MEM_ZERO,
2216                                                 sizeof(*flow_meter_aso_obj),
2217                                                 0, SOCKET_ID_ANY);
2218         if (!flow_meter_aso_obj) {
2219                 DRV_LOG(ERR, "Failed to allocate FLOW_METER_ASO object data");
2220                 rte_errno = ENOMEM;
2221                 return NULL;
2222         }
2223         ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, hdr);
2224         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2225                 MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2226         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2227                 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO);
2228         MLX5_SET(general_obj_in_cmd_hdr, ptr, log_obj_range,
2229                 log_obj_size);
2230         ptr = MLX5_ADDR_OF(create_flow_meter_aso_in, in, flow_meter_aso);
2231         MLX5_SET(flow_meter_aso, ptr, access_pd, pd);
2232         flow_meter_aso_obj->obj = mlx5_glue->devx_obj_create(
2233                                                         ctx, in, sizeof(in),
2234                                                         out, sizeof(out));
2235         if (!flow_meter_aso_obj->obj) {
2236                 rte_errno = errno;
2237                 DRV_LOG(ERR, "Failed to create FLOW_METER_ASO obj using DevX.");
2238                 mlx5_free(flow_meter_aso_obj);
2239                 return NULL;
2240         }
2241         flow_meter_aso_obj->id = MLX5_GET(general_obj_out_cmd_hdr,
2242                                                                 out, obj_id);
2243         return flow_meter_aso_obj;
2244 }
2245
2246 /**
2247  * Create general object of type GENEVE TLV option using DevX API.
2248  *
2249  * @param[in] ctx
2250  *   Context returned from mlx5 open_device() glue function.
2251  * @param [in] class
2252  *   TLV option variable value of class
2253  * @param [in] type
2254  *   TLV option variable value of type
2255  * @param [in] len
2256  *   TLV option variable value of len
2257  *
2258  * @return
2259  *   The DevX object created, NULL otherwise and rte_errno is set.
2260  */
2261 struct mlx5_devx_obj *
2262 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
2263                 uint16_t class, uint8_t type, uint8_t len)
2264 {
2265         uint32_t in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {0};
2266         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2267         struct mlx5_devx_obj *geneve_tlv_opt_obj = mlx5_malloc(MLX5_MEM_ZERO,
2268                                                    sizeof(*geneve_tlv_opt_obj),
2269                                                    0, SOCKET_ID_ANY);
2270
2271         if (!geneve_tlv_opt_obj) {
2272                 DRV_LOG(ERR, "Failed to allocate geneve tlv option object.");
2273                 rte_errno = ENOMEM;
2274                 return NULL;
2275         }
2276         void *hdr = MLX5_ADDR_OF(create_geneve_tlv_option_in, in, hdr);
2277         void *opt = MLX5_ADDR_OF(create_geneve_tlv_option_in, in,
2278                         geneve_tlv_opt);
2279         MLX5_SET(general_obj_in_cmd_hdr, hdr, opcode,
2280                         MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2281         MLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,
2282                  MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT);
2283         MLX5_SET(geneve_tlv_option, opt, option_class,
2284                         rte_be_to_cpu_16(class));
2285         MLX5_SET(geneve_tlv_option, opt, option_type, type);
2286         MLX5_SET(geneve_tlv_option, opt, option_data_length, len);
2287         geneve_tlv_opt_obj->obj = mlx5_glue->devx_obj_create(ctx, in,
2288                                         sizeof(in), out, sizeof(out));
2289         if (!geneve_tlv_opt_obj->obj) {
2290                 rte_errno = errno;
2291                 DRV_LOG(ERR, "Failed to create Geneve tlv option "
2292                                 "Obj using DevX.");
2293                 mlx5_free(geneve_tlv_opt_obj);
2294                 return NULL;
2295         }
2296         geneve_tlv_opt_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2297         return geneve_tlv_opt_obj;
2298 }
2299
2300 int
2301 mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id)
2302 {
2303 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
2304         uint32_t in[MLX5_ST_SZ_DW(query_rq_in)] = {0};
2305         uint32_t out[MLX5_ST_SZ_DW(query_rq_out)] = {0};
2306         int rc;
2307         void *rq_ctx;
2308
2309         MLX5_SET(query_rq_in, in, opcode, MLX5_CMD_OP_QUERY_RQ);
2310         MLX5_SET(query_rq_in, in, rqn, ((struct ibv_wq *)wq)->wq_num);
2311         rc = mlx5_glue->devx_wq_query(wq, in, sizeof(in), out, sizeof(out));
2312         if (rc) {
2313                 rte_errno = errno;
2314                 DRV_LOG(ERR, "Failed to query WQ counter set ID using DevX - "
2315                         "rc = %d, errno = %d.", rc, errno);
2316                 return -rc;
2317         };
2318         rq_ctx = MLX5_ADDR_OF(query_rq_out, out, rq_context);
2319         *counter_set_id = MLX5_GET(rqc, rq_ctx, counter_set_id);
2320         return 0;
2321 #else
2322         (void)wq;
2323         (void)counter_set_id;
2324         return -ENOTSUP;
2325 #endif
2326 }
2327
2328 /*
2329  * Allocate queue counters via devx interface.
2330  *
2331  * @param[in] ctx
2332  *   Context returned from mlx5 open_device() glue function.
2333  *
2334  * @return
2335  *   Pointer to counter object on success, a NULL value otherwise and
2336  *   rte_errno is set.
2337  */
2338 struct mlx5_devx_obj *
2339 mlx5_devx_cmd_queue_counter_alloc(void *ctx)
2340 {
2341         struct mlx5_devx_obj *dcs = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dcs), 0,
2342                                                 SOCKET_ID_ANY);
2343         uint32_t in[MLX5_ST_SZ_DW(alloc_q_counter_in)]   = {0};
2344         uint32_t out[MLX5_ST_SZ_DW(alloc_q_counter_out)] = {0};
2345
2346         if (!dcs) {
2347                 rte_errno = ENOMEM;
2348                 return NULL;
2349         }
2350         MLX5_SET(alloc_q_counter_in, in, opcode, MLX5_CMD_OP_ALLOC_Q_COUNTER);
2351         dcs->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in), out,
2352                                               sizeof(out));
2353         if (!dcs->obj) {
2354                 DRV_LOG(DEBUG, "Can't allocate q counter set by DevX - error "
2355                         "%d.", errno);
2356                 rte_errno = errno;
2357                 mlx5_free(dcs);
2358                 return NULL;
2359         }
2360         dcs->id = MLX5_GET(alloc_q_counter_out, out, counter_set_id);
2361         return dcs;
2362 }
2363
2364 /**
2365  * Query queue counters values.
2366  *
2367  * @param[in] dcs
2368  *   devx object of the queue counter set.
2369  * @param[in] clear
2370  *   Whether hardware should clear the counters after the query or not.
2371  *  @param[out] out_of_buffers
2372  *   Number of dropped occurred due to lack of WQE for the associated QPs/RQs.
2373  *
2374  * @return
2375  *   0 on success, a negative value otherwise.
2376  */
2377 int
2378 mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
2379                                   uint32_t *out_of_buffers)
2380 {
2381         uint32_t out[MLX5_ST_SZ_BYTES(query_q_counter_out)] = {0};
2382         uint32_t in[MLX5_ST_SZ_DW(query_q_counter_in)] = {0};
2383         int rc;
2384
2385         MLX5_SET(query_q_counter_in, in, opcode,
2386                  MLX5_CMD_OP_QUERY_Q_COUNTER);
2387         MLX5_SET(query_q_counter_in, in, op_mod, 0);
2388         MLX5_SET(query_q_counter_in, in, counter_set_id, dcs->id);
2389         MLX5_SET(query_q_counter_in, in, clear, !!clear);
2390         rc = mlx5_glue->devx_obj_query(dcs->obj, in, sizeof(in), out,
2391                                        sizeof(out));
2392         if (rc) {
2393                 DRV_LOG(ERR, "Failed to query devx q counter set - rc %d", rc);
2394                 rte_errno = rc;
2395                 return -rc;
2396         }
2397         *out_of_buffers = MLX5_GET(query_q_counter_out, out, out_of_buffer);
2398         return 0;
2399 }
2400
2401 /**
2402  * Create general object of type DEK using DevX API.
2403  *
2404  * @param[in] ctx
2405  *   Context returned from mlx5 open_device() glue function.
2406  * @param [in] attr
2407  *   Pointer to DEK attributes structure.
2408  *
2409  * @return
2410  *   The DevX object created, NULL otherwise and rte_errno is set.
2411  */
2412 struct mlx5_devx_obj *
2413 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr)
2414 {
2415         uint32_t in[MLX5_ST_SZ_DW(create_dek_in)] = {0};
2416         uint32_t out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {0};
2417         struct mlx5_devx_obj *dek_obj = NULL;
2418         void *ptr = NULL, *key_addr = NULL;
2419
2420         dek_obj = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*dek_obj),
2421                               0, SOCKET_ID_ANY);
2422         if (dek_obj == NULL) {
2423                 DRV_LOG(ERR, "Failed to allocate DEK object data");
2424                 rte_errno = ENOMEM;
2425                 return NULL;
2426         }
2427         ptr = MLX5_ADDR_OF(create_dek_in, in, hdr);
2428         MLX5_SET(general_obj_in_cmd_hdr, ptr, opcode,
2429                  MLX5_CMD_OP_CREATE_GENERAL_OBJECT);
2430         MLX5_SET(general_obj_in_cmd_hdr, ptr, obj_type,
2431                  MLX5_GENERAL_OBJ_TYPE_DEK);
2432         ptr = MLX5_ADDR_OF(create_dek_in, in, dek);
2433         MLX5_SET(dek, ptr, key_size, attr->key_size);
2434         MLX5_SET(dek, ptr, has_keytag, attr->has_keytag);
2435         MLX5_SET(dek, ptr, key_purpose, attr->key_purpose);
2436         MLX5_SET(dek, ptr, pd, attr->pd);
2437         MLX5_SET64(dek, ptr, opaque, attr->opaque);
2438         key_addr = MLX5_ADDR_OF(dek, ptr, key);
2439         memcpy(key_addr, (void *)(attr->key), MLX5_CRYPTO_KEY_MAX_SIZE);
2440         dek_obj->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),
2441                                                   out, sizeof(out));
2442         if (dek_obj->obj == NULL) {
2443                 rte_errno = errno;
2444                 DRV_LOG(ERR, "Failed to create DEK obj using DevX.");
2445                 mlx5_free(dek_obj);
2446                 return NULL;
2447         }
2448         dek_obj->id = MLX5_GET(general_obj_out_cmd_hdr, out, obj_id);
2449         return dek_obj;
2450 }