1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_
6 #define RTE_PMD_MLX5_DEVX_CMDS_H_
8 #include <rte_compat.h>
10 #include "mlx5_glue.h"
13 /* This is limitation of libibverbs: in length variable type is u16. */
14 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \
15 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4))
17 struct mlx5_devx_mkey_attr {
22 uint32_t log_entity_size;
24 uint32_t relaxed_ordering_write:1;
25 uint32_t relaxed_ordering_read:1;
28 uint32_t set_remote_rw:1;
29 struct mlx5_klm *klm_array;
33 /* HCA qos attributes. */
34 struct mlx5_hca_qos_attr {
35 uint32_t sup:1; /* Whether QOS is supported. */
36 uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */
37 uint32_t packet_pacing:1; /* Packet pacing is supported. */
38 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */
39 uint32_t flow_meter:1;
41 * Flow meter is supported, updated version.
42 * When flow_meter is 1, it indicates that REG_C sharing is supported.
43 * If flow_meter is 1, flow_meter_old is also 1.
44 * Using older driver versions, flow_meter_old can be 1
45 * while flow_meter is 0.
47 uint32_t flow_meter_aso_sup:1;
48 /* Whether FLOW_METER_ASO Object is supported. */
49 uint8_t log_max_flow_meter;
50 /* Power of the maximum supported meters. */
51 uint8_t flow_meter_reg_c_ids;
52 /* Bitmap of the reg_Cs available for flow meter to use. */
53 uint32_t log_meter_aso_granularity:5;
54 /* Power of the minimum allocation granularity Object. */
55 uint32_t log_meter_aso_max_alloc:5;
56 /* Power of the maximum allocation granularity Object. */
57 uint32_t log_max_num_meter_aso:5;
58 /* Power of the maximum number of supported objects. */
62 struct mlx5_hca_vdpa_attr {
63 uint8_t virtio_queue_type;
65 uint32_t desc_tunnel_offload_type:1;
66 uint32_t eth_frame_offload_type:1;
67 uint32_t virtio_version_1_0:1;
72 uint32_t event_mode:3;
73 uint32_t log_doorbell_stride:5;
74 uint32_t log_doorbell_bar_size:5;
75 uint32_t queue_counters_valid:1;
76 uint32_t max_num_virtio_queues;
81 uint64_t doorbell_bar_offset;
84 struct mlx5_hca_flow_attr {
85 uint32_t tunnel_header_0_1;
86 uint32_t tunnel_header_2_3;
89 /* HCA supports this number of time periods for LRO. */
90 #define MLX5_LRO_NUM_SUPP_PERIODS 4
93 struct mlx5_hca_attr {
94 uint32_t eswitch_manager:1;
95 uint32_t flow_counters_dump:1;
96 uint32_t log_max_rqt_size:5;
97 uint32_t parse_graph_flex_node:1;
98 uint8_t flow_counter_bulk_alloc_bitmap;
99 uint32_t eth_net_offloads:1;
101 uint32_t wqe_vlan_insert:1;
104 uint32_t wqe_inline_mode:2;
105 uint32_t vport_inline_mode:3;
106 uint32_t tunnel_stateless_geneve_rx:1;
107 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
108 uint32_t tunnel_stateless_gtp:1;
109 uint32_t max_lso_cap;
110 uint32_t scatter_fcs:1;
112 uint32_t tunnel_lro_gre:1;
113 uint32_t tunnel_lro_vxlan:1;
114 uint32_t tunnel_stateless_gre:1;
115 uint32_t tunnel_stateless_vxlan:1;
119 uint32_t lro_max_msg_sz_mode:2;
120 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
121 uint16_t lro_min_mss_size;
122 uint32_t flex_parser_protocols;
123 uint32_t max_geneve_tlv_options;
124 uint32_t max_geneve_tlv_option_data_len;
126 uint32_t log_max_hairpin_queues:5;
127 uint32_t log_max_hairpin_wq_data_sz:5;
128 uint32_t log_max_hairpin_num_packets:5;
130 uint32_t relaxed_ordering_write:1;
131 uint32_t relaxed_ordering_read:1;
132 uint32_t access_register_user:1;
133 uint32_t wqe_index_ignore:1;
134 uint32_t cross_channel:1;
135 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */
136 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */
137 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */
138 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */
139 uint32_t scatter_fcs_w_decap_disable:1;
140 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */
142 uint32_t rq_ts_format:2;
143 uint32_t sq_ts_format:2;
144 uint32_t steering_format_version:4;
145 uint32_t qp_ts_format:2;
146 uint32_t regexp_params:1;
147 uint32_t regexp_version:3;
148 uint32_t reg_c_preserve:1;
149 uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */
150 uint32_t crypto:1; /* Crypto engine is supported. */
151 uint32_t aes_xts:1; /* AES-XTS crypto is supported. */
152 uint32_t dek:1; /* General obj type DEK is supported. */
153 uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */
154 uint32_t credential:1; /* General obj type CREDENTIAL supported. */
155 uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */
156 uint32_t regexp_num_of_engines;
157 uint32_t log_max_ft_sampler_num:8;
158 uint32_t inner_ipv4_ihl:1;
159 uint32_t outer_ipv4_ihl:1;
160 uint32_t geneve_tlv_opt;
161 uint32_t cqe_compression:1;
162 uint32_t mini_cqe_resp_flow_tag:1;
163 uint32_t mini_cqe_resp_l3_l4_tag:1;
164 uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */
165 struct mlx5_hca_qos_attr qos;
166 struct mlx5_hca_vdpa_attr vdpa;
167 struct mlx5_hca_flow_attr flow;
173 uint32_t log_max_mrw_sz;
174 uint32_t log_max_srq;
175 uint32_t log_max_srq_sz;
176 uint32_t rss_ind_tbl_cap;
177 uint32_t mmo_dma_sq_en:1;
178 uint32_t mmo_compress_sq_en:1;
179 uint32_t mmo_decompress_sq_en:1;
180 uint32_t mmo_dma_qp_en:1;
181 uint32_t mmo_compress_qp_en:1;
182 uint32_t mmo_decompress_qp_en:1;
183 uint32_t mmo_regex_qp_en:1;
184 uint32_t mmo_regex_sq_en:1;
185 uint32_t compress_min_block_size:4;
186 uint32_t log_max_mmo_dma:5;
187 uint32_t log_max_mmo_compress:5;
188 uint32_t log_max_mmo_decompress:5;
189 uint32_t umr_modify_entity_size_disabled:1;
190 uint32_t umr_indirect_mkey_disabled:1;
194 struct mlx5_devx_lag_context {
195 uint32_t fdb_selection_mode:1;
196 uint32_t port_select_mode:3;
197 uint32_t lag_state:3;
198 uint32_t tx_remap_affinity_1:4;
199 uint32_t tx_remap_affinity_2:4;
202 struct mlx5_devx_wq_attr {
204 uint32_t wq_signature:1;
205 uint32_t end_padding_mode:2;
207 uint32_t hds_skip_first_sge:1;
208 uint32_t log2_hds_buf_size:3;
209 uint32_t page_offset:5;
212 uint32_t uar_page:24;
216 uint32_t log_wq_stride:4;
217 uint32_t log_wq_pg_sz:5;
218 uint32_t log_wq_sz:5;
219 uint32_t dbr_umem_valid:1;
220 uint32_t wq_umem_valid:1;
221 uint32_t log_hairpin_num_packets:5;
222 uint32_t log_hairpin_data_sz:5;
223 uint32_t single_wqe_log_num_of_strides:4;
224 uint32_t two_byte_shift_en:1;
225 uint32_t single_stride_log_num_of_bytes:3;
226 uint32_t dbr_umem_id;
228 uint64_t wq_umem_offset;
231 /* Create RQ attributes structure, used by create RQ operation. */
232 struct mlx5_devx_create_rq_attr {
234 uint32_t delay_drop_en:1;
235 uint32_t scatter_fcs:1;
237 uint32_t mem_rq_type:4;
239 uint32_t flush_in_error_en:1;
241 uint32_t ts_format:2;
242 uint32_t user_index:24;
244 uint32_t counter_set_id:8;
246 struct mlx5_devx_wq_attr wq_attr;
249 /* Modify RQ attributes structure, used by modify RQ operation. */
250 struct mlx5_devx_modify_rq_attr {
252 uint32_t rq_state:4; /* Current RQ state. */
253 uint32_t state:4; /* Required RQ state. */
254 uint32_t scatter_fcs:1;
256 uint32_t counter_set_id:8;
257 uint32_t hairpin_peer_sq:24;
258 uint32_t hairpin_peer_vhca:16;
259 uint64_t modify_bitmask;
260 uint32_t lwm:16; /* Contained WQ lwm. */
263 struct mlx5_rx_hash_field_select {
264 uint32_t l3_prot_type:1;
265 uint32_t l4_prot_type:1;
266 uint32_t selected_fields:30;
269 /* TIR attributes structure, used by TIR operations. */
270 struct mlx5_devx_tir_attr {
271 uint32_t disp_type:4;
272 uint32_t lro_timeout_period_usecs:16;
273 uint32_t lro_enable_mask:4;
274 uint32_t lro_max_msg_sz:8;
275 uint32_t inline_rqn:24;
276 uint32_t rx_hash_symmetric:1;
277 uint32_t tunneled_offload_en:1;
278 uint32_t indirect_table:24;
279 uint32_t rx_hash_fn:4;
280 uint32_t self_lb_block:2;
281 uint32_t transport_domain:24;
282 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN];
283 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
284 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
287 /* TIR attributes structure, used by TIR modify. */
288 struct mlx5_devx_modify_tir_attr {
290 uint64_t modify_bitmask;
291 struct mlx5_devx_tir_attr tir;
294 /* RQT attributes structure, used by RQT operations. */
295 struct mlx5_devx_rqt_attr {
297 uint32_t rqt_max_size:16;
298 uint32_t rqt_actual_size:16;
302 /* TIS attributes structure. */
303 struct mlx5_devx_tis_attr {
304 uint32_t strict_lag_tx_port_affinity:1;
306 uint32_t lag_tx_port_affinity:4;
308 uint32_t transport_domain:24;
311 /* SQ attributes structure, used by SQ create operation. */
312 struct mlx5_devx_create_sq_attr {
314 uint32_t cd_master:1;
316 uint32_t flush_in_error_en:1;
317 uint32_t allow_multi_pkt_send_wqe:1;
318 uint32_t min_wqe_inline_mode:3;
321 uint32_t allow_swp:1;
324 uint32_t static_sq_wq:1;
325 uint32_t ts_format:2;
326 uint32_t user_index:24;
328 uint32_t packet_pacing_rate_limit_index:16;
329 uint32_t tis_lst_sz:16;
331 struct mlx5_devx_wq_attr wq_attr;
334 /* SQ attributes structure, used by SQ modify operation. */
335 struct mlx5_devx_modify_sq_attr {
338 uint32_t hairpin_peer_rq:24;
339 uint32_t hairpin_peer_vhca:16;
343 /* CQ attributes structure, used by CQ operations. */
344 struct mlx5_devx_cq_attr {
345 uint32_t q_umem_valid:1;
346 uint32_t db_umem_valid:1;
347 uint32_t use_first_only:1;
348 uint32_t overrun_ignore:1;
349 uint32_t cqe_comp_en:1;
350 uint32_t mini_cqe_res_format:2;
351 uint32_t mini_cqe_res_format_ext:2;
352 uint32_t log_cq_size:5;
353 uint32_t log_page_size:5;
354 uint32_t uar_page_id;
356 uint64_t q_umem_offset;
358 uint64_t db_umem_offset;
363 /* Virtq attributes structure, used by VIRTQ operations. */
364 struct mlx5_devx_virtq_attr {
365 uint16_t hw_available_index;
366 uint16_t hw_used_index;
369 uint32_t virtio_version_1_0:1;
374 uint32_t event_mode:3;
376 uint32_t hw_latency_mode:2;
377 uint32_t hw_max_latency_us:12;
378 uint32_t hw_max_pending_comp:16;
379 uint32_t dirty_bitmap_dump_enable:1;
380 uint32_t dirty_bitmap_mkey;
381 uint32_t dirty_bitmap_size;
384 uint32_t queue_index;
386 uint32_t counters_obj_id;
387 uint64_t dirty_bitmap_addr;
391 uint64_t available_addr;
401 struct mlx5_devx_qp_attr {
403 uint32_t uar_index:24;
405 uint32_t log_page_size:5;
406 uint32_t rq_size:17; /* Must be power of 2. */
407 uint32_t log_rq_stride:3;
408 uint32_t sq_size:17; /* Must be power of 2. */
409 uint32_t ts_format:2;
410 uint32_t dbr_umem_valid:1;
411 uint32_t dbr_umem_id;
412 uint64_t dbr_address;
414 uint64_t wq_umem_offset;
415 uint32_t user_index:24;
419 struct mlx5_devx_virtio_q_couners_attr {
420 uint64_t received_desc;
421 uint64_t completed_desc;
423 uint32_t bad_desc_errors;
424 uint32_t exceed_max_chain;
425 uint32_t invalid_buffer;
429 * graph flow match sample attributes structure,
430 * used by flex parser operations.
432 struct mlx5_devx_match_sample_attr {
433 uint32_t flow_match_sample_en:1;
434 uint32_t flow_match_sample_field_offset:16;
435 uint32_t flow_match_sample_offset_mode:4;
436 uint32_t flow_match_sample_field_offset_mask;
437 uint32_t flow_match_sample_field_offset_shift:4;
438 uint32_t flow_match_sample_field_base_offset:8;
439 uint32_t flow_match_sample_tunnel_mode:3;
440 uint32_t flow_match_sample_field_id;
443 /* graph node arc attributes structure, used by flex parser operations. */
444 struct mlx5_devx_graph_arc_attr {
445 uint32_t compare_condition_value:16;
446 uint32_t start_inner_tunnel:1;
447 uint32_t arc_parse_graph_node:8;
448 uint32_t parse_graph_node_handle;
451 /* Maximal number of samples per graph node. */
452 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8
454 /* Maximal number of input/output arcs per graph node. */
455 #define MLX5_GRAPH_NODE_ARC_NUM 8
457 /* parse graph node attributes structure, used by flex parser operations. */
458 struct mlx5_devx_graph_node_attr {
459 uint32_t modify_field_select;
460 uint32_t header_length_mode:4;
461 uint32_t header_length_base_value:16;
462 uint32_t header_length_field_shift:4;
463 uint32_t header_length_field_offset:16;
464 uint32_t header_length_field_mask;
465 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM];
466 uint32_t next_header_field_offset:16;
467 uint32_t next_header_field_size:5;
468 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM];
469 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM];
472 /* Encryption key size is up to 1024 bit, 128 bytes. */
473 #define MLX5_CRYPTO_KEY_MAX_SIZE 128
475 struct mlx5_devx_dek_attr {
477 uint32_t has_keytag:1;
478 uint32_t key_purpose:4;
481 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE];
484 struct mlx5_devx_import_kek_attr {
485 uint64_t modify_field_select;
488 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE];
491 #define MLX5_CRYPTO_CREDENTIAL_SIZE 48
493 struct mlx5_devx_credential_attr {
494 uint64_t modify_field_select;
496 uint32_t credential_role:8;
497 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE];
500 struct mlx5_devx_crypto_login_attr {
501 uint64_t modify_field_select;
502 uint32_t credential_pointer:24;
503 uint32_t session_import_kek_ptr:24;
504 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE];
507 /* mlx5_devx_cmds.c */
510 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx,
513 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
515 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
516 int clear, uint32_t n_counters,
517 uint64_t *pkts, uint64_t *bytes,
518 uint32_t mkey, void *addr,
522 int mlx5_devx_cmd_query_hca_attr(void *ctx,
523 struct mlx5_hca_attr *attr);
525 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx,
526 struct mlx5_devx_mkey_attr *attr);
528 int mlx5_devx_get_out_command_status(void *out);
530 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
533 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx,
534 struct mlx5_devx_create_rq_attr *rq_attr,
537 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
538 struct mlx5_devx_modify_rq_attr *rq_attr);
540 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx,
541 struct mlx5_devx_tir_attr *tir_attr);
543 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx,
544 struct mlx5_devx_rqt_attr *rqt_attr);
546 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx,
547 struct mlx5_devx_create_sq_attr *sq_attr);
549 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
550 struct mlx5_devx_modify_sq_attr *sq_attr);
552 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx,
553 struct mlx5_devx_tis_attr *tis_attr);
555 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx);
557 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain,
560 int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file);
562 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx,
563 struct mlx5_devx_cq_attr *attr);
565 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx,
566 struct mlx5_devx_virtq_attr *attr);
568 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
569 struct mlx5_devx_virtq_attr *attr);
571 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
572 struct mlx5_devx_virtq_attr *attr);
574 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx,
575 struct mlx5_devx_qp_attr *attr);
577 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,
578 uint32_t qp_st_mod_op, uint32_t remote_qp_id);
580 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
581 struct mlx5_devx_rqt_attr *rqt_attr);
583 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
584 struct mlx5_devx_modify_tir_attr *tir_attr);
586 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
587 uint32_t ids[], uint32_t num);
590 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx,
591 struct mlx5_devx_graph_node_attr *data);
594 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id,
595 uint32_t arg, uint32_t *data, uint32_t dw_cnt);
598 int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id,
599 uint32_t arg, uint32_t *data, uint32_t dw_cnt);
602 struct mlx5_devx_obj *
603 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
604 uint16_t class, uint8_t type, uint8_t len);
607 * Create virtio queue counters object DevX API.
613 * The DevX object created, NULL otherwise and rte_errno is set.
616 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx);
619 * Query virtio queue counters object using DevX API.
621 * @param[in] couners_obj
622 * Pointer to virtq object structure.
623 * @param [in/out] attr
624 * Pointer to virtio queue counters attributes structure.
627 * 0 on success, a negative errno value otherwise and rte_errno is set.
630 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
631 struct mlx5_devx_virtio_q_couners_attr *attr);
633 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx,
636 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx);
639 int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id);
642 struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx);
644 int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
645 uint32_t *out_of_buffers);
647 struct mlx5_devx_obj *mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx,
648 uint32_t pd, uint32_t log_obj_size);
651 * Create general object of type FLOW_METER_ASO using DevX API..
656 * PD value to associate the FLOW_METER_ASO object with.
657 * @param [in] log_obj_size
658 * log_obj_size define to allocate number of 2 * meters
659 * in one FLOW_METER_ASO object.
662 * The DevX object created, NULL otherwise and rte_errno is set.
665 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx,
666 uint32_t pd, uint32_t log_obj_size);
668 struct mlx5_devx_obj *
669 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr);
672 struct mlx5_devx_obj *
673 mlx5_devx_cmd_create_import_kek_obj(void *ctx,
674 struct mlx5_devx_import_kek_attr *attr);
677 struct mlx5_devx_obj *
678 mlx5_devx_cmd_create_credential_obj(void *ctx,
679 struct mlx5_devx_credential_attr *attr);
682 struct mlx5_devx_obj *
683 mlx5_devx_cmd_create_crypto_login_obj(void *ctx,
684 struct mlx5_devx_crypto_login_attr *attr);
688 mlx5_devx_cmd_query_lag(void *ctx,
689 struct mlx5_devx_lag_context *lag_ctx);
690 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */