1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_
6 #define RTE_PMD_MLX5_DEVX_CMDS_H_
12 /* devX creation object */
13 struct mlx5_devx_obj {
14 struct mlx5dv_devx_obj *obj; /* The DV object. */
15 int id; /* The object ID. */
18 /* UMR memory buffer used to define 1 entry in indirect mkey. */
25 /* This is limitation of libibverbs: in length variable type is u16. */
26 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \
27 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4))
29 struct mlx5_devx_mkey_attr {
34 uint32_t log_entity_size;
36 struct mlx5_klm *klm_array;
40 /* HCA qos attributes. */
41 struct mlx5_hca_qos_attr {
42 uint32_t sup:1; /* Whether QOS is supported. */
43 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */
44 uint32_t flow_meter_reg_share:1;
45 /* Whether reg_c share is supported. */
46 uint8_t log_max_flow_meter;
47 /* Power of the maximum supported meters. */
48 uint8_t flow_meter_reg_c_ids;
49 /* Bitmap of the reg_Cs available for flow meter to use. */
53 struct mlx5_hca_vdpa_attr {
54 uint8_t virtio_queue_type;
56 uint32_t desc_tunnel_offload_type:1;
57 uint32_t eth_frame_offload_type:1;
58 uint32_t virtio_version_1_0:1;
63 uint32_t event_mode:3;
64 uint32_t log_doorbell_stride:5;
65 uint32_t log_doorbell_bar_size:5;
66 uint32_t max_num_virtio_queues;
67 uint32_t umem_1_buffer_param_a;
68 uint32_t umem_1_buffer_param_b;
69 uint32_t umem_2_buffer_param_a;
70 uint32_t umem_2_buffer_param_b;
71 uint32_t umem_3_buffer_param_a;
72 uint32_t umem_3_buffer_param_b;
73 uint64_t doorbell_bar_offset;
76 /* HCA supports this number of time periods for LRO. */
77 #define MLX5_LRO_NUM_SUPP_PERIODS 4
80 struct mlx5_hca_attr {
81 uint32_t eswitch_manager:1;
82 uint32_t flow_counters_dump:1;
83 uint8_t flow_counter_bulk_alloc_bitmap;
84 uint32_t eth_net_offloads:1;
86 uint32_t wqe_vlan_insert:1;
87 uint32_t wqe_inline_mode:2;
88 uint32_t vport_inline_mode:3;
89 uint32_t tunnel_stateless_geneve_rx:1;
90 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
91 uint32_t tunnel_stateless_gtp:1;
93 uint32_t tunnel_lro_gre:1;
94 uint32_t tunnel_lro_vxlan:1;
95 uint32_t lro_max_msg_sz_mode:2;
96 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
97 uint32_t flex_parser_protocols;
99 uint32_t log_max_hairpin_queues:5;
100 uint32_t log_max_hairpin_wq_data_sz:5;
101 uint32_t log_max_hairpin_num_packets:5;
103 struct mlx5_hca_qos_attr qos;
104 struct mlx5_hca_vdpa_attr vdpa;
107 struct mlx5_devx_wq_attr {
109 uint32_t wq_signature:1;
110 uint32_t end_padding_mode:2;
112 uint32_t hds_skip_first_sge:1;
113 uint32_t log2_hds_buf_size:3;
114 uint32_t page_offset:5;
117 uint32_t uar_page:24;
121 uint32_t log_wq_stride:4;
122 uint32_t log_wq_pg_sz:5;
123 uint32_t log_wq_sz:5;
124 uint32_t dbr_umem_valid:1;
125 uint32_t wq_umem_valid:1;
126 uint32_t log_hairpin_num_packets:5;
127 uint32_t log_hairpin_data_sz:5;
128 uint32_t single_wqe_log_num_of_strides:4;
129 uint32_t two_byte_shift_en:1;
130 uint32_t single_stride_log_num_of_bytes:3;
131 uint32_t dbr_umem_id;
133 uint64_t wq_umem_offset;
136 /* Create RQ attributes structure, used by create RQ operation. */
137 struct mlx5_devx_create_rq_attr {
139 uint32_t delay_drop_en:1;
140 uint32_t scatter_fcs:1;
142 uint32_t mem_rq_type:4;
144 uint32_t flush_in_error_en:1;
146 uint32_t user_index:24;
148 uint32_t counter_set_id:8;
150 struct mlx5_devx_wq_attr wq_attr;
153 /* Modify RQ attributes structure, used by modify RQ operation. */
154 struct mlx5_devx_modify_rq_attr {
156 uint32_t rq_state:4; /* Current RQ state. */
157 uint32_t state:4; /* Required RQ state. */
158 uint32_t scatter_fcs:1;
160 uint32_t counter_set_id:8;
161 uint32_t hairpin_peer_sq:24;
162 uint32_t hairpin_peer_vhca:16;
163 uint64_t modify_bitmask;
164 uint32_t lwm:16; /* Contained WQ lwm. */
167 struct mlx5_rx_hash_field_select {
168 uint32_t l3_prot_type:1;
169 uint32_t l4_prot_type:1;
170 uint32_t selected_fields:30;
173 /* TIR attributes structure, used by TIR operations. */
174 struct mlx5_devx_tir_attr {
175 uint32_t disp_type:4;
176 uint32_t lro_timeout_period_usecs:16;
177 uint32_t lro_enable_mask:4;
178 uint32_t lro_max_msg_sz:8;
179 uint32_t inline_rqn:24;
180 uint32_t rx_hash_symmetric:1;
181 uint32_t tunneled_offload_en:1;
182 uint32_t indirect_table:24;
183 uint32_t rx_hash_fn:4;
184 uint32_t self_lb_block:2;
185 uint32_t transport_domain:24;
186 uint32_t rx_hash_toeplitz_key[10];
187 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
188 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
191 /* RQT attributes structure, used by RQT operations. */
192 struct mlx5_devx_rqt_attr {
193 uint32_t rqt_max_size:16;
194 uint32_t rqt_actual_size:16;
198 /* TIS attributes structure. */
199 struct mlx5_devx_tis_attr {
200 uint32_t strict_lag_tx_port_affinity:1;
202 uint32_t lag_tx_port_affinity:4;
204 uint32_t transport_domain:24;
207 /* SQ attributes structure, used by SQ create operation. */
208 struct mlx5_devx_create_sq_attr {
210 uint32_t cd_master:1;
212 uint32_t flush_in_error_en:1;
213 uint32_t allow_multi_pkt_send_wqe:1;
214 uint32_t min_wqe_inline_mode:3;
217 uint32_t allow_swp:1;
219 uint32_t user_index:24;
221 uint32_t packet_pacing_rate_limit_index:16;
222 uint32_t tis_lst_sz:16;
224 struct mlx5_devx_wq_attr wq_attr;
227 /* SQ attributes structure, used by SQ modify operation. */
228 struct mlx5_devx_modify_sq_attr {
231 uint32_t hairpin_peer_rq:24;
232 uint32_t hairpin_peer_vhca:16;
236 /* CQ attributes structure, used by CQ operations. */
237 struct mlx5_devx_cq_attr {
238 uint32_t q_umem_valid:1;
239 uint32_t db_umem_valid:1;
240 uint32_t use_first_only:1;
241 uint32_t overrun_ignore:1;
242 uint32_t log_cq_size:5;
243 uint32_t log_page_size:5;
244 uint32_t uar_page_id;
246 uint64_t q_umem_offset;
248 uint64_t db_umem_offset;
253 /* mlx5_devx_cmds.c */
255 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
257 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
258 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
259 int clear, uint32_t n_counters,
260 uint64_t *pkts, uint64_t *bytes,
261 uint32_t mkey, void *addr,
262 struct mlx5dv_devx_cmd_comp *cmd_comp,
264 int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
265 struct mlx5_hca_attr *attr);
266 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
267 struct mlx5_devx_mkey_attr *attr);
268 int mlx5_devx_get_out_command_status(void *out);
269 int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
271 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
272 struct mlx5_devx_create_rq_attr *rq_attr,
274 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
275 struct mlx5_devx_modify_rq_attr *rq_attr);
276 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
277 struct mlx5_devx_tir_attr *tir_attr);
278 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
279 struct mlx5_devx_rqt_attr *rqt_attr);
280 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(struct ibv_context *ctx,
281 struct mlx5_devx_create_sq_attr *sq_attr);
282 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
283 struct mlx5_devx_modify_sq_attr *sq_attr);
284 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(struct ibv_context *ctx,
285 struct mlx5_devx_tis_attr *tis_attr);
286 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(struct ibv_context *ctx);
287 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain,
289 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(struct ibv_context *ctx,
290 struct mlx5_devx_cq_attr *attr);
291 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */