1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_
6 #define RTE_PMD_MLX5_DEVX_CMDS_H_
12 /* devX creation object */
13 struct mlx5_devx_obj {
14 struct mlx5dv_devx_obj *obj; /* The DV object. */
15 int id; /* The object ID. */
18 /* UMR memory buffer used to define 1 entry in indirect mkey. */
25 /* This is limitation of libibverbs: in length variable type is u16. */
26 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \
27 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4))
29 struct mlx5_devx_mkey_attr {
34 uint32_t log_entity_size;
36 struct mlx5_klm *klm_array;
40 /* HCA qos attributes. */
41 struct mlx5_hca_qos_attr {
42 uint32_t sup:1; /* Whether QOS is supported. */
43 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */
44 uint32_t flow_meter_reg_share:1;
45 /* Whether reg_c share is supported. */
46 uint8_t log_max_flow_meter;
47 /* Power of the maximum supported meters. */
48 uint8_t flow_meter_reg_c_ids;
49 /* Bitmap of the reg_Cs available for flow meter to use. */
53 struct mlx5_hca_vdpa_attr {
54 uint8_t virtio_queue_type;
56 uint32_t desc_tunnel_offload_type:1;
57 uint32_t eth_frame_offload_type:1;
58 uint32_t virtio_version_1_0:1;
63 uint32_t event_mode:3;
64 uint32_t log_doorbell_stride:5;
65 uint32_t log_doorbell_bar_size:5;
66 uint32_t max_num_virtio_queues;
71 uint64_t doorbell_bar_offset;
74 /* HCA supports this number of time periods for LRO. */
75 #define MLX5_LRO_NUM_SUPP_PERIODS 4
78 struct mlx5_hca_attr {
79 uint32_t eswitch_manager:1;
80 uint32_t flow_counters_dump:1;
81 uint32_t log_max_rqt_size:5;
82 uint8_t flow_counter_bulk_alloc_bitmap;
83 uint32_t eth_net_offloads:1;
85 uint32_t wqe_vlan_insert:1;
86 uint32_t wqe_inline_mode:2;
87 uint32_t vport_inline_mode:3;
88 uint32_t tunnel_stateless_geneve_rx:1;
89 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
90 uint32_t tunnel_stateless_gtp:1;
92 uint32_t tunnel_lro_gre:1;
93 uint32_t tunnel_lro_vxlan:1;
94 uint32_t lro_max_msg_sz_mode:2;
95 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
96 uint32_t flex_parser_protocols;
98 uint32_t log_max_hairpin_queues:5;
99 uint32_t log_max_hairpin_wq_data_sz:5;
100 uint32_t log_max_hairpin_num_packets:5;
102 struct mlx5_hca_qos_attr qos;
103 struct mlx5_hca_vdpa_attr vdpa;
106 struct mlx5_devx_wq_attr {
108 uint32_t wq_signature:1;
109 uint32_t end_padding_mode:2;
111 uint32_t hds_skip_first_sge:1;
112 uint32_t log2_hds_buf_size:3;
113 uint32_t page_offset:5;
116 uint32_t uar_page:24;
120 uint32_t log_wq_stride:4;
121 uint32_t log_wq_pg_sz:5;
122 uint32_t log_wq_sz:5;
123 uint32_t dbr_umem_valid:1;
124 uint32_t wq_umem_valid:1;
125 uint32_t log_hairpin_num_packets:5;
126 uint32_t log_hairpin_data_sz:5;
127 uint32_t single_wqe_log_num_of_strides:4;
128 uint32_t two_byte_shift_en:1;
129 uint32_t single_stride_log_num_of_bytes:3;
130 uint32_t dbr_umem_id;
132 uint64_t wq_umem_offset;
135 /* Create RQ attributes structure, used by create RQ operation. */
136 struct mlx5_devx_create_rq_attr {
138 uint32_t delay_drop_en:1;
139 uint32_t scatter_fcs:1;
141 uint32_t mem_rq_type:4;
143 uint32_t flush_in_error_en:1;
145 uint32_t user_index:24;
147 uint32_t counter_set_id:8;
149 struct mlx5_devx_wq_attr wq_attr;
152 /* Modify RQ attributes structure, used by modify RQ operation. */
153 struct mlx5_devx_modify_rq_attr {
155 uint32_t rq_state:4; /* Current RQ state. */
156 uint32_t state:4; /* Required RQ state. */
157 uint32_t scatter_fcs:1;
159 uint32_t counter_set_id:8;
160 uint32_t hairpin_peer_sq:24;
161 uint32_t hairpin_peer_vhca:16;
162 uint64_t modify_bitmask;
163 uint32_t lwm:16; /* Contained WQ lwm. */
166 struct mlx5_rx_hash_field_select {
167 uint32_t l3_prot_type:1;
168 uint32_t l4_prot_type:1;
169 uint32_t selected_fields:30;
172 /* TIR attributes structure, used by TIR operations. */
173 struct mlx5_devx_tir_attr {
174 uint32_t disp_type:4;
175 uint32_t lro_timeout_period_usecs:16;
176 uint32_t lro_enable_mask:4;
177 uint32_t lro_max_msg_sz:8;
178 uint32_t inline_rqn:24;
179 uint32_t rx_hash_symmetric:1;
180 uint32_t tunneled_offload_en:1;
181 uint32_t indirect_table:24;
182 uint32_t rx_hash_fn:4;
183 uint32_t self_lb_block:2;
184 uint32_t transport_domain:24;
185 uint32_t rx_hash_toeplitz_key[10];
186 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
187 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
190 /* RQT attributes structure, used by RQT operations. */
191 struct mlx5_devx_rqt_attr {
193 uint32_t rqt_max_size:16;
194 uint32_t rqt_actual_size:16;
198 /* TIS attributes structure. */
199 struct mlx5_devx_tis_attr {
200 uint32_t strict_lag_tx_port_affinity:1;
202 uint32_t lag_tx_port_affinity:4;
204 uint32_t transport_domain:24;
207 /* SQ attributes structure, used by SQ create operation. */
208 struct mlx5_devx_create_sq_attr {
210 uint32_t cd_master:1;
212 uint32_t flush_in_error_en:1;
213 uint32_t allow_multi_pkt_send_wqe:1;
214 uint32_t min_wqe_inline_mode:3;
217 uint32_t allow_swp:1;
219 uint32_t user_index:24;
221 uint32_t packet_pacing_rate_limit_index:16;
222 uint32_t tis_lst_sz:16;
224 struct mlx5_devx_wq_attr wq_attr;
227 /* SQ attributes structure, used by SQ modify operation. */
228 struct mlx5_devx_modify_sq_attr {
231 uint32_t hairpin_peer_rq:24;
232 uint32_t hairpin_peer_vhca:16;
236 /* CQ attributes structure, used by CQ operations. */
237 struct mlx5_devx_cq_attr {
238 uint32_t q_umem_valid:1;
239 uint32_t db_umem_valid:1;
240 uint32_t use_first_only:1;
241 uint32_t overrun_ignore:1;
242 uint32_t log_cq_size:5;
243 uint32_t log_page_size:5;
244 uint32_t uar_page_id;
246 uint64_t q_umem_offset;
248 uint64_t db_umem_offset;
253 /* Virtq attributes structure, used by VIRTQ operations. */
254 struct mlx5_devx_virtq_attr {
255 uint16_t hw_available_index;
256 uint16_t hw_used_index;
258 uint32_t virtio_version_1_0:1;
263 uint32_t event_mode:3;
265 uint32_t dirty_bitmap_dump_enable:1;
266 uint32_t dirty_bitmap_mkey;
267 uint32_t dirty_bitmap_size;
270 uint32_t queue_index;
272 uint64_t dirty_bitmap_addr;
276 uint64_t available_addr;
285 struct mlx5_devx_qp_attr {
287 uint32_t uar_index:24;
289 uint32_t log_page_size:5;
290 uint32_t rq_size:17; /* Must be power of 2. */
291 uint32_t log_rq_stride:3;
292 uint32_t sq_size:17; /* Must be power of 2. */
293 uint32_t dbr_umem_valid:1;
294 uint32_t dbr_umem_id;
295 uint64_t dbr_address;
297 uint64_t wq_umem_offset;
300 /* mlx5_devx_cmds.c */
302 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx,
304 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
305 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
306 int clear, uint32_t n_counters,
307 uint64_t *pkts, uint64_t *bytes,
308 uint32_t mkey, void *addr,
309 struct mlx5dv_devx_cmd_comp *cmd_comp,
311 int mlx5_devx_cmd_query_hca_attr(struct ibv_context *ctx,
312 struct mlx5_hca_attr *attr);
313 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
314 struct mlx5_devx_mkey_attr *attr);
315 int mlx5_devx_get_out_command_status(void *out);
316 int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
318 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
319 struct mlx5_devx_create_rq_attr *rq_attr,
321 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
322 struct mlx5_devx_modify_rq_attr *rq_attr);
323 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(struct ibv_context *ctx,
324 struct mlx5_devx_tir_attr *tir_attr);
325 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(struct ibv_context *ctx,
326 struct mlx5_devx_rqt_attr *rqt_attr);
327 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(struct ibv_context *ctx,
328 struct mlx5_devx_create_sq_attr *sq_attr);
329 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
330 struct mlx5_devx_modify_sq_attr *sq_attr);
331 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(struct ibv_context *ctx,
332 struct mlx5_devx_tis_attr *tis_attr);
333 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(struct ibv_context *ctx);
334 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain,
336 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(struct ibv_context *ctx,
337 struct mlx5_devx_cq_attr *attr);
338 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(struct ibv_context *ctx,
339 struct mlx5_devx_virtq_attr *attr);
340 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
341 struct mlx5_devx_virtq_attr *attr);
342 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
343 struct mlx5_devx_virtq_attr *attr);
344 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(struct ibv_context *ctx,
345 struct mlx5_devx_qp_attr *attr);
346 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,
347 uint32_t qp_st_mod_op, uint32_t remote_qp_id);
348 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
349 struct mlx5_devx_rqt_attr *rqt_attr);
351 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */