1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_
6 #define RTE_PMD_MLX5_DEVX_CMDS_H_
12 /* This is limitation of libibverbs: in length variable type is u16. */
13 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \
14 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4))
16 struct mlx5_devx_mkey_attr {
21 uint32_t log_entity_size;
23 uint32_t relaxed_ordering:1;
24 struct mlx5_klm *klm_array;
28 /* HCA qos attributes. */
29 struct mlx5_hca_qos_attr {
30 uint32_t sup:1; /* Whether QOS is supported. */
31 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */
32 uint32_t packet_pacing:1; /* Packet pacing is supported. */
33 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */
34 uint32_t flow_meter_reg_share:1;
35 /* Whether reg_c share is supported. */
36 uint8_t log_max_flow_meter;
37 /* Power of the maximum supported meters. */
38 uint8_t flow_meter_reg_c_ids;
39 /* Bitmap of the reg_Cs available for flow meter to use. */
43 struct mlx5_hca_vdpa_attr {
44 uint8_t virtio_queue_type;
46 uint32_t desc_tunnel_offload_type:1;
47 uint32_t eth_frame_offload_type:1;
48 uint32_t virtio_version_1_0:1;
53 uint32_t event_mode:3;
54 uint32_t log_doorbell_stride:5;
55 uint32_t log_doorbell_bar_size:5;
56 uint32_t queue_counters_valid:1;
57 uint32_t max_num_virtio_queues;
62 uint64_t doorbell_bar_offset;
65 /* HCA supports this number of time periods for LRO. */
66 #define MLX5_LRO_NUM_SUPP_PERIODS 4
69 struct mlx5_hca_attr {
70 uint32_t eswitch_manager:1;
71 uint32_t flow_counters_dump:1;
72 uint32_t log_max_rqt_size:5;
73 uint8_t flow_counter_bulk_alloc_bitmap;
74 uint32_t eth_net_offloads:1;
76 uint32_t wqe_vlan_insert:1;
77 uint32_t wqe_inline_mode:2;
78 uint32_t vport_inline_mode:3;
79 uint32_t tunnel_stateless_geneve_rx:1;
80 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
81 uint32_t tunnel_stateless_gtp:1;
83 uint32_t tunnel_lro_gre:1;
84 uint32_t tunnel_lro_vxlan:1;
85 uint32_t lro_max_msg_sz_mode:2;
86 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
87 uint32_t flex_parser_protocols;
89 uint32_t log_max_hairpin_queues:5;
90 uint32_t log_max_hairpin_wq_data_sz:5;
91 uint32_t log_max_hairpin_num_packets:5;
93 uint32_t relaxed_ordering_write:1;
94 uint32_t relaxed_ordering_read:1;
95 uint32_t wqe_index_ignore:1;
96 uint32_t cross_channel:1;
97 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */
98 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */
99 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */
101 uint32_t regexp_num_of_engines;
102 struct mlx5_hca_qos_attr qos;
103 struct mlx5_hca_vdpa_attr vdpa;
106 struct mlx5_devx_wq_attr {
108 uint32_t wq_signature:1;
109 uint32_t end_padding_mode:2;
111 uint32_t hds_skip_first_sge:1;
112 uint32_t log2_hds_buf_size:3;
113 uint32_t page_offset:5;
116 uint32_t uar_page:24;
120 uint32_t log_wq_stride:4;
121 uint32_t log_wq_pg_sz:5;
122 uint32_t log_wq_sz:5;
123 uint32_t dbr_umem_valid:1;
124 uint32_t wq_umem_valid:1;
125 uint32_t log_hairpin_num_packets:5;
126 uint32_t log_hairpin_data_sz:5;
127 uint32_t single_wqe_log_num_of_strides:4;
128 uint32_t two_byte_shift_en:1;
129 uint32_t single_stride_log_num_of_bytes:3;
130 uint32_t dbr_umem_id;
132 uint64_t wq_umem_offset;
135 /* Create RQ attributes structure, used by create RQ operation. */
136 struct mlx5_devx_create_rq_attr {
138 uint32_t delay_drop_en:1;
139 uint32_t scatter_fcs:1;
141 uint32_t mem_rq_type:4;
143 uint32_t flush_in_error_en:1;
145 uint32_t user_index:24;
147 uint32_t counter_set_id:8;
149 struct mlx5_devx_wq_attr wq_attr;
152 /* Modify RQ attributes structure, used by modify RQ operation. */
153 struct mlx5_devx_modify_rq_attr {
155 uint32_t rq_state:4; /* Current RQ state. */
156 uint32_t state:4; /* Required RQ state. */
157 uint32_t scatter_fcs:1;
159 uint32_t counter_set_id:8;
160 uint32_t hairpin_peer_sq:24;
161 uint32_t hairpin_peer_vhca:16;
162 uint64_t modify_bitmask;
163 uint32_t lwm:16; /* Contained WQ lwm. */
166 struct mlx5_rx_hash_field_select {
167 uint32_t l3_prot_type:1;
168 uint32_t l4_prot_type:1;
169 uint32_t selected_fields:30;
172 /* TIR attributes structure, used by TIR operations. */
173 struct mlx5_devx_tir_attr {
174 uint32_t disp_type:4;
175 uint32_t lro_timeout_period_usecs:16;
176 uint32_t lro_enable_mask:4;
177 uint32_t lro_max_msg_sz:8;
178 uint32_t inline_rqn:24;
179 uint32_t rx_hash_symmetric:1;
180 uint32_t tunneled_offload_en:1;
181 uint32_t indirect_table:24;
182 uint32_t rx_hash_fn:4;
183 uint32_t self_lb_block:2;
184 uint32_t transport_domain:24;
185 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN];
186 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
187 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
190 /* RQT attributes structure, used by RQT operations. */
191 struct mlx5_devx_rqt_attr {
193 uint32_t rqt_max_size:16;
194 uint32_t rqt_actual_size:16;
198 /* TIS attributes structure. */
199 struct mlx5_devx_tis_attr {
200 uint32_t strict_lag_tx_port_affinity:1;
202 uint32_t lag_tx_port_affinity:4;
204 uint32_t transport_domain:24;
207 /* SQ attributes structure, used by SQ create operation. */
208 struct mlx5_devx_create_sq_attr {
210 uint32_t cd_master:1;
212 uint32_t flush_in_error_en:1;
213 uint32_t allow_multi_pkt_send_wqe:1;
214 uint32_t min_wqe_inline_mode:3;
217 uint32_t allow_swp:1;
220 uint32_t static_sq_wq:1;
221 uint32_t user_index:24;
223 uint32_t packet_pacing_rate_limit_index:16;
224 uint32_t tis_lst_sz:16;
226 struct mlx5_devx_wq_attr wq_attr;
229 /* SQ attributes structure, used by SQ modify operation. */
230 struct mlx5_devx_modify_sq_attr {
233 uint32_t hairpin_peer_rq:24;
234 uint32_t hairpin_peer_vhca:16;
238 /* CQ attributes structure, used by CQ operations. */
239 struct mlx5_devx_cq_attr {
240 uint32_t q_umem_valid:1;
241 uint32_t db_umem_valid:1;
242 uint32_t use_first_only:1;
243 uint32_t overrun_ignore:1;
245 uint32_t log_cq_size:5;
246 uint32_t log_page_size:5;
247 uint32_t uar_page_id;
249 uint64_t q_umem_offset;
251 uint64_t db_umem_offset;
256 /* Virtq attributes structure, used by VIRTQ operations. */
257 struct mlx5_devx_virtq_attr {
258 uint16_t hw_available_index;
259 uint16_t hw_used_index;
262 uint32_t virtio_version_1_0:1;
267 uint32_t event_mode:3;
269 uint32_t dirty_bitmap_dump_enable:1;
270 uint32_t dirty_bitmap_mkey;
271 uint32_t dirty_bitmap_size;
274 uint32_t queue_index;
276 uint32_t counters_obj_id;
277 uint64_t dirty_bitmap_addr;
281 uint64_t available_addr;
290 struct mlx5_devx_qp_attr {
292 uint32_t uar_index:24;
294 uint32_t log_page_size:5;
295 uint32_t rq_size:17; /* Must be power of 2. */
296 uint32_t log_rq_stride:3;
297 uint32_t sq_size:17; /* Must be power of 2. */
298 uint32_t dbr_umem_valid:1;
299 uint32_t dbr_umem_id;
300 uint64_t dbr_address;
302 uint64_t wq_umem_offset;
305 struct mlx5_devx_virtio_q_couners_attr {
306 uint64_t received_desc;
307 uint64_t completed_desc;
309 uint32_t bad_desc_errors;
310 uint32_t exceed_max_chain;
311 uint32_t invalid_buffer;
314 /* mlx5_devx_cmds.c */
317 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx,
320 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
322 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
323 int clear, uint32_t n_counters,
324 uint64_t *pkts, uint64_t *bytes,
325 uint32_t mkey, void *addr,
329 int mlx5_devx_cmd_query_hca_attr(void *ctx,
330 struct mlx5_hca_attr *attr);
332 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx,
333 struct mlx5_devx_mkey_attr *attr);
335 int mlx5_devx_get_out_command_status(void *out);
337 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
340 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx,
341 struct mlx5_devx_create_rq_attr *rq_attr,
344 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
345 struct mlx5_devx_modify_rq_attr *rq_attr);
347 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx,
348 struct mlx5_devx_tir_attr *tir_attr);
350 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx,
351 struct mlx5_devx_rqt_attr *rqt_attr);
353 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx,
354 struct mlx5_devx_create_sq_attr *sq_attr);
356 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
357 struct mlx5_devx_modify_sq_attr *sq_attr);
359 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx,
360 struct mlx5_devx_tis_attr *tis_attr);
362 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx);
364 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain,
367 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx,
368 struct mlx5_devx_cq_attr *attr);
370 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx,
371 struct mlx5_devx_virtq_attr *attr);
373 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
374 struct mlx5_devx_virtq_attr *attr);
376 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
377 struct mlx5_devx_virtq_attr *attr);
379 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx,
380 struct mlx5_devx_qp_attr *attr);
382 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,
383 uint32_t qp_st_mod_op, uint32_t remote_qp_id);
385 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
386 struct mlx5_devx_rqt_attr *rqt_attr);
389 * Create virtio queue counters object DevX API.
395 * The DevX object created, NULL otherwise and rte_errno is set.
398 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx);
401 * Query virtio queue counters object using DevX API.
403 * @param[in] couners_obj
404 * Pointer to virtq object structure.
405 * @param [in/out] attr
406 * Pointer to virtio queue counters attributes structure.
409 * 0 on success, a negative errno value otherwise and rte_errno is set.
412 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
413 struct mlx5_devx_virtio_q_couners_attr *attr);
415 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */