1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_
6 #define RTE_PMD_MLX5_DEVX_CMDS_H_
12 /* This is limitation of libibverbs: in length variable type is u16. */
13 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \
14 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4))
16 struct mlx5_devx_mkey_attr {
21 uint32_t log_entity_size;
23 uint32_t relaxed_ordering:1;
24 struct mlx5_klm *klm_array;
28 /* HCA qos attributes. */
29 struct mlx5_hca_qos_attr {
30 uint32_t sup:1; /* Whether QOS is supported. */
31 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */
32 uint32_t packet_pacing:1; /* Packet pacing is supported. */
33 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */
34 uint32_t flow_meter_reg_share:1;
35 /* Whether reg_c share is supported. */
36 uint8_t log_max_flow_meter;
37 /* Power of the maximum supported meters. */
38 uint8_t flow_meter_reg_c_ids;
39 /* Bitmap of the reg_Cs available for flow meter to use. */
43 struct mlx5_hca_vdpa_attr {
44 uint8_t virtio_queue_type;
46 uint32_t desc_tunnel_offload_type:1;
47 uint32_t eth_frame_offload_type:1;
48 uint32_t virtio_version_1_0:1;
53 uint32_t event_mode:3;
54 uint32_t log_doorbell_stride:5;
55 uint32_t log_doorbell_bar_size:5;
56 uint32_t queue_counters_valid:1;
57 uint32_t max_num_virtio_queues;
62 uint64_t doorbell_bar_offset;
65 /* HCA supports this number of time periods for LRO. */
66 #define MLX5_LRO_NUM_SUPP_PERIODS 4
69 struct mlx5_hca_attr {
70 uint32_t eswitch_manager:1;
71 uint32_t flow_counters_dump:1;
72 uint32_t log_max_rqt_size:5;
73 uint32_t parse_graph_flex_node:1;
74 uint8_t flow_counter_bulk_alloc_bitmap;
75 uint32_t eth_net_offloads:1;
77 uint32_t wqe_vlan_insert:1;
78 uint32_t wqe_inline_mode:2;
79 uint32_t vport_inline_mode:3;
80 uint32_t tunnel_stateless_geneve_rx:1;
81 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
82 uint32_t tunnel_stateless_gtp:1;
84 uint32_t tunnel_lro_gre:1;
85 uint32_t tunnel_lro_vxlan:1;
86 uint32_t lro_max_msg_sz_mode:2;
87 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
88 uint16_t lro_min_mss_size;
89 uint32_t flex_parser_protocols;
91 uint32_t log_max_hairpin_queues:5;
92 uint32_t log_max_hairpin_wq_data_sz:5;
93 uint32_t log_max_hairpin_num_packets:5;
95 uint32_t relaxed_ordering_write:1;
96 uint32_t relaxed_ordering_read:1;
97 uint32_t access_register_user:1;
98 uint32_t wqe_index_ignore:1;
99 uint32_t cross_channel:1;
100 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */
101 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */
102 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */
103 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */
104 uint32_t scatter_fcs_w_decap_disable:1;
106 uint32_t regexp_num_of_engines;
107 uint32_t log_max_ft_sampler_num:8;
108 struct mlx5_hca_qos_attr qos;
109 struct mlx5_hca_vdpa_attr vdpa;
112 struct mlx5_devx_wq_attr {
114 uint32_t wq_signature:1;
115 uint32_t end_padding_mode:2;
117 uint32_t hds_skip_first_sge:1;
118 uint32_t log2_hds_buf_size:3;
119 uint32_t page_offset:5;
122 uint32_t uar_page:24;
126 uint32_t log_wq_stride:4;
127 uint32_t log_wq_pg_sz:5;
128 uint32_t log_wq_sz:5;
129 uint32_t dbr_umem_valid:1;
130 uint32_t wq_umem_valid:1;
131 uint32_t log_hairpin_num_packets:5;
132 uint32_t log_hairpin_data_sz:5;
133 uint32_t single_wqe_log_num_of_strides:4;
134 uint32_t two_byte_shift_en:1;
135 uint32_t single_stride_log_num_of_bytes:3;
136 uint32_t dbr_umem_id;
138 uint64_t wq_umem_offset;
141 /* Create RQ attributes structure, used by create RQ operation. */
142 struct mlx5_devx_create_rq_attr {
144 uint32_t delay_drop_en:1;
145 uint32_t scatter_fcs:1;
147 uint32_t mem_rq_type:4;
149 uint32_t flush_in_error_en:1;
151 uint32_t user_index:24;
153 uint32_t counter_set_id:8;
155 struct mlx5_devx_wq_attr wq_attr;
158 /* Modify RQ attributes structure, used by modify RQ operation. */
159 struct mlx5_devx_modify_rq_attr {
161 uint32_t rq_state:4; /* Current RQ state. */
162 uint32_t state:4; /* Required RQ state. */
163 uint32_t scatter_fcs:1;
165 uint32_t counter_set_id:8;
166 uint32_t hairpin_peer_sq:24;
167 uint32_t hairpin_peer_vhca:16;
168 uint64_t modify_bitmask;
169 uint32_t lwm:16; /* Contained WQ lwm. */
172 struct mlx5_rx_hash_field_select {
173 uint32_t l3_prot_type:1;
174 uint32_t l4_prot_type:1;
175 uint32_t selected_fields:30;
178 /* TIR attributes structure, used by TIR operations. */
179 struct mlx5_devx_tir_attr {
180 uint32_t disp_type:4;
181 uint32_t lro_timeout_period_usecs:16;
182 uint32_t lro_enable_mask:4;
183 uint32_t lro_max_msg_sz:8;
184 uint32_t inline_rqn:24;
185 uint32_t rx_hash_symmetric:1;
186 uint32_t tunneled_offload_en:1;
187 uint32_t indirect_table:24;
188 uint32_t rx_hash_fn:4;
189 uint32_t self_lb_block:2;
190 uint32_t transport_domain:24;
191 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN];
192 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
193 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
196 /* TIR attributes structure, used by TIR modify. */
197 struct mlx5_devx_modify_tir_attr {
199 uint64_t modify_bitmask;
200 struct mlx5_devx_tir_attr tir;
203 /* RQT attributes structure, used by RQT operations. */
204 struct mlx5_devx_rqt_attr {
206 uint32_t rqt_max_size:16;
207 uint32_t rqt_actual_size:16;
211 /* TIS attributes structure. */
212 struct mlx5_devx_tis_attr {
213 uint32_t strict_lag_tx_port_affinity:1;
215 uint32_t lag_tx_port_affinity:4;
217 uint32_t transport_domain:24;
220 /* SQ attributes structure, used by SQ create operation. */
221 struct mlx5_devx_create_sq_attr {
223 uint32_t cd_master:1;
225 uint32_t flush_in_error_en:1;
226 uint32_t allow_multi_pkt_send_wqe:1;
227 uint32_t min_wqe_inline_mode:3;
230 uint32_t allow_swp:1;
233 uint32_t static_sq_wq:1;
234 uint32_t user_index:24;
236 uint32_t packet_pacing_rate_limit_index:16;
237 uint32_t tis_lst_sz:16;
239 struct mlx5_devx_wq_attr wq_attr;
242 /* SQ attributes structure, used by SQ modify operation. */
243 struct mlx5_devx_modify_sq_attr {
246 uint32_t hairpin_peer_rq:24;
247 uint32_t hairpin_peer_vhca:16;
251 /* CQ attributes structure, used by CQ operations. */
252 struct mlx5_devx_cq_attr {
253 uint32_t q_umem_valid:1;
254 uint32_t db_umem_valid:1;
255 uint32_t use_first_only:1;
256 uint32_t overrun_ignore:1;
257 uint32_t cqe_comp_en:1;
258 uint32_t mini_cqe_res_format:2;
259 uint32_t mini_cqe_res_format_ext:2;
261 uint32_t log_cq_size:5;
262 uint32_t log_page_size:5;
263 uint32_t uar_page_id;
265 uint64_t q_umem_offset;
267 uint64_t db_umem_offset;
272 /* Virtq attributes structure, used by VIRTQ operations. */
273 struct mlx5_devx_virtq_attr {
274 uint16_t hw_available_index;
275 uint16_t hw_used_index;
278 uint32_t virtio_version_1_0:1;
283 uint32_t event_mode:3;
285 uint32_t dirty_bitmap_dump_enable:1;
286 uint32_t dirty_bitmap_mkey;
287 uint32_t dirty_bitmap_size;
290 uint32_t queue_index;
292 uint32_t counters_obj_id;
293 uint64_t dirty_bitmap_addr;
297 uint64_t available_addr;
307 struct mlx5_devx_qp_attr {
309 uint32_t uar_index:24;
311 uint32_t log_page_size:5;
312 uint32_t rq_size:17; /* Must be power of 2. */
313 uint32_t log_rq_stride:3;
314 uint32_t sq_size:17; /* Must be power of 2. */
315 uint32_t dbr_umem_valid:1;
316 uint32_t dbr_umem_id;
317 uint64_t dbr_address;
319 uint64_t wq_umem_offset;
322 struct mlx5_devx_virtio_q_couners_attr {
323 uint64_t received_desc;
324 uint64_t completed_desc;
326 uint32_t bad_desc_errors;
327 uint32_t exceed_max_chain;
328 uint32_t invalid_buffer;
332 * graph flow match sample attributes structure,
333 * used by flex parser operations.
335 struct mlx5_devx_match_sample_attr {
336 uint32_t flow_match_sample_en:1;
337 uint32_t flow_match_sample_field_offset:16;
338 uint32_t flow_match_sample_offset_mode:4;
339 uint32_t flow_match_sample_field_offset_mask;
340 uint32_t flow_match_sample_field_offset_shift:4;
341 uint32_t flow_match_sample_field_base_offset:8;
342 uint32_t flow_match_sample_tunnel_mode:3;
343 uint32_t flow_match_sample_field_id;
346 /* graph node arc attributes structure, used by flex parser operations. */
347 struct mlx5_devx_graph_arc_attr {
348 uint32_t compare_condition_value:16;
349 uint32_t start_inner_tunnel:1;
350 uint32_t arc_parse_graph_node:8;
351 uint32_t parse_graph_node_handle;
354 /* Maximal number of samples per graph node. */
355 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8
357 /* Maximal number of input/output arcs per graph node. */
358 #define MLX5_GRAPH_NODE_ARC_NUM 8
360 /* parse graph node attributes structure, used by flex parser operations. */
361 struct mlx5_devx_graph_node_attr {
362 uint32_t modify_field_select;
363 uint32_t header_length_mode:4;
364 uint32_t header_length_base_value:16;
365 uint32_t header_length_field_shift:4;
366 uint32_t header_length_field_offset:16;
367 uint32_t header_length_field_mask;
368 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM];
369 uint32_t next_header_field_offset:16;
370 uint32_t next_header_field_size:5;
371 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM];
372 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM];
375 /* mlx5_devx_cmds.c */
378 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx,
381 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
383 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
384 int clear, uint32_t n_counters,
385 uint64_t *pkts, uint64_t *bytes,
386 uint32_t mkey, void *addr,
390 int mlx5_devx_cmd_query_hca_attr(void *ctx,
391 struct mlx5_hca_attr *attr);
393 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx,
394 struct mlx5_devx_mkey_attr *attr);
396 int mlx5_devx_get_out_command_status(void *out);
398 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
401 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx,
402 struct mlx5_devx_create_rq_attr *rq_attr,
405 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
406 struct mlx5_devx_modify_rq_attr *rq_attr);
408 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx,
409 struct mlx5_devx_tir_attr *tir_attr);
411 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx,
412 struct mlx5_devx_rqt_attr *rqt_attr);
414 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx,
415 struct mlx5_devx_create_sq_attr *sq_attr);
417 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
418 struct mlx5_devx_modify_sq_attr *sq_attr);
420 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx,
421 struct mlx5_devx_tis_attr *tis_attr);
423 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx);
425 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain,
428 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx,
429 struct mlx5_devx_cq_attr *attr);
431 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx,
432 struct mlx5_devx_virtq_attr *attr);
434 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
435 struct mlx5_devx_virtq_attr *attr);
437 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
438 struct mlx5_devx_virtq_attr *attr);
440 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx,
441 struct mlx5_devx_qp_attr *attr);
443 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,
444 uint32_t qp_st_mod_op, uint32_t remote_qp_id);
446 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
447 struct mlx5_devx_rqt_attr *rqt_attr);
449 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
450 struct mlx5_devx_modify_tir_attr *tir_attr);
452 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
453 uint32_t ids[], uint32_t num);
456 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx,
457 struct mlx5_devx_graph_node_attr *data);
460 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id,
461 uint32_t arg, uint32_t *data, uint32_t dw_cnt);
463 * Create virtio queue counters object DevX API.
469 * The DevX object created, NULL otherwise and rte_errno is set.
472 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx);
475 * Query virtio queue counters object using DevX API.
477 * @param[in] couners_obj
478 * Pointer to virtq object structure.
479 * @param [in/out] attr
480 * Pointer to virtio queue counters attributes structure.
483 * 0 on success, a negative errno value otherwise and rte_errno is set.
486 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
487 struct mlx5_devx_virtio_q_couners_attr *attr);
489 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */