1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_
6 #define RTE_PMD_MLX5_DEVX_CMDS_H_
12 * Defines the amount of retries to allocate the first UAR in the page.
13 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
14 * UAR base address if UAR was not the first object in the UAR page.
15 * It caused the PMD failure and we should try to get another UAR
16 * till we get the first one with non-NULL base address returned.
18 #define MLX5_ALLOC_UAR_RETRY 32
20 /* This is limitation of libibverbs: in length variable type is u16. */
21 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \
22 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4))
24 struct mlx5_devx_mkey_attr {
29 uint32_t log_entity_size;
31 uint32_t relaxed_ordering_write:1;
32 uint32_t relaxed_ordering_read:1;
33 struct mlx5_klm *klm_array;
37 /* HCA qos attributes. */
38 struct mlx5_hca_qos_attr {
39 uint32_t sup:1; /* Whether QOS is supported. */
40 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */
41 uint32_t packet_pacing:1; /* Packet pacing is supported. */
42 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */
43 uint32_t flow_meter_reg_share:1;
44 /* Whether reg_c share is supported. */
45 uint8_t log_max_flow_meter;
46 /* Power of the maximum supported meters. */
47 uint8_t flow_meter_reg_c_ids;
48 /* Bitmap of the reg_Cs available for flow meter to use. */
52 struct mlx5_hca_vdpa_attr {
53 uint8_t virtio_queue_type;
55 uint32_t desc_tunnel_offload_type:1;
56 uint32_t eth_frame_offload_type:1;
57 uint32_t virtio_version_1_0:1;
62 uint32_t event_mode:3;
63 uint32_t log_doorbell_stride:5;
64 uint32_t log_doorbell_bar_size:5;
65 uint32_t queue_counters_valid:1;
66 uint32_t max_num_virtio_queues;
71 uint64_t doorbell_bar_offset;
74 /* HCA supports this number of time periods for LRO. */
75 #define MLX5_LRO_NUM_SUPP_PERIODS 4
78 struct mlx5_hca_attr {
79 uint32_t eswitch_manager:1;
80 uint32_t flow_counters_dump:1;
81 uint32_t log_max_rqt_size:5;
82 uint32_t parse_graph_flex_node:1;
83 uint8_t flow_counter_bulk_alloc_bitmap;
84 uint32_t eth_net_offloads:1;
86 uint32_t wqe_vlan_insert:1;
87 uint32_t wqe_inline_mode:2;
88 uint32_t vport_inline_mode:3;
89 uint32_t tunnel_stateless_geneve_rx:1;
90 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
91 uint32_t tunnel_stateless_gtp:1;
93 uint32_t tunnel_lro_gre:1;
94 uint32_t tunnel_lro_vxlan:1;
95 uint32_t lro_max_msg_sz_mode:2;
96 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
97 uint16_t lro_min_mss_size;
98 uint32_t flex_parser_protocols;
100 uint32_t log_max_hairpin_queues:5;
101 uint32_t log_max_hairpin_wq_data_sz:5;
102 uint32_t log_max_hairpin_num_packets:5;
104 uint32_t relaxed_ordering_write:1;
105 uint32_t relaxed_ordering_read:1;
106 uint32_t access_register_user:1;
107 uint32_t wqe_index_ignore:1;
108 uint32_t cross_channel:1;
109 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */
110 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */
111 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */
112 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */
113 uint32_t scatter_fcs_w_decap_disable:1;
114 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */
116 uint32_t regexp_num_of_engines;
117 uint32_t log_max_ft_sampler_num:8;
118 struct mlx5_hca_qos_attr qos;
119 struct mlx5_hca_vdpa_attr vdpa;
125 uint32_t log_max_mrw_sz;
126 uint32_t log_max_srq;
127 uint32_t log_max_srq_sz;
128 uint32_t rss_ind_tbl_cap;
131 struct mlx5_devx_wq_attr {
133 uint32_t wq_signature:1;
134 uint32_t end_padding_mode:2;
136 uint32_t hds_skip_first_sge:1;
137 uint32_t log2_hds_buf_size:3;
138 uint32_t page_offset:5;
141 uint32_t uar_page:24;
145 uint32_t log_wq_stride:4;
146 uint32_t log_wq_pg_sz:5;
147 uint32_t log_wq_sz:5;
148 uint32_t dbr_umem_valid:1;
149 uint32_t wq_umem_valid:1;
150 uint32_t log_hairpin_num_packets:5;
151 uint32_t log_hairpin_data_sz:5;
152 uint32_t single_wqe_log_num_of_strides:4;
153 uint32_t two_byte_shift_en:1;
154 uint32_t single_stride_log_num_of_bytes:3;
155 uint32_t dbr_umem_id;
157 uint64_t wq_umem_offset;
160 /* Create RQ attributes structure, used by create RQ operation. */
161 struct mlx5_devx_create_rq_attr {
163 uint32_t delay_drop_en:1;
164 uint32_t scatter_fcs:1;
166 uint32_t mem_rq_type:4;
168 uint32_t flush_in_error_en:1;
170 uint32_t user_index:24;
172 uint32_t counter_set_id:8;
174 struct mlx5_devx_wq_attr wq_attr;
177 /* Modify RQ attributes structure, used by modify RQ operation. */
178 struct mlx5_devx_modify_rq_attr {
180 uint32_t rq_state:4; /* Current RQ state. */
181 uint32_t state:4; /* Required RQ state. */
182 uint32_t scatter_fcs:1;
184 uint32_t counter_set_id:8;
185 uint32_t hairpin_peer_sq:24;
186 uint32_t hairpin_peer_vhca:16;
187 uint64_t modify_bitmask;
188 uint32_t lwm:16; /* Contained WQ lwm. */
191 struct mlx5_rx_hash_field_select {
192 uint32_t l3_prot_type:1;
193 uint32_t l4_prot_type:1;
194 uint32_t selected_fields:30;
197 /* TIR attributes structure, used by TIR operations. */
198 struct mlx5_devx_tir_attr {
199 uint32_t disp_type:4;
200 uint32_t lro_timeout_period_usecs:16;
201 uint32_t lro_enable_mask:4;
202 uint32_t lro_max_msg_sz:8;
203 uint32_t inline_rqn:24;
204 uint32_t rx_hash_symmetric:1;
205 uint32_t tunneled_offload_en:1;
206 uint32_t indirect_table:24;
207 uint32_t rx_hash_fn:4;
208 uint32_t self_lb_block:2;
209 uint32_t transport_domain:24;
210 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN];
211 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
212 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
215 /* TIR attributes structure, used by TIR modify. */
216 struct mlx5_devx_modify_tir_attr {
218 uint64_t modify_bitmask;
219 struct mlx5_devx_tir_attr tir;
222 /* RQT attributes structure, used by RQT operations. */
223 struct mlx5_devx_rqt_attr {
225 uint32_t rqt_max_size:16;
226 uint32_t rqt_actual_size:16;
230 /* TIS attributes structure. */
231 struct mlx5_devx_tis_attr {
232 uint32_t strict_lag_tx_port_affinity:1;
234 uint32_t lag_tx_port_affinity:4;
236 uint32_t transport_domain:24;
239 /* SQ attributes structure, used by SQ create operation. */
240 struct mlx5_devx_create_sq_attr {
242 uint32_t cd_master:1;
244 uint32_t flush_in_error_en:1;
245 uint32_t allow_multi_pkt_send_wqe:1;
246 uint32_t min_wqe_inline_mode:3;
249 uint32_t allow_swp:1;
252 uint32_t static_sq_wq:1;
253 uint32_t user_index:24;
255 uint32_t packet_pacing_rate_limit_index:16;
256 uint32_t tis_lst_sz:16;
258 struct mlx5_devx_wq_attr wq_attr;
261 /* SQ attributes structure, used by SQ modify operation. */
262 struct mlx5_devx_modify_sq_attr {
265 uint32_t hairpin_peer_rq:24;
266 uint32_t hairpin_peer_vhca:16;
270 /* CQ attributes structure, used by CQ operations. */
271 struct mlx5_devx_cq_attr {
272 uint32_t q_umem_valid:1;
273 uint32_t db_umem_valid:1;
274 uint32_t use_first_only:1;
275 uint32_t overrun_ignore:1;
276 uint32_t cqe_comp_en:1;
277 uint32_t mini_cqe_res_format:2;
278 uint32_t mini_cqe_res_format_ext:2;
280 uint32_t log_cq_size:5;
281 uint32_t log_page_size:5;
282 uint32_t uar_page_id;
284 uint64_t q_umem_offset;
286 uint64_t db_umem_offset;
291 /* Virtq attributes structure, used by VIRTQ operations. */
292 struct mlx5_devx_virtq_attr {
293 uint16_t hw_available_index;
294 uint16_t hw_used_index;
297 uint32_t virtio_version_1_0:1;
302 uint32_t event_mode:3;
304 uint32_t dirty_bitmap_dump_enable:1;
305 uint32_t dirty_bitmap_mkey;
306 uint32_t dirty_bitmap_size;
309 uint32_t queue_index;
311 uint32_t counters_obj_id;
312 uint64_t dirty_bitmap_addr;
316 uint64_t available_addr;
326 struct mlx5_devx_qp_attr {
328 uint32_t uar_index:24;
330 uint32_t log_page_size:5;
331 uint32_t rq_size:17; /* Must be power of 2. */
332 uint32_t log_rq_stride:3;
333 uint32_t sq_size:17; /* Must be power of 2. */
334 uint32_t dbr_umem_valid:1;
335 uint32_t dbr_umem_id;
336 uint64_t dbr_address;
338 uint64_t wq_umem_offset;
341 struct mlx5_devx_virtio_q_couners_attr {
342 uint64_t received_desc;
343 uint64_t completed_desc;
345 uint32_t bad_desc_errors;
346 uint32_t exceed_max_chain;
347 uint32_t invalid_buffer;
351 * graph flow match sample attributes structure,
352 * used by flex parser operations.
354 struct mlx5_devx_match_sample_attr {
355 uint32_t flow_match_sample_en:1;
356 uint32_t flow_match_sample_field_offset:16;
357 uint32_t flow_match_sample_offset_mode:4;
358 uint32_t flow_match_sample_field_offset_mask;
359 uint32_t flow_match_sample_field_offset_shift:4;
360 uint32_t flow_match_sample_field_base_offset:8;
361 uint32_t flow_match_sample_tunnel_mode:3;
362 uint32_t flow_match_sample_field_id;
365 /* graph node arc attributes structure, used by flex parser operations. */
366 struct mlx5_devx_graph_arc_attr {
367 uint32_t compare_condition_value:16;
368 uint32_t start_inner_tunnel:1;
369 uint32_t arc_parse_graph_node:8;
370 uint32_t parse_graph_node_handle;
373 /* Maximal number of samples per graph node. */
374 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8
376 /* Maximal number of input/output arcs per graph node. */
377 #define MLX5_GRAPH_NODE_ARC_NUM 8
379 /* parse graph node attributes structure, used by flex parser operations. */
380 struct mlx5_devx_graph_node_attr {
381 uint32_t modify_field_select;
382 uint32_t header_length_mode:4;
383 uint32_t header_length_base_value:16;
384 uint32_t header_length_field_shift:4;
385 uint32_t header_length_field_offset:16;
386 uint32_t header_length_field_mask;
387 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM];
388 uint32_t next_header_field_offset:16;
389 uint32_t next_header_field_size:5;
390 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM];
391 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM];
394 /* mlx5_devx_cmds.c */
397 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx,
400 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
402 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
403 int clear, uint32_t n_counters,
404 uint64_t *pkts, uint64_t *bytes,
405 uint32_t mkey, void *addr,
409 int mlx5_devx_cmd_query_hca_attr(void *ctx,
410 struct mlx5_hca_attr *attr);
412 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx,
413 struct mlx5_devx_mkey_attr *attr);
415 int mlx5_devx_get_out_command_status(void *out);
417 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
420 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx,
421 struct mlx5_devx_create_rq_attr *rq_attr,
424 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
425 struct mlx5_devx_modify_rq_attr *rq_attr);
427 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx,
428 struct mlx5_devx_tir_attr *tir_attr);
430 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx,
431 struct mlx5_devx_rqt_attr *rqt_attr);
433 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx,
434 struct mlx5_devx_create_sq_attr *sq_attr);
436 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
437 struct mlx5_devx_modify_sq_attr *sq_attr);
439 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx,
440 struct mlx5_devx_tis_attr *tis_attr);
442 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx);
444 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain,
447 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx,
448 struct mlx5_devx_cq_attr *attr);
450 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx,
451 struct mlx5_devx_virtq_attr *attr);
453 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
454 struct mlx5_devx_virtq_attr *attr);
456 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
457 struct mlx5_devx_virtq_attr *attr);
459 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx,
460 struct mlx5_devx_qp_attr *attr);
462 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,
463 uint32_t qp_st_mod_op, uint32_t remote_qp_id);
465 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
466 struct mlx5_devx_rqt_attr *rqt_attr);
468 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
469 struct mlx5_devx_modify_tir_attr *tir_attr);
471 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
472 uint32_t ids[], uint32_t num);
475 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx,
476 struct mlx5_devx_graph_node_attr *data);
479 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id,
480 uint32_t arg, uint32_t *data, uint32_t dw_cnt);
482 * Create virtio queue counters object DevX API.
488 * The DevX object created, NULL otherwise and rte_errno is set.
491 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx);
494 * Query virtio queue counters object using DevX API.
496 * @param[in] couners_obj
497 * Pointer to virtq object structure.
498 * @param [in/out] attr
499 * Pointer to virtio queue counters attributes structure.
502 * 0 on success, a negative errno value otherwise and rte_errno is set.
505 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
506 struct mlx5_devx_virtio_q_couners_attr *attr);
508 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx,
512 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx);
513 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */