1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_
6 #define RTE_PMD_MLX5_DEVX_CMDS_H_
8 #include <rte_compat.h>
9 #include <rte_bitops.h>
11 #include "mlx5_glue.h"
14 /* This is limitation of libibverbs: in length variable type is u16. */
15 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \
16 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4))
18 struct mlx5_devx_mkey_attr {
23 uint32_t log_entity_size;
25 uint32_t relaxed_ordering_write:1;
26 uint32_t relaxed_ordering_read:1;
29 uint32_t set_remote_rw:1;
30 struct mlx5_klm *klm_array;
34 /* HCA qos attributes. */
35 struct mlx5_hca_qos_attr {
36 uint32_t sup:1; /* Whether QOS is supported. */
37 uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */
38 uint32_t packet_pacing:1; /* Packet pacing is supported. */
39 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */
40 uint32_t flow_meter:1;
42 * Flow meter is supported, updated version.
43 * When flow_meter is 1, it indicates that REG_C sharing is supported.
44 * If flow_meter is 1, flow_meter_old is also 1.
45 * Using older driver versions, flow_meter_old can be 1
46 * while flow_meter is 0.
48 uint32_t flow_meter_aso_sup:1;
49 /* Whether FLOW_METER_ASO Object is supported. */
50 uint8_t log_max_flow_meter;
51 /* Power of the maximum supported meters. */
52 uint8_t flow_meter_reg_c_ids;
53 /* Bitmap of the reg_Cs available for flow meter to use. */
54 uint32_t log_meter_aso_granularity:5;
55 /* Power of the minimum allocation granularity Object. */
56 uint32_t log_meter_aso_max_alloc:5;
57 /* Power of the maximum allocation granularity Object. */
58 uint32_t log_max_num_meter_aso:5;
59 /* Power of the maximum number of supported objects. */
63 struct mlx5_hca_vdpa_attr {
64 uint8_t virtio_queue_type;
66 uint32_t desc_tunnel_offload_type:1;
67 uint32_t eth_frame_offload_type:1;
68 uint32_t virtio_version_1_0:1;
73 uint32_t event_mode:3;
74 uint32_t log_doorbell_stride:5;
75 uint32_t log_doorbell_bar_size:5;
76 uint32_t queue_counters_valid:1;
77 uint32_t vnet_modify_ext:1;
78 uint32_t virtio_net_q_addr_modify:1;
79 uint32_t virtio_q_index_modify:1;
80 uint32_t max_num_virtio_queues;
85 uint64_t doorbell_bar_offset;
88 struct mlx5_hca_flow_attr {
89 uint32_t tunnel_header_0_1;
90 uint32_t tunnel_header_2_3;
94 * Accumulate port PARSE_GRAPH_NODE capabilities from
95 * PARSE_GRAPH_NODE Capabilities and HCA Capabilities 2 tables
98 struct mlx5_hca_flex_attr {
101 uint16_t header_length_mode;
102 uint16_t sample_offset_mode;
103 uint8_t max_num_arc_in;
104 uint8_t max_num_arc_out;
105 uint8_t max_num_sample;
106 uint8_t max_num_prog_sample:5; /* From HCA CAP 2 */
107 uint8_t sample_id_in_out:1;
108 uint16_t max_base_header_length;
109 uint8_t max_sample_base_offset;
110 uint16_t max_next_header_offset;
111 uint8_t header_length_mask_width;
114 /* ISO C restricts enumerator values to range of 'int' */
117 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_HEAD = RTE_BIT32(1),
118 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MAC = RTE_BIT32(2),
119 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IP = RTE_BIT32(3),
120 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GRE = RTE_BIT32(4),
121 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_UDP = RTE_BIT32(5),
122 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_MPLS = RTE_BIT32(6),
123 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_TCP = RTE_BIT32(7),
124 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_VXLAN_GRE = RTE_BIT32(8),
125 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_GENEVE = RTE_BIT32(9),
126 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPSEC_ESP = RTE_BIT32(10),
127 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV4 = RTE_BIT32(11),
128 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_IPV6 = RTE_BIT32(12),
129 PARSE_GRAPH_NODE_CAP_SUPPORTED_PROTOCOL_PROGRAMMABLE = RTE_BIT32(31)
133 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_FIXED = RTE_BIT32(0),
134 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_EXPLISIT_FIELD = RTE_BIT32(1),
135 PARSE_GRAPH_NODE_CAP_LENGTH_MODE_BITMASK_FIELD = RTE_BIT32(2)
139 * DWORD shift is the base for calculating header_length_field_mask
140 * value in the MLX5_GRAPH_NODE_LEN_FIELD mode.
142 #define MLX5_PARSE_GRAPH_NODE_HDR_LEN_SHIFT_DWORD 0x02
144 static inline uint32_t
145 mlx5_hca_parse_graph_node_base_hdr_len_mask
146 (const struct mlx5_hca_flex_attr *attr)
148 return (1 << attr->header_length_mask_width) - 1;
151 /* HCA supports this number of time periods for LRO. */
152 #define MLX5_LRO_NUM_SUPP_PERIODS 4
154 /* HCA attributes. */
155 struct mlx5_hca_attr {
156 uint32_t eswitch_manager:1;
157 uint32_t flow_counters_dump:1;
158 uint32_t mem_rq_rmp:1;
159 uint32_t log_max_rmp:5;
160 uint32_t log_max_rqt_size:5;
161 uint32_t parse_graph_flex_node:1;
162 uint8_t flow_counter_bulk_alloc_bitmap;
163 uint32_t eth_net_offloads:1;
165 uint32_t wqe_vlan_insert:1;
168 uint32_t wqe_inline_mode:2;
169 uint32_t vport_inline_mode:3;
170 uint32_t tunnel_stateless_geneve_rx:1;
171 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
172 uint32_t tunnel_stateless_gtp:1;
173 uint32_t max_lso_cap;
174 uint32_t scatter_fcs:1;
176 uint32_t tunnel_lro_gre:1;
177 uint32_t tunnel_lro_vxlan:1;
178 uint32_t tunnel_stateless_gre:1;
179 uint32_t tunnel_stateless_vxlan:1;
183 uint32_t lro_max_msg_sz_mode:2;
184 uint32_t rq_delay_drop:1;
185 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
186 uint16_t lro_min_mss_size;
187 uint32_t flex_parser_protocols;
188 uint32_t max_geneve_tlv_options;
189 uint32_t max_geneve_tlv_option_data_len;
191 uint32_t log_max_hairpin_queues:5;
192 uint32_t log_max_hairpin_wq_data_sz:5;
193 uint32_t log_max_hairpin_num_packets:5;
195 uint32_t relaxed_ordering_write:1;
196 uint32_t relaxed_ordering_read:1;
197 uint32_t access_register_user:1;
198 uint32_t wqe_index_ignore:1;
199 uint32_t cross_channel:1;
200 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */
201 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */
202 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */
203 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */
204 uint32_t scatter_fcs_w_decap_disable:1;
205 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */
207 uint32_t wait_on_time:1;
208 uint32_t rq_ts_format:2;
209 uint32_t sq_ts_format:2;
210 uint32_t steering_format_version:4;
211 uint32_t qp_ts_format:2;
212 uint32_t regexp_params:1;
213 uint32_t regexp_version:3;
214 uint32_t reg_c_preserve:1;
215 uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */
216 uint32_t crypto:1; /* Crypto engine is supported. */
217 uint32_t aes_xts:1; /* AES-XTS crypto is supported. */
218 uint32_t dek:1; /* General obj type DEK is supported. */
219 uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */
220 uint32_t credential:1; /* General obj type CREDENTIAL supported. */
221 uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */
222 uint32_t regexp_num_of_engines;
223 uint32_t log_max_ft_sampler_num:8;
224 uint32_t inner_ipv4_ihl:1;
225 uint32_t outer_ipv4_ihl:1;
226 uint32_t geneve_tlv_opt;
227 uint32_t cqe_compression:1;
228 uint32_t mini_cqe_resp_flow_tag:1;
229 uint32_t mini_cqe_resp_l3_l4_tag:1;
230 uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */
231 struct mlx5_hca_qos_attr qos;
232 struct mlx5_hca_vdpa_attr vdpa;
233 struct mlx5_hca_flow_attr flow;
234 struct mlx5_hca_flex_attr flex;
240 uint32_t log_max_mrw_sz;
241 uint32_t log_max_srq;
242 uint32_t log_max_srq_sz;
243 uint32_t rss_ind_tbl_cap;
244 uint32_t mmo_dma_sq_en:1;
245 uint32_t mmo_compress_sq_en:1;
246 uint32_t mmo_decompress_sq_en:1;
247 uint32_t mmo_dma_qp_en:1;
248 uint32_t mmo_compress_qp_en:1;
249 uint32_t mmo_decompress_qp_en:1;
250 uint32_t mmo_regex_qp_en:1;
251 uint32_t mmo_regex_sq_en:1;
252 uint32_t compress_min_block_size:4;
253 uint32_t log_max_mmo_dma:5;
254 uint32_t log_max_mmo_compress:5;
255 uint32_t log_max_mmo_decompress:5;
256 uint32_t umr_modify_entity_size_disabled:1;
257 uint32_t umr_indirect_mkey_disabled:1;
258 uint32_t log_min_stride_wqe_sz:5;
259 uint32_t esw_mgr_vport_id_valid:1; /* E-Switch Mgr vport ID is valid. */
260 uint32_t crypto_wrapped_import_method:1;
261 uint16_t esw_mgr_vport_id; /* E-Switch Mgr vport ID . */
262 uint16_t max_wqe_sz_sq;
263 uint32_t modify_outer_ip_ecn:1;
267 struct mlx5_devx_lag_context {
268 uint32_t fdb_selection_mode:1;
269 uint32_t port_select_mode:3;
270 uint32_t lag_state:3;
271 uint32_t tx_remap_affinity_1:4;
272 uint32_t tx_remap_affinity_2:4;
275 struct mlx5_devx_wq_attr {
277 uint32_t wq_signature:1;
278 uint32_t end_padding_mode:2;
280 uint32_t hds_skip_first_sge:1;
281 uint32_t log2_hds_buf_size:3;
282 uint32_t page_offset:5;
285 uint32_t uar_page:24;
289 uint32_t log_wq_stride:4;
290 uint32_t log_wq_pg_sz:5;
291 uint32_t log_wq_sz:5;
292 uint32_t dbr_umem_valid:1;
293 uint32_t wq_umem_valid:1;
294 uint32_t log_hairpin_num_packets:5;
295 uint32_t log_hairpin_data_sz:5;
296 uint32_t single_wqe_log_num_of_strides:4;
297 uint32_t two_byte_shift_en:1;
298 uint32_t single_stride_log_num_of_bytes:3;
299 uint32_t dbr_umem_id;
301 uint64_t wq_umem_offset;
304 /* Create RQ attributes structure, used by create RQ operation. */
305 struct mlx5_devx_create_rq_attr {
307 uint32_t delay_drop_en:1;
308 uint32_t scatter_fcs:1;
310 uint32_t mem_rq_type:4;
312 uint32_t flush_in_error_en:1;
314 uint32_t ts_format:2;
315 uint32_t user_index:24;
317 uint32_t counter_set_id:8;
319 struct mlx5_devx_wq_attr wq_attr;
322 /* Modify RQ attributes structure, used by modify RQ operation. */
323 struct mlx5_devx_modify_rq_attr {
325 uint32_t rq_state:4; /* Current RQ state. */
326 uint32_t state:4; /* Required RQ state. */
327 uint32_t scatter_fcs:1;
329 uint32_t counter_set_id:8;
330 uint32_t hairpin_peer_sq:24;
331 uint32_t hairpin_peer_vhca:16;
332 uint64_t modify_bitmask;
333 uint32_t lwm:16; /* Contained WQ lwm. */
336 /* Create RMP attributes structure, used by create RMP operation. */
337 struct mlx5_devx_create_rmp_attr {
341 uint32_t basic_cyclic_rcv_wqe:1;
344 struct mlx5_devx_wq_attr wq_attr;
347 struct mlx5_rx_hash_field_select {
348 uint32_t l3_prot_type:1;
349 uint32_t l4_prot_type:1;
350 uint32_t selected_fields:30;
353 /* TIR attributes structure, used by TIR operations. */
354 struct mlx5_devx_tir_attr {
355 uint32_t disp_type:4;
356 uint32_t lro_timeout_period_usecs:16;
357 uint32_t lro_enable_mask:4;
358 uint32_t lro_max_msg_sz:8;
359 uint32_t inline_rqn:24;
360 uint32_t rx_hash_symmetric:1;
361 uint32_t tunneled_offload_en:1;
362 uint32_t indirect_table:24;
363 uint32_t rx_hash_fn:4;
364 uint32_t self_lb_block:2;
365 uint32_t transport_domain:24;
366 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN];
367 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
368 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
371 /* TIR attributes structure, used by TIR modify. */
372 struct mlx5_devx_modify_tir_attr {
374 uint64_t modify_bitmask;
375 struct mlx5_devx_tir_attr tir;
378 /* RQT attributes structure, used by RQT operations. */
379 struct mlx5_devx_rqt_attr {
381 uint32_t rqt_max_size:16;
382 uint32_t rqt_actual_size:16;
386 /* TIS attributes structure. */
387 struct mlx5_devx_tis_attr {
388 uint32_t strict_lag_tx_port_affinity:1;
390 uint32_t lag_tx_port_affinity:4;
392 uint32_t transport_domain:24;
395 /* SQ attributes structure, used by SQ create operation. */
396 struct mlx5_devx_create_sq_attr {
398 uint32_t cd_master:1;
400 uint32_t flush_in_error_en:1;
401 uint32_t allow_multi_pkt_send_wqe:1;
402 uint32_t min_wqe_inline_mode:3;
405 uint32_t allow_swp:1;
408 uint32_t static_sq_wq:1;
409 uint32_t ts_format:2;
410 uint32_t user_index:24;
412 uint32_t packet_pacing_rate_limit_index:16;
413 uint32_t tis_lst_sz:16;
415 struct mlx5_devx_wq_attr wq_attr;
418 /* SQ attributes structure, used by SQ modify operation. */
419 struct mlx5_devx_modify_sq_attr {
422 uint32_t hairpin_peer_rq:24;
423 uint32_t hairpin_peer_vhca:16;
427 /* CQ attributes structure, used by CQ operations. */
428 struct mlx5_devx_cq_attr {
429 uint32_t q_umem_valid:1;
430 uint32_t db_umem_valid:1;
431 uint32_t use_first_only:1;
432 uint32_t overrun_ignore:1;
433 uint32_t cqe_comp_en:1;
434 uint32_t mini_cqe_res_format:2;
435 uint32_t mini_cqe_res_format_ext:2;
436 uint32_t log_cq_size:5;
437 uint32_t log_page_size:5;
438 uint32_t uar_page_id;
440 uint64_t q_umem_offset;
442 uint64_t db_umem_offset;
447 /* Virtq attributes structure, used by VIRTQ operations. */
448 struct mlx5_devx_virtq_attr {
449 uint16_t hw_available_index;
450 uint16_t hw_used_index;
453 uint32_t virtio_version_1_0:1;
458 uint32_t event_mode:3;
460 uint32_t hw_latency_mode:2;
461 uint32_t hw_max_latency_us:12;
462 uint32_t hw_max_pending_comp:16;
463 uint32_t dirty_bitmap_dump_enable:1;
464 uint32_t dirty_bitmap_mkey;
465 uint32_t dirty_bitmap_size;
468 uint32_t queue_index;
470 uint32_t counters_obj_id;
471 uint64_t dirty_bitmap_addr;
472 uint64_t mod_fields_bitmap;
475 uint64_t available_addr;
486 struct mlx5_devx_qp_attr {
488 uint32_t uar_index:24;
490 uint32_t log_page_size:5;
491 uint32_t num_of_receive_wqes:17; /* Must be power of 2. */
492 uint32_t log_rq_stride:3;
493 uint32_t num_of_send_wqbbs:17; /* Must be power of 2. */
494 uint32_t ts_format:2;
495 uint32_t dbr_umem_valid:1;
496 uint32_t dbr_umem_id;
497 uint64_t dbr_address;
499 uint64_t wq_umem_offset;
500 uint32_t user_index:24;
504 struct mlx5_devx_virtio_q_couners_attr {
505 uint64_t received_desc;
506 uint64_t completed_desc;
508 uint32_t bad_desc_errors;
509 uint32_t exceed_max_chain;
510 uint32_t invalid_buffer;
514 * graph flow match sample attributes structure,
515 * used by flex parser operations.
517 struct mlx5_devx_match_sample_attr {
518 uint32_t flow_match_sample_en:1;
519 uint32_t flow_match_sample_field_offset:16;
520 uint32_t flow_match_sample_offset_mode:4;
521 uint32_t flow_match_sample_field_offset_mask;
522 uint32_t flow_match_sample_field_offset_shift:4;
523 uint32_t flow_match_sample_field_base_offset:8;
524 uint32_t flow_match_sample_tunnel_mode:3;
525 uint32_t flow_match_sample_field_id;
528 /* graph node arc attributes structure, used by flex parser operations. */
529 struct mlx5_devx_graph_arc_attr {
530 uint32_t compare_condition_value:16;
531 uint32_t start_inner_tunnel:1;
532 uint32_t arc_parse_graph_node:8;
533 uint32_t parse_graph_node_handle;
536 /* Maximal number of samples per graph node. */
537 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8
539 /* Maximal number of input/output arcs per graph node. */
540 #define MLX5_GRAPH_NODE_ARC_NUM 8
542 /* parse graph node attributes structure, used by flex parser operations. */
543 struct mlx5_devx_graph_node_attr {
544 uint32_t modify_field_select;
545 uint32_t header_length_mode:4;
546 uint32_t header_length_base_value:16;
547 uint32_t header_length_field_shift:4;
548 uint32_t header_length_field_offset:16;
549 uint32_t header_length_field_mask;
550 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM];
551 uint32_t next_header_field_offset:16;
552 uint32_t next_header_field_size:5;
553 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM];
554 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM];
557 /* Encryption key size is up to 1024 bit, 128 bytes. */
558 #define MLX5_CRYPTO_KEY_MAX_SIZE 128
560 struct mlx5_devx_dek_attr {
562 uint32_t has_keytag:1;
563 uint32_t key_purpose:4;
566 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE];
569 struct mlx5_devx_import_kek_attr {
570 uint64_t modify_field_select;
573 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE];
576 #define MLX5_CRYPTO_CREDENTIAL_SIZE 48
578 struct mlx5_devx_credential_attr {
579 uint64_t modify_field_select;
581 uint32_t credential_role:8;
582 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE];
585 struct mlx5_devx_crypto_login_attr {
586 uint64_t modify_field_select;
587 uint32_t credential_pointer:24;
588 uint32_t session_import_kek_ptr:24;
589 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE];
592 /* mlx5_devx_cmds.c */
595 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx,
598 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
600 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
601 int clear, uint32_t n_counters,
602 uint64_t *pkts, uint64_t *bytes,
603 uint32_t mkey, void *addr,
607 int mlx5_devx_cmd_query_hca_attr(void *ctx,
608 struct mlx5_hca_attr *attr);
610 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx,
611 struct mlx5_devx_mkey_attr *attr);
613 int mlx5_devx_get_out_command_status(void *out);
615 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
618 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx,
619 struct mlx5_devx_create_rq_attr *rq_attr,
622 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
623 struct mlx5_devx_modify_rq_attr *rq_attr);
625 struct mlx5_devx_obj *mlx5_devx_cmd_create_rmp(void *ctx,
626 struct mlx5_devx_create_rmp_attr *rq_attr, int socket);
628 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx,
629 struct mlx5_devx_tir_attr *tir_attr);
631 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx,
632 struct mlx5_devx_rqt_attr *rqt_attr);
634 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx,
635 struct mlx5_devx_create_sq_attr *sq_attr);
637 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
638 struct mlx5_devx_modify_sq_attr *sq_attr);
640 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx,
641 struct mlx5_devx_tis_attr *tis_attr);
643 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx);
645 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain,
648 int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file);
650 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx,
651 struct mlx5_devx_cq_attr *attr);
653 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx,
654 struct mlx5_devx_virtq_attr *attr);
656 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
657 struct mlx5_devx_virtq_attr *attr);
659 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
660 struct mlx5_devx_virtq_attr *attr);
662 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx,
663 struct mlx5_devx_qp_attr *attr);
665 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,
666 uint32_t qp_st_mod_op, uint32_t remote_qp_id);
668 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
669 struct mlx5_devx_rqt_attr *rqt_attr);
671 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
672 struct mlx5_devx_modify_tir_attr *tir_attr);
674 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
675 uint32_t ids[], uint32_t num);
678 struct mlx5_devx_obj *
679 mlx5_devx_cmd_create_flex_parser(void *ctx,
680 struct mlx5_devx_graph_node_attr *data);
683 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id,
684 uint32_t arg, uint32_t *data, uint32_t dw_cnt);
687 int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id,
688 uint32_t arg, uint32_t *data, uint32_t dw_cnt);
691 struct mlx5_devx_obj *
692 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
693 uint16_t class, uint8_t type, uint8_t len);
696 * Create virtio queue counters object DevX API.
702 * The DevX object created, NULL otherwise and rte_errno is set.
705 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx);
708 * Query virtio queue counters object using DevX API.
710 * @param[in] couners_obj
711 * Pointer to virtq object structure.
712 * @param [in/out] attr
713 * Pointer to virtio queue counters attributes structure.
716 * 0 on success, a negative errno value otherwise and rte_errno is set.
719 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
720 struct mlx5_devx_virtio_q_couners_attr *attr);
722 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx,
725 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx);
728 int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id);
731 struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx);
733 int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
734 uint32_t *out_of_buffers);
736 struct mlx5_devx_obj *mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx,
737 uint32_t pd, uint32_t log_obj_size);
740 * Create general object of type FLOW_METER_ASO using DevX API..
745 * PD value to associate the FLOW_METER_ASO object with.
746 * @param [in] log_obj_size
747 * log_obj_size define to allocate number of 2 * meters
748 * in one FLOW_METER_ASO object.
751 * The DevX object created, NULL otherwise and rte_errno is set.
754 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx,
755 uint32_t pd, uint32_t log_obj_size);
757 struct mlx5_devx_obj *
758 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr);
761 struct mlx5_devx_obj *
762 mlx5_devx_cmd_create_import_kek_obj(void *ctx,
763 struct mlx5_devx_import_kek_attr *attr);
766 struct mlx5_devx_obj *
767 mlx5_devx_cmd_create_credential_obj(void *ctx,
768 struct mlx5_devx_credential_attr *attr);
771 struct mlx5_devx_obj *
772 mlx5_devx_cmd_create_crypto_login_obj(void *ctx,
773 struct mlx5_devx_crypto_login_attr *attr);
777 mlx5_devx_cmd_query_lag(void *ctx,
778 struct mlx5_devx_lag_context *lag_ctx);
779 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */