1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_
6 #define RTE_PMD_MLX5_DEVX_CMDS_H_
10 #include <rte_compat.h>
13 * Defines the amount of retries to allocate the first UAR in the page.
14 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
15 * UAR base address if UAR was not the first object in the UAR page.
16 * It caused the PMD failure and we should try to get another UAR
17 * till we get the first one with non-NULL base address returned.
19 #define MLX5_ALLOC_UAR_RETRY 32
21 /* This is limitation of libibverbs: in length variable type is u16. */
22 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \
23 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4))
25 struct mlx5_devx_mkey_attr {
30 uint32_t log_entity_size;
32 uint32_t relaxed_ordering_write:1;
33 uint32_t relaxed_ordering_read:1;
36 uint32_t set_remote_rw:1;
37 struct mlx5_klm *klm_array;
41 /* HCA qos attributes. */
42 struct mlx5_hca_qos_attr {
43 uint32_t sup:1; /* Whether QOS is supported. */
44 uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */
45 uint32_t packet_pacing:1; /* Packet pacing is supported. */
46 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */
47 uint32_t flow_meter:1;
49 * Flow meter is supported, updated version.
50 * When flow_meter is 1, it indicates that REG_C sharing is supported.
51 * If flow_meter is 1, flow_meter_old is also 1.
52 * Using older driver versions, flow_meter_old can be 1
53 * while flow_meter is 0.
55 uint32_t flow_meter_aso_sup:1;
56 /* Whether FLOW_METER_ASO Object is supported. */
57 uint8_t log_max_flow_meter;
58 /* Power of the maximum supported meters. */
59 uint8_t flow_meter_reg_c_ids;
60 /* Bitmap of the reg_Cs available for flow meter to use. */
61 uint32_t log_meter_aso_granularity:5;
62 /* Power of the minimum allocation granularity Object. */
63 uint32_t log_meter_aso_max_alloc:5;
64 /* Power of the maximum allocation granularity Object. */
65 uint32_t log_max_num_meter_aso:5;
66 /* Power of the maximum number of supported objects. */
70 struct mlx5_hca_vdpa_attr {
71 uint8_t virtio_queue_type;
73 uint32_t desc_tunnel_offload_type:1;
74 uint32_t eth_frame_offload_type:1;
75 uint32_t virtio_version_1_0:1;
80 uint32_t event_mode:3;
81 uint32_t log_doorbell_stride:5;
82 uint32_t log_doorbell_bar_size:5;
83 uint32_t queue_counters_valid:1;
84 uint32_t max_num_virtio_queues;
89 uint64_t doorbell_bar_offset;
92 struct mlx5_hca_flow_attr {
93 uint32_t tunnel_header_0_1;
94 uint32_t tunnel_header_2_3;
97 /* HCA supports this number of time periods for LRO. */
98 #define MLX5_LRO_NUM_SUPP_PERIODS 4
100 /* HCA attributes. */
101 struct mlx5_hca_attr {
102 uint32_t eswitch_manager:1;
103 uint32_t flow_counters_dump:1;
104 uint32_t log_max_rqt_size:5;
105 uint32_t parse_graph_flex_node:1;
106 uint8_t flow_counter_bulk_alloc_bitmap;
107 uint32_t eth_net_offloads:1;
109 uint32_t wqe_vlan_insert:1;
111 uint32_t wqe_inline_mode:2;
112 uint32_t vport_inline_mode:3;
113 uint32_t tunnel_stateless_geneve_rx:1;
114 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
115 uint32_t tunnel_stateless_gtp:1;
117 uint32_t tunnel_lro_gre:1;
118 uint32_t tunnel_lro_vxlan:1;
119 uint32_t lro_max_msg_sz_mode:2;
120 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
121 uint16_t lro_min_mss_size;
122 uint32_t flex_parser_protocols;
123 uint32_t max_geneve_tlv_options;
124 uint32_t max_geneve_tlv_option_data_len;
126 uint32_t log_max_hairpin_queues:5;
127 uint32_t log_max_hairpin_wq_data_sz:5;
128 uint32_t log_max_hairpin_num_packets:5;
130 uint32_t relaxed_ordering_write:1;
131 uint32_t relaxed_ordering_read:1;
132 uint32_t access_register_user:1;
133 uint32_t wqe_index_ignore:1;
134 uint32_t cross_channel:1;
135 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */
136 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */
137 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */
138 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */
139 uint32_t scatter_fcs_w_decap_disable:1;
140 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */
142 uint32_t rq_ts_format:2;
143 uint32_t sq_ts_format:2;
144 uint32_t steering_format_version:4;
145 uint32_t qp_ts_format:2;
147 uint32_t reg_c_preserve:1;
148 uint32_t ct_offload:1; /* General obj type ASO CT offload supported. */
149 uint32_t crypto:1; /* Crypto engine is supported. */
150 uint32_t aes_xts:1; /* AES-XTS crypto is supported. */
151 uint32_t dek:1; /* General obj type DEK is supported. */
152 uint32_t import_kek:1; /* General obj type IMPORT_KEK supported. */
153 uint32_t credential:1; /* General obj type CREDENTIAL supported. */
154 uint32_t crypto_login:1; /* General obj type CRYPTO_LOGIN supported. */
155 uint32_t regexp_num_of_engines;
156 uint32_t log_max_ft_sampler_num:8;
157 uint32_t inner_ipv4_ihl:1;
158 uint32_t outer_ipv4_ihl:1;
159 uint32_t geneve_tlv_opt;
160 uint32_t cqe_compression:1;
161 uint32_t mini_cqe_resp_flow_tag:1;
162 uint32_t mini_cqe_resp_l3_l4_tag:1;
163 uint32_t pkt_integrity_match:1; /* 1 if HW supports integrity item */
164 struct mlx5_hca_qos_attr qos;
165 struct mlx5_hca_vdpa_attr vdpa;
166 struct mlx5_hca_flow_attr flow;
172 uint32_t log_max_mrw_sz;
173 uint32_t log_max_srq;
174 uint32_t log_max_srq_sz;
175 uint32_t rss_ind_tbl_cap;
176 uint32_t mmo_dma_sq_en:1;
177 uint32_t mmo_compress_sq_en:1;
178 uint32_t mmo_decompress_sq_en:1;
179 uint32_t mmo_dma_qp_en:1;
180 uint32_t mmo_compress_qp_en:1;
181 uint32_t mmo_decompress_qp_en:1;
182 uint32_t mmo_regex_qp_en:1;
183 uint32_t mmo_regex_sq_en:1;
184 uint32_t compress_min_block_size:4;
185 uint32_t log_max_mmo_dma:5;
186 uint32_t log_max_mmo_compress:5;
187 uint32_t log_max_mmo_decompress:5;
188 uint32_t umr_modify_entity_size_disabled:1;
189 uint32_t umr_indirect_mkey_disabled:1;
192 struct mlx5_devx_wq_attr {
194 uint32_t wq_signature:1;
195 uint32_t end_padding_mode:2;
197 uint32_t hds_skip_first_sge:1;
198 uint32_t log2_hds_buf_size:3;
199 uint32_t page_offset:5;
202 uint32_t uar_page:24;
206 uint32_t log_wq_stride:4;
207 uint32_t log_wq_pg_sz:5;
208 uint32_t log_wq_sz:5;
209 uint32_t dbr_umem_valid:1;
210 uint32_t wq_umem_valid:1;
211 uint32_t log_hairpin_num_packets:5;
212 uint32_t log_hairpin_data_sz:5;
213 uint32_t single_wqe_log_num_of_strides:4;
214 uint32_t two_byte_shift_en:1;
215 uint32_t single_stride_log_num_of_bytes:3;
216 uint32_t dbr_umem_id;
218 uint64_t wq_umem_offset;
221 /* Create RQ attributes structure, used by create RQ operation. */
222 struct mlx5_devx_create_rq_attr {
224 uint32_t delay_drop_en:1;
225 uint32_t scatter_fcs:1;
227 uint32_t mem_rq_type:4;
229 uint32_t flush_in_error_en:1;
231 uint32_t ts_format:2;
232 uint32_t user_index:24;
234 uint32_t counter_set_id:8;
236 struct mlx5_devx_wq_attr wq_attr;
239 /* Modify RQ attributes structure, used by modify RQ operation. */
240 struct mlx5_devx_modify_rq_attr {
242 uint32_t rq_state:4; /* Current RQ state. */
243 uint32_t state:4; /* Required RQ state. */
244 uint32_t scatter_fcs:1;
246 uint32_t counter_set_id:8;
247 uint32_t hairpin_peer_sq:24;
248 uint32_t hairpin_peer_vhca:16;
249 uint64_t modify_bitmask;
250 uint32_t lwm:16; /* Contained WQ lwm. */
253 struct mlx5_rx_hash_field_select {
254 uint32_t l3_prot_type:1;
255 uint32_t l4_prot_type:1;
256 uint32_t selected_fields:30;
259 /* TIR attributes structure, used by TIR operations. */
260 struct mlx5_devx_tir_attr {
261 uint32_t disp_type:4;
262 uint32_t lro_timeout_period_usecs:16;
263 uint32_t lro_enable_mask:4;
264 uint32_t lro_max_msg_sz:8;
265 uint32_t inline_rqn:24;
266 uint32_t rx_hash_symmetric:1;
267 uint32_t tunneled_offload_en:1;
268 uint32_t indirect_table:24;
269 uint32_t rx_hash_fn:4;
270 uint32_t self_lb_block:2;
271 uint32_t transport_domain:24;
272 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN];
273 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
274 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
277 /* TIR attributes structure, used by TIR modify. */
278 struct mlx5_devx_modify_tir_attr {
280 uint64_t modify_bitmask;
281 struct mlx5_devx_tir_attr tir;
284 /* RQT attributes structure, used by RQT operations. */
285 struct mlx5_devx_rqt_attr {
287 uint32_t rqt_max_size:16;
288 uint32_t rqt_actual_size:16;
292 /* TIS attributes structure. */
293 struct mlx5_devx_tis_attr {
294 uint32_t strict_lag_tx_port_affinity:1;
296 uint32_t lag_tx_port_affinity:4;
298 uint32_t transport_domain:24;
301 /* SQ attributes structure, used by SQ create operation. */
302 struct mlx5_devx_create_sq_attr {
304 uint32_t cd_master:1;
306 uint32_t flush_in_error_en:1;
307 uint32_t allow_multi_pkt_send_wqe:1;
308 uint32_t min_wqe_inline_mode:3;
311 uint32_t allow_swp:1;
314 uint32_t static_sq_wq:1;
315 uint32_t ts_format:2;
316 uint32_t user_index:24;
318 uint32_t packet_pacing_rate_limit_index:16;
319 uint32_t tis_lst_sz:16;
321 struct mlx5_devx_wq_attr wq_attr;
324 /* SQ attributes structure, used by SQ modify operation. */
325 struct mlx5_devx_modify_sq_attr {
328 uint32_t hairpin_peer_rq:24;
329 uint32_t hairpin_peer_vhca:16;
333 /* CQ attributes structure, used by CQ operations. */
334 struct mlx5_devx_cq_attr {
335 uint32_t q_umem_valid:1;
336 uint32_t db_umem_valid:1;
337 uint32_t use_first_only:1;
338 uint32_t overrun_ignore:1;
339 uint32_t cqe_comp_en:1;
340 uint32_t mini_cqe_res_format:2;
341 uint32_t mini_cqe_res_format_ext:2;
342 uint32_t log_cq_size:5;
343 uint32_t log_page_size:5;
344 uint32_t uar_page_id;
346 uint64_t q_umem_offset;
348 uint64_t db_umem_offset;
353 /* Virtq attributes structure, used by VIRTQ operations. */
354 struct mlx5_devx_virtq_attr {
355 uint16_t hw_available_index;
356 uint16_t hw_used_index;
359 uint32_t virtio_version_1_0:1;
364 uint32_t event_mode:3;
366 uint32_t hw_latency_mode:2;
367 uint32_t hw_max_latency_us:12;
368 uint32_t hw_max_pending_comp:16;
369 uint32_t dirty_bitmap_dump_enable:1;
370 uint32_t dirty_bitmap_mkey;
371 uint32_t dirty_bitmap_size;
374 uint32_t queue_index;
376 uint32_t counters_obj_id;
377 uint64_t dirty_bitmap_addr;
381 uint64_t available_addr;
391 struct mlx5_devx_qp_attr {
393 uint32_t uar_index:24;
395 uint32_t log_page_size:5;
396 uint32_t rq_size:17; /* Must be power of 2. */
397 uint32_t log_rq_stride:3;
398 uint32_t sq_size:17; /* Must be power of 2. */
399 uint32_t ts_format:2;
400 uint32_t dbr_umem_valid:1;
401 uint32_t dbr_umem_id;
402 uint64_t dbr_address;
404 uint64_t wq_umem_offset;
405 uint32_t user_index:24;
408 struct mlx5_devx_virtio_q_couners_attr {
409 uint64_t received_desc;
410 uint64_t completed_desc;
412 uint32_t bad_desc_errors;
413 uint32_t exceed_max_chain;
414 uint32_t invalid_buffer;
418 * graph flow match sample attributes structure,
419 * used by flex parser operations.
421 struct mlx5_devx_match_sample_attr {
422 uint32_t flow_match_sample_en:1;
423 uint32_t flow_match_sample_field_offset:16;
424 uint32_t flow_match_sample_offset_mode:4;
425 uint32_t flow_match_sample_field_offset_mask;
426 uint32_t flow_match_sample_field_offset_shift:4;
427 uint32_t flow_match_sample_field_base_offset:8;
428 uint32_t flow_match_sample_tunnel_mode:3;
429 uint32_t flow_match_sample_field_id;
432 /* graph node arc attributes structure, used by flex parser operations. */
433 struct mlx5_devx_graph_arc_attr {
434 uint32_t compare_condition_value:16;
435 uint32_t start_inner_tunnel:1;
436 uint32_t arc_parse_graph_node:8;
437 uint32_t parse_graph_node_handle;
440 /* Maximal number of samples per graph node. */
441 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8
443 /* Maximal number of input/output arcs per graph node. */
444 #define MLX5_GRAPH_NODE_ARC_NUM 8
446 /* parse graph node attributes structure, used by flex parser operations. */
447 struct mlx5_devx_graph_node_attr {
448 uint32_t modify_field_select;
449 uint32_t header_length_mode:4;
450 uint32_t header_length_base_value:16;
451 uint32_t header_length_field_shift:4;
452 uint32_t header_length_field_offset:16;
453 uint32_t header_length_field_mask;
454 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM];
455 uint32_t next_header_field_offset:16;
456 uint32_t next_header_field_size:5;
457 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM];
458 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM];
461 /* Encryption key size is up to 1024 bit, 128 bytes. */
462 #define MLX5_CRYPTO_KEY_MAX_SIZE 128
464 struct mlx5_devx_dek_attr {
466 uint32_t has_keytag:1;
467 uint32_t key_purpose:4;
470 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE];
473 struct mlx5_devx_import_kek_attr {
474 uint64_t modify_field_select;
477 uint8_t key[MLX5_CRYPTO_KEY_MAX_SIZE];
480 #define MLX5_CRYPTO_CREDENTIAL_SIZE 48
482 struct mlx5_devx_credential_attr {
483 uint64_t modify_field_select;
485 uint32_t credential_role:8;
486 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE];
489 struct mlx5_devx_crypto_login_attr {
490 uint64_t modify_field_select;
491 uint32_t credential_pointer:24;
492 uint32_t session_import_kek_ptr:24;
493 uint8_t credential[MLX5_CRYPTO_CREDENTIAL_SIZE];
496 /* mlx5_devx_cmds.c */
499 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx,
502 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
504 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
505 int clear, uint32_t n_counters,
506 uint64_t *pkts, uint64_t *bytes,
507 uint32_t mkey, void *addr,
511 int mlx5_devx_cmd_query_hca_attr(void *ctx,
512 struct mlx5_hca_attr *attr);
514 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx,
515 struct mlx5_devx_mkey_attr *attr);
517 int mlx5_devx_get_out_command_status(void *out);
519 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
522 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx,
523 struct mlx5_devx_create_rq_attr *rq_attr,
526 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
527 struct mlx5_devx_modify_rq_attr *rq_attr);
529 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx,
530 struct mlx5_devx_tir_attr *tir_attr);
532 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx,
533 struct mlx5_devx_rqt_attr *rqt_attr);
535 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx,
536 struct mlx5_devx_create_sq_attr *sq_attr);
538 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
539 struct mlx5_devx_modify_sq_attr *sq_attr);
541 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx,
542 struct mlx5_devx_tis_attr *tis_attr);
544 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx);
546 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain,
549 int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file);
551 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx,
552 struct mlx5_devx_cq_attr *attr);
554 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx,
555 struct mlx5_devx_virtq_attr *attr);
557 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
558 struct mlx5_devx_virtq_attr *attr);
560 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
561 struct mlx5_devx_virtq_attr *attr);
563 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx,
564 struct mlx5_devx_qp_attr *attr);
566 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,
567 uint32_t qp_st_mod_op, uint32_t remote_qp_id);
569 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
570 struct mlx5_devx_rqt_attr *rqt_attr);
572 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
573 struct mlx5_devx_modify_tir_attr *tir_attr);
575 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
576 uint32_t ids[], uint32_t num);
579 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx,
580 struct mlx5_devx_graph_node_attr *data);
583 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id,
584 uint32_t arg, uint32_t *data, uint32_t dw_cnt);
587 int mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id,
588 uint32_t arg, uint32_t *data, uint32_t dw_cnt);
591 struct mlx5_devx_obj *
592 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
593 uint16_t class, uint8_t type, uint8_t len);
596 * Create virtio queue counters object DevX API.
602 * The DevX object created, NULL otherwise and rte_errno is set.
605 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx);
608 * Query virtio queue counters object using DevX API.
610 * @param[in] couners_obj
611 * Pointer to virtq object structure.
612 * @param [in/out] attr
613 * Pointer to virtio queue counters attributes structure.
616 * 0 on success, a negative errno value otherwise and rte_errno is set.
619 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
620 struct mlx5_devx_virtio_q_couners_attr *attr);
622 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx,
625 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx);
628 int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id);
631 struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx);
633 int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
634 uint32_t *out_of_buffers);
636 struct mlx5_devx_obj *mlx5_devx_cmd_create_conn_track_offload_obj(void *ctx,
637 uint32_t pd, uint32_t log_obj_size);
640 * Create general object of type FLOW_METER_ASO using DevX API..
645 * PD value to associate the FLOW_METER_ASO object with.
646 * @param [in] log_obj_size
647 * log_obj_size define to allocate number of 2 * meters
648 * in one FLOW_METER_ASO object.
651 * The DevX object created, NULL otherwise and rte_errno is set.
654 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx,
655 uint32_t pd, uint32_t log_obj_size);
657 struct mlx5_devx_obj *
658 mlx5_devx_cmd_create_dek_obj(void *ctx, struct mlx5_devx_dek_attr *attr);
661 struct mlx5_devx_obj *
662 mlx5_devx_cmd_create_import_kek_obj(void *ctx,
663 struct mlx5_devx_import_kek_attr *attr);
666 struct mlx5_devx_obj *
667 mlx5_devx_cmd_create_credential_obj(void *ctx,
668 struct mlx5_devx_credential_attr *attr);
671 struct mlx5_devx_obj *
672 mlx5_devx_cmd_create_crypto_login_obj(void *ctx,
673 struct mlx5_devx_crypto_login_attr *attr);
675 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */