1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_
6 #define RTE_PMD_MLX5_DEVX_CMDS_H_
10 #include <rte_compat.h>
13 * Defines the amount of retries to allocate the first UAR in the page.
14 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
15 * UAR base address if UAR was not the first object in the UAR page.
16 * It caused the PMD failure and we should try to get another UAR
17 * till we get the first one with non-NULL base address returned.
19 #define MLX5_ALLOC_UAR_RETRY 32
21 /* This is limitation of libibverbs: in length variable type is u16. */
22 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \
23 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4))
25 struct mlx5_devx_mkey_attr {
30 uint32_t log_entity_size;
32 uint32_t relaxed_ordering_write:1;
33 uint32_t relaxed_ordering_read:1;
35 struct mlx5_klm *klm_array;
39 /* HCA qos attributes. */
40 struct mlx5_hca_qos_attr {
41 uint32_t sup:1; /* Whether QOS is supported. */
42 uint32_t flow_meter_old:1; /* Flow meter is supported, old version. */
43 uint32_t packet_pacing:1; /* Packet pacing is supported. */
44 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */
45 uint32_t flow_meter:1;
47 * Flow meter is supported, updated version.
48 * When flow_meter is 1, it indicates that REG_C sharing is supported.
49 * If flow_meter is 1, flow_meter_old is also 1.
50 * Using older driver versions, flow_meter_old can be 1
51 * while flow_meter is 0.
53 uint32_t flow_meter_aso_sup:1;
54 /* Whether FLOW_METER_ASO Object is supported. */
55 uint8_t log_max_flow_meter;
56 /* Power of the maximum supported meters. */
57 uint8_t flow_meter_reg_c_ids;
58 /* Bitmap of the reg_Cs available for flow meter to use. */
59 uint32_t log_meter_aso_granularity:5;
60 /* Power of the minimum allocation granularity Object. */
61 uint32_t log_meter_aso_max_alloc:5;
62 /* Power of the maximum allocation granularity Object. */
63 uint32_t log_max_num_meter_aso:5;
64 /* Power of the maximum number of supported objects. */
68 struct mlx5_hca_vdpa_attr {
69 uint8_t virtio_queue_type;
71 uint32_t desc_tunnel_offload_type:1;
72 uint32_t eth_frame_offload_type:1;
73 uint32_t virtio_version_1_0:1;
78 uint32_t event_mode:3;
79 uint32_t log_doorbell_stride:5;
80 uint32_t log_doorbell_bar_size:5;
81 uint32_t queue_counters_valid:1;
82 uint32_t max_num_virtio_queues;
87 uint64_t doorbell_bar_offset;
90 /* HCA supports this number of time periods for LRO. */
91 #define MLX5_LRO_NUM_SUPP_PERIODS 4
94 struct mlx5_hca_attr {
95 uint32_t eswitch_manager:1;
96 uint32_t flow_counters_dump:1;
97 uint32_t log_max_rqt_size:5;
98 uint32_t parse_graph_flex_node:1;
99 uint8_t flow_counter_bulk_alloc_bitmap;
100 uint32_t eth_net_offloads:1;
102 uint32_t wqe_vlan_insert:1;
103 uint32_t wqe_inline_mode:2;
104 uint32_t vport_inline_mode:3;
105 uint32_t tunnel_stateless_geneve_rx:1;
106 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
107 uint32_t tunnel_stateless_gtp:1;
109 uint32_t tunnel_lro_gre:1;
110 uint32_t tunnel_lro_vxlan:1;
111 uint32_t lro_max_msg_sz_mode:2;
112 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
113 uint16_t lro_min_mss_size;
114 uint32_t flex_parser_protocols;
115 uint32_t max_geneve_tlv_options;
116 uint32_t max_geneve_tlv_option_data_len;
118 uint32_t log_max_hairpin_queues:5;
119 uint32_t log_max_hairpin_wq_data_sz:5;
120 uint32_t log_max_hairpin_num_packets:5;
122 uint32_t relaxed_ordering_write:1;
123 uint32_t relaxed_ordering_read:1;
124 uint32_t access_register_user:1;
125 uint32_t wqe_index_ignore:1;
126 uint32_t cross_channel:1;
127 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */
128 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */
129 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */
130 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */
131 uint32_t scatter_fcs_w_decap_disable:1;
132 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */
134 uint32_t rq_ts_format:2;
135 uint32_t sq_ts_format:2;
136 uint32_t qp_ts_format:2;
138 uint32_t reg_c_preserve:1;
139 uint32_t crypto:1; /* Crypto engine is supported. */
140 uint32_t aes_xts:1; /* AES-XTS crypto is supported. */
141 uint32_t regexp_num_of_engines;
142 uint32_t log_max_ft_sampler_num:8;
143 uint32_t geneve_tlv_opt;
144 uint32_t cqe_compression:1;
145 uint32_t mini_cqe_resp_flow_tag:1;
146 uint32_t mini_cqe_resp_l3_l4_tag:1;
147 struct mlx5_hca_qos_attr qos;
148 struct mlx5_hca_vdpa_attr vdpa;
154 uint32_t log_max_mrw_sz;
155 uint32_t log_max_srq;
156 uint32_t log_max_srq_sz;
157 uint32_t rss_ind_tbl_cap;
158 uint32_t mmo_dma_en:1;
159 uint32_t mmo_compress_en:1;
160 uint32_t mmo_decompress_en:1;
161 uint32_t compress_min_block_size:4;
162 uint32_t log_max_mmo_dma:5;
163 uint32_t log_max_mmo_compress:5;
164 uint32_t log_max_mmo_decompress:5;
165 uint32_t umr_modify_entity_size_disabled:1;
166 uint32_t umr_indirect_mkey_disabled:1;
169 struct mlx5_devx_wq_attr {
171 uint32_t wq_signature:1;
172 uint32_t end_padding_mode:2;
174 uint32_t hds_skip_first_sge:1;
175 uint32_t log2_hds_buf_size:3;
176 uint32_t page_offset:5;
179 uint32_t uar_page:24;
183 uint32_t log_wq_stride:4;
184 uint32_t log_wq_pg_sz:5;
185 uint32_t log_wq_sz:5;
186 uint32_t dbr_umem_valid:1;
187 uint32_t wq_umem_valid:1;
188 uint32_t log_hairpin_num_packets:5;
189 uint32_t log_hairpin_data_sz:5;
190 uint32_t single_wqe_log_num_of_strides:4;
191 uint32_t two_byte_shift_en:1;
192 uint32_t single_stride_log_num_of_bytes:3;
193 uint32_t dbr_umem_id;
195 uint64_t wq_umem_offset;
198 /* Create RQ attributes structure, used by create RQ operation. */
199 struct mlx5_devx_create_rq_attr {
201 uint32_t delay_drop_en:1;
202 uint32_t scatter_fcs:1;
204 uint32_t mem_rq_type:4;
206 uint32_t flush_in_error_en:1;
208 uint32_t ts_format:2;
209 uint32_t user_index:24;
211 uint32_t counter_set_id:8;
213 struct mlx5_devx_wq_attr wq_attr;
216 /* Modify RQ attributes structure, used by modify RQ operation. */
217 struct mlx5_devx_modify_rq_attr {
219 uint32_t rq_state:4; /* Current RQ state. */
220 uint32_t state:4; /* Required RQ state. */
221 uint32_t scatter_fcs:1;
223 uint32_t counter_set_id:8;
224 uint32_t hairpin_peer_sq:24;
225 uint32_t hairpin_peer_vhca:16;
226 uint64_t modify_bitmask;
227 uint32_t lwm:16; /* Contained WQ lwm. */
230 struct mlx5_rx_hash_field_select {
231 uint32_t l3_prot_type:1;
232 uint32_t l4_prot_type:1;
233 uint32_t selected_fields:30;
236 /* TIR attributes structure, used by TIR operations. */
237 struct mlx5_devx_tir_attr {
238 uint32_t disp_type:4;
239 uint32_t lro_timeout_period_usecs:16;
240 uint32_t lro_enable_mask:4;
241 uint32_t lro_max_msg_sz:8;
242 uint32_t inline_rqn:24;
243 uint32_t rx_hash_symmetric:1;
244 uint32_t tunneled_offload_en:1;
245 uint32_t indirect_table:24;
246 uint32_t rx_hash_fn:4;
247 uint32_t self_lb_block:2;
248 uint32_t transport_domain:24;
249 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN];
250 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
251 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
254 /* TIR attributes structure, used by TIR modify. */
255 struct mlx5_devx_modify_tir_attr {
257 uint64_t modify_bitmask;
258 struct mlx5_devx_tir_attr tir;
261 /* RQT attributes structure, used by RQT operations. */
262 struct mlx5_devx_rqt_attr {
264 uint32_t rqt_max_size:16;
265 uint32_t rqt_actual_size:16;
269 /* TIS attributes structure. */
270 struct mlx5_devx_tis_attr {
271 uint32_t strict_lag_tx_port_affinity:1;
273 uint32_t lag_tx_port_affinity:4;
275 uint32_t transport_domain:24;
278 /* SQ attributes structure, used by SQ create operation. */
279 struct mlx5_devx_create_sq_attr {
281 uint32_t cd_master:1;
283 uint32_t flush_in_error_en:1;
284 uint32_t allow_multi_pkt_send_wqe:1;
285 uint32_t min_wqe_inline_mode:3;
288 uint32_t allow_swp:1;
291 uint32_t static_sq_wq:1;
292 uint32_t ts_format:2;
293 uint32_t user_index:24;
295 uint32_t packet_pacing_rate_limit_index:16;
296 uint32_t tis_lst_sz:16;
298 struct mlx5_devx_wq_attr wq_attr;
301 /* SQ attributes structure, used by SQ modify operation. */
302 struct mlx5_devx_modify_sq_attr {
305 uint32_t hairpin_peer_rq:24;
306 uint32_t hairpin_peer_vhca:16;
310 /* CQ attributes structure, used by CQ operations. */
311 struct mlx5_devx_cq_attr {
312 uint32_t q_umem_valid:1;
313 uint32_t db_umem_valid:1;
314 uint32_t use_first_only:1;
315 uint32_t overrun_ignore:1;
316 uint32_t cqe_comp_en:1;
317 uint32_t mini_cqe_res_format:2;
318 uint32_t mini_cqe_res_format_ext:2;
319 uint32_t log_cq_size:5;
320 uint32_t log_page_size:5;
321 uint32_t uar_page_id;
323 uint64_t q_umem_offset;
325 uint64_t db_umem_offset;
330 /* Virtq attributes structure, used by VIRTQ operations. */
331 struct mlx5_devx_virtq_attr {
332 uint16_t hw_available_index;
333 uint16_t hw_used_index;
336 uint32_t virtio_version_1_0:1;
341 uint32_t event_mode:3;
343 uint32_t hw_latency_mode:2;
344 uint32_t hw_max_latency_us:12;
345 uint32_t hw_max_pending_comp:16;
346 uint32_t dirty_bitmap_dump_enable:1;
347 uint32_t dirty_bitmap_mkey;
348 uint32_t dirty_bitmap_size;
351 uint32_t queue_index;
353 uint32_t counters_obj_id;
354 uint64_t dirty_bitmap_addr;
358 uint64_t available_addr;
368 struct mlx5_devx_qp_attr {
370 uint32_t uar_index:24;
372 uint32_t log_page_size:5;
373 uint32_t rq_size:17; /* Must be power of 2. */
374 uint32_t log_rq_stride:3;
375 uint32_t sq_size:17; /* Must be power of 2. */
376 uint32_t ts_format:2;
377 uint32_t dbr_umem_valid:1;
378 uint32_t dbr_umem_id;
379 uint64_t dbr_address;
381 uint64_t wq_umem_offset;
384 struct mlx5_devx_virtio_q_couners_attr {
385 uint64_t received_desc;
386 uint64_t completed_desc;
388 uint32_t bad_desc_errors;
389 uint32_t exceed_max_chain;
390 uint32_t invalid_buffer;
394 * graph flow match sample attributes structure,
395 * used by flex parser operations.
397 struct mlx5_devx_match_sample_attr {
398 uint32_t flow_match_sample_en:1;
399 uint32_t flow_match_sample_field_offset:16;
400 uint32_t flow_match_sample_offset_mode:4;
401 uint32_t flow_match_sample_field_offset_mask;
402 uint32_t flow_match_sample_field_offset_shift:4;
403 uint32_t flow_match_sample_field_base_offset:8;
404 uint32_t flow_match_sample_tunnel_mode:3;
405 uint32_t flow_match_sample_field_id;
408 /* graph node arc attributes structure, used by flex parser operations. */
409 struct mlx5_devx_graph_arc_attr {
410 uint32_t compare_condition_value:16;
411 uint32_t start_inner_tunnel:1;
412 uint32_t arc_parse_graph_node:8;
413 uint32_t parse_graph_node_handle;
416 /* Maximal number of samples per graph node. */
417 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8
419 /* Maximal number of input/output arcs per graph node. */
420 #define MLX5_GRAPH_NODE_ARC_NUM 8
422 /* parse graph node attributes structure, used by flex parser operations. */
423 struct mlx5_devx_graph_node_attr {
424 uint32_t modify_field_select;
425 uint32_t header_length_mode:4;
426 uint32_t header_length_base_value:16;
427 uint32_t header_length_field_shift:4;
428 uint32_t header_length_field_offset:16;
429 uint32_t header_length_field_mask;
430 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM];
431 uint32_t next_header_field_offset:16;
432 uint32_t next_header_field_size:5;
433 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM];
434 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM];
437 /* mlx5_devx_cmds.c */
440 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx,
443 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
445 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
446 int clear, uint32_t n_counters,
447 uint64_t *pkts, uint64_t *bytes,
448 uint32_t mkey, void *addr,
452 int mlx5_devx_cmd_query_hca_attr(void *ctx,
453 struct mlx5_hca_attr *attr);
455 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx,
456 struct mlx5_devx_mkey_attr *attr);
458 int mlx5_devx_get_out_command_status(void *out);
460 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
463 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx,
464 struct mlx5_devx_create_rq_attr *rq_attr,
467 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
468 struct mlx5_devx_modify_rq_attr *rq_attr);
470 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx,
471 struct mlx5_devx_tir_attr *tir_attr);
473 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx,
474 struct mlx5_devx_rqt_attr *rqt_attr);
476 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx,
477 struct mlx5_devx_create_sq_attr *sq_attr);
479 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
480 struct mlx5_devx_modify_sq_attr *sq_attr);
482 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx,
483 struct mlx5_devx_tis_attr *tis_attr);
485 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx);
487 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain,
490 int mlx5_devx_cmd_flow_single_dump(void *rule, FILE *file);
492 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx,
493 struct mlx5_devx_cq_attr *attr);
495 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx,
496 struct mlx5_devx_virtq_attr *attr);
498 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
499 struct mlx5_devx_virtq_attr *attr);
501 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
502 struct mlx5_devx_virtq_attr *attr);
504 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx,
505 struct mlx5_devx_qp_attr *attr);
507 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,
508 uint32_t qp_st_mod_op, uint32_t remote_qp_id);
510 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
511 struct mlx5_devx_rqt_attr *rqt_attr);
513 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
514 struct mlx5_devx_modify_tir_attr *tir_attr);
516 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
517 uint32_t ids[], uint32_t num);
520 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx,
521 struct mlx5_devx_graph_node_attr *data);
524 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id,
525 uint32_t arg, uint32_t *data, uint32_t dw_cnt);
528 struct mlx5_devx_obj *
529 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
530 uint16_t class, uint8_t type, uint8_t len);
533 * Create virtio queue counters object DevX API.
539 * The DevX object created, NULL otherwise and rte_errno is set.
542 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx);
545 * Query virtio queue counters object using DevX API.
547 * @param[in] couners_obj
548 * Pointer to virtq object structure.
549 * @param [in/out] attr
550 * Pointer to virtio queue counters attributes structure.
553 * 0 on success, a negative errno value otherwise and rte_errno is set.
556 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
557 struct mlx5_devx_virtio_q_couners_attr *attr);
559 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx,
562 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx);
565 int mlx5_devx_cmd_wq_query(void *wq, uint32_t *counter_set_id);
568 struct mlx5_devx_obj *mlx5_devx_cmd_queue_counter_alloc(void *ctx);
570 int mlx5_devx_cmd_queue_counter_query(struct mlx5_devx_obj *dcs, int clear,
571 uint32_t *out_of_buffers);
573 * Create general object of type FLOW_METER_ASO using DevX API..
578 * PD value to associate the FLOW_METER_ASO object with.
579 * @param [in] log_obj_size
580 * log_obj_size define to allocate number of 2 * meters
581 * in one FLOW_METER_ASO object.
584 * The DevX object created, NULL otherwise and rte_errno is set.
587 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_meter_aso_obj(void *ctx,
588 uint32_t pd, uint32_t log_obj_size);
589 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */