1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_
6 #define RTE_PMD_MLX5_DEVX_CMDS_H_
10 #include <rte_compat.h>
13 * Defines the amount of retries to allocate the first UAR in the page.
14 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as
15 * UAR base address if UAR was not the first object in the UAR page.
16 * It caused the PMD failure and we should try to get another UAR
17 * till we get the first one with non-NULL base address returned.
19 #define MLX5_ALLOC_UAR_RETRY 32
21 /* This is limitation of libibverbs: in length variable type is u16. */
22 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \
23 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4))
25 struct mlx5_devx_mkey_attr {
30 uint32_t log_entity_size;
32 uint32_t relaxed_ordering_write:1;
33 uint32_t relaxed_ordering_read:1;
34 struct mlx5_klm *klm_array;
38 /* HCA qos attributes. */
39 struct mlx5_hca_qos_attr {
40 uint32_t sup:1; /* Whether QOS is supported. */
41 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */
42 uint32_t packet_pacing:1; /* Packet pacing is supported. */
43 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */
44 uint32_t flow_meter_reg_share:1;
45 /* Whether reg_c share is supported. */
46 uint8_t log_max_flow_meter;
47 /* Power of the maximum supported meters. */
48 uint8_t flow_meter_reg_c_ids;
49 /* Bitmap of the reg_Cs available for flow meter to use. */
53 struct mlx5_hca_vdpa_attr {
54 uint8_t virtio_queue_type;
56 uint32_t desc_tunnel_offload_type:1;
57 uint32_t eth_frame_offload_type:1;
58 uint32_t virtio_version_1_0:1;
63 uint32_t event_mode:3;
64 uint32_t log_doorbell_stride:5;
65 uint32_t log_doorbell_bar_size:5;
66 uint32_t queue_counters_valid:1;
67 uint32_t max_num_virtio_queues;
72 uint64_t doorbell_bar_offset;
75 /* HCA supports this number of time periods for LRO. */
76 #define MLX5_LRO_NUM_SUPP_PERIODS 4
79 struct mlx5_hca_attr {
80 uint32_t eswitch_manager:1;
81 uint32_t flow_counters_dump:1;
82 uint32_t log_max_rqt_size:5;
83 uint32_t parse_graph_flex_node:1;
84 uint8_t flow_counter_bulk_alloc_bitmap;
85 uint32_t eth_net_offloads:1;
87 uint32_t wqe_vlan_insert:1;
88 uint32_t wqe_inline_mode:2;
89 uint32_t vport_inline_mode:3;
90 uint32_t tunnel_stateless_geneve_rx:1;
91 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
92 uint32_t tunnel_stateless_gtp:1;
94 uint32_t tunnel_lro_gre:1;
95 uint32_t tunnel_lro_vxlan:1;
96 uint32_t lro_max_msg_sz_mode:2;
97 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
98 uint16_t lro_min_mss_size;
99 uint32_t flex_parser_protocols;
100 uint32_t max_geneve_tlv_options;
101 uint32_t max_geneve_tlv_option_data_len;
103 uint32_t log_max_hairpin_queues:5;
104 uint32_t log_max_hairpin_wq_data_sz:5;
105 uint32_t log_max_hairpin_num_packets:5;
107 uint32_t relaxed_ordering_write:1;
108 uint32_t relaxed_ordering_read:1;
109 uint32_t access_register_user:1;
110 uint32_t wqe_index_ignore:1;
111 uint32_t cross_channel:1;
112 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */
113 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */
114 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */
115 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */
116 uint32_t scatter_fcs_w_decap_disable:1;
117 uint32_t flow_hit_aso:1; /* General obj type FLOW_HIT_ASO supported. */
119 uint32_t reg_c_preserve:1;
120 uint32_t regexp_num_of_engines;
121 uint32_t log_max_ft_sampler_num:8;
122 uint32_t geneve_tlv_opt;
123 struct mlx5_hca_qos_attr qos;
124 struct mlx5_hca_vdpa_attr vdpa;
130 uint32_t log_max_mrw_sz;
131 uint32_t log_max_srq;
132 uint32_t log_max_srq_sz;
133 uint32_t rss_ind_tbl_cap;
134 uint32_t mmo_dma_en:1;
135 uint32_t mmo_compress_en:1;
136 uint32_t mmo_decompress_en:1;
137 uint32_t compress_min_block_size:4;
138 uint32_t log_max_mmo_dma:5;
139 uint32_t log_max_mmo_compress:5;
140 uint32_t log_max_mmo_decompress:5;
143 struct mlx5_devx_wq_attr {
145 uint32_t wq_signature:1;
146 uint32_t end_padding_mode:2;
148 uint32_t hds_skip_first_sge:1;
149 uint32_t log2_hds_buf_size:3;
150 uint32_t page_offset:5;
153 uint32_t uar_page:24;
157 uint32_t log_wq_stride:4;
158 uint32_t log_wq_pg_sz:5;
159 uint32_t log_wq_sz:5;
160 uint32_t dbr_umem_valid:1;
161 uint32_t wq_umem_valid:1;
162 uint32_t log_hairpin_num_packets:5;
163 uint32_t log_hairpin_data_sz:5;
164 uint32_t single_wqe_log_num_of_strides:4;
165 uint32_t two_byte_shift_en:1;
166 uint32_t single_stride_log_num_of_bytes:3;
167 uint32_t dbr_umem_id;
169 uint64_t wq_umem_offset;
172 /* Create RQ attributes structure, used by create RQ operation. */
173 struct mlx5_devx_create_rq_attr {
175 uint32_t delay_drop_en:1;
176 uint32_t scatter_fcs:1;
178 uint32_t mem_rq_type:4;
180 uint32_t flush_in_error_en:1;
182 uint32_t user_index:24;
184 uint32_t counter_set_id:8;
186 struct mlx5_devx_wq_attr wq_attr;
189 /* Modify RQ attributes structure, used by modify RQ operation. */
190 struct mlx5_devx_modify_rq_attr {
192 uint32_t rq_state:4; /* Current RQ state. */
193 uint32_t state:4; /* Required RQ state. */
194 uint32_t scatter_fcs:1;
196 uint32_t counter_set_id:8;
197 uint32_t hairpin_peer_sq:24;
198 uint32_t hairpin_peer_vhca:16;
199 uint64_t modify_bitmask;
200 uint32_t lwm:16; /* Contained WQ lwm. */
203 struct mlx5_rx_hash_field_select {
204 uint32_t l3_prot_type:1;
205 uint32_t l4_prot_type:1;
206 uint32_t selected_fields:30;
209 /* TIR attributes structure, used by TIR operations. */
210 struct mlx5_devx_tir_attr {
211 uint32_t disp_type:4;
212 uint32_t lro_timeout_period_usecs:16;
213 uint32_t lro_enable_mask:4;
214 uint32_t lro_max_msg_sz:8;
215 uint32_t inline_rqn:24;
216 uint32_t rx_hash_symmetric:1;
217 uint32_t tunneled_offload_en:1;
218 uint32_t indirect_table:24;
219 uint32_t rx_hash_fn:4;
220 uint32_t self_lb_block:2;
221 uint32_t transport_domain:24;
222 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN];
223 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
224 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
227 /* TIR attributes structure, used by TIR modify. */
228 struct mlx5_devx_modify_tir_attr {
230 uint64_t modify_bitmask;
231 struct mlx5_devx_tir_attr tir;
234 /* RQT attributes structure, used by RQT operations. */
235 struct mlx5_devx_rqt_attr {
237 uint32_t rqt_max_size:16;
238 uint32_t rqt_actual_size:16;
242 /* TIS attributes structure. */
243 struct mlx5_devx_tis_attr {
244 uint32_t strict_lag_tx_port_affinity:1;
246 uint32_t lag_tx_port_affinity:4;
248 uint32_t transport_domain:24;
251 /* SQ attributes structure, used by SQ create operation. */
252 struct mlx5_devx_create_sq_attr {
254 uint32_t cd_master:1;
256 uint32_t flush_in_error_en:1;
257 uint32_t allow_multi_pkt_send_wqe:1;
258 uint32_t min_wqe_inline_mode:3;
261 uint32_t allow_swp:1;
264 uint32_t static_sq_wq:1;
265 uint32_t user_index:24;
267 uint32_t packet_pacing_rate_limit_index:16;
268 uint32_t tis_lst_sz:16;
270 struct mlx5_devx_wq_attr wq_attr;
273 /* SQ attributes structure, used by SQ modify operation. */
274 struct mlx5_devx_modify_sq_attr {
277 uint32_t hairpin_peer_rq:24;
278 uint32_t hairpin_peer_vhca:16;
282 /* CQ attributes structure, used by CQ operations. */
283 struct mlx5_devx_cq_attr {
284 uint32_t q_umem_valid:1;
285 uint32_t db_umem_valid:1;
286 uint32_t use_first_only:1;
287 uint32_t overrun_ignore:1;
288 uint32_t cqe_comp_en:1;
289 uint32_t mini_cqe_res_format:2;
290 uint32_t mini_cqe_res_format_ext:2;
291 uint32_t log_cq_size:5;
292 uint32_t log_page_size:5;
293 uint32_t uar_page_id;
295 uint64_t q_umem_offset;
297 uint64_t db_umem_offset;
302 /* Virtq attributes structure, used by VIRTQ operations. */
303 struct mlx5_devx_virtq_attr {
304 uint16_t hw_available_index;
305 uint16_t hw_used_index;
308 uint32_t virtio_version_1_0:1;
313 uint32_t event_mode:3;
315 uint32_t hw_latency_mode:2;
316 uint32_t hw_max_latency_us:12;
317 uint32_t hw_max_pending_comp:16;
318 uint32_t dirty_bitmap_dump_enable:1;
319 uint32_t dirty_bitmap_mkey;
320 uint32_t dirty_bitmap_size;
323 uint32_t queue_index;
325 uint32_t counters_obj_id;
326 uint64_t dirty_bitmap_addr;
330 uint64_t available_addr;
340 struct mlx5_devx_qp_attr {
342 uint32_t uar_index:24;
344 uint32_t log_page_size:5;
345 uint32_t rq_size:17; /* Must be power of 2. */
346 uint32_t log_rq_stride:3;
347 uint32_t sq_size:17; /* Must be power of 2. */
348 uint32_t dbr_umem_valid:1;
349 uint32_t dbr_umem_id;
350 uint64_t dbr_address;
352 uint64_t wq_umem_offset;
355 struct mlx5_devx_virtio_q_couners_attr {
356 uint64_t received_desc;
357 uint64_t completed_desc;
359 uint32_t bad_desc_errors;
360 uint32_t exceed_max_chain;
361 uint32_t invalid_buffer;
365 * graph flow match sample attributes structure,
366 * used by flex parser operations.
368 struct mlx5_devx_match_sample_attr {
369 uint32_t flow_match_sample_en:1;
370 uint32_t flow_match_sample_field_offset:16;
371 uint32_t flow_match_sample_offset_mode:4;
372 uint32_t flow_match_sample_field_offset_mask;
373 uint32_t flow_match_sample_field_offset_shift:4;
374 uint32_t flow_match_sample_field_base_offset:8;
375 uint32_t flow_match_sample_tunnel_mode:3;
376 uint32_t flow_match_sample_field_id;
379 /* graph node arc attributes structure, used by flex parser operations. */
380 struct mlx5_devx_graph_arc_attr {
381 uint32_t compare_condition_value:16;
382 uint32_t start_inner_tunnel:1;
383 uint32_t arc_parse_graph_node:8;
384 uint32_t parse_graph_node_handle;
387 /* Maximal number of samples per graph node. */
388 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8
390 /* Maximal number of input/output arcs per graph node. */
391 #define MLX5_GRAPH_NODE_ARC_NUM 8
393 /* parse graph node attributes structure, used by flex parser operations. */
394 struct mlx5_devx_graph_node_attr {
395 uint32_t modify_field_select;
396 uint32_t header_length_mode:4;
397 uint32_t header_length_base_value:16;
398 uint32_t header_length_field_shift:4;
399 uint32_t header_length_field_offset:16;
400 uint32_t header_length_field_mask;
401 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM];
402 uint32_t next_header_field_offset:16;
403 uint32_t next_header_field_size:5;
404 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM];
405 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM];
408 /* mlx5_devx_cmds.c */
411 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx,
414 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
416 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
417 int clear, uint32_t n_counters,
418 uint64_t *pkts, uint64_t *bytes,
419 uint32_t mkey, void *addr,
423 int mlx5_devx_cmd_query_hca_attr(void *ctx,
424 struct mlx5_hca_attr *attr);
426 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx,
427 struct mlx5_devx_mkey_attr *attr);
429 int mlx5_devx_get_out_command_status(void *out);
431 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
434 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx,
435 struct mlx5_devx_create_rq_attr *rq_attr,
438 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
439 struct mlx5_devx_modify_rq_attr *rq_attr);
441 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx,
442 struct mlx5_devx_tir_attr *tir_attr);
444 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx,
445 struct mlx5_devx_rqt_attr *rqt_attr);
447 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx,
448 struct mlx5_devx_create_sq_attr *sq_attr);
450 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
451 struct mlx5_devx_modify_sq_attr *sq_attr);
453 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx,
454 struct mlx5_devx_tis_attr *tis_attr);
456 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx);
458 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain,
461 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx,
462 struct mlx5_devx_cq_attr *attr);
464 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx,
465 struct mlx5_devx_virtq_attr *attr);
467 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
468 struct mlx5_devx_virtq_attr *attr);
470 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
471 struct mlx5_devx_virtq_attr *attr);
473 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx,
474 struct mlx5_devx_qp_attr *attr);
476 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,
477 uint32_t qp_st_mod_op, uint32_t remote_qp_id);
479 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
480 struct mlx5_devx_rqt_attr *rqt_attr);
482 int mlx5_devx_cmd_modify_tir(struct mlx5_devx_obj *tir,
483 struct mlx5_devx_modify_tir_attr *tir_attr);
485 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
486 uint32_t ids[], uint32_t num);
489 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx,
490 struct mlx5_devx_graph_node_attr *data);
493 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id,
494 uint32_t arg, uint32_t *data, uint32_t dw_cnt);
497 struct mlx5_devx_obj *
498 mlx5_devx_cmd_create_geneve_tlv_option(void *ctx,
499 uint16_t class, uint8_t type, uint8_t len);
502 * Create virtio queue counters object DevX API.
508 * The DevX object created, NULL otherwise and rte_errno is set.
511 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx);
514 * Query virtio queue counters object using DevX API.
516 * @param[in] couners_obj
517 * Pointer to virtq object structure.
518 * @param [in/out] attr
519 * Pointer to virtio queue counters attributes structure.
522 * 0 on success, a negative errno value otherwise and rte_errno is set.
525 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
526 struct mlx5_devx_virtio_q_couners_attr *attr);
528 struct mlx5_devx_obj *mlx5_devx_cmd_create_flow_hit_aso_obj(void *ctx,
532 struct mlx5_devx_obj *mlx5_devx_cmd_alloc_pd(void *ctx);
533 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */