1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2016 6WIND S.A.
3 * Copyright 2016 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_PRM_H_
7 #define RTE_PMD_MLX5_PRM_H_
12 #include <rte_byteorder.h>
14 #include <mlx5_glue.h>
15 #include "mlx5_autoconf.h"
17 /* RSS hash key size. */
18 #define MLX5_RSS_HASH_KEY_LEN 40
20 /* Get CQE owner bit. */
21 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
24 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
27 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
29 /* Get CQE solicited event. */
30 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
32 /* Invalidate a CQE. */
33 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
35 /* Hardware index widths. */
36 #define MLX5_CQ_INDEX_WIDTH 24
37 #define MLX5_WQ_INDEX_WIDTH 16
39 /* WQE Segment sizes in bytes. */
40 #define MLX5_WSEG_SIZE 16u
41 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
42 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
43 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
45 /* WQE/WQEBB size in bytes. */
46 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
49 * Max size of a WQE session.
50 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
51 * the WQE size field in Control Segment is 6 bits wide.
53 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
56 * Default minimum number of Tx queues for inlining packets.
57 * If there are less queues as specified we assume we have
58 * no enough CPU resources (cycles) to perform inlining,
59 * the PCIe throughput is not supposed as bottleneck and
60 * inlining is disabled.
62 #define MLX5_INLINE_MAX_TXQS 8u
63 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
66 * Default packet length threshold to be inlined with
67 * enhanced MPW. If packet length exceeds the threshold
68 * the data are not inlined. Should be aligned in WQEBB
69 * boundary with accounting the title Control and Ethernet
72 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
73 MLX5_DSEG_MIN_INLINE_SIZE)
75 * Maximal inline data length sent with enhanced MPW.
76 * Is based on maximal WQE size.
78 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
79 MLX5_WQE_CSEG_SIZE - \
80 MLX5_WQE_ESEG_SIZE - \
81 MLX5_WQE_DSEG_SIZE + \
82 MLX5_DSEG_MIN_INLINE_SIZE)
84 * Minimal amount of packets to be sent with EMPW.
85 * This limits the minimal required size of sent EMPW.
86 * If there are no enough resources to built minimal
87 * EMPW the sending loop exits.
89 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
91 * Maximal amount of packets to be sent with EMPW.
92 * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
93 * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
94 * without CQE generation request, being multiplied by
95 * MLX5_TX_COMP_MAX_CQE it may cause significant latency
96 * in tx burst routine at the moment of freeing multiple mbufs.
98 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
99 #define MLX5_MPW_MAX_PACKETS 6
100 #define MLX5_MPW_INLINE_MAX_PACKETS 6
103 * Default packet length threshold to be inlined with
104 * ordinary SEND. Inlining saves the MR key search
105 * and extra PCIe data fetch transaction, but eats the
108 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
109 MLX5_ESEG_MIN_INLINE_SIZE - \
110 MLX5_WQE_CSEG_SIZE - \
111 MLX5_WQE_ESEG_SIZE - \
114 * Maximal inline data length sent with ordinary SEND.
115 * Is based on maximal WQE size.
117 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
118 MLX5_WQE_CSEG_SIZE - \
119 MLX5_WQE_ESEG_SIZE - \
120 MLX5_WQE_DSEG_SIZE + \
121 MLX5_ESEG_MIN_INLINE_SIZE)
123 /* Missed in mlx5dv.h, should define here. */
124 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW
125 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
128 #ifndef HAVE_MLX5_OPCODE_SEND_EN
129 #define MLX5_OPCODE_SEND_EN 0x17u
132 #ifndef HAVE_MLX5_OPCODE_WAIT
133 #define MLX5_OPCODE_WAIT 0x0fu
136 #ifndef HAVE_MLX5_OPCODE_ACCESS_ASO
137 #define MLX5_OPCODE_ACCESS_ASO 0x2du
140 /* CQE value to inform that VLAN is stripped. */
141 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
144 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
147 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
150 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
153 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
156 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
158 /* IP is fragmented. */
159 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
161 /* L2 header is valid. */
162 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
164 /* L3 header is valid. */
165 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
167 /* L4 header is valid. */
168 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
170 /* Outer packet, 0 IPv4, 1 IPv6. */
171 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
173 /* Tunnel packet bit in the CQE. */
174 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
176 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
177 #define MLX5_CQE_LRO_PUSH_MASK 0x40
179 /* Mask for L4 type in the CQE hdr_type_etc field. */
180 #define MLX5_CQE_L4_TYPE_MASK 0x70
182 /* The bit index of L4 type in CQE hdr_type_etc field. */
183 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
185 /* L4 type to indicate TCP packet without acknowledgment. */
186 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
188 /* L4 type to indicate TCP packet with acknowledgment. */
189 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
191 /* Inner L3 checksum offload (Tunneled packets only). */
192 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
194 /* Inner L4 checksum offload (Tunneled packets only). */
195 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
197 /* Outer L4 type is TCP. */
198 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5)
200 /* Outer L4 type is UDP. */
201 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5)
203 /* Outer L3 type is IPV4. */
204 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
206 /* Outer L3 type is IPV6. */
207 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
209 /* Inner L4 type is TCP. */
210 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
212 /* Inner L4 type is UDP. */
213 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
215 /* Inner L3 type is IPV4. */
216 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
218 /* Inner L3 type is IPV6. */
219 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
221 /* VLAN insertion flag. */
222 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
224 /* Data inline segment flag. */
225 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
227 /* Is flow mark valid. */
228 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
229 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
231 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
234 /* INVALID is used by packets matching no flow rules. */
235 #define MLX5_FLOW_MARK_INVALID 0
237 /* Maximum allowed value to mark a packet. */
238 #define MLX5_FLOW_MARK_MAX 0xfffff0
240 /* Default mark value used when none is provided. */
241 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
243 /* Default mark mask for metadata legacy mode. */
244 #define MLX5_FLOW_MARK_MASK 0xffffff
246 /* Byte length mask when mark is enable in miniCQE */
247 #define MLX5_LEN_WITH_MARK_MASK 0xffffff00
249 /* Maximum number of DS in WQE. Limited by 6-bit field. */
250 #define MLX5_DSEG_MAX 63
252 /* The completion mode offset in the WQE control segment line 2. */
253 #define MLX5_COMP_MODE_OFFSET 2
255 /* Amount of data bytes in minimal inline data segment. */
256 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
258 /* Amount of data bytes in minimal inline eth segment. */
259 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
261 /* Amount of data bytes after eth data segment. */
262 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
264 /* The maximum log value of segments per RQ WQE. */
265 #define MLX5_MAX_LOG_RQ_SEGS 5u
267 /* The alignment needed for WQ buffer. */
268 #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size()
270 /* The alignment needed for CQ buffer. */
271 #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size()
273 /* Completion mode. */
274 enum mlx5_completion_mode {
275 MLX5_COMP_ONLY_ERR = 0x0,
276 MLX5_COMP_ONLY_FIRST_ERR = 0x1,
277 MLX5_COMP_ALWAYS = 0x2,
278 MLX5_COMP_CQE_AND_EQE = 0x3,
285 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
288 /* WQE Control segment. */
289 struct mlx5_wqe_cseg {
294 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
297 * WQE CSEG opcode field size is 32 bits, divided:
299 * Bits 23:8 wqe_index
302 #define WQE_CSEG_OPC_MOD_OFFSET 24
303 #define WQE_CSEG_WQE_INDEX_OFFSET 8
305 /* Header of data segment. Minimal size Data Segment */
306 struct mlx5_wqe_dseg {
309 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
317 /* Subset of struct WQE Ethernet Segment. */
318 struct mlx5_wqe_eseg {
326 uint16_t inline_hdr_sz;
328 uint16_t inline_data;
335 uint32_t flow_metadata;
341 struct mlx5_wqe_qseg {
348 /* The title WQEBB, header of WQE. */
351 struct mlx5_wqe_cseg cseg;
354 struct mlx5_wqe_eseg eseg;
356 struct mlx5_wqe_dseg dseg[2];
357 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
361 /* WQE for Multi-Packet RQ. */
362 struct mlx5_wqe_mprq {
363 struct mlx5_wqe_srq_next_seg next_seg;
364 struct mlx5_wqe_data_seg dseg;
367 #define MLX5_MPRQ_LEN_MASK 0x000ffff
368 #define MLX5_MPRQ_LEN_SHIFT 0
369 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
370 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
371 #define MLX5_MPRQ_FILLER_MASK 0x80000000
372 #define MLX5_MPRQ_FILLER_SHIFT 31
374 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
376 /* CQ element structure - should be equal to the cache line size */
378 #if (RTE_CACHE_LINE_SIZE == 128)
384 uint8_t lro_tcppsh_abort_dupack;
386 uint16_t lro_tcp_win;
387 uint32_t lro_ack_seq_num;
388 uint32_t rx_hash_res;
389 uint8_t rx_hash_type;
393 uint16_t hdr_type_etc;
397 uint32_t flow_table_metadata;
401 uint32_t sop_drop_qpn;
402 uint16_t wqe_counter;
409 uint32_t sop_drop_qpn;
410 uint16_t wqe_counter;
415 struct mlx5_wqe_rseg {
421 #define MLX5_UMRC_IF_OFFSET 31u
422 #define MLX5_UMRC_KO_OFFSET 16u
423 #define MLX5_UMRC_TO_BS_OFFSET 0u
425 struct mlx5_wqe_umr_cseg {
426 uint32_t if_cf_toe_cq_res;
432 struct mlx5_wqe_mkey_cseg {
433 uint32_t fr_res_af_sf;
439 uint32_t bsf_octword_size;
440 uint32_t reserved3[4];
441 uint32_t translations_octword_size;
447 MLX5_BSF_SIZE_16B = 0x0,
448 MLX5_BSF_SIZE_32B = 0x1,
449 MLX5_BSF_SIZE_64B = 0x2,
450 MLX5_BSF_SIZE_128B = 0x3,
454 MLX5_BSF_P_TYPE_SIGNATURE = 0x0,
455 MLX5_BSF_P_TYPE_CRYPTO = 0x1,
459 MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0,
460 MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1,
461 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2,
462 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3,
466 MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0,
470 MLX5_BLOCK_SIZE_512B = 0x1,
471 MLX5_BLOCK_SIZE_520B = 0x2,
472 MLX5_BLOCK_SIZE_4096B = 0x3,
473 MLX5_BLOCK_SIZE_4160B = 0x4,
474 MLX5_BLOCK_SIZE_1MB = 0x5,
475 MLX5_BLOCK_SIZE_4048B = 0x6,
478 #define MLX5_BSF_SIZE_OFFSET 30
479 #define MLX5_BSF_P_TYPE_OFFSET 24
480 #define MLX5_ENCRYPTION_ORDER_OFFSET 16
481 #define MLX5_BLOCK_SIZE_OFFSET 24
483 struct mlx5_wqe_umr_bsf_seg {
485 * bs_bpt_eo_es contains:
486 * bs bsf_size 2 bits at MLX5_BSF_SIZE_OFFSET
487 * bpt bsf_p_type 2 bits at MLX5_BSF_P_TYPE_OFFSET
488 * eo encryption_order 4 bits at MLX5_ENCRYPTION_ORDER_OFFSET
489 * es encryption_standard 4 bits at offset 0
491 uint32_t bs_bpt_eo_es;
492 uint32_t raw_data_size;
495 * bsp crypto_block_size_pointer 8 bits at MLX5_BLOCK_SIZE_OFFSET
496 * res reserved 24 bits
500 uint8_t xts_initial_tweak[16];
503 * res reserved 8 bits
504 * dp dek_pointer 24 bits at offset 0
509 uint32_t reserved2[4];
513 #pragma GCC diagnostic ignored "-Wpedantic"
516 struct mlx5_umr_wqe {
517 struct mlx5_wqe_cseg ctr;
518 struct mlx5_wqe_umr_cseg ucseg;
519 struct mlx5_wqe_mkey_cseg mkc;
521 struct mlx5_wqe_dseg kseg[0];
522 struct mlx5_wqe_umr_bsf_seg bsf[0];
526 struct mlx5_rdma_write_wqe {
527 struct mlx5_wqe_cseg ctr;
528 struct mlx5_wqe_rseg rseg;
529 struct mlx5_wqe_dseg dseg[0];
533 #pragma GCC diagnostic error "-Wpedantic"
537 /* MMO metadata segment */
539 #define MLX5_OPCODE_MMO 0x2fu
540 #define MLX5_OPC_MOD_MMO_REGEX 0x4u
541 #define MLX5_OPC_MOD_MMO_COMP 0x2u
542 #define MLX5_OPC_MOD_MMO_DECOMP 0x3u
543 #define MLX5_OPC_MOD_MMO_DMA 0x1u
545 #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u
546 #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u
547 #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u
548 #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u
549 #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS)
550 #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u
551 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u
552 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u
554 struct mlx5_wqe_metadata_seg {
555 uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */
560 struct mlx5_gga_wqe {
564 uint32_t gga_ctrl1; /* ws 12-15, bs 16-19, dyns 20-23. */
566 uint32_t opaque_lkey;
567 uint64_t opaque_vaddr;
568 struct mlx5_wqe_dseg gather;
569 struct mlx5_wqe_dseg scatter;
572 struct mlx5_gga_compress_opaque {
575 uint32_t scattered_length;
576 uint32_t gathered_length;
577 uint64_t scatter_crc;
581 uint8_t reserved1[216];
584 struct mlx5_ifc_regexp_mmo_control_bits {
585 uint8_t reserved_at_31[0x2];
587 uint8_t reserved_at_28[0x1];
588 uint8_t subset_id_0[0xc];
589 uint8_t reserved_at_16[0x4];
590 uint8_t subset_id_1[0xc];
592 uint8_t subset_id_2[0xc];
593 uint8_t reserved_at_16_1[0x4];
594 uint8_t subset_id_3[0xc];
597 struct mlx5_ifc_regexp_metadata_bits {
598 uint8_t rof_version[0x10];
599 uint8_t latency_count[0x10];
600 uint8_t instruction_count[0x10];
601 uint8_t primary_thread_count[0x10];
602 uint8_t match_count[0x8];
603 uint8_t detected_match_count[0x8];
604 uint8_t status[0x10];
605 uint8_t job_id[0x20];
606 uint8_t reserved[0x80];
609 struct mlx5_ifc_regexp_match_tuple_bits {
610 uint8_t length[0x10];
611 uint8_t start_ptr[0x10];
612 uint8_t rule_id[0x20];
615 /* Adding direct verbs to data-path. */
617 /* CQ sequence number mask. */
618 #define MLX5_CQ_SQN_MASK 0x3
620 /* CQ sequence number index. */
621 #define MLX5_CQ_SQN_OFFSET 28
623 /* CQ doorbell index mask. */
624 #define MLX5_CI_MASK 0xffffff
626 /* CQ doorbell offset. */
627 #define MLX5_CQ_ARM_DB 1
629 /* CQ doorbell offset*/
630 #define MLX5_CQ_DOORBELL 0x20
632 /* CQE format value. */
633 #define MLX5_COMPRESSED 0x3
635 /* CQ doorbell cmd types. */
636 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24)
637 #define MLX5_CQ_DBR_CMD_ALL (0 << 24)
639 /* Action type of header modification. */
641 MLX5_MODIFICATION_TYPE_SET = 0x1,
642 MLX5_MODIFICATION_TYPE_ADD = 0x2,
643 MLX5_MODIFICATION_TYPE_COPY = 0x3,
646 /* The field of packet to be modified. */
647 enum mlx5_modification_field {
648 MLX5_MODI_OUT_NONE = -1,
649 MLX5_MODI_OUT_SMAC_47_16 = 1,
650 MLX5_MODI_OUT_SMAC_15_0,
651 MLX5_MODI_OUT_ETHERTYPE,
652 MLX5_MODI_OUT_DMAC_47_16,
653 MLX5_MODI_OUT_DMAC_15_0,
654 MLX5_MODI_OUT_IP_DSCP,
655 MLX5_MODI_OUT_TCP_FLAGS,
656 MLX5_MODI_OUT_TCP_SPORT,
657 MLX5_MODI_OUT_TCP_DPORT,
658 MLX5_MODI_OUT_IPV4_TTL,
659 MLX5_MODI_OUT_UDP_SPORT,
660 MLX5_MODI_OUT_UDP_DPORT,
661 MLX5_MODI_OUT_SIPV6_127_96,
662 MLX5_MODI_OUT_SIPV6_95_64,
663 MLX5_MODI_OUT_SIPV6_63_32,
664 MLX5_MODI_OUT_SIPV6_31_0,
665 MLX5_MODI_OUT_DIPV6_127_96,
666 MLX5_MODI_OUT_DIPV6_95_64,
667 MLX5_MODI_OUT_DIPV6_63_32,
668 MLX5_MODI_OUT_DIPV6_31_0,
671 MLX5_MODI_OUT_FIRST_VID,
672 MLX5_MODI_IN_SMAC_47_16 = 0x31,
673 MLX5_MODI_IN_SMAC_15_0,
674 MLX5_MODI_IN_ETHERTYPE,
675 MLX5_MODI_IN_DMAC_47_16,
676 MLX5_MODI_IN_DMAC_15_0,
677 MLX5_MODI_IN_IP_DSCP,
678 MLX5_MODI_IN_TCP_FLAGS,
679 MLX5_MODI_IN_TCP_SPORT,
680 MLX5_MODI_IN_TCP_DPORT,
681 MLX5_MODI_IN_IPV4_TTL,
682 MLX5_MODI_IN_UDP_SPORT,
683 MLX5_MODI_IN_UDP_DPORT,
684 MLX5_MODI_IN_SIPV6_127_96,
685 MLX5_MODI_IN_SIPV6_95_64,
686 MLX5_MODI_IN_SIPV6_63_32,
687 MLX5_MODI_IN_SIPV6_31_0,
688 MLX5_MODI_IN_DIPV6_127_96,
689 MLX5_MODI_IN_DIPV6_95_64,
690 MLX5_MODI_IN_DIPV6_63_32,
691 MLX5_MODI_IN_DIPV6_31_0,
694 MLX5_MODI_OUT_IPV6_HOPLIMIT,
695 MLX5_MODI_IN_IPV6_HOPLIMIT,
696 MLX5_MODI_META_DATA_REG_A,
697 MLX5_MODI_META_DATA_REG_B = 0x50,
698 MLX5_MODI_META_REG_C_0,
699 MLX5_MODI_META_REG_C_1,
700 MLX5_MODI_META_REG_C_2,
701 MLX5_MODI_META_REG_C_3,
702 MLX5_MODI_META_REG_C_4,
703 MLX5_MODI_META_REG_C_5,
704 MLX5_MODI_META_REG_C_6,
705 MLX5_MODI_META_REG_C_7,
706 MLX5_MODI_OUT_TCP_SEQ_NUM,
707 MLX5_MODI_IN_TCP_SEQ_NUM,
708 MLX5_MODI_OUT_TCP_ACK_NUM,
709 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
710 MLX5_MODI_GTP_TEID = 0x6E,
713 /* Total number of metadata reg_c's. */
714 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1)
730 /* Modification sub command. */
731 struct mlx5_modification_cmd {
735 unsigned int length:5;
736 unsigned int rsvd0:3;
737 unsigned int offset:5;
738 unsigned int rsvd1:3;
739 unsigned int field:12;
740 unsigned int action_type:4;
747 unsigned int rsvd2:8;
748 unsigned int dst_offset:5;
749 unsigned int rsvd3:3;
750 unsigned int dst_field:12;
751 unsigned int rsvd4:4;
756 typedef uint64_t u64;
757 typedef uint32_t u32;
758 typedef uint16_t u16;
761 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
762 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
763 #define __mlx5_bit_off(typ, fld) ((unsigned int)(uintptr_t) \
764 (&(__mlx5_nullp(typ)->fld)))
765 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
766 (__mlx5_bit_off(typ, fld) & 0x1f))
767 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
768 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
769 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
770 __mlx5_dw_bit_off(typ, fld))
771 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
772 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
773 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
774 (__mlx5_bit_off(typ, fld) & 0xf))
775 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
776 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \
777 __mlx5_16_bit_off(typ, fld))
778 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
779 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
780 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
781 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
783 /* insert a value to a struct */
784 #define MLX5_SET(typ, p, fld, v) \
787 *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \
788 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
789 __mlx5_dw_off(typ, fld))) & \
790 (~__mlx5_dw_mask(typ, fld))) | \
791 (((_v) & __mlx5_mask(typ, fld)) << \
792 __mlx5_dw_bit_off(typ, fld))); \
795 #define MLX5_SET64(typ, p, fld, v) \
797 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \
798 *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \
799 rte_cpu_to_be_64(v); \
802 #define MLX5_SET16(typ, p, fld, v) \
805 *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \
806 rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
807 __mlx5_16_off(typ, fld))) & \
808 (~__mlx5_16_mask(typ, fld))) | \
809 (((_v) & __mlx5_mask16(typ, fld)) << \
810 __mlx5_16_bit_off(typ, fld))); \
813 #define MLX5_GET_VOLATILE(typ, p, fld) \
814 ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\
815 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
816 __mlx5_mask(typ, fld))
817 #define MLX5_GET(typ, p, fld) \
818 ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\
819 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
820 __mlx5_mask(typ, fld))
821 #define MLX5_GET16(typ, p, fld) \
822 ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
823 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
824 __mlx5_mask16(typ, fld))
825 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \
826 __mlx5_64_off(typ, fld)))
827 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
828 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
830 struct mlx5_ifc_fte_match_set_misc_bits {
831 u8 gre_c_present[0x1];
832 u8 reserved_at_1[0x1];
833 u8 gre_k_present[0x1];
834 u8 gre_s_present[0x1];
835 u8 source_vhci_port[0x4];
837 u8 reserved_at_20[0x10];
838 u8 source_port[0x10];
839 u8 outer_second_prio[0x3];
840 u8 outer_second_cfi[0x1];
841 u8 outer_second_vid[0xc];
842 u8 inner_second_prio[0x3];
843 u8 inner_second_cfi[0x1];
844 u8 inner_second_vid[0xc];
845 u8 outer_second_cvlan_tag[0x1];
846 u8 inner_second_cvlan_tag[0x1];
847 u8 outer_second_svlan_tag[0x1];
848 u8 inner_second_svlan_tag[0x1];
849 u8 reserved_at_64[0xc];
850 u8 gre_protocol[0x10];
854 u8 reserved_at_b8[0x8];
856 u8 reserved_at_e4[0x7];
858 u8 reserved_at_e0[0xc];
859 u8 outer_ipv6_flow_label[0x14];
860 u8 reserved_at_100[0xc];
861 u8 inner_ipv6_flow_label[0x14];
862 u8 reserved_at_120[0xa];
863 u8 geneve_opt_len[0x6];
864 u8 geneve_protocol_type[0x10];
865 u8 reserved_at_140[0xc0];
868 struct mlx5_ifc_ipv4_layout_bits {
869 u8 reserved_at_0[0x60];
873 struct mlx5_ifc_ipv6_layout_bits {
877 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
878 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
879 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
880 u8 reserved_at_0[0x80];
883 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
902 u8 reserved_at_c0[0x10];
906 u8 ipv4_checksum_ok[0x1];
907 u8 l4_checksum_ok[0x1];
908 u8 ip_ttl_hoplimit[0x8];
911 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
912 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
915 struct mlx5_ifc_fte_match_mpls_bits {
922 struct mlx5_ifc_fte_match_set_misc2_bits {
923 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
924 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
925 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
926 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
927 u8 metadata_reg_c_7[0x20];
928 u8 metadata_reg_c_6[0x20];
929 u8 metadata_reg_c_5[0x20];
930 u8 metadata_reg_c_4[0x20];
931 u8 metadata_reg_c_3[0x20];
932 u8 metadata_reg_c_2[0x20];
933 u8 metadata_reg_c_1[0x20];
934 u8 metadata_reg_c_0[0x20];
935 u8 metadata_reg_a[0x20];
936 u8 metadata_reg_b[0x20];
937 u8 reserved_at_1c0[0x40];
940 struct mlx5_ifc_fte_match_set_misc3_bits {
941 u8 inner_tcp_seq_num[0x20];
942 u8 outer_tcp_seq_num[0x20];
943 u8 inner_tcp_ack_num[0x20];
944 u8 outer_tcp_ack_num[0x20];
945 u8 reserved_at_auto1[0x8];
946 u8 outer_vxlan_gpe_vni[0x18];
947 u8 outer_vxlan_gpe_next_protocol[0x8];
948 u8 outer_vxlan_gpe_flags[0x8];
949 u8 reserved_at_a8[0x10];
950 u8 icmp_header_data[0x20];
951 u8 icmpv6_header_data[0x20];
956 u8 geneve_tlv_option_0_data[0x20];
958 u8 gtpu_msg_type[0x08];
959 u8 gtpu_msg_flags[0x08];
960 u8 reserved_at_170[0x10];
962 u8 gtpu_first_ext_dw_0[0x20];
964 u8 reserved_at_240[0x20];
968 struct mlx5_ifc_fte_match_set_misc4_bits {
969 u8 prog_sample_field_value_0[0x20];
970 u8 prog_sample_field_id_0[0x20];
971 u8 prog_sample_field_value_1[0x20];
972 u8 prog_sample_field_id_1[0x20];
973 u8 prog_sample_field_value_2[0x20];
974 u8 prog_sample_field_id_2[0x20];
975 u8 prog_sample_field_value_3[0x20];
976 u8 prog_sample_field_id_3[0x20];
977 u8 reserved_at_100[0x100];
981 struct mlx5_ifc_fte_match_param_bits {
982 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
983 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
984 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
985 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
986 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
987 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
989 * Add reserved bit to match the struct size with the size defined in PRM.
990 * This extension is not required in Linux.
992 #ifndef HAVE_INFINIBAND_VERBS_H
993 u8 reserved_0[0x400];
997 struct mlx5_ifc_dest_format_struct_bits {
998 u8 destination_type[0x8];
999 u8 destination_id[0x18];
1000 u8 reserved_0[0x20];
1004 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
1005 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
1006 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
1007 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
1008 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT,
1009 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT,
1013 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
1014 MLX5_CMD_OP_CREATE_MKEY = 0x200,
1015 MLX5_CMD_OP_CREATE_CQ = 0x400,
1016 MLX5_CMD_OP_CREATE_QP = 0x500,
1017 MLX5_CMD_OP_RST2INIT_QP = 0x502,
1018 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
1019 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
1020 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
1021 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
1022 MLX5_CMD_OP_QP_2ERR = 0x507,
1023 MLX5_CMD_OP_QP_2RST = 0x50A,
1024 MLX5_CMD_OP_QUERY_QP = 0x50B,
1025 MLX5_CMD_OP_SQD2RTS_QP = 0x50C,
1026 MLX5_CMD_OP_INIT2INIT_QP = 0x50E,
1027 MLX5_CMD_OP_SUSPEND_QP = 0x50F,
1028 MLX5_CMD_OP_RESUME_QP = 0x510,
1029 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
1030 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
1031 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
1032 MLX5_CMD_OP_ALLOC_PD = 0x800,
1033 MLX5_CMD_OP_DEALLOC_PD = 0x801,
1034 MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
1035 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
1036 MLX5_CMD_OP_CREATE_TIR = 0x900,
1037 MLX5_CMD_OP_MODIFY_TIR = 0x901,
1038 MLX5_CMD_OP_CREATE_SQ = 0X904,
1039 MLX5_CMD_OP_MODIFY_SQ = 0X905,
1040 MLX5_CMD_OP_CREATE_RQ = 0x908,
1041 MLX5_CMD_OP_MODIFY_RQ = 0x909,
1042 MLX5_CMD_OP_QUERY_RQ = 0x90b,
1043 MLX5_CMD_OP_CREATE_TIS = 0x912,
1044 MLX5_CMD_OP_QUERY_TIS = 0x915,
1045 MLX5_CMD_OP_CREATE_RQT = 0x916,
1046 MLX5_CMD_OP_MODIFY_RQT = 0x917,
1047 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
1048 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
1049 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
1050 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
1051 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
1052 MLX5_CMD_SET_REGEX_PARAMS = 0xb04,
1053 MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,
1054 MLX5_CMD_SET_REGEX_REGISTERS = 0xb06,
1055 MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
1056 MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c,
1060 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
1061 MLX5_MKC_ACCESS_MODE_KLM = 0x2,
1062 MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3,
1065 #define MLX5_ADAPTER_PAGE_SHIFT 12
1066 #define MLX5_LOG_RQ_STRIDE_SHIFT 4
1068 * The batch counter dcs id starts from 0x800000 and none batch counter
1069 * starts from 0. As currently, the counter is changed to be indexed by
1070 * pool index and the offset of the counter in the pool counters_raw array.
1071 * It means now the counter index is same for batch and none batch counter.
1072 * Add the 0x800000 batch counter offset to the batch counter index helps
1073 * indicate the counter index is from batch or none batch container pool.
1075 #define MLX5_CNT_BATCH_OFFSET 0x800000
1077 /* The counter batch query requires ID align with 4. */
1078 #define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4
1080 /* Flow counters. */
1081 struct mlx5_ifc_alloc_flow_counter_out_bits {
1083 u8 reserved_at_8[0x18];
1085 u8 flow_counter_id[0x20];
1086 u8 reserved_at_60[0x20];
1089 struct mlx5_ifc_alloc_flow_counter_in_bits {
1091 u8 reserved_at_10[0x10];
1092 u8 reserved_at_20[0x10];
1094 u8 flow_counter_id[0x20];
1095 u8 reserved_at_40[0x18];
1096 u8 flow_counter_bulk[0x8];
1099 struct mlx5_ifc_dealloc_flow_counter_out_bits {
1101 u8 reserved_at_8[0x18];
1103 u8 reserved_at_40[0x40];
1106 struct mlx5_ifc_dealloc_flow_counter_in_bits {
1108 u8 reserved_at_10[0x10];
1109 u8 reserved_at_20[0x10];
1111 u8 flow_counter_id[0x20];
1112 u8 reserved_at_60[0x20];
1115 struct mlx5_ifc_traffic_counter_bits {
1120 struct mlx5_ifc_query_flow_counter_out_bits {
1122 u8 reserved_at_8[0x18];
1124 u8 reserved_at_40[0x40];
1125 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
1128 struct mlx5_ifc_query_flow_counter_in_bits {
1130 u8 reserved_at_10[0x10];
1131 u8 reserved_at_20[0x10];
1133 u8 reserved_at_40[0x20];
1137 u8 dump_to_memory[0x1];
1138 u8 num_of_counters[0x1e];
1139 u8 flow_counter_id[0x20];
1142 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u
1143 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u
1145 struct mlx5_ifc_klm_bits {
1146 u8 byte_count[0x20];
1151 struct mlx5_ifc_mkc_bits {
1152 u8 reserved_at_0[0x1];
1154 u8 reserved_at_2[0x1];
1155 u8 access_mode_4_2[0x3];
1156 u8 reserved_at_6[0x7];
1157 u8 relaxed_ordering_write[0x1];
1158 u8 reserved_at_e[0x1];
1159 u8 small_fence_on_rdma_read_response[0x1];
1166 u8 access_mode_1_0[0x2];
1167 u8 reserved_at_18[0x8];
1170 u8 reserved_at_40[0x20];
1174 u8 reserved_at_63[0x2];
1175 u8 expected_sigerr_count[0x1];
1176 u8 reserved_at_66[0x1];
1179 u8 start_addr[0x40];
1181 u8 bsf_octword_size[0x20];
1182 u8 reserved_at_120[0x80];
1183 u8 translations_octword_size[0x20];
1184 u8 reserved_at_1c0[0x19];
1185 u8 relaxed_ordering_read[0x1];
1186 u8 reserved_at_1da[0x1];
1187 u8 log_page_size[0x5];
1188 u8 reserved_at_1e0[0x3];
1190 u8 reserved_at_1e5[0x1b];
1193 /* Range of values for MKEY context crypto_en field. */
1195 MLX5_MKEY_CRYPTO_DISABLED = 0x0,
1196 MLX5_MKEY_CRYPTO_ENABLED = 0x1,
1199 struct mlx5_ifc_create_mkey_out_bits {
1201 u8 reserved_at_8[0x18];
1203 u8 reserved_at_40[0x8];
1204 u8 mkey_index[0x18];
1205 u8 reserved_at_60[0x20];
1208 struct mlx5_ifc_create_mkey_in_bits {
1210 u8 reserved_at_10[0x10];
1211 u8 reserved_at_20[0x10];
1213 u8 reserved_at_40[0x20];
1215 u8 reserved_at_61[0x1f];
1216 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
1217 u8 reserved_at_280[0x80];
1218 u8 translations_octword_actual_size[0x20];
1219 u8 mkey_umem_id[0x20];
1220 u8 mkey_umem_offset[0x40];
1221 u8 reserved_at_380[0x500];
1222 u8 klm_pas_mtt[][0x20];
1226 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
1227 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
1228 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
1229 MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1,
1230 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,
1231 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
1234 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \
1235 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ)
1236 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \
1237 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS)
1238 #define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \
1239 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH)
1240 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \
1241 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO)
1242 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO \
1243 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO)
1244 #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \
1245 (1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT)
1246 #define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \
1247 (1ULL << MLX5_GENERAL_OBJ_TYPE_DEK)
1248 #define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \
1249 (1ULL << MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK)
1250 #define MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL \
1251 (1ULL << MLX5_GENERAL_OBJ_TYPE_CREDENTIAL)
1252 #define MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN \
1253 (1ULL << MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN)
1256 MLX5_HCA_CAP_OPMOD_GET_MAX = 0,
1257 MLX5_HCA_CAP_OPMOD_GET_CUR = 1,
1261 MLX5_CAP_INLINE_MODE_L2,
1262 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
1263 MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
1267 MLX5_INLINE_MODE_NONE,
1268 MLX5_INLINE_MODE_L2,
1269 MLX5_INLINE_MODE_IP,
1270 MLX5_INLINE_MODE_TCP_UDP,
1271 MLX5_INLINE_MODE_RESERVED4,
1272 MLX5_INLINE_MODE_INNER_L2,
1273 MLX5_INLINE_MODE_INNER_IP,
1274 MLX5_INLINE_MODE_INNER_TCP_UDP,
1277 /* The supported timestamp formats reported in HCA attributes. */
1279 MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR = 0x0,
1280 MLX5_HCA_CAP_TIMESTAMP_FORMAT_RT = 0x1,
1281 MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR_RT = 0x2,
1284 /* The timestamp format attributes to configure queues (RQ/SQ/QP). */
1286 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
1287 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1,
1288 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
1291 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
1292 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
1293 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
1294 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
1295 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
1296 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
1297 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
1298 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
1299 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
1300 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
1301 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
1303 struct mlx5_ifc_cmd_hca_cap_bits {
1304 u8 reserved_at_0[0x30];
1306 u8 reserved_at_40[0x20];
1307 u8 reserved_at_60[0x3];
1308 u8 log_regexp_scatter_gather_size[0x5];
1309 u8 reserved_at_68[0x3];
1310 u8 log_dma_mmo_size[0x5];
1311 u8 reserved_at_70[0x3];
1312 u8 log_compress_mmo_size[0x5];
1313 u8 reserved_at_78[0x3];
1314 u8 log_decompress_mmo_size[0x5];
1315 u8 log_max_srq_sz[0x8];
1316 u8 log_max_qp_sz[0x8];
1317 u8 reserved_at_90[0x9];
1318 u8 wqe_index_ignore_cap[0x1];
1319 u8 dynamic_qp_allocation[0x1];
1322 u8 reserved_at_a1[0x3];
1323 u8 regexp_num_of_engines[0x4];
1324 u8 reserved_at_a8[0x1];
1325 u8 reg_c_preserve[0x1];
1326 u8 reserved_at_aa[0x1];
1327 u8 log_max_srq[0x5];
1328 u8 reserved_at_b0[0x3];
1329 u8 regexp_log_crspace_size[0x5];
1330 u8 reserved_at_b8[0x3];
1331 u8 scatter_fcs_w_decap_disable[0x1];
1332 u8 reserved_at_bc[0x4];
1333 u8 reserved_at_c0[0x8];
1334 u8 log_max_cq_sz[0x8];
1335 u8 reserved_at_d0[0xb];
1337 u8 log_max_eq_sz[0x8];
1338 u8 relaxed_ordering_write[0x1];
1339 u8 relaxed_ordering_read[0x1];
1340 u8 access_register_user[0x1];
1341 u8 log_max_mkey[0x5];
1342 u8 reserved_at_f0[0x8];
1343 u8 dump_fill_mkey[0x1];
1344 u8 reserved_at_f9[0x3];
1346 u8 max_indirection[0x8];
1347 u8 fixed_buffer_size[0x1];
1348 u8 log_max_mrw_sz[0x7];
1349 u8 force_teardown[0x1];
1350 u8 reserved_at_111[0x1];
1351 u8 log_max_bsf_list_size[0x6];
1352 u8 umr_extended_translation_offset[0x1];
1354 u8 log_max_klm_list_size[0x6];
1355 u8 non_wire_sq[0x1];
1356 u8 reserved_at_121[0x9];
1357 u8 log_max_ra_req_dc[0x6];
1358 u8 reserved_at_130[0x3];
1359 u8 log_max_static_sq_wq[0x5];
1360 u8 reserved_at_138[0x2];
1361 u8 log_max_ra_res_dc[0x6];
1362 u8 reserved_at_140[0xa];
1363 u8 log_max_ra_req_qp[0x6];
1364 u8 rtr2rts_qp_counters_set_id[0x1];
1365 u8 rts2rts_udp_sport[0x1];
1366 u8 rts2rts_lag_tx_port_affinity[0x1];
1368 u8 compress_min_block_size[0x4];
1371 u8 log_max_ra_res_qp[0x6];
1373 u8 cc_query_allowed[0x1];
1374 u8 cc_modify_allowed[0x1];
1376 u8 cache_line_128byte[0x1];
1377 u8 reserved_at_165[0xa];
1379 u8 gid_table_size[0x10];
1380 u8 out_of_seq_cnt[0x1];
1381 u8 vport_counters[0x1];
1382 u8 retransmission_q_counters[0x1];
1384 u8 modify_rq_counter_set_id[0x1];
1385 u8 rq_delay_drop[0x1];
1387 u8 pkey_table_size[0x10];
1388 u8 vport_group_manager[0x1];
1389 u8 vhca_group_manager[0x1];
1392 u8 vnic_env_queue_counters[0x1];
1394 u8 nic_flow_table[0x1];
1395 u8 eswitch_manager[0x1];
1396 u8 device_memory[0x1];
1399 u8 local_ca_ack_delay[0x5];
1400 u8 port_module_event[0x1];
1401 u8 enhanced_error_q_counters[0x1];
1402 u8 ports_check[0x1];
1403 u8 reserved_at_1b3[0x1];
1404 u8 disable_link_up[0x1];
1408 u8 reserved_at_1c0[0x1];
1411 u8 log_max_msg[0x5];
1412 u8 reserved_at_1c8[0x4];
1414 u8 temp_warn_event[0x1];
1416 u8 general_notification_event[0x1];
1417 u8 reserved_at_1d3[0x2];
1421 u8 reserved_at_1d8[0x1];
1429 u8 stat_rate_support[0x10];
1430 u8 reserved_at_1f0[0xc];
1431 u8 cqe_version[0x4];
1432 u8 compact_address_vector[0x1];
1433 u8 striding_rq[0x1];
1434 u8 reserved_at_202[0x1];
1435 u8 ipoib_enhanced_offloads[0x1];
1436 u8 ipoib_basic_offloads[0x1];
1437 u8 reserved_at_205[0x1];
1438 u8 repeated_block_disabled[0x1];
1439 u8 umr_modify_entity_size_disabled[0x1];
1440 u8 umr_modify_atomic_disabled[0x1];
1441 u8 umr_indirect_mkey_disabled[0x1];
1443 u8 reserved_at_20c[0x3];
1444 u8 drain_sigerr[0x1];
1445 u8 cmdif_checksum[0x2];
1447 u8 reserved_at_213[0x1];
1448 u8 wq_signature[0x1];
1449 u8 sctr_data_cqe[0x1];
1450 u8 reserved_at_216[0x1];
1456 u8 eth_net_offloads[0x1];
1459 u8 reserved_at_21f[0x1];
1462 u8 cq_moderation[0x1];
1463 u8 reserved_at_223[0x3];
1464 u8 cq_eq_remap[0x1];
1466 u8 block_lb_mc[0x1];
1467 u8 reserved_at_229[0x1];
1468 u8 scqe_break_moderation[0x1];
1469 u8 cq_period_start_from_cqe[0x1];
1471 u8 reserved_at_22d[0x1];
1473 u8 vector_calc[0x1];
1474 u8 umr_ptr_rlky[0x1];
1476 u8 reserved_at_232[0x4];
1479 u8 set_deth_sqpn[0x1];
1480 u8 reserved_at_239[0x3];
1486 u8 reserved_at_241[0x9];
1488 u8 reserved_at_250[0x8];
1491 u8 driver_version[0x1];
1492 u8 pad_tx_eth_packet[0x1];
1493 u8 reserved_at_263[0x8];
1494 u8 log_bf_reg_size[0x5];
1495 u8 reserved_at_270[0xb];
1497 u8 num_lag_ports[0x4];
1498 u8 reserved_at_280[0x10];
1499 u8 max_wqe_sz_sq[0x10];
1500 u8 reserved_at_2a0[0x10];
1501 u8 max_wqe_sz_rq[0x10];
1502 u8 max_flow_counter_31_16[0x10];
1503 u8 max_wqe_sz_sq_dc[0x10];
1504 u8 reserved_at_2e0[0x7];
1505 u8 max_qp_mcg[0x19];
1506 u8 reserved_at_300[0x10];
1507 u8 flow_counter_bulk_alloc[0x08];
1508 u8 log_max_mcg[0x8];
1509 u8 reserved_at_320[0x3];
1510 u8 log_max_transport_domain[0x5];
1511 u8 reserved_at_328[0x3];
1513 u8 reserved_at_330[0xb];
1514 u8 log_max_xrcd[0x5];
1515 u8 nic_receive_steering_discard[0x1];
1516 u8 receive_discard_vport_down[0x1];
1517 u8 transmit_discard_vport_down[0x1];
1518 u8 reserved_at_343[0x5];
1519 u8 log_max_flow_counter_bulk[0x8];
1520 u8 max_flow_counter_15_0[0x10];
1522 u8 flow_counters_dump[0x1];
1523 u8 reserved_at_360[0x1];
1525 u8 reserved_at_368[0x3];
1527 u8 reserved_at_370[0x3];
1528 u8 log_max_tir[0x5];
1529 u8 reserved_at_378[0x3];
1530 u8 log_max_tis[0x5];
1531 u8 basic_cyclic_rcv_wqe[0x1];
1532 u8 reserved_at_381[0x2];
1533 u8 log_max_rmp[0x5];
1534 u8 reserved_at_388[0x3];
1535 u8 log_max_rqt[0x5];
1536 u8 reserved_at_390[0x3];
1537 u8 log_max_rqt_size[0x5];
1538 u8 reserved_at_398[0x3];
1539 u8 log_max_tis_per_sq[0x5];
1540 u8 ext_stride_num_range[0x1];
1541 u8 reserved_at_3a1[0x2];
1542 u8 log_max_stride_sz_rq[0x5];
1543 u8 reserved_at_3a8[0x3];
1544 u8 log_min_stride_sz_rq[0x5];
1545 u8 reserved_at_3b0[0x3];
1546 u8 log_max_stride_sz_sq[0x5];
1547 u8 reserved_at_3b8[0x3];
1548 u8 log_min_stride_sz_sq[0x5];
1550 u8 reserved_at_3c1[0x2];
1551 u8 log_max_hairpin_queues[0x5];
1552 u8 reserved_at_3c8[0x3];
1553 u8 log_max_hairpin_wq_data_sz[0x5];
1554 u8 reserved_at_3d0[0x3];
1555 u8 log_max_hairpin_num_packets[0x5];
1556 u8 reserved_at_3d8[0x3];
1557 u8 log_max_wq_sz[0x5];
1558 u8 nic_vport_change_event[0x1];
1559 u8 disable_local_lb_uc[0x1];
1560 u8 disable_local_lb_mc[0x1];
1561 u8 log_min_hairpin_wq_data_sz[0x5];
1562 u8 reserved_at_3e8[0x3];
1563 u8 log_max_vlan_list[0x5];
1564 u8 reserved_at_3f0[0x3];
1565 u8 log_max_current_mc_list[0x5];
1566 u8 reserved_at_3f8[0x3];
1567 u8 log_max_current_uc_list[0x5];
1568 u8 general_obj_types[0x40];
1569 u8 sq_ts_format[0x2];
1570 u8 rq_ts_format[0x2];
1571 u8 reserved_at_444[0x1C];
1572 u8 reserved_at_460[0x8];
1575 u8 reserved_at_46a[0x6];
1576 u8 max_num_eqs[0x10];
1577 u8 reserved_at_480[0x3];
1578 u8 log_max_l2_table[0x5];
1579 u8 reserved_at_488[0x8];
1580 u8 log_uar_page_sz[0x10];
1581 u8 reserved_at_4a0[0x20];
1582 u8 device_frequency_mhz[0x20];
1583 u8 device_frequency_khz[0x20];
1584 u8 reserved_at_500[0x20];
1585 u8 num_of_uars_per_page[0x20];
1586 u8 flex_parser_protocols[0x20];
1587 u8 max_geneve_tlv_options[0x8];
1588 u8 reserved_at_568[0x3];
1589 u8 max_geneve_tlv_option_data_len[0x5];
1590 u8 reserved_at_570[0x49];
1591 u8 mini_cqe_resp_l3_l4_tag[0x1];
1592 u8 mini_cqe_resp_flow_tag[0x1];
1593 u8 enhanced_cqe_compression[0x1];
1594 u8 mini_cqe_resp_stride_index[0x1];
1595 u8 cqe_128_always[0x1];
1596 u8 cqe_compression_128[0x1];
1597 u8 cqe_compression[0x1];
1598 u8 cqe_compression_timeout[0x10];
1599 u8 cqe_compression_max_num[0x10];
1600 u8 reserved_at_5e0[0x10];
1601 u8 tag_matching[0x1];
1602 u8 rndv_offload_rc[0x1];
1603 u8 rndv_offload_dc[0x1];
1604 u8 log_tag_matching_list_sz[0x5];
1605 u8 reserved_at_5f8[0x3];
1606 u8 log_max_xrq[0x5];
1607 u8 affiliate_nic_vport_criteria[0x8];
1608 u8 native_port_num[0x8];
1609 u8 num_vhca_ports[0x8];
1610 u8 reserved_at_618[0x6];
1611 u8 sw_owner_id[0x1];
1612 u8 reserved_at_61f[0x1e1];
1615 struct mlx5_ifc_qos_cap_bits {
1616 u8 packet_pacing[0x1];
1617 u8 esw_scheduling[0x1];
1618 u8 esw_bw_share[0x1];
1619 u8 esw_rate_limit[0x1];
1620 u8 reserved_at_4[0x1];
1621 u8 packet_pacing_burst_bound[0x1];
1622 u8 packet_pacing_typical_size[0x1];
1623 u8 flow_meter_old[0x1];
1624 u8 reserved_at_8[0x8];
1625 u8 log_max_flow_meter[0x8];
1626 u8 flow_meter_reg_id[0x8];
1627 u8 wqe_rate_pp[0x1];
1628 u8 reserved_at_25[0x7];
1630 u8 reserved_at_2e[0x17];
1631 u8 packet_pacing_max_rate[0x20];
1632 u8 packet_pacing_min_rate[0x20];
1633 u8 reserved_at_80[0x10];
1634 u8 packet_pacing_rate_table_size[0x10];
1635 u8 esw_element_type[0x10];
1636 u8 esw_tsar_type[0x10];
1637 u8 reserved_at_c0[0x10];
1638 u8 max_qos_para_vport[0x10];
1639 u8 max_tsar_bw_share[0x20];
1640 u8 nic_element_type[0x10];
1641 u8 nic_tsar_type[0x10];
1642 u8 reserved_at_120[0x3];
1643 u8 log_meter_aso_granularity[0x5];
1644 u8 reserved_at_128[0x3];
1645 u8 log_meter_aso_max_alloc[0x5];
1646 u8 reserved_at_130[0x3];
1647 u8 log_max_num_meter_aso[0x5];
1648 u8 reserved_at_138[0x6b0];
1651 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1655 u8 lro_psh_flag[0x1];
1656 u8 lro_time_stamp[0x1];
1657 u8 lro_max_msg_sz_mode[0x2];
1658 u8 wqe_vlan_insert[0x1];
1659 u8 self_lb_en_modifiable[0x1];
1662 u8 max_lso_cap[0x5];
1663 u8 multi_pkt_send_wqe[0x2];
1664 u8 wqe_inline_mode[0x2];
1665 u8 rss_ind_tbl_cap[0x4];
1667 u8 scatter_fcs[0x1];
1668 u8 enhanced_multi_pkt_send_wqe[0x1];
1669 u8 tunnel_lso_const_out_ip_id[0x1];
1670 u8 tunnel_lro_gre[0x1];
1671 u8 tunnel_lro_vxlan[0x1];
1672 u8 tunnel_stateless_gre[0x1];
1673 u8 tunnel_stateless_vxlan[0x1];
1677 u8 reserved_at_23[0x8];
1678 u8 tunnel_stateless_gtp[0x1];
1679 u8 reserved_at_25[0x4];
1680 u8 max_vxlan_udp_ports[0x8];
1681 u8 reserved_at_38[0x6];
1682 u8 max_geneve_opt_len[0x1];
1683 u8 tunnel_stateless_geneve_rx[0x1];
1684 u8 reserved_at_40[0x10];
1685 u8 lro_min_mss_size[0x10];
1686 u8 reserved_at_60[0x120];
1687 u8 lro_timer_supported_periods[4][0x20];
1688 u8 reserved_at_200[0x600];
1692 MLX5_VIRTQ_TYPE_SPLIT = 0,
1693 MLX5_VIRTQ_TYPE_PACKED = 1,
1697 MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0,
1698 MLX5_VIRTQ_EVENT_MODE_QP = 1,
1699 MLX5_VIRTQ_EVENT_MODE_MSIX = 2,
1702 struct mlx5_ifc_virtio_emulation_cap_bits {
1703 u8 desc_tunnel_offload_type[0x1];
1704 u8 eth_frame_offload_type[0x1];
1705 u8 virtio_version_1_0[0x1];
1710 u8 reserved_at_7[0x1][0x9];
1712 u8 virtio_queue_type[0x8];
1713 u8 reserved_at_20[0x13];
1714 u8 log_doorbell_stride[0x5];
1715 u8 reserved_at_3b[0x3];
1716 u8 log_doorbell_bar_size[0x5];
1717 u8 doorbell_bar_offset[0x40];
1718 u8 reserved_at_80[0x8];
1719 u8 max_num_virtio_queues[0x18];
1720 u8 reserved_at_a0[0x60];
1721 u8 umem_1_buffer_param_a[0x20];
1722 u8 umem_1_buffer_param_b[0x20];
1723 u8 umem_2_buffer_param_a[0x20];
1724 u8 umem_2_buffer_param_b[0x20];
1725 u8 umem_3_buffer_param_a[0x20];
1726 u8 umem_3_buffer_param_b[0x20];
1727 u8 reserved_at_1c0[0x620];
1730 struct mlx5_ifc_flow_table_prop_layout_bits {
1733 u8 flow_counter[0x1];
1734 u8 flow_modify_en[0x1];
1735 u8 modify_root[0x1];
1736 u8 identified_miss_table[0x1];
1737 u8 flow_table_modify[0x1];
1740 u8 reset_root_to_default[0x1];
1743 u8 fpga_vendor_acceleration[0x1];
1745 u8 push_vlan_2[0x1];
1746 u8 reformat_and_vlan_action[0x1];
1747 u8 modify_and_vlan_action[0x1];
1749 u8 reformat_l3_tunnel_to_l2[0x1];
1750 u8 reformat_l2_to_l3_tunnel[0x1];
1751 u8 reformat_and_modify_action[0x1];
1752 u8 reserved_at_15[0x9];
1753 u8 sw_owner_v2[0x1];
1754 u8 reserved_at_1f[0x1];
1755 u8 reserved_at_20[0x2];
1756 u8 log_max_ft_size[0x6];
1757 u8 log_max_modify_header_context[0x8];
1758 u8 max_modify_header_actions[0x8];
1759 u8 max_ft_level[0x8];
1760 u8 reserved_at_40[0x8];
1761 u8 log_max_ft_sampler_num[8];
1762 u8 metadata_reg_b_width[0x8];
1763 u8 metadata_reg_a_width[0x8];
1764 u8 reserved_at_60[0x18];
1765 u8 log_max_ft_num[0x8];
1766 u8 reserved_at_80[0x10];
1767 u8 log_max_flow_counter[0x8];
1768 u8 log_max_destination[0x8];
1769 u8 reserved_at_a0[0x18];
1770 u8 log_max_flow[0x8];
1771 u8 reserved_at_c0[0x140];
1774 struct mlx5_ifc_roce_caps_bits {
1775 u8 reserved_0[0x1e];
1776 u8 qp_ts_format[0x2];
1777 u8 reserved_at_20[0x7e0];
1781 * Table 1872 - Flow Table Fields Supported 2 Format
1783 struct mlx5_ifc_ft_fields_support_2_bits {
1784 u8 reserved_at_0[0x14];
1785 u8 inner_ipv4_ihl[0x1];
1786 u8 outer_ipv4_ihl[0x1];
1787 u8 psp_syndrome[0x1];
1788 u8 inner_l3_ok[0x1];
1789 u8 inner_l4_ok[0x1];
1790 u8 outer_l3_ok[0x1];
1791 u8 outer_l4_ok[0x1];
1793 u8 inner_ipv4_checksum_ok[0x1];
1794 u8 inner_l4_checksum_ok[0x1];
1795 u8 outer_ipv4_checksum_ok[0x1];
1796 u8 outer_l4_checksum_ok[0x1];
1799 struct mlx5_ifc_flow_table_nic_cap_bits {
1800 u8 reserved_at_0[0x200];
1801 struct mlx5_ifc_flow_table_prop_layout_bits
1802 flow_table_properties_nic_receive;
1803 struct mlx5_ifc_flow_table_prop_layout_bits
1804 flow_table_properties_unused[5];
1805 u8 reserved_at_1C0[0x200];
1806 u8 header_modify_nic_receive[0x400];
1807 struct mlx5_ifc_ft_fields_support_2_bits
1808 ft_field_support_2_nic_receive;
1811 union mlx5_ifc_hca_cap_union_bits {
1812 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1813 struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1814 per_protocol_networking_offload_caps;
1815 struct mlx5_ifc_qos_cap_bits qos_cap;
1816 struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
1817 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1818 struct mlx5_ifc_roce_caps_bits roce_caps;
1819 u8 reserved_at_0[0x8000];
1822 struct mlx5_ifc_set_action_in_bits {
1823 u8 action_type[0x4];
1825 u8 reserved_at_10[0x3];
1827 u8 reserved_at_18[0x3];
1832 struct mlx5_ifc_query_hca_cap_out_bits {
1834 u8 reserved_at_8[0x18];
1836 u8 reserved_at_40[0x40];
1837 union mlx5_ifc_hca_cap_union_bits capability;
1840 struct mlx5_ifc_query_hca_cap_in_bits {
1842 u8 reserved_at_10[0x10];
1843 u8 reserved_at_20[0x10];
1845 u8 reserved_at_40[0x40];
1848 struct mlx5_ifc_mac_address_layout_bits {
1849 u8 reserved_at_0[0x10];
1850 u8 mac_addr_47_32[0x10];
1851 u8 mac_addr_31_0[0x20];
1854 struct mlx5_ifc_nic_vport_context_bits {
1855 u8 reserved_at_0[0x5];
1856 u8 min_wqe_inline_mode[0x3];
1857 u8 reserved_at_8[0x15];
1858 u8 disable_mc_local_lb[0x1];
1859 u8 disable_uc_local_lb[0x1];
1861 u8 arm_change_event[0x1];
1862 u8 reserved_at_21[0x1a];
1863 u8 event_on_mtu[0x1];
1864 u8 event_on_promisc_change[0x1];
1865 u8 event_on_vlan_change[0x1];
1866 u8 event_on_mc_address_change[0x1];
1867 u8 event_on_uc_address_change[0x1];
1868 u8 reserved_at_40[0xc];
1869 u8 affiliation_criteria[0x4];
1870 u8 affiliated_vhca_id[0x10];
1871 u8 reserved_at_60[0xd0];
1873 u8 system_image_guid[0x40];
1876 u8 reserved_at_200[0x140];
1877 u8 qkey_violation_counter[0x10];
1878 u8 reserved_at_350[0x430];
1881 u8 promisc_all[0x1];
1882 u8 reserved_at_783[0x2];
1883 u8 allowed_list_type[0x3];
1884 u8 reserved_at_788[0xc];
1885 u8 allowed_list_size[0xc];
1886 struct mlx5_ifc_mac_address_layout_bits permanent_address;
1887 u8 reserved_at_7e0[0x20];
1890 struct mlx5_ifc_query_nic_vport_context_out_bits {
1892 u8 reserved_at_8[0x18];
1894 u8 reserved_at_40[0x40];
1895 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
1898 struct mlx5_ifc_query_nic_vport_context_in_bits {
1900 u8 reserved_at_10[0x10];
1901 u8 reserved_at_20[0x10];
1903 u8 other_vport[0x1];
1904 u8 reserved_at_41[0xf];
1905 u8 vport_number[0x10];
1906 u8 reserved_at_60[0x5];
1907 u8 allowed_list_type[0x3];
1908 u8 reserved_at_68[0x18];
1911 struct mlx5_ifc_tisc_bits {
1912 u8 strict_lag_tx_port_affinity[0x1];
1913 u8 reserved_at_1[0x3];
1914 u8 lag_tx_port_affinity[0x04];
1915 u8 reserved_at_8[0x4];
1917 u8 reserved_at_10[0x10];
1918 u8 reserved_at_20[0x100];
1919 u8 reserved_at_120[0x8];
1920 u8 transport_domain[0x18];
1921 u8 reserved_at_140[0x8];
1922 u8 underlay_qpn[0x18];
1923 u8 reserved_at_160[0x3a0];
1926 struct mlx5_ifc_query_tis_out_bits {
1928 u8 reserved_at_8[0x18];
1930 u8 reserved_at_40[0x40];
1931 struct mlx5_ifc_tisc_bits tis_context;
1934 struct mlx5_ifc_query_tis_in_bits {
1936 u8 reserved_at_10[0x10];
1937 u8 reserved_at_20[0x10];
1939 u8 reserved_at_40[0x8];
1941 u8 reserved_at_60[0x20];
1944 struct mlx5_ifc_alloc_transport_domain_out_bits {
1946 u8 reserved_at_8[0x18];
1948 u8 reserved_at_40[0x8];
1949 u8 transport_domain[0x18];
1950 u8 reserved_at_60[0x20];
1953 struct mlx5_ifc_alloc_transport_domain_in_bits {
1955 u8 reserved_at_10[0x10];
1956 u8 reserved_at_20[0x10];
1958 u8 reserved_at_40[0x40];
1962 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1963 MLX5_WQ_TYPE_CYCLIC = 0x1,
1964 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1965 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1969 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1970 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1973 struct mlx5_ifc_wq_bits {
1975 u8 wq_signature[0x1];
1976 u8 end_padding_mode[0x2];
1978 u8 reserved_at_8[0x18];
1979 u8 hds_skip_first_sge[0x1];
1980 u8 log2_hds_buf_size[0x3];
1981 u8 reserved_at_24[0x7];
1982 u8 page_offset[0x5];
1984 u8 reserved_at_40[0x8];
1986 u8 reserved_at_60[0x8];
1989 u8 hw_counter[0x20];
1990 u8 sw_counter[0x20];
1991 u8 reserved_at_100[0xc];
1992 u8 log_wq_stride[0x4];
1993 u8 reserved_at_110[0x3];
1994 u8 log_wq_pg_sz[0x5];
1995 u8 reserved_at_118[0x3];
1997 u8 dbr_umem_valid[0x1];
1998 u8 wq_umem_valid[0x1];
1999 u8 reserved_at_122[0x1];
2000 u8 log_hairpin_num_packets[0x5];
2001 u8 reserved_at_128[0x3];
2002 u8 log_hairpin_data_sz[0x5];
2003 u8 reserved_at_130[0x4];
2004 u8 single_wqe_log_num_of_strides[0x4];
2005 u8 two_byte_shift_en[0x1];
2006 u8 reserved_at_139[0x4];
2007 u8 single_stride_log_num_of_bytes[0x3];
2008 u8 dbr_umem_id[0x20];
2009 u8 wq_umem_id[0x20];
2010 u8 wq_umem_offset[0x40];
2011 u8 reserved_at_1c0[0x440];
2015 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2016 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2020 MLX5_RQC_STATE_RST = 0x0,
2021 MLX5_RQC_STATE_RDY = 0x1,
2022 MLX5_RQC_STATE_ERR = 0x3,
2025 struct mlx5_ifc_rqc_bits {
2027 u8 delay_drop_en[0x1];
2028 u8 scatter_fcs[0x1];
2030 u8 mem_rq_type[0x4];
2032 u8 reserved_at_c[0x1];
2033 u8 flush_in_error_en[0x1];
2035 u8 reserved_at_f[0xB];
2037 u8 reserved_at_1c[0x4];
2038 u8 reserved_at_20[0x8];
2039 u8 user_index[0x18];
2040 u8 reserved_at_40[0x8];
2042 u8 counter_set_id[0x8];
2043 u8 reserved_at_68[0x18];
2044 u8 reserved_at_80[0x8];
2046 u8 reserved_at_a0[0x8];
2047 u8 hairpin_peer_sq[0x18];
2048 u8 reserved_at_c0[0x10];
2049 u8 hairpin_peer_vhca[0x10];
2050 u8 reserved_at_e0[0xa0];
2051 struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
2054 struct mlx5_ifc_create_rq_out_bits {
2056 u8 reserved_at_8[0x18];
2058 u8 reserved_at_40[0x8];
2060 u8 reserved_at_60[0x20];
2063 struct mlx5_ifc_create_rq_in_bits {
2066 u8 reserved_at_20[0x10];
2068 u8 reserved_at_40[0xc0];
2069 struct mlx5_ifc_rqc_bits ctx;
2072 struct mlx5_ifc_modify_rq_out_bits {
2074 u8 reserved_at_8[0x18];
2076 u8 reserved_at_40[0x40];
2079 struct mlx5_ifc_query_rq_out_bits {
2081 u8 reserved_at_8[0x18];
2083 u8 reserved_at_40[0xc0];
2084 struct mlx5_ifc_rqc_bits rq_context;
2087 struct mlx5_ifc_query_rq_in_bits {
2089 u8 reserved_at_10[0x10];
2090 u8 reserved_at_20[0x10];
2092 u8 reserved_at_40[0x8];
2094 u8 reserved_at_60[0x20];
2097 struct mlx5_ifc_create_tis_out_bits {
2099 u8 reserved_at_8[0x18];
2101 u8 reserved_at_40[0x8];
2103 u8 reserved_at_60[0x20];
2106 struct mlx5_ifc_create_tis_in_bits {
2109 u8 reserved_at_20[0x10];
2111 u8 reserved_at_40[0xc0];
2112 struct mlx5_ifc_tisc_bits ctx;
2116 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
2117 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
2118 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
2119 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
2122 struct mlx5_ifc_modify_rq_in_bits {
2125 u8 reserved_at_20[0x10];
2128 u8 reserved_at_44[0x4];
2130 u8 reserved_at_60[0x20];
2131 u8 modify_bitmask[0x40];
2132 u8 reserved_at_c0[0x40];
2133 struct mlx5_ifc_rqc_bits ctx;
2137 MLX5_L3_PROT_TYPE_IPV4 = 0,
2138 MLX5_L3_PROT_TYPE_IPV6 = 1,
2142 MLX5_L4_PROT_TYPE_TCP = 0,
2143 MLX5_L4_PROT_TYPE_UDP = 1,
2147 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
2148 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
2149 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
2150 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
2151 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
2154 struct mlx5_ifc_rx_hash_field_select_bits {
2155 u8 l3_prot_type[0x1];
2156 u8 l4_prot_type[0x1];
2157 u8 selected_fields[0x1e];
2161 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2162 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2166 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2167 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2171 MLX5_RX_HASH_FN_NONE = 0x0,
2172 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2173 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2177 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
2178 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
2182 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 = 0x0,
2183 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2 = 0x1,
2186 struct mlx5_ifc_tirc_bits {
2187 u8 reserved_at_0[0x20];
2189 u8 reserved_at_24[0x1c];
2190 u8 reserved_at_40[0x40];
2191 u8 reserved_at_80[0x4];
2192 u8 lro_timeout_period_usecs[0x10];
2193 u8 lro_enable_mask[0x4];
2194 u8 lro_max_msg_sz[0x8];
2195 u8 reserved_at_a0[0x40];
2196 u8 reserved_at_e0[0x8];
2197 u8 inline_rqn[0x18];
2198 u8 rx_hash_symmetric[0x1];
2199 u8 reserved_at_101[0x1];
2200 u8 tunneled_offload_en[0x1];
2201 u8 reserved_at_103[0x5];
2202 u8 indirect_table[0x18];
2204 u8 reserved_at_124[0x2];
2205 u8 self_lb_block[0x2];
2206 u8 transport_domain[0x18];
2207 u8 rx_hash_toeplitz_key[10][0x20];
2208 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2209 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2210 u8 reserved_at_2c0[0x4c0];
2213 struct mlx5_ifc_create_tir_out_bits {
2215 u8 reserved_at_8[0x18];
2217 u8 reserved_at_40[0x8];
2219 u8 reserved_at_60[0x20];
2222 struct mlx5_ifc_create_tir_in_bits {
2225 u8 reserved_at_20[0x10];
2227 u8 reserved_at_40[0xc0];
2228 struct mlx5_ifc_tirc_bits ctx;
2232 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0,
2233 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1,
2234 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2,
2235 /* bit 3 - tunneled_offload_en modify not supported. */
2236 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4,
2239 struct mlx5_ifc_modify_tir_out_bits {
2241 u8 reserved_at_8[0x18];
2243 u8 reserved_at_40[0x40];
2246 struct mlx5_ifc_modify_tir_in_bits {
2249 u8 reserved_at_20[0x10];
2251 u8 reserved_at_40[0x8];
2253 u8 reserved_at_60[0x20];
2254 u8 modify_bitmask[0x40];
2255 u8 reserved_at_c0[0x40];
2256 struct mlx5_ifc_tirc_bits ctx;
2260 MLX5_INLINE_Q_TYPE_RQ = 0x0,
2261 MLX5_INLINE_Q_TYPE_VIRTQ = 0x1,
2264 struct mlx5_ifc_rq_num_bits {
2265 u8 reserved_at_0[0x8];
2269 struct mlx5_ifc_rqtc_bits {
2270 u8 reserved_at_0[0xa5];
2271 u8 list_q_type[0x3];
2272 u8 reserved_at_a8[0x8];
2273 u8 rqt_max_size[0x10];
2274 u8 reserved_at_c0[0x10];
2275 u8 rqt_actual_size[0x10];
2276 u8 reserved_at_e0[0x6a0];
2277 struct mlx5_ifc_rq_num_bits rq_num[];
2280 struct mlx5_ifc_create_rqt_out_bits {
2282 u8 reserved_at_8[0x18];
2284 u8 reserved_at_40[0x8];
2286 u8 reserved_at_60[0x20];
2290 #pragma GCC diagnostic ignored "-Wpedantic"
2292 struct mlx5_ifc_create_rqt_in_bits {
2295 u8 reserved_at_20[0x10];
2297 u8 reserved_at_40[0xc0];
2298 struct mlx5_ifc_rqtc_bits rqt_context;
2301 struct mlx5_ifc_modify_rqt_in_bits {
2304 u8 reserved_at_20[0x10];
2306 u8 reserved_at_40[0x8];
2308 u8 reserved_at_60[0x20];
2309 u8 modify_bitmask[0x40];
2310 u8 reserved_at_c0[0x40];
2311 struct mlx5_ifc_rqtc_bits rqt_context;
2314 #pragma GCC diagnostic error "-Wpedantic"
2317 struct mlx5_ifc_modify_rqt_out_bits {
2319 u8 reserved_at_8[0x18];
2321 u8 reserved_at_40[0x40];
2325 MLX5_SQC_STATE_RST = 0x0,
2326 MLX5_SQC_STATE_RDY = 0x1,
2327 MLX5_SQC_STATE_ERR = 0x3,
2330 struct mlx5_ifc_sqc_bits {
2334 u8 flush_in_error_en[0x1];
2335 u8 allow_multi_pkt_send_wqe[0x1];
2336 u8 min_wqe_inline_mode[0x3];
2342 u8 static_sq_wq[0x1];
2343 u8 reserved_at_11[0x9];
2345 u8 reserved_at_1c[0x4];
2346 u8 reserved_at_20[0x8];
2347 u8 user_index[0x18];
2348 u8 reserved_at_40[0x8];
2350 u8 reserved_at_60[0x8];
2351 u8 hairpin_peer_rq[0x18];
2352 u8 reserved_at_80[0x10];
2353 u8 hairpin_peer_vhca[0x10];
2354 u8 reserved_at_a0[0x50];
2355 u8 packet_pacing_rate_limit_index[0x10];
2356 u8 tis_lst_sz[0x10];
2357 u8 reserved_at_110[0x10];
2358 u8 reserved_at_120[0x40];
2359 u8 reserved_at_160[0x8];
2361 struct mlx5_ifc_wq_bits wq;
2364 struct mlx5_ifc_query_sq_in_bits {
2366 u8 reserved_at_10[0x10];
2367 u8 reserved_at_20[0x10];
2369 u8 reserved_at_40[0x8];
2371 u8 reserved_at_60[0x20];
2374 struct mlx5_ifc_modify_sq_out_bits {
2376 u8 reserved_at_8[0x18];
2378 u8 reserved_at_40[0x40];
2381 struct mlx5_ifc_modify_sq_in_bits {
2384 u8 reserved_at_20[0x10];
2387 u8 reserved_at_44[0x4];
2389 u8 reserved_at_60[0x20];
2390 u8 modify_bitmask[0x40];
2391 u8 reserved_at_c0[0x40];
2392 struct mlx5_ifc_sqc_bits ctx;
2395 struct mlx5_ifc_create_sq_out_bits {
2397 u8 reserved_at_8[0x18];
2399 u8 reserved_at_40[0x8];
2401 u8 reserved_at_60[0x20];
2404 struct mlx5_ifc_create_sq_in_bits {
2407 u8 reserved_at_20[0x10];
2409 u8 reserved_at_40[0xc0];
2410 struct mlx5_ifc_sqc_bits ctx;
2414 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
2415 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
2416 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
2417 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
2418 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
2421 struct mlx5_ifc_flow_meter_parameters_bits {
2423 u8 bucket_overflow[0x1];
2424 u8 start_color[0x2];
2425 u8 both_buckets_on_green[0x1];
2427 u8 reserved_at_1[0x19];
2428 u8 reserved_at_2[0x20];
2429 u8 reserved_at_3[0x3];
2430 u8 cbs_exponent[0x5];
2431 u8 cbs_mantissa[0x8];
2432 u8 reserved_at_4[0x3];
2433 u8 cir_exponent[0x5];
2434 u8 cir_mantissa[0x8];
2435 u8 reserved_at_5[0x20];
2436 u8 reserved_at_6[0x3];
2437 u8 ebs_exponent[0x5];
2438 u8 ebs_mantissa[0x8];
2439 u8 reserved_at_7[0x3];
2440 u8 eir_exponent[0x5];
2441 u8 eir_mantissa[0x8];
2442 u8 reserved_at_8[0x60];
2444 #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF)
2445 #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8
2448 MLX5_METER_MODE_IP_LEN = 0x0,
2449 MLX5_METER_MODE_L2_LEN = 0x1,
2450 MLX5_METER_MODE_L2_IPG_LEN = 0x2,
2451 MLX5_METER_MODE_PKT = 0x3,
2455 MLX5_CQE_SIZE_64B = 0x0,
2456 MLX5_CQE_SIZE_128B = 0x1,
2459 struct mlx5_ifc_cqc_bits {
2462 u8 initiator_src_dct[0x1];
2463 u8 dbr_umem_valid[0x1];
2464 u8 reserved_at_7[0x1];
2467 u8 reserved_at_c[0x1];
2468 u8 scqe_break_moderation_en[0x1];
2470 u8 cq_period_mode[0x2];
2471 u8 cqe_comp_en[0x1];
2472 u8 mini_cqe_res_format[0x2];
2474 u8 reserved_at_18[0x1];
2475 u8 cqe_comp_layout[0x7];
2476 u8 dbr_umem_id[0x20];
2477 u8 reserved_at_40[0x14];
2478 u8 page_offset[0x6];
2479 u8 reserved_at_5a[0x2];
2480 u8 mini_cqe_res_format_ext[0x2];
2481 u8 cq_timestamp_format[0x2];
2482 u8 reserved_at_60[0x3];
2483 u8 log_cq_size[0x5];
2485 u8 reserved_at_80[0x4];
2487 u8 cq_max_count[0x10];
2488 u8 reserved_at_a0[0x18];
2490 u8 reserved_at_c0[0x3];
2491 u8 log_page_size[0x5];
2492 u8 reserved_at_c8[0x18];
2493 u8 reserved_at_e0[0x20];
2494 u8 reserved_at_100[0x8];
2495 u8 last_notified_index[0x18];
2496 u8 reserved_at_120[0x8];
2497 u8 last_solicit_index[0x18];
2498 u8 reserved_at_140[0x8];
2499 u8 consumer_counter[0x18];
2500 u8 reserved_at_160[0x8];
2501 u8 producer_counter[0x18];
2502 u8 local_partition_id[0xc];
2503 u8 process_id[0x14];
2504 u8 reserved_at_1A0[0x20];
2508 struct mlx5_ifc_health_buffer_bits {
2509 u8 reserved_0[0x100];
2510 u8 assert_existptr[0x20];
2511 u8 assert_callra[0x20];
2512 u8 reserved_1[0x40];
2513 u8 fw_version[0x20];
2515 u8 reserved_2[0x20];
2516 u8 irisc_index[0x8];
2521 struct mlx5_ifc_initial_seg_bits {
2522 u8 fw_rev_minor[0x10];
2523 u8 fw_rev_major[0x10];
2524 u8 cmd_interface_rev[0x10];
2525 u8 fw_rev_subminor[0x10];
2526 u8 reserved_0[0x40];
2527 u8 cmdq_phy_addr_63_32[0x20];
2528 u8 cmdq_phy_addr_31_12[0x14];
2530 u8 nic_interface[0x2];
2531 u8 log_cmdq_size[0x4];
2532 u8 log_cmdq_stride[0x4];
2533 u8 command_doorbell_vector[0x20];
2534 u8 reserved_2[0xf00];
2535 u8 initializing[0x1];
2536 u8 nic_interface_supported[0x7];
2537 u8 reserved_4[0x18];
2538 struct mlx5_ifc_health_buffer_bits health_buffer;
2539 u8 no_dram_nic_offset[0x20];
2540 u8 reserved_5[0x6de0];
2541 u8 internal_timer_h[0x20];
2542 u8 internal_timer_l[0x20];
2543 u8 reserved_6[0x20];
2544 u8 reserved_7[0x1f];
2546 u8 health_syndrome[0x8];
2547 u8 health_counter[0x18];
2548 u8 reserved_8[0x17fc0];
2551 struct mlx5_ifc_create_cq_out_bits {
2553 u8 reserved_at_8[0x18];
2555 u8 reserved_at_40[0x8];
2557 u8 reserved_at_60[0x20];
2560 struct mlx5_ifc_create_cq_in_bits {
2563 u8 reserved_at_20[0x10];
2565 u8 reserved_at_40[0x40];
2566 struct mlx5_ifc_cqc_bits cq_context;
2567 u8 cq_umem_offset[0x40];
2568 u8 cq_umem_id[0x20];
2569 u8 cq_umem_valid[0x1];
2570 u8 reserved_at_2e1[0x1f];
2571 u8 reserved_at_300[0x580];
2576 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
2577 MLX5_GENERAL_OBJ_TYPE_DEK = 0x000c,
2578 MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
2579 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
2580 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d,
2581 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL = 0x001e,
2582 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN = 0x001f,
2583 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,
2584 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024,
2585 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025,
2588 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
2590 u8 reserved_at_10[0x20];
2593 u8 reserved_at_60[0x3];
2594 u8 log_obj_range[0x5];
2595 u8 reserved_at_58[0x18];
2598 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
2600 u8 reserved_at_8[0x18];
2603 u8 reserved_at_60[0x20];
2606 struct mlx5_ifc_virtio_q_counters_bits {
2607 u8 modify_field_select[0x40];
2608 u8 reserved_at_40[0x40];
2609 u8 received_desc[0x40];
2610 u8 completed_desc[0x40];
2611 u8 error_cqes[0x20];
2612 u8 bad_desc_errors[0x20];
2613 u8 exceed_max_chain[0x20];
2614 u8 invalid_buffer[0x20];
2615 u8 reserved_at_180[0x50];
2618 struct mlx5_ifc_geneve_tlv_option_bits {
2619 u8 modify_field_select[0x40];
2620 u8 reserved_at_40[0x18];
2621 u8 geneve_option_fte_index[0x8];
2622 u8 option_class[0x10];
2623 u8 option_type[0x8];
2624 u8 reserved_at_78[0x3];
2625 u8 option_data_length[0x5];
2626 u8 reserved_at_80[0x180];
2629 struct mlx5_ifc_create_virtio_q_counters_in_bits {
2630 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2631 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2634 struct mlx5_ifc_query_virtio_q_counters_out_bits {
2635 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2636 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2639 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
2640 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2641 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
2645 MLX5_CRYPTO_KEY_SIZE_128b = 0x0,
2646 MLX5_CRYPTO_KEY_SIZE_256b = 0x1,
2650 MLX5_CRYPTO_KEY_PURPOSE_TLS = 0x1,
2651 MLX5_CRYPTO_KEY_PURPOSE_IPSEC = 0x2,
2652 MLX5_CRYPTO_KEY_PURPOSE_AES_XTS = 0x3,
2653 MLX5_CRYPTO_KEY_PURPOSE_MACSEC = 0x4,
2654 MLX5_CRYPTO_KEY_PURPOSE_GCM = 0x5,
2655 MLX5_CRYPTO_KEY_PURPOSE_PSP = 0x6,
2658 struct mlx5_ifc_dek_bits {
2659 u8 modify_field_select[0x40];
2661 u8 reserved_at_48[0xc];
2664 u8 reserved_at_59[0x3];
2665 u8 key_purpose[0x4];
2666 u8 reserved_at_60[0x8];
2668 u8 reserved_at_80[0x100];
2670 u8 reserved_at_1c0[0x40];
2672 u8 reserved_at_600[0x200];
2675 struct mlx5_ifc_create_dek_in_bits {
2676 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2677 struct mlx5_ifc_dek_bits dek;
2680 struct mlx5_ifc_import_kek_bits {
2681 u8 modify_field_select[0x40];
2683 u8 reserved_at_48[0xc];
2685 u8 reserved_at_58[0x1a8];
2687 u8 reserved_at_600[0x200];
2690 struct mlx5_ifc_create_import_kek_in_bits {
2691 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2692 struct mlx5_ifc_import_kek_bits import_kek;
2696 MLX5_CREDENTIAL_ROLE_OFFICER = 0x0,
2697 MLX5_CREDENTIAL_ROLE_USER = 0x1,
2700 struct mlx5_ifc_credential_bits {
2701 u8 modify_field_select[0x40];
2703 u8 reserved_at_48[0x10];
2704 u8 credential_role[0x8];
2705 u8 reserved_at_60[0x1a0];
2706 u8 credential[0x180];
2707 u8 reserved_at_380[0x480];
2710 struct mlx5_ifc_create_credential_in_bits {
2711 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2712 struct mlx5_ifc_credential_bits credential;
2715 struct mlx5_ifc_crypto_login_bits {
2716 u8 modify_field_select[0x40];
2717 u8 reserved_at_40[0x48];
2718 u8 credential_pointer[0x18];
2719 u8 reserved_at_a0[0x8];
2720 u8 session_import_kek_ptr[0x18];
2721 u8 reserved_at_c0[0x140];
2722 u8 credential[0x180];
2723 u8 reserved_at_380[0x480];
2726 struct mlx5_ifc_create_crypto_login_in_bits {
2727 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2728 struct mlx5_ifc_crypto_login_bits crypto_login;
2732 MLX5_VIRTQ_STATE_INIT = 0,
2733 MLX5_VIRTQ_STATE_RDY = 1,
2734 MLX5_VIRTQ_STATE_SUSPEND = 2,
2735 MLX5_VIRTQ_STATE_ERROR = 3,
2739 MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),
2740 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),
2741 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),
2744 struct mlx5_ifc_virtio_q_bits {
2745 u8 virtio_q_type[0x8];
2746 u8 reserved_at_8[0x5];
2748 u8 queue_index[0x10];
2749 u8 full_emulation[0x1];
2750 u8 virtio_version_1_0[0x1];
2751 u8 reserved_at_22[0x2];
2752 u8 offload_type[0x4];
2753 u8 event_qpn_or_msix[0x18];
2754 u8 doorbell_stride_idx[0x10];
2755 u8 queue_size[0x10];
2756 u8 device_emulation_id[0x20];
2759 u8 available_addr[0x40];
2760 u8 virtio_q_mkey[0x20];
2761 u8 reserved_at_160[0x18];
2764 u8 umem_1_size[0x20];
2765 u8 umem_1_offset[0x40];
2767 u8 umem_2_size[0x20];
2768 u8 umem_2_offset[0x40];
2770 u8 umem_3_size[0x20];
2771 u8 umem_3_offset[0x40];
2772 u8 counter_set_id[0x20];
2773 u8 reserved_at_320[0x8];
2775 u8 reserved_at_340[0x2];
2776 u8 queue_period_mode[0x2];
2777 u8 queue_period_us[0xc];
2778 u8 queue_max_count[0x10];
2779 u8 reserved_at_360[0xa0];
2782 struct mlx5_ifc_virtio_net_q_bits {
2783 u8 modify_field_select[0x40];
2784 u8 reserved_at_40[0x40];
2789 u8 reserved_at_84[0x6];
2790 u8 dirty_bitmap_dump_enable[0x1];
2791 u8 vhost_log_page[0x5];
2792 u8 reserved_at_90[0xc];
2794 u8 reserved_at_a0[0x8];
2795 u8 tisn_or_qpn[0x18];
2796 u8 dirty_bitmap_mkey[0x20];
2797 u8 dirty_bitmap_size[0x20];
2798 u8 dirty_bitmap_addr[0x40];
2799 u8 hw_available_index[0x10];
2800 u8 hw_used_index[0x10];
2801 u8 reserved_at_160[0xa0];
2802 struct mlx5_ifc_virtio_q_bits virtio_q_context;
2805 struct mlx5_ifc_create_virtq_in_bits {
2806 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2807 struct mlx5_ifc_virtio_net_q_bits virtq;
2810 struct mlx5_ifc_query_virtq_out_bits {
2811 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2812 struct mlx5_ifc_virtio_net_q_bits virtq;
2815 struct mlx5_ifc_flow_hit_aso_bits {
2816 u8 modify_field_select[0x40];
2817 u8 reserved_at_40[0x48];
2819 u8 reserved_at_a0[0x160];
2823 struct mlx5_ifc_create_flow_hit_aso_in_bits {
2824 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2825 struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso;
2828 struct mlx5_ifc_flow_meter_aso_bits {
2829 u8 modify_field_select[0x40];
2830 u8 reserved_at_40[0x48];
2832 u8 reserved_at_a0[0x160];
2833 u8 parameters[0x200];
2836 struct mlx5_ifc_create_flow_meter_aso_in_bits {
2837 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2838 struct mlx5_ifc_flow_meter_aso_bits flow_meter_aso;
2840 enum mlx5_access_aso_opc_mod {
2841 ASO_OPC_MOD_IPSEC = 0x0,
2842 ASO_OPC_MOD_CONNECTION_TRACKING = 0x1,
2843 ASO_OPC_MOD_POLICER = 0x2,
2844 ASO_OPC_MOD_RACE_AVOIDANCE = 0x3,
2845 ASO_OPC_MOD_FLOW_HIT = 0x4,
2848 #define ASO_CSEG_DATA_MASK_MODE_OFFSET 30
2850 enum mlx5_aso_data_mask_mode {
2851 BITWISE_64BIT = 0x0,
2852 BYTEWISE_64BYTE = 0x1,
2853 CALCULATED_64BYTE = 0x2,
2856 #define ASO_CSEG_COND_0_OPER_OFFSET 20
2857 #define ASO_CSEG_COND_1_OPER_OFFSET 16
2859 enum mlx5_aso_pre_cond_op {
2860 ASO_OP_ALWAYS_FALSE = 0x0,
2861 ASO_OP_ALWAYS_TRUE = 0x1,
2863 ASO_OP_NOT_EQUAL = 0x3,
2864 ASO_OP_GREATER_OR_EQUAL = 0x4,
2865 ASO_OP_LESSER_OR_EQUAL = 0x5,
2866 ASO_OP_LESSER = 0x6,
2867 ASO_OP_GREATER = 0x7,
2868 ASO_OP_CYCLIC_GREATER = 0x8,
2869 ASO_OP_CYCLIC_LESSER = 0x9,
2872 #define ASO_CSEG_COND_OPER_OFFSET 6
2875 ASO_OPER_LOGICAL_AND = 0x0,
2876 ASO_OPER_LOGICAL_OR = 0x1,
2879 /* ASO WQE CTRL segment. */
2880 struct mlx5_aso_cseg {
2884 uint32_t operand_masks;
2885 uint32_t condition_0_data;
2886 uint32_t condition_0_mask;
2887 uint32_t condition_1_data;
2888 uint32_t condition_1_mask;
2889 uint64_t bitwise_data;
2893 /* A meter data segment - 2 per ASO WQE. */
2894 struct mlx5_aso_mtr_dseg {
2895 uint32_t v_bo_sc_bbog_mm;
2897 * bit 31: valid, 30: bucket overflow, 28-29: start color,
2898 * 27: both buckets on green, 24-25: meter mode.
2903 * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa,
2904 * bit 8-12: cir_exponent, bit 0-7 cir_mantissa.
2909 * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa,
2910 * bit 8-12: eir_exponent, bit 0-7 eir_mantissa.
2916 #define ASO_DSEG_VALID_OFFSET 31
2917 #define ASO_DSEG_BO_OFFSET 30
2918 #define ASO_DSEG_SC_OFFSET 28
2919 #define ASO_DSEG_MTR_MODE 24
2920 #define ASO_DSEG_CBS_EXP_OFFSET 24
2921 #define ASO_DSEG_CBS_MAN_OFFSET 16
2922 #define ASO_DSEG_CIR_EXP_MASK 0x1F
2923 #define ASO_DSEG_CIR_EXP_OFFSET 8
2924 #define ASO_DSEG_EBS_EXP_OFFSET 24
2925 #define ASO_DSEG_EBS_MAN_OFFSET 16
2926 #define ASO_DSEG_EXP_MASK 0x1F
2927 #define ASO_DSEG_MAN_MASK 0xFF
2929 #define MLX5_ASO_WQE_DSEG_SIZE 0x40
2930 #define MLX5_ASO_METERS_PER_WQE 2
2931 #define MLX5_ASO_MTRS_PER_POOL 128
2933 /* ASO WQE data segment. */
2934 struct mlx5_aso_dseg {
2936 uint8_t data[MLX5_ASO_WQE_DSEG_SIZE];
2937 struct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE];
2942 struct mlx5_aso_wqe {
2943 struct mlx5_wqe_cseg general_cseg;
2944 struct mlx5_aso_cseg aso_cseg;
2945 struct mlx5_aso_dseg aso_dseg;
2949 MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
2953 MLX5_QP_ST_RC = 0x0,
2957 MLX5_QP_PM_MIGRATED = 0x3,
2961 MLX5_NON_ZERO_RQ = 0x0,
2964 MLX5_ZERO_LEN_RQ = 0x3,
2967 struct mlx5_ifc_ads_bits {
2970 u8 reserved_at_2[0xe];
2971 u8 pkey_index[0x10];
2972 u8 reserved_at_20[0x8];
2976 u8 ack_timeout[0x5];
2977 u8 reserved_at_45[0x3];
2978 u8 src_addr_index[0x8];
2979 u8 reserved_at_50[0x4];
2982 u8 reserved_at_60[0x4];
2984 u8 flow_label[0x14];
2985 u8 rgid_rip[16][0x8];
2986 u8 reserved_at_100[0x4];
2989 u8 reserved_at_106[0x1];
2997 u8 vhca_port_num[0x8];
2998 u8 rmac_47_32[0x10];
3002 struct mlx5_ifc_qpc_bits {
3004 u8 lag_tx_port_affinity[0x4];
3006 u8 reserved_at_10[0x3];
3008 u8 reserved_at_15[0x1];
3009 u8 req_e2e_credit_mode[0x2];
3010 u8 offload_type[0x4];
3011 u8 end_padding_mode[0x2];
3012 u8 reserved_at_1e[0x2];
3013 u8 wq_signature[0x1];
3014 u8 block_lb_mc[0x1];
3015 u8 atomic_like_write_en[0x1];
3016 u8 latency_sensitive[0x1];
3017 u8 reserved_at_24[0x1];
3018 u8 drain_sigerr[0x1];
3019 u8 reserved_at_26[0x2];
3022 u8 log_msg_max[0x5];
3023 u8 reserved_at_48[0x1];
3024 u8 log_rq_size[0x4];
3025 u8 log_rq_stride[0x3];
3027 u8 log_sq_size[0x4];
3028 u8 reserved_at_55[0x3];
3030 u8 reserved_at_5a[0x1];
3032 u8 ulp_stateless_offload_mode[0x4];
3033 u8 counter_set_id[0x8];
3035 u8 reserved_at_80[0x8];
3036 u8 user_index[0x18];
3037 u8 reserved_at_a0[0x3];
3038 u8 log_page_size[0x5];
3039 u8 remote_qpn[0x18];
3040 struct mlx5_ifc_ads_bits primary_address_path;
3041 struct mlx5_ifc_ads_bits secondary_address_path;
3042 u8 log_ack_req_freq[0x4];
3043 u8 reserved_at_384[0x4];
3044 u8 log_sra_max[0x3];
3045 u8 reserved_at_38b[0x2];
3046 u8 retry_count[0x3];
3048 u8 reserved_at_393[0x1];
3050 u8 cur_rnr_retry[0x3];
3051 u8 cur_retry_count[0x3];
3052 u8 reserved_at_39b[0x5];
3053 u8 reserved_at_3a0[0x20];
3054 u8 reserved_at_3c0[0x8];
3055 u8 next_send_psn[0x18];
3056 u8 reserved_at_3e0[0x8];
3058 u8 reserved_at_400[0x8];
3060 u8 reserved_at_420[0x20];
3061 u8 reserved_at_440[0x8];
3062 u8 last_acked_psn[0x18];
3063 u8 reserved_at_460[0x8];
3065 u8 reserved_at_480[0x8];
3066 u8 log_rra_max[0x3];
3067 u8 reserved_at_48b[0x1];
3068 u8 atomic_mode[0x4];
3072 u8 reserved_at_493[0x1];
3073 u8 page_offset[0x6];
3074 u8 reserved_at_49a[0x3];
3075 u8 cd_slave_receive[0x1];
3076 u8 cd_slave_send[0x1];
3078 u8 reserved_at_4a0[0x3];
3079 u8 min_rnr_nak[0x5];
3080 u8 next_rcv_psn[0x18];
3081 u8 reserved_at_4c0[0x8];
3083 u8 reserved_at_4e0[0x8];
3087 u8 reserved_at_560[0x5];
3089 u8 srqn_rmpn_xrqn[0x18];
3090 u8 reserved_at_580[0x8];
3092 u8 hw_sq_wqebb_counter[0x10];
3093 u8 sw_sq_wqebb_counter[0x10];
3094 u8 hw_rq_counter[0x20];
3095 u8 sw_rq_counter[0x20];
3096 u8 reserved_at_600[0x20];
3097 u8 reserved_at_620[0xf];
3101 u8 dc_access_key[0x40];
3102 u8 reserved_at_680[0x3];
3103 u8 dbr_umem_valid[0x1];
3104 u8 reserved_at_684[0x9c];
3105 u8 dbr_umem_id[0x20];
3108 struct mlx5_ifc_create_qp_out_bits {
3110 u8 reserved_at_8[0x18];
3112 u8 reserved_at_40[0x8];
3114 u8 reserved_at_60[0x20];
3118 #pragma GCC diagnostic ignored "-Wpedantic"
3120 struct mlx5_ifc_create_qp_in_bits {
3123 u8 reserved_at_20[0x10];
3125 u8 reserved_at_40[0x40];
3126 u8 opt_param_mask[0x20];
3127 u8 reserved_at_a0[0x20];
3128 struct mlx5_ifc_qpc_bits qpc;
3129 u8 wq_umem_offset[0x40];
3130 u8 wq_umem_id[0x20];
3131 u8 wq_umem_valid[0x1];
3132 u8 reserved_at_861[0x1f];
3136 #pragma GCC diagnostic error "-Wpedantic"
3139 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3141 u8 reserved_at_8[0x18];
3143 u8 reserved_at_40[0x40];
3146 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3149 u8 reserved_at_20[0x10];
3151 u8 reserved_at_40[0x8];
3153 u8 reserved_at_60[0x20];
3154 u8 opt_param_mask[0x20];
3155 u8 reserved_at_a0[0x20];
3156 struct mlx5_ifc_qpc_bits qpc;
3157 u8 reserved_at_800[0x80];
3160 struct mlx5_ifc_sqd2rts_qp_out_bits {
3162 u8 reserved_at_8[0x18];
3164 u8 reserved_at_40[0x40];
3167 struct mlx5_ifc_sqd2rts_qp_in_bits {
3170 u8 reserved_at_20[0x10];
3172 u8 reserved_at_40[0x8];
3174 u8 reserved_at_60[0x20];
3175 u8 opt_param_mask[0x20];
3176 u8 reserved_at_a0[0x20];
3177 struct mlx5_ifc_qpc_bits qpc;
3178 u8 reserved_at_800[0x80];
3181 struct mlx5_ifc_rts2rts_qp_out_bits {
3183 u8 reserved_at_8[0x18];
3185 u8 reserved_at_40[0x40];
3188 struct mlx5_ifc_rts2rts_qp_in_bits {
3191 u8 reserved_at_20[0x10];
3193 u8 reserved_at_40[0x8];
3195 u8 reserved_at_60[0x20];
3196 u8 opt_param_mask[0x20];
3197 u8 reserved_at_a0[0x20];
3198 struct mlx5_ifc_qpc_bits qpc;
3199 u8 reserved_at_800[0x80];
3202 struct mlx5_ifc_rtr2rts_qp_out_bits {
3204 u8 reserved_at_8[0x18];
3206 u8 reserved_at_40[0x40];
3209 struct mlx5_ifc_rtr2rts_qp_in_bits {
3212 u8 reserved_at_20[0x10];
3214 u8 reserved_at_40[0x8];
3216 u8 reserved_at_60[0x20];
3217 u8 opt_param_mask[0x20];
3218 u8 reserved_at_a0[0x20];
3219 struct mlx5_ifc_qpc_bits qpc;
3220 u8 reserved_at_800[0x80];
3223 struct mlx5_ifc_rst2init_qp_out_bits {
3225 u8 reserved_at_8[0x18];
3227 u8 reserved_at_40[0x40];
3230 struct mlx5_ifc_rst2init_qp_in_bits {
3233 u8 reserved_at_20[0x10];
3235 u8 reserved_at_40[0x8];
3237 u8 reserved_at_60[0x20];
3238 u8 opt_param_mask[0x20];
3239 u8 reserved_at_a0[0x20];
3240 struct mlx5_ifc_qpc_bits qpc;
3241 u8 reserved_at_800[0x80];
3244 struct mlx5_ifc_init2rtr_qp_out_bits {
3246 u8 reserved_at_8[0x18];
3248 u8 reserved_at_40[0x40];
3251 struct mlx5_ifc_init2rtr_qp_in_bits {
3254 u8 reserved_at_20[0x10];
3256 u8 reserved_at_40[0x8];
3258 u8 reserved_at_60[0x20];
3259 u8 opt_param_mask[0x20];
3260 u8 reserved_at_a0[0x20];
3261 struct mlx5_ifc_qpc_bits qpc;
3262 u8 reserved_at_800[0x80];
3265 struct mlx5_ifc_init2init_qp_out_bits {
3267 u8 reserved_at_8[0x18];
3269 u8 reserved_at_40[0x40];
3272 struct mlx5_ifc_init2init_qp_in_bits {
3275 u8 reserved_at_20[0x10];
3277 u8 reserved_at_40[0x8];
3279 u8 reserved_at_60[0x20];
3280 u8 opt_param_mask[0x20];
3281 u8 reserved_at_a0[0x20];
3282 struct mlx5_ifc_qpc_bits qpc;
3283 u8 reserved_at_800[0x80];
3286 struct mlx5_ifc_dealloc_pd_out_bits {
3288 u8 reserved_0[0x18];
3290 u8 reserved_1[0x40];
3293 struct mlx5_ifc_dealloc_pd_in_bits {
3295 u8 reserved_0[0x10];
3296 u8 reserved_1[0x10];
3300 u8 reserved_3[0x20];
3303 struct mlx5_ifc_alloc_pd_out_bits {
3305 u8 reserved_0[0x18];
3309 u8 reserved_2[0x20];
3312 struct mlx5_ifc_alloc_pd_in_bits {
3314 u8 reserved_0[0x10];
3315 u8 reserved_1[0x10];
3317 u8 reserved_2[0x40];
3321 #pragma GCC diagnostic ignored "-Wpedantic"
3323 struct mlx5_ifc_query_qp_out_bits {
3325 u8 reserved_at_8[0x18];
3327 u8 reserved_at_40[0x40];
3328 u8 opt_param_mask[0x20];
3329 u8 reserved_at_a0[0x20];
3330 struct mlx5_ifc_qpc_bits qpc;
3331 u8 reserved_at_800[0x80];
3335 #pragma GCC diagnostic error "-Wpedantic"
3338 struct mlx5_ifc_query_qp_in_bits {
3340 u8 reserved_at_10[0x10];
3341 u8 reserved_at_20[0x10];
3343 u8 reserved_at_40[0x8];
3345 u8 reserved_at_60[0x20];
3349 MLX5_DATA_RATE = 0x0,
3350 MLX5_WQE_RATE = 0x1,
3353 struct mlx5_ifc_set_pp_rate_limit_context_bits {
3354 u8 rate_limit[0x20];
3355 u8 burst_upper_bound[0x20];
3356 u8 reserved_at_40[0xC];
3358 u8 typical_packet_size[0x10];
3359 u8 reserved_at_60[0x120];
3362 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u
3365 #pragma GCC diagnostic ignored "-Wpedantic"
3367 struct mlx5_ifc_access_register_out_bits {
3369 u8 reserved_at_8[0x18];
3371 u8 reserved_at_40[0x40];
3372 u8 register_data[0][0x20];
3375 struct mlx5_ifc_access_register_in_bits {
3377 u8 reserved_at_10[0x10];
3378 u8 reserved_at_20[0x10];
3380 u8 reserved_at_40[0x10];
3381 u8 register_id[0x10];
3383 u8 register_data[0][0x20];
3386 #pragma GCC diagnostic error "-Wpedantic"
3390 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
3391 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
3395 MLX5_REGISTER_ID_MTUTC = 0x9055,
3396 MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002,
3397 MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003,
3398 MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004,
3399 MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005,
3402 struct mlx5_ifc_register_mtutc_bits {
3403 u8 time_stamp_mode[0x2];
3404 u8 time_stamp_state[0x2];
3405 u8 reserved_at_4[0x18];
3407 u8 freq_adjustment[0x20];
3408 u8 reserved_at_40[0x40];
3411 u8 time_adjustment[0x20];
3414 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0
3415 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1
3417 struct mlx5_ifc_crypto_operational_register_bits {
3418 u8 wrapped_crypto_operational[0x1];
3419 u8 reserved_at_1[0x1b];
3421 u8 reserved_at_20[0x20];
3422 u8 credential[0x140];
3424 u8 reserved_at_280[0x180];
3427 struct mlx5_ifc_crypto_commissioning_register_bits {
3428 u8 token[0x1]; /* TODO: add size after PRM update */
3431 struct mlx5_ifc_import_kek_handle_register_bits {
3432 struct mlx5_ifc_crypto_login_bits crypto_login_object;
3433 struct mlx5_ifc_import_kek_bits import_kek_object;
3434 u8 reserved_at_200[0x4];
3435 u8 write_operation[0x4];
3436 u8 import_kek_id[0x18];
3437 u8 reserved_at_220[0xe0];
3440 struct mlx5_ifc_credential_handle_register_bits {
3441 struct mlx5_ifc_crypto_login_bits crypto_login_object;
3442 struct mlx5_ifc_credential_bits credential_object;
3443 u8 reserved_at_200[0x4];
3444 u8 write_operation[0x4];
3445 u8 credential_id[0x18];
3446 u8 reserved_at_220[0xe0];
3450 MLX5_REGISTER_ADD_OPERATION = 0x1,
3451 MLX5_REGISTER_DELETE_OPERATION = 0x2,
3454 struct mlx5_ifc_parse_graph_arc_bits {
3455 u8 start_inner_tunnel[0x1];
3456 u8 reserved_at_1[0x7];
3457 u8 arc_parse_graph_node[0x8];
3458 u8 compare_condition_value[0x10];
3459 u8 parse_graph_node_handle[0x20];
3460 u8 reserved_at_40[0x40];
3463 struct mlx5_ifc_parse_graph_flow_match_sample_bits {
3464 u8 flow_match_sample_en[0x1];
3465 u8 reserved_at_1[0x3];
3466 u8 flow_match_sample_offset_mode[0x4];
3467 u8 reserved_at_5[0x8];
3468 u8 flow_match_sample_field_offset[0x10];
3469 u8 reserved_at_32[0x4];
3470 u8 flow_match_sample_field_offset_shift[0x4];
3471 u8 flow_match_sample_field_base_offset[0x8];
3472 u8 reserved_at_48[0xd];
3473 u8 flow_match_sample_tunnel_mode[0x3];
3474 u8 flow_match_sample_field_offset_mask[0x20];
3475 u8 flow_match_sample_field_id[0x20];
3478 struct mlx5_ifc_parse_graph_flex_bits {
3479 u8 modify_field_select[0x40];
3480 u8 reserved_at_64[0x20];
3481 u8 header_length_base_value[0x10];
3482 u8 reserved_at_112[0x4];
3483 u8 header_length_field_shift[0x4];
3484 u8 reserved_at_120[0x4];
3485 u8 header_length_mode[0x4];
3486 u8 header_length_field_offset[0x10];
3487 u8 next_header_field_offset[0x10];
3488 u8 reserved_at_160[0x1b];
3489 u8 next_header_field_size[0x5];
3490 u8 header_length_field_mask[0x20];
3491 u8 reserved_at_224[0x20];
3492 struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8];
3493 struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8];
3494 struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8];
3497 struct mlx5_ifc_create_flex_parser_in_bits {
3498 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3499 struct mlx5_ifc_parse_graph_flex_bits flex;
3502 struct mlx5_ifc_create_flex_parser_out_bits {
3503 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3504 struct mlx5_ifc_parse_graph_flex_bits flex;
3507 struct mlx5_ifc_parse_graph_flex_out_bits {
3509 u8 reserved_at_8[0x18];
3511 u8 reserved_at_40[0x40];
3512 struct mlx5_ifc_parse_graph_flex_bits capability;
3515 struct regexp_params_field_select_bits {
3516 u8 reserved_at_0[0x1e];
3517 u8 stop_engine[0x1];
3521 struct mlx5_ifc_regexp_params_bits {
3522 u8 reserved_at_0[0x1f];
3523 u8 stop_engine[0x1];
3524 u8 db_umem_id[0x20];
3525 u8 db_umem_offset[0x40];
3526 u8 reserved_at_80[0x100];
3529 struct mlx5_ifc_set_regexp_params_in_bits {
3532 u8 reserved_at_20[0x10];
3534 u8 reserved_at_40[0x18];
3536 struct regexp_params_field_select_bits field_select;
3537 struct mlx5_ifc_regexp_params_bits regexp_params;
3540 struct mlx5_ifc_set_regexp_params_out_bits {
3542 u8 reserved_at_8[0x18];
3544 u8 reserved_at_18[0x40];
3547 struct mlx5_ifc_query_regexp_params_in_bits {
3550 u8 reserved_at_20[0x10];
3552 u8 reserved_at_40[0x18];
3557 struct mlx5_ifc_query_regexp_params_out_bits {
3559 u8 reserved_at_8[0x18];
3562 struct mlx5_ifc_regexp_params_bits regexp_params;
3565 struct mlx5_ifc_set_regexp_register_in_bits {
3568 u8 reserved_at_20[0x10];
3570 u8 reserved_at_40[0x18];
3572 u8 register_address[0x20];
3573 u8 register_data[0x20];
3577 struct mlx5_ifc_set_regexp_register_out_bits {
3579 u8 reserved_at_8[0x18];
3584 struct mlx5_ifc_query_regexp_register_in_bits {
3587 u8 reserved_at_20[0x10];
3589 u8 reserved_at_40[0x18];
3591 u8 register_address[0x20];
3594 struct mlx5_ifc_query_regexp_register_out_bits {
3596 u8 reserved_at_8[0x18];
3599 u8 register_data[0x20];
3602 /* Queue counters. */
3603 struct mlx5_ifc_alloc_q_counter_out_bits {
3605 u8 reserved_at_8[0x18];
3607 u8 reserved_at_40[0x18];
3608 u8 counter_set_id[0x8];
3609 u8 reserved_at_60[0x20];
3612 struct mlx5_ifc_alloc_q_counter_in_bits {
3615 u8 reserved_at_20[0x10];
3617 u8 reserved_at_40[0x40];
3620 struct mlx5_ifc_query_q_counter_out_bits {
3622 u8 reserved_at_8[0x18];
3624 u8 reserved_at_40[0x40];
3625 u8 rx_write_requests[0x20];
3626 u8 reserved_at_a0[0x20];
3627 u8 rx_read_requests[0x20];
3628 u8 reserved_at_e0[0x20];
3629 u8 rx_atomic_requests[0x20];
3630 u8 reserved_at_120[0x20];
3631 u8 rx_dct_connect[0x20];
3632 u8 reserved_at_160[0x20];
3633 u8 out_of_buffer[0x20];
3634 u8 reserved_at_1a0[0x20];
3635 u8 out_of_sequence[0x20];
3636 u8 reserved_at_1e0[0x20];
3637 u8 duplicate_request[0x20];
3638 u8 reserved_at_220[0x20];
3639 u8 rnr_nak_retry_err[0x20];
3640 u8 reserved_at_260[0x20];
3641 u8 packet_seq_err[0x20];
3642 u8 reserved_at_2a0[0x20];
3643 u8 implied_nak_seq_err[0x20];
3644 u8 reserved_at_2e0[0x20];
3645 u8 local_ack_timeout_err[0x20];
3646 u8 reserved_at_320[0xa0];
3647 u8 resp_local_length_error[0x20];
3648 u8 req_local_length_error[0x20];
3649 u8 resp_local_qp_error[0x20];
3650 u8 local_operation_error[0x20];
3651 u8 resp_local_protection[0x20];
3652 u8 req_local_protection[0x20];
3653 u8 resp_cqe_error[0x20];
3654 u8 req_cqe_error[0x20];
3655 u8 req_mw_binding[0x20];
3656 u8 req_bad_response[0x20];
3657 u8 req_remote_invalid_request[0x20];
3658 u8 resp_remote_invalid_request[0x20];
3659 u8 req_remote_access_errors[0x20];
3660 u8 resp_remote_access_errors[0x20];
3661 u8 req_remote_operation_errors[0x20];
3662 u8 req_transport_retries_exceeded[0x20];
3663 u8 cq_overflow[0x20];
3664 u8 resp_cqe_flush_error[0x20];
3665 u8 req_cqe_flush_error[0x20];
3666 u8 reserved_at_620[0x1e0];
3669 struct mlx5_ifc_query_q_counter_in_bits {
3672 u8 reserved_at_20[0x10];
3674 u8 reserved_at_40[0x80];
3676 u8 reserved_at_c1[0x1f];
3677 u8 reserved_at_e0[0x18];
3678 u8 counter_set_id[0x8];
3681 /* CQE format mask. */
3682 #define MLX5E_CQE_FORMAT_MASK 0xc
3685 #define MLX5_OPC_MOD_MPW 0x01
3687 /* Compressed Rx CQE structure. */
3688 struct mlx5_mini_cqe8 {
3690 uint32_t rx_hash_result;
3694 uint16_t flow_tag_high;
3700 uint16_t stride_idx;
3703 uint16_t wqe_counter;
3704 uint8_t s_wqe_opcode;
3709 uint32_t byte_cnt_flow;
3714 /* Mini CQE responder format. */
3716 MLX5_CQE_RESP_FORMAT_HASH = 0x0,
3717 MLX5_CQE_RESP_FORMAT_CSUM = 0x1,
3718 MLX5_CQE_RESP_FORMAT_FTAG_STRIDX = 0x2,
3719 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3,
3720 MLX5_CQE_RESP_FORMAT_L34H_STRIDX = 0x4,
3723 /* srTCM PRM flow meter parameters. */
3725 MLX5_FLOW_COLOR_RED = 0,
3726 MLX5_FLOW_COLOR_YELLOW,
3727 MLX5_FLOW_COLOR_GREEN,
3728 MLX5_FLOW_COLOR_UNDEFINED,
3731 /* Maximum value of srTCM metering parameters. */
3732 #define MLX5_SRTCM_CBS_MAX (0xFF * (1ULL << 0x1F))
3733 #define MLX5_SRTCM_CIR_MAX (8 * (1ULL << 30) * 0xFF)
3734 #define MLX5_SRTCM_EBS_MAX 0
3736 /* The bits meter color use. */
3737 #define MLX5_MTR_COLOR_BITS 8
3739 /* The bit size of one register. */
3740 #define MLX5_REG_BITS 32
3742 /* Idle bits for non-color usage in color register. */
3743 #define MLX5_MTR_IDLE_BITS_IN_COLOR_REG (MLX5_REG_BITS - MLX5_MTR_COLOR_BITS)
3745 /* Length mode of dynamic flex parser graph node. */
3746 enum mlx5_parse_graph_node_len_mode {
3747 MLX5_GRAPH_NODE_LEN_FIXED = 0x0,
3748 MLX5_GRAPH_NODE_LEN_FIELD = 0x1,
3749 MLX5_GRAPH_NODE_LEN_BITMASK = 0x2,
3752 /* Offset mode of the samples of flex parser. */
3753 enum mlx5_parse_graph_flow_match_sample_offset_mode {
3754 MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0,
3755 MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1,
3756 MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2,
3759 /* Node index for an input / output arc of the flex parser graph. */
3760 enum mlx5_parse_graph_arc_node_index {
3761 MLX5_GRAPH_ARC_NODE_NULL = 0x0,
3762 MLX5_GRAPH_ARC_NODE_HEAD = 0x1,
3763 MLX5_GRAPH_ARC_NODE_MAC = 0x2,
3764 MLX5_GRAPH_ARC_NODE_IP = 0x3,
3765 MLX5_GRAPH_ARC_NODE_GRE = 0x4,
3766 MLX5_GRAPH_ARC_NODE_UDP = 0x5,
3767 MLX5_GRAPH_ARC_NODE_MPLS = 0x6,
3768 MLX5_GRAPH_ARC_NODE_TCP = 0x7,
3769 MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8,
3770 MLX5_GRAPH_ARC_NODE_GENEVE = 0x9,
3771 MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa,
3772 MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f,
3776 * Convert a user mark to flow mark.
3779 * Mark value to convert.
3782 * Converted mark value.
3784 static inline uint32_t
3785 mlx5_flow_mark_set(uint32_t val)
3790 * Add one to the user value to differentiate un-marked flows from
3791 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
3792 * remains untouched.
3794 if (val != MLX5_FLOW_MARK_DEFAULT)
3796 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
3798 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
3799 * word, byte-swapped by the kernel on little-endian systems. In this
3800 * case, left-shifting the resulting big-endian value ensures the
3801 * least significant 24 bits are retained when converting it back.
3803 ret = rte_cpu_to_be_32(val) >> 8;
3811 * Convert a mark to user mark.
3814 * Mark value to convert.
3817 * Converted mark value.
3819 static inline uint32_t
3820 mlx5_flow_mark_get(uint32_t val)
3823 * Subtract one from the retrieved value. It was added by
3824 * mlx5_flow_mark_set() to distinguish unmarked flows.
3826 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
3827 return (val >> 8) - 1;
3834 * Convert a timestamp format to configure settings in the queue context.
3837 * timestamp format supported by the queue.
3840 * Converted timstamp format settings.
3842 static inline uint32_t
3843 mlx5_ts_format_conv(uint32_t ts_format)
3845 return ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ?
3846 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
3847 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
3850 #endif /* RTE_PMD_MLX5_PRM_H_ */