drivers/common/mlx5/mlx5_prm.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2016 6WIND S.A.
   3  * Copyright 2016 Mellanox Technologies, Ltd
   4  */
   5
   6 #ifndef RTE_PMD_MLX5_PRM_H_
   7 #define RTE_PMD_MLX5_PRM_H_
   8
   9 #include <unistd.h>
  10
  11 #include <rte_vect.h>
  12 #include <rte_byteorder.h>
  13
  14 #include <mlx5_glue.h>
  15 #include "mlx5_autoconf.h"
  16
  17 /* RSS hash key size. */
  18 #define MLX5_RSS_HASH_KEY_LEN 40
  19
  20 /* Get CQE owner bit. */
  21 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
  22
  23 /* Get CQE format. */
  24 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
  25
  26 /* Get CQE opcode. */
  27 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
  28
  29 /* Get CQE solicited event. */
  30 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
  31
  32 /* Invalidate a CQE. */
  33 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
  34
  35 /* Hardware index widths. */
  36 #define MLX5_CQ_INDEX_WIDTH 24
  37 #define MLX5_WQ_INDEX_WIDTH 16
  38
  39 /* WQE Segment sizes in bytes. */
  40 #define MLX5_WSEG_SIZE 16u
  41 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
  42 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
  43 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
  44
  45 /* WQE/WQEBB size in bytes. */
  46 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
  47
  48 /*
  49  * Max size of a WQE session.
  50  * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
  51  * the WQE size field in Control Segment is 6 bits wide.
  52  */
  53 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
  54
  55 /*
  56  * Default minimum number of Tx queues for inlining packets.
  57  * If there are less queues as specified we assume we have
  58  * no enough CPU resources (cycles) to perform inlining,
  59  * the PCIe throughput is not supposed as bottleneck and
  60  * inlining is disabled.
  61  */
  62 #define MLX5_INLINE_MAX_TXQS 8u
  63 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
  64
  65 /*
  66  * Default packet length threshold to be inlined with
  67  * enhanced MPW. If packet length exceeds the threshold
  68  * the data are not inlined. Should be aligned in WQEBB
  69  * boundary with accounting the title Control and Ethernet
  70  * segments.
  71  */
  72 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
  73                                   MLX5_DSEG_MIN_INLINE_SIZE)
  74 /*
  75  * Maximal inline data length sent with enhanced MPW.
  76  * Is based on maximal WQE size.
  77  */
  78 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
  79                                   MLX5_WQE_CSEG_SIZE - \
  80                                   MLX5_WQE_ESEG_SIZE - \
  81                                   MLX5_WQE_DSEG_SIZE + \
  82                                   MLX5_DSEG_MIN_INLINE_SIZE)
  83 /*
  84  * Minimal amount of packets to be sent with EMPW.
  85  * This limits the minimal required size of sent EMPW.
  86  * If there are no enough resources to built minimal
  87  * EMPW the sending loop exits.
  88  */
  89 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
  90 /*
  91  * Maximal amount of packets to be sent with EMPW.
  92  * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
  93  * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
  94  * without CQE generation request, being multiplied by
  95  * MLX5_TX_COMP_MAX_CQE it may cause significant latency
  96  * in tx burst routine at the moment of freeing multiple mbufs.
  97  */
  98 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
  99 #define MLX5_MPW_MAX_PACKETS 6
 100 #define MLX5_MPW_INLINE_MAX_PACKETS 6
 101
 102 /*
 103  * Default packet length threshold to be inlined with
 104  * ordinary SEND. Inlining saves the MR key search
 105  * and extra PCIe data fetch transaction, but eats the
 106  * CPU cycles.
 107  */
 108 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
 109                                   MLX5_ESEG_MIN_INLINE_SIZE - \
 110                                   MLX5_WQE_CSEG_SIZE - \
 111                                   MLX5_WQE_ESEG_SIZE - \
 112                                   MLX5_WQE_DSEG_SIZE)
 113 /*
 114  * Maximal inline data length sent with ordinary SEND.
 115  * Is based on maximal WQE size.
 116  */
 117 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
 118                                   MLX5_WQE_CSEG_SIZE - \
 119                                   MLX5_WQE_ESEG_SIZE - \
 120                                   MLX5_WQE_DSEG_SIZE + \
 121                                   MLX5_ESEG_MIN_INLINE_SIZE)
 122
 123 /* Missed in mlx5dv.h, should define here. */
 124 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW
 125 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
 126 #endif
 127
 128 #ifndef HAVE_MLX5_OPCODE_SEND_EN
 129 #define MLX5_OPCODE_SEND_EN 0x17u
 130 #endif
 131
 132 #ifndef HAVE_MLX5_OPCODE_WAIT
 133 #define MLX5_OPCODE_WAIT 0x0fu
 134 #endif
 135
 136 #define MLX5_OPC_MOD_WAIT_CQ_PI 0u
 137 #define MLX5_OPC_MOD_WAIT_DATA 1u
 138 #define MLX5_OPC_MOD_WAIT_TIME 2u
 139
 140
 141 #define MLX5_WAIT_COND_INVERT 0x10u
 142 #define MLX5_WAIT_COND_ALWAYS_TRUE 0u
 143 #define MLX5_WAIT_COND_EQUAL 1u
 144 #define MLX5_WAIT_COND_BIGGER 2u
 145 #define MLX5_WAIT_COND_SMALLER 3u
 146 #define MLX5_WAIT_COND_CYCLIC_BIGGER 4u
 147 #define MLX5_WAIT_COND_CYCLIC_SMALLER 5u
 148
 149 #ifndef HAVE_MLX5_OPCODE_ACCESS_ASO
 150 #define MLX5_OPCODE_ACCESS_ASO 0x2du
 151 #endif
 152
 153 /* CQE value to inform that VLAN is stripped. */
 154 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
 155
 156 /* IPv4 options. */
 157 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
 158
 159 /* IPv6 packet. */
 160 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
 161
 162 /* IPv4 packet. */
 163 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
 164
 165 /* TCP packet. */
 166 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
 167
 168 /* UDP packet. */
 169 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
 170
 171 /* IP is fragmented. */
 172 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
 173
 174 /* L2 header is valid. */
 175 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
 176
 177 /* L3 header is valid. */
 178 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
 179
 180 /* L4 header is valid. */
 181 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
 182
 183 /* Outer packet, 0 IPv4, 1 IPv6. */
 184 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
 185
 186 /* Tunnel packet bit in the CQE. */
 187 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
 188
 189 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
 190 #define MLX5_CQE_LRO_PUSH_MASK 0x40
 191
 192 /* Mask for L4 type in the CQE hdr_type_etc field. */
 193 #define MLX5_CQE_L4_TYPE_MASK 0x70
 194
 195 /* The bit index of L4 type in CQE hdr_type_etc field. */
 196 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
 197
 198 /* L4 type to indicate TCP packet without acknowledgment. */
 199 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
 200
 201 /* L4 type to indicate TCP packet with acknowledgment. */
 202 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
 203
 204 /* Inner L3 checksum offload (Tunneled packets only). */
 205 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
 206
 207 /* Inner L4 checksum offload (Tunneled packets only). */
 208 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
 209
 210 /* Outer L4 type is TCP. */
 211 #define MLX5_ETH_WQE_L4_OUTER_TCP  (0u << 5)
 212
 213 /* Outer L4 type is UDP. */
 214 #define MLX5_ETH_WQE_L4_OUTER_UDP  (1u << 5)
 215
 216 /* Outer L3 type is IPV4. */
 217 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
 218
 219 /* Outer L3 type is IPV6. */
 220 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
 221
 222 /* Inner L4 type is TCP. */
 223 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
 224
 225 /* Inner L4 type is UDP. */
 226 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
 227
 228 /* Inner L3 type is IPV4. */
 229 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
 230
 231 /* Inner L3 type is IPV6. */
 232 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
 233
 234 /* VLAN insertion flag. */
 235 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
 236
 237 /* Data inline segment flag. */
 238 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
 239
 240 /* Is flow mark valid. */
 241 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
 242 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
 243 #else
 244 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
 245 #endif
 246
 247 /* INVALID is used by packets matching no flow rules. */
 248 #define MLX5_FLOW_MARK_INVALID 0
 249
 250 /* Maximum allowed value to mark a packet. */
 251 #define MLX5_FLOW_MARK_MAX 0xfffff0
 252
 253 /* Default mark value used when none is provided. */
 254 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
 255
 256 /* Default mark mask for metadata legacy mode. */
 257 #define MLX5_FLOW_MARK_MASK 0xffffff
 258
 259 /* Byte length mask when mark is enable in miniCQE */
 260 #define MLX5_LEN_WITH_MARK_MASK 0xffffff00
 261
 262 /* Maximum number of DS in WQE. Limited by 6-bit field. */
 263 #define MLX5_DSEG_MAX 63
 264
 265 /* The 32 bit syndrome offset in struct mlx5_err_cqe. */
 266 #define MLX5_ERROR_CQE_SYNDROME_OFFSET 52
 267
 268 /* The completion mode offset in the WQE control segment line 2. */
 269 #define MLX5_COMP_MODE_OFFSET 2
 270
 271 /* Amount of data bytes in minimal inline data segment. */
 272 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
 273
 274 /* Amount of data bytes in minimal inline eth segment. */
 275 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
 276
 277 /* Amount of data bytes after eth data segment. */
 278 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
 279
 280 /* The maximum log value of segments per RQ WQE. */
 281 #define MLX5_MAX_LOG_RQ_SEGS 5u
 282
 283 /* Log 2 of the default size of a WQE for Multi-Packet RQ. */
 284 #define MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE 14U
 285
 286 /* The alignment needed for WQ buffer. */
 287 #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size()
 288
 289 /* The alignment needed for CQ buffer. */
 290 #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size()
 291
 292 /* Completion mode. */
 293 enum mlx5_completion_mode {
 294         MLX5_COMP_ONLY_ERR = 0x0,
 295         MLX5_COMP_ONLY_FIRST_ERR = 0x1,
 296         MLX5_COMP_ALWAYS = 0x2,
 297         MLX5_COMP_CQE_AND_EQE = 0x3,
 298 };
 299
 300 /* MPW mode. */
 301 enum mlx5_mpw_mode {
 302         MLX5_MPW_DISABLED,
 303         MLX5_MPW,
 304         MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
 305 };
 306
 307 /* WQE Control segment. */
 308 struct mlx5_wqe_cseg {
 309         uint32_t opcode;
 310         uint32_t sq_ds;
 311         uint32_t flags;
 312         uint32_t misc;
 313 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
 314
 315 /*
 316  * WQE CSEG opcode field size is 32 bits, divided:
 317  * Bits 31:24 OPC_MOD
 318  * Bits 23:8 wqe_index
 319  * Bits 7:0 OPCODE
 320  */
 321 #define WQE_CSEG_OPC_MOD_OFFSET         24
 322 #define WQE_CSEG_WQE_INDEX_OFFSET        8
 323
 324 /* Header of data segment. Minimal size Data Segment */
 325 struct mlx5_wqe_dseg {
 326         uint32_t bcount;
 327         union {
 328                 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
 329                 struct {
 330                         uint32_t lkey;
 331                         uint64_t pbuf;
 332                 } __rte_packed;
 333         };
 334 } __rte_packed;
 335
 336 /* Subset of struct WQE Ethernet Segment. */
 337 struct mlx5_wqe_eseg {
 338         union {
 339                 struct {
 340                         uint32_t swp_offs;
 341                         uint8_t cs_flags;
 342                         uint8_t swp_flags;
 343                         uint16_t mss;
 344                         uint32_t metadata;
 345                         uint16_t inline_hdr_sz;
 346                         union {
 347                                 uint16_t inline_data;
 348                                 uint16_t vlan_tag;
 349                         };
 350                 } __rte_packed;
 351                 struct {
 352                         uint32_t offsets;
 353                         uint32_t flags;
 354                         uint32_t flow_metadata;
 355                         uint32_t inline_hdr;
 356                 } __rte_packed;
 357         };
 358 } __rte_packed;
 359
 360 struct mlx5_wqe_qseg {
 361         uint32_t reserved0;
 362         uint32_t reserved1;
 363         uint32_t max_index;
 364         uint32_t qpn_cqn;
 365 } __rte_packed;
 366
 367 struct mlx5_wqe_wseg {
 368         uint32_t operation;
 369         uint32_t lkey;
 370         uint32_t va_high;
 371         uint32_t va_low;
 372         uint64_t value;
 373         uint64_t mask;
 374 } __rte_packed;
 375
 376 /* The title WQEBB, header of WQE. */
 377 struct mlx5_wqe {
 378         union {
 379                 struct mlx5_wqe_cseg cseg;
 380                 uint32_t ctrl[4];
 381         };
 382         struct mlx5_wqe_eseg eseg;
 383         union {
 384                 struct mlx5_wqe_dseg dseg[2];
 385                 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
 386         };
 387 } __rte_packed;
 388
 389 /* WQE for Multi-Packet RQ. */
 390 struct mlx5_wqe_mprq {
 391         struct mlx5_wqe_srq_next_seg next_seg;
 392         struct mlx5_wqe_data_seg dseg;
 393 };
 394
 395 #define MLX5_MPRQ_LEN_MASK 0x000ffff
 396 #define MLX5_MPRQ_LEN_SHIFT 0
 397 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
 398 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
 399 #define MLX5_MPRQ_FILLER_MASK 0x80000000
 400 #define MLX5_MPRQ_FILLER_SHIFT 31
 401
 402 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
 403
 404 /* CQ element structure - should be equal to the cache line size */
 405 struct mlx5_cqe {
 406 #if (RTE_CACHE_LINE_SIZE == 128)
 407         uint8_t padding[64];
 408 #endif
 409         uint8_t pkt_info;
 410         uint8_t rsvd0;
 411         uint16_t wqe_id;
 412         uint8_t lro_tcppsh_abort_dupack;
 413         uint8_t lro_min_ttl;
 414         uint16_t lro_tcp_win;
 415         uint32_t lro_ack_seq_num;
 416         uint32_t rx_hash_res;
 417         uint8_t rx_hash_type;
 418         uint8_t rsvd1[3];
 419         uint16_t csum;
 420         uint8_t rsvd2[6];
 421         uint16_t hdr_type_etc;
 422         uint16_t vlan_info;
 423         uint8_t lro_num_seg;
 424         union {
 425                 uint8_t user_index_bytes[3];
 426                 struct {
 427                         uint8_t user_index_hi;
 428                         uint16_t user_index_low;
 429                 } __rte_packed;
 430         };
 431         uint32_t flow_table_metadata;
 432         uint8_t rsvd4[4];
 433         uint32_t byte_cnt;
 434         uint64_t timestamp;
 435         uint32_t sop_drop_qpn;
 436         uint16_t wqe_counter;
 437         uint8_t rsvd5;
 438         uint8_t op_own;
 439 };
 440
 441 struct mlx5_cqe_ts {
 442         uint64_t timestamp;
 443         uint32_t sop_drop_qpn;
 444         uint16_t wqe_counter;
 445         uint8_t rsvd5;
 446         uint8_t op_own;
 447 };
 448
 449 struct mlx5_wqe_rseg {
 450         uint64_t raddr;
 451         uint32_t rkey;
 452         uint32_t reserved;
 453 } __rte_packed;
 454
 455 #define MLX5_UMRC_IF_OFFSET 31u
 456 #define MLX5_UMRC_KO_OFFSET 16u
 457 #define MLX5_UMRC_TO_BS_OFFSET 0u
 458
 459 struct mlx5_wqe_umr_cseg {
 460         uint32_t if_cf_toe_cq_res;
 461         uint32_t ko_to_bs;
 462         uint64_t mkey_mask;
 463         uint32_t rsvd1[8];
 464 } __rte_packed;
 465
 466 struct mlx5_wqe_mkey_cseg {
 467         uint32_t fr_res_af_sf;
 468         uint32_t qpn_mkey;
 469         uint32_t reserved2;
 470         uint32_t flags_pd;
 471         uint64_t start_addr;
 472         uint64_t len;
 473         uint32_t bsf_octword_size;
 474         uint32_t reserved3[4];
 475         uint32_t translations_octword_size;
 476         uint32_t res4_lps;
 477         uint32_t reserved;
 478 } __rte_packed;
 479
 480 enum {
 481         MLX5_BSF_SIZE_16B = 0x0,
 482         MLX5_BSF_SIZE_32B = 0x1,
 483         MLX5_BSF_SIZE_64B = 0x2,
 484         MLX5_BSF_SIZE_128B = 0x3,
 485 };
 486
 487 enum {
 488         MLX5_BSF_P_TYPE_SIGNATURE = 0x0,
 489         MLX5_BSF_P_TYPE_CRYPTO = 0x1,
 490 };
 491
 492 enum {
 493         MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0,
 494         MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1,
 495         MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2,
 496         MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3,
 497 };
 498
 499 enum {
 500         MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0,
 501 };
 502
 503 enum {
 504         MLX5_BLOCK_SIZE_512B    = 0x1,
 505         MLX5_BLOCK_SIZE_520B    = 0x2,
 506         MLX5_BLOCK_SIZE_4096B   = 0x3,
 507         MLX5_BLOCK_SIZE_4160B   = 0x4,
 508         MLX5_BLOCK_SIZE_1MB     = 0x5,
 509         MLX5_BLOCK_SIZE_4048B   = 0x6,
 510 };
 511
 512 #define MLX5_BSF_SIZE_OFFSET            30
 513 #define MLX5_BSF_P_TYPE_OFFSET          24
 514 #define MLX5_ENCRYPTION_ORDER_OFFSET    16
 515 #define MLX5_BLOCK_SIZE_OFFSET          24
 516
 517 struct mlx5_wqe_umr_bsf_seg {
 518         /*
 519          * bs_bpt_eo_es contains:
 520          * bs   bsf_size                2 bits at MLX5_BSF_SIZE_OFFSET
 521          * bpt  bsf_p_type              2 bits at MLX5_BSF_P_TYPE_OFFSET
 522          * eo   encryption_order        4 bits at MLX5_ENCRYPTION_ORDER_OFFSET
 523          * es   encryption_standard     4 bits at offset 0
 524          */
 525         uint32_t bs_bpt_eo_es;
 526         uint32_t raw_data_size;
 527         /*
 528          * bsp_res contains:
 529          * bsp  crypto_block_size_pointer       8 bits at MLX5_BLOCK_SIZE_OFFSET
 530          * res  reserved 24 bits
 531          */
 532         uint32_t bsp_res;
 533         uint32_t reserved0;
 534         uint8_t xts_initial_tweak[16];
 535         /*
 536          * res_dp contains:
 537          * res  reserved 8 bits
 538          * dp   dek_pointer             24 bits at offset 0
 539          */
 540         uint32_t res_dp;
 541         uint32_t reserved1;
 542         uint64_t keytag;
 543         uint32_t reserved2[4];
 544 } __rte_packed;
 545
 546 #ifdef PEDANTIC
 547 #pragma GCC diagnostic ignored "-Wpedantic"
 548 #endif
 549
 550 struct mlx5_umr_wqe {
 551         struct mlx5_wqe_cseg ctr;
 552         struct mlx5_wqe_umr_cseg ucseg;
 553         struct mlx5_wqe_mkey_cseg mkc;
 554         union {
 555                 struct mlx5_wqe_dseg kseg[0];
 556                 struct mlx5_wqe_umr_bsf_seg bsf[0];
 557         };
 558 } __rte_packed;
 559
 560 struct mlx5_rdma_write_wqe {
 561         struct mlx5_wqe_cseg ctr;
 562         struct mlx5_wqe_rseg rseg;
 563         struct mlx5_wqe_dseg dseg[0];
 564 } __rte_packed;
 565
 566 #ifdef PEDANTIC
 567 #pragma GCC diagnostic error "-Wpedantic"
 568 #endif
 569
 570 /* GGA */
 571 /* MMO metadata segment */
 572
 573 #define MLX5_OPCODE_MMO 0x2fu
 574 #define MLX5_OPC_MOD_MMO_REGEX 0x4u
 575 #define MLX5_OPC_MOD_MMO_COMP 0x2u
 576 #define MLX5_OPC_MOD_MMO_DECOMP 0x3u
 577 #define MLX5_OPC_MOD_MMO_DMA 0x1u
 578
 579 #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u
 580 #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u
 581 #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u
 582 #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u
 583 #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS)
 584 #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u
 585 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u
 586 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u
 587 #define MLX5_GGA_COMP_OUT_OF_SPACE_SYNDROME_BE 0x29D0084
 588 #define MLX5_GGA_COMP_MISSING_BFINAL_SYNDROME_BE 0x29D0011
 589
 590 struct mlx5_wqe_metadata_seg {
 591         uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */
 592         uint32_t lkey;
 593         uint64_t addr;
 594 };
 595
 596 struct mlx5_gga_wqe {
 597         uint32_t opcode;
 598         uint32_t sq_ds;
 599         uint32_t flags;
 600         uint32_t gga_ctrl1;  /* ws 12-15, bs 16-19, dyns 20-23. */
 601         uint32_t gga_ctrl2;
 602         uint32_t opaque_lkey;
 603         uint64_t opaque_vaddr;
 604         struct mlx5_wqe_dseg gather;
 605         struct mlx5_wqe_dseg scatter;
 606 } __rte_packed;
 607
 608 struct mlx5_gga_compress_opaque {
 609         uint32_t syndrom;
 610         uint32_t reserved0;
 611         uint32_t scattered_length;
 612         uint32_t gathered_length;
 613         uint64_t scatter_crc;
 614         uint64_t gather_crc;
 615         uint32_t crc32;
 616         uint32_t adler32;
 617         uint8_t reserved1[216];
 618 } __rte_packed;
 619
 620 struct mlx5_ifc_regexp_mmo_control_bits {
 621         uint8_t reserved_at_31[0x2];
 622         uint8_t le[0x1];
 623         uint8_t reserved_at_28[0x1];
 624         uint8_t subset_id_0[0xc];
 625         uint8_t reserved_at_16[0x4];
 626         uint8_t subset_id_1[0xc];
 627         uint8_t ctrl[0x4];
 628         uint8_t subset_id_2[0xc];
 629         uint8_t reserved_at_16_1[0x4];
 630         uint8_t subset_id_3[0xc];
 631 };
 632
 633 struct mlx5_ifc_regexp_metadata_bits {
 634         uint8_t rof_version[0x10];
 635         uint8_t latency_count[0x10];
 636         uint8_t instruction_count[0x10];
 637         uint8_t primary_thread_count[0x10];
 638         uint8_t match_count[0x8];
 639         uint8_t detected_match_count[0x8];
 640         uint8_t status[0x10];
 641         uint8_t job_id[0x20];
 642         uint8_t reserved[0x80];
 643 };
 644
 645 struct mlx5_ifc_regexp_match_tuple_bits {
 646         uint8_t length[0x10];
 647         uint8_t start_ptr[0x10];
 648         uint8_t rule_id[0x20];
 649 };
 650
 651 /* Adding direct verbs to data-path. */
 652
 653 /* CQ sequence number mask. */
 654 #define MLX5_CQ_SQN_MASK 0x3
 655
 656 /* CQ sequence number index. */
 657 #define MLX5_CQ_SQN_OFFSET 28
 658
 659 /* CQ doorbell index mask. */
 660 #define MLX5_CI_MASK 0xffffff
 661
 662 /* CQ doorbell offset. */
 663 #define MLX5_CQ_ARM_DB 1
 664
 665 /* CQ doorbell offset*/
 666 #define MLX5_CQ_DOORBELL 0x20
 667
 668 /* CQE format value. */
 669 #define MLX5_COMPRESSED 0x3
 670
 671 /* CQ doorbell cmd types. */
 672 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24)
 673 #define MLX5_CQ_DBR_CMD_ALL (0 << 24)
 674
 675 /* Action type of header modification. */
 676 enum {
 677         MLX5_MODIFICATION_TYPE_SET = 0x1,
 678         MLX5_MODIFICATION_TYPE_ADD = 0x2,
 679         MLX5_MODIFICATION_TYPE_COPY = 0x3,
 680 };
 681
 682 /* The field of packet to be modified. */
 683 enum mlx5_modification_field {
 684         MLX5_MODI_OUT_NONE = -1,
 685         MLX5_MODI_OUT_SMAC_47_16 = 1,
 686         MLX5_MODI_OUT_SMAC_15_0,
 687         MLX5_MODI_OUT_ETHERTYPE,
 688         MLX5_MODI_OUT_DMAC_47_16,
 689         MLX5_MODI_OUT_DMAC_15_0,
 690         MLX5_MODI_OUT_IP_DSCP,
 691         MLX5_MODI_OUT_TCP_FLAGS,
 692         MLX5_MODI_OUT_TCP_SPORT,
 693         MLX5_MODI_OUT_TCP_DPORT,
 694         MLX5_MODI_OUT_IPV4_TTL,
 695         MLX5_MODI_OUT_UDP_SPORT,
 696         MLX5_MODI_OUT_UDP_DPORT,
 697         MLX5_MODI_OUT_SIPV6_127_96,
 698         MLX5_MODI_OUT_SIPV6_95_64,
 699         MLX5_MODI_OUT_SIPV6_63_32,
 700         MLX5_MODI_OUT_SIPV6_31_0,
 701         MLX5_MODI_OUT_DIPV6_127_96,
 702         MLX5_MODI_OUT_DIPV6_95_64,
 703         MLX5_MODI_OUT_DIPV6_63_32,
 704         MLX5_MODI_OUT_DIPV6_31_0,
 705         MLX5_MODI_OUT_SIPV4,
 706         MLX5_MODI_OUT_DIPV4,
 707         MLX5_MODI_OUT_FIRST_VID,
 708         MLX5_MODI_IN_SMAC_47_16 = 0x31,
 709         MLX5_MODI_IN_SMAC_15_0,
 710         MLX5_MODI_IN_ETHERTYPE,
 711         MLX5_MODI_IN_DMAC_47_16,
 712         MLX5_MODI_IN_DMAC_15_0,
 713         MLX5_MODI_IN_IP_DSCP,
 714         MLX5_MODI_IN_TCP_FLAGS,
 715         MLX5_MODI_IN_TCP_SPORT,
 716         MLX5_MODI_IN_TCP_DPORT,
 717         MLX5_MODI_IN_IPV4_TTL,
 718         MLX5_MODI_IN_UDP_SPORT,
 719         MLX5_MODI_IN_UDP_DPORT,
 720         MLX5_MODI_IN_SIPV6_127_96,
 721         MLX5_MODI_IN_SIPV6_95_64,
 722         MLX5_MODI_IN_SIPV6_63_32,
 723         MLX5_MODI_IN_SIPV6_31_0,
 724         MLX5_MODI_IN_DIPV6_127_96,
 725         MLX5_MODI_IN_DIPV6_95_64,
 726         MLX5_MODI_IN_DIPV6_63_32,
 727         MLX5_MODI_IN_DIPV6_31_0,
 728         MLX5_MODI_IN_SIPV4,
 729         MLX5_MODI_IN_DIPV4,
 730         MLX5_MODI_OUT_IPV6_HOPLIMIT,
 731         MLX5_MODI_IN_IPV6_HOPLIMIT,
 732         MLX5_MODI_META_DATA_REG_A,
 733         MLX5_MODI_META_DATA_REG_B = 0x50,
 734         MLX5_MODI_META_REG_C_0,
 735         MLX5_MODI_META_REG_C_1,
 736         MLX5_MODI_META_REG_C_2,
 737         MLX5_MODI_META_REG_C_3,
 738         MLX5_MODI_META_REG_C_4,
 739         MLX5_MODI_META_REG_C_5,
 740         MLX5_MODI_META_REG_C_6,
 741         MLX5_MODI_META_REG_C_7,
 742         MLX5_MODI_OUT_TCP_SEQ_NUM,
 743         MLX5_MODI_IN_TCP_SEQ_NUM,
 744         MLX5_MODI_OUT_TCP_ACK_NUM,
 745         MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
 746         MLX5_MODI_GTP_TEID = 0x6E,
 747 };
 748
 749 /* Total number of metadata reg_c's. */
 750 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1)
 751
 752 enum modify_reg {
 753         REG_NON = 0,
 754         REG_A,
 755         REG_B,
 756         REG_C_0,
 757         REG_C_1,
 758         REG_C_2,
 759         REG_C_3,
 760         REG_C_4,
 761         REG_C_5,
 762         REG_C_6,
 763         REG_C_7,
 764 };
 765
 766 /* Modification sub command. */
 767 struct mlx5_modification_cmd {
 768         union {
 769                 uint32_t data0;
 770                 struct {
 771                         unsigned int length:5;
 772                         unsigned int rsvd0:3;
 773                         unsigned int offset:5;
 774                         unsigned int rsvd1:3;
 775                         unsigned int field:12;
 776                         unsigned int action_type:4;
 777                 };
 778         };
 779         union {
 780                 uint32_t data1;
 781                 uint8_t data[4];
 782                 struct {
 783                         unsigned int rsvd2:8;
 784                         unsigned int dst_offset:5;
 785                         unsigned int rsvd3:3;
 786                         unsigned int dst_field:12;
 787                         unsigned int rsvd4:4;
 788                 };
 789         };
 790 };
 791
 792 typedef uint64_t u64;
 793 typedef uint32_t u32;
 794 typedef uint16_t u16;
 795 typedef uint8_t u8;
 796
 797 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
 798 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
 799 #define __mlx5_bit_off(typ, fld) ((unsigned int)(uintptr_t) \
 800                                   (&(__mlx5_nullp(typ)->fld)))
 801 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
 802                                     (__mlx5_bit_off(typ, fld) & 0x1f))
 803 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
 804 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
 805 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
 806                                   __mlx5_dw_bit_off(typ, fld))
 807 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
 808 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
 809 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
 810                                     (__mlx5_bit_off(typ, fld) & 0xf))
 811 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
 812 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \
 813                                   __mlx5_16_bit_off(typ, fld))
 814 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
 815 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
 816 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
 817 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
 818
 819 /* insert a value to a struct */
 820 #define MLX5_SET(typ, p, fld, v) \
 821         do { \
 822                 u32 _v = v; \
 823                 *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \
 824                 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
 825                                   __mlx5_dw_off(typ, fld))) & \
 826                                   (~__mlx5_dw_mask(typ, fld))) | \
 827                                  (((_v) & __mlx5_mask(typ, fld)) << \
 828                                    __mlx5_dw_bit_off(typ, fld))); \
 829         } while (0)
 830
 831 #define MLX5_SET64(typ, p, fld, v) \
 832         do { \
 833                 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \
 834                 *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \
 835                         rte_cpu_to_be_64(v); \
 836         } while (0)
 837
 838 #define MLX5_SET16(typ, p, fld, v) \
 839         do { \
 840                 u16 _v = v; \
 841                 *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \
 842                 rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
 843                                   __mlx5_16_off(typ, fld))) & \
 844                                   (~__mlx5_16_mask(typ, fld))) | \
 845                                  (((_v) & __mlx5_mask16(typ, fld)) << \
 846                                   __mlx5_16_bit_off(typ, fld))); \
 847         } while (0)
 848
 849 #define MLX5_GET_VOLATILE(typ, p, fld) \
 850         ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\
 851         __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
 852         __mlx5_mask(typ, fld))
 853 #define MLX5_GET(typ, p, fld) \
 854         ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\
 855         __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
 856         __mlx5_mask(typ, fld))
 857 #define MLX5_GET16(typ, p, fld) \
 858         ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
 859           __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
 860          __mlx5_mask16(typ, fld))
 861 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \
 862                                                    __mlx5_64_off(typ, fld)))
 863 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
 864 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
 865
 866 struct mlx5_ifc_fte_match_set_misc_bits {
 867         u8 gre_c_present[0x1];
 868         u8 reserved_at_1[0x1];
 869         u8 gre_k_present[0x1];
 870         u8 gre_s_present[0x1];
 871         u8 source_vhci_port[0x4];
 872         u8 source_sqn[0x18];
 873         u8 reserved_at_20[0x10];
 874         u8 source_port[0x10];
 875         u8 outer_second_prio[0x3];
 876         u8 outer_second_cfi[0x1];
 877         u8 outer_second_vid[0xc];
 878         u8 inner_second_prio[0x3];
 879         u8 inner_second_cfi[0x1];
 880         u8 inner_second_vid[0xc];
 881         u8 outer_second_cvlan_tag[0x1];
 882         u8 inner_second_cvlan_tag[0x1];
 883         u8 outer_second_svlan_tag[0x1];
 884         u8 inner_second_svlan_tag[0x1];
 885         u8 reserved_at_64[0xc];
 886         u8 gre_protocol[0x10];
 887         u8 gre_key_h[0x18];
 888         u8 gre_key_l[0x8];
 889         u8 vxlan_vni[0x18];
 890         u8 reserved_at_b8[0x8];
 891         u8 geneve_vni[0x18];
 892         u8 reserved_at_e4[0x6];
 893         u8 geneve_tlv_option_0_exist[0x1];
 894         u8 geneve_oam[0x1];
 895         u8 reserved_at_e0[0xc];
 896         u8 outer_ipv6_flow_label[0x14];
 897         u8 reserved_at_100[0xc];
 898         u8 inner_ipv6_flow_label[0x14];
 899         u8 reserved_at_120[0xa];
 900         u8 geneve_opt_len[0x6];
 901         u8 geneve_protocol_type[0x10];
 902         u8 reserved_at_140[0xc0];
 903 };
 904
 905 struct mlx5_ifc_ipv4_layout_bits {
 906         u8 reserved_at_0[0x60];
 907         u8 ipv4[0x20];
 908 };
 909
 910 struct mlx5_ifc_ipv6_layout_bits {
 911         u8 ipv6[16][0x8];
 912 };
 913
 914 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 915         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 916         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 917         u8 reserved_at_0[0x80];
 918 };
 919
 920 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 921         u8 smac_47_16[0x20];
 922         u8 smac_15_0[0x10];
 923         u8 ethertype[0x10];
 924         u8 dmac_47_16[0x20];
 925         u8 dmac_15_0[0x10];
 926         u8 first_prio[0x3];
 927         u8 first_cfi[0x1];
 928         u8 first_vid[0xc];
 929         u8 ip_protocol[0x8];
 930         u8 ip_dscp[0x6];
 931         u8 ip_ecn[0x2];
 932         u8 cvlan_tag[0x1];
 933         u8 svlan_tag[0x1];
 934         u8 frag[0x1];
 935         u8 ip_version[0x4];
 936         u8 tcp_flags[0x9];
 937         u8 tcp_sport[0x10];
 938         u8 tcp_dport[0x10];
 939         u8 reserved_at_c0[0x10];
 940         u8 ipv4_ihl[0x4];
 941         u8 l3_ok[0x1];
 942         u8 l4_ok[0x1];
 943         u8 ipv4_checksum_ok[0x1];
 944         u8 l4_checksum_ok[0x1];
 945         u8 ip_ttl_hoplimit[0x8];
 946         u8 udp_sport[0x10];
 947         u8 udp_dport[0x10];
 948         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 949         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 950 };
 951
 952 struct mlx5_ifc_fte_match_mpls_bits {
 953         u8 mpls_label[0x14];
 954         u8 mpls_exp[0x3];
 955         u8 mpls_s_bos[0x1];
 956         u8 mpls_ttl[0x8];
 957 };
 958
 959 struct mlx5_ifc_fte_match_set_misc2_bits {
 960         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 961         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 962         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 963         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 964         u8 metadata_reg_c_7[0x20];
 965         u8 metadata_reg_c_6[0x20];
 966         u8 metadata_reg_c_5[0x20];
 967         u8 metadata_reg_c_4[0x20];
 968         u8 metadata_reg_c_3[0x20];
 969         u8 metadata_reg_c_2[0x20];
 970         u8 metadata_reg_c_1[0x20];
 971         u8 metadata_reg_c_0[0x20];
 972         u8 metadata_reg_a[0x20];
 973         u8 metadata_reg_b[0x20];
 974         u8 reserved_at_1c0[0x40];
 975 };
 976
 977 struct mlx5_ifc_fte_match_set_misc3_bits {
 978         u8 inner_tcp_seq_num[0x20];
 979         u8 outer_tcp_seq_num[0x20];
 980         u8 inner_tcp_ack_num[0x20];
 981         u8 outer_tcp_ack_num[0x20];
 982         u8 reserved_at_auto1[0x8];
 983         u8 outer_vxlan_gpe_vni[0x18];
 984         u8 outer_vxlan_gpe_next_protocol[0x8];
 985         u8 outer_vxlan_gpe_flags[0x8];
 986         u8 reserved_at_a8[0x10];
 987         u8 icmp_header_data[0x20];
 988         u8 icmpv6_header_data[0x20];
 989         u8 icmp_type[0x8];
 990         u8 icmp_code[0x8];
 991         u8 icmpv6_type[0x8];
 992         u8 icmpv6_code[0x8];
 993         u8 geneve_tlv_option_0_data[0x20];
 994         u8 gtpu_teid[0x20];
 995         u8 gtpu_msg_type[0x08];
 996         u8 gtpu_msg_flags[0x08];
 997         u8 reserved_at_170[0x10];
 998         u8 gtpu_dw_2[0x20];
 999         u8 gtpu_first_ext_dw_0[0x20];
1000         u8 gtpu_dw_0[0x20];
1001         u8 reserved_at_240[0x20];
1002
1003 };
1004
1005 struct mlx5_ifc_fte_match_set_misc4_bits {
1006         u8 prog_sample_field_value_0[0x20];
1007         u8 prog_sample_field_id_0[0x20];
1008         u8 prog_sample_field_value_1[0x20];
1009         u8 prog_sample_field_id_1[0x20];
1010         u8 prog_sample_field_value_2[0x20];
1011         u8 prog_sample_field_id_2[0x20];
1012         u8 prog_sample_field_value_3[0x20];
1013         u8 prog_sample_field_id_3[0x20];
1014         u8 prog_sample_field_value_4[0x20];
1015         u8 prog_sample_field_id_4[0x20];
1016         u8 prog_sample_field_value_5[0x20];
1017         u8 prog_sample_field_id_5[0x20];
1018         u8 prog_sample_field_value_6[0x20];
1019         u8 prog_sample_field_id_6[0x20];
1020         u8 prog_sample_field_value_7[0x20];
1021         u8 prog_sample_field_id_7[0x20];
1022 };
1023
1024 struct mlx5_ifc_fte_match_set_misc5_bits {
1025         u8 macsec_tag_0[0x20];
1026         u8 macsec_tag_1[0x20];
1027         u8 macsec_tag_2[0x20];
1028         u8 macsec_tag_3[0x20];
1029         u8 tunnel_header_0[0x20];
1030         u8 tunnel_header_1[0x20];
1031         u8 tunnel_header_2[0x20];
1032         u8 tunnel_header_3[0x20];
1033         u8 reserved[0x100];
1034 };
1035
1036 /* Flow matcher. */
1037 struct mlx5_ifc_fte_match_param_bits {
1038         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1039         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1040         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1041         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1042         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1043         struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1044         struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
1045 /*
1046  * Add reserved bit to match the struct size with the size defined in PRM.
1047  * This extension is not required in Linux.
1048  */
1049 #ifndef HAVE_INFINIBAND_VERBS_H
1050         u8 reserved_0[0x200];
1051 #endif
1052 };
1053
1054 struct mlx5_ifc_dest_format_struct_bits {
1055         u8 destination_type[0x8];
1056         u8 destination_id[0x18];
1057         u8 reserved_0[0x20];
1058 };
1059
1060 enum {
1061         MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
1062         MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
1063         MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
1064         MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
1065         MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT,
1066         MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT,
1067         MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT,
1068 };
1069
1070 enum {
1071         MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
1072         MLX5_CMD_OP_CREATE_MKEY = 0x200,
1073         MLX5_CMD_OP_CREATE_CQ = 0x400,
1074         MLX5_CMD_OP_CREATE_QP = 0x500,
1075         MLX5_CMD_OP_RST2INIT_QP = 0x502,
1076         MLX5_CMD_OP_INIT2RTR_QP = 0x503,
1077         MLX5_CMD_OP_RTR2RTS_QP = 0x504,
1078         MLX5_CMD_OP_RTS2RTS_QP = 0x505,
1079         MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
1080         MLX5_CMD_OP_QP_2ERR = 0x507,
1081         MLX5_CMD_OP_QP_2RST = 0x50A,
1082         MLX5_CMD_OP_QUERY_QP = 0x50B,
1083         MLX5_CMD_OP_SQD2RTS_QP = 0x50C,
1084         MLX5_CMD_OP_INIT2INIT_QP = 0x50E,
1085         MLX5_CMD_OP_SUSPEND_QP = 0x50F,
1086         MLX5_CMD_OP_RESUME_QP = 0x510,
1087         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
1088         MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
1089         MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
1090         MLX5_CMD_OP_ALLOC_PD = 0x800,
1091         MLX5_CMD_OP_DEALLOC_PD = 0x801,
1092         MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
1093         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
1094         MLX5_CMD_OP_QUERY_LAG = 0x842,
1095         MLX5_CMD_OP_CREATE_TIR = 0x900,
1096         MLX5_CMD_OP_MODIFY_TIR = 0x901,
1097         MLX5_CMD_OP_CREATE_SQ = 0X904,
1098         MLX5_CMD_OP_MODIFY_SQ = 0X905,
1099         MLX5_CMD_OP_CREATE_RQ = 0x908,
1100         MLX5_CMD_OP_MODIFY_RQ = 0x909,
1101         MLX5_CMD_OP_QUERY_RQ = 0x90b,
1102         MLX5_CMD_OP_CREATE_RMP = 0x90c,
1103         MLX5_CMD_OP_MODIFY_RMP = 0x90d,
1104         MLX5_CMD_OP_DESTROY_RMP = 0x90e,
1105         MLX5_CMD_OP_QUERY_RMP = 0x90f,
1106         MLX5_CMD_OP_CREATE_TIS = 0x912,
1107         MLX5_CMD_OP_QUERY_TIS = 0x915,
1108         MLX5_CMD_OP_CREATE_RQT = 0x916,
1109         MLX5_CMD_OP_MODIFY_RQT = 0x917,
1110         MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
1111         MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
1112         MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
1113         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
1114         MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
1115         MLX5_CMD_SET_REGEX_PARAMS = 0xb04,
1116         MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,
1117         MLX5_CMD_SET_REGEX_REGISTERS = 0xb06,
1118         MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
1119         MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c,
1120 };
1121
1122 enum {
1123         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
1124         MLX5_MKC_ACCESS_MODE_KLM   = 0x2,
1125         MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3,
1126 };
1127
1128 #define MLX5_ADAPTER_PAGE_SHIFT 12
1129 #define MLX5_LOG_RQ_STRIDE_SHIFT 4
1130 /**
1131  * The batch counter dcs id starts from 0x800000 and none batch counter
1132  * starts from 0. As currently, the counter is changed to be indexed by
1133  * pool index and the offset of the counter in the pool counters_raw array.
1134  * It means now the counter index is same for batch and none batch counter.
1135  * Add the 0x800000 batch counter offset to the batch counter index helps
1136  * indicate the counter index is from batch or none batch container pool.
1137  */
1138 #define MLX5_CNT_BATCH_OFFSET 0x800000
1139
1140 /* The counter batch query requires ID align with 4. */
1141 #define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4
1142
1143 /* Flow counters. */
1144 struct mlx5_ifc_alloc_flow_counter_out_bits {
1145         u8 status[0x8];
1146         u8 reserved_at_8[0x18];
1147         u8 syndrome[0x20];
1148         u8 flow_counter_id[0x20];
1149         u8 reserved_at_60[0x20];
1150 };
1151
1152 struct mlx5_ifc_alloc_flow_counter_in_bits {
1153         u8 opcode[0x10];
1154         u8 reserved_at_10[0x10];
1155         u8 reserved_at_20[0x10];
1156         u8 op_mod[0x10];
1157         u8 flow_counter_id[0x20];
1158         u8 reserved_at_40[0x18];
1159         u8 flow_counter_bulk[0x8];
1160 };
1161
1162 struct mlx5_ifc_dealloc_flow_counter_out_bits {
1163         u8 status[0x8];
1164         u8 reserved_at_8[0x18];
1165         u8 syndrome[0x20];
1166         u8 reserved_at_40[0x40];
1167 };
1168
1169 struct mlx5_ifc_dealloc_flow_counter_in_bits {
1170         u8 opcode[0x10];
1171         u8 reserved_at_10[0x10];
1172         u8 reserved_at_20[0x10];
1173         u8 op_mod[0x10];
1174         u8 flow_counter_id[0x20];
1175         u8 reserved_at_60[0x20];
1176 };
1177
1178 struct mlx5_ifc_traffic_counter_bits {
1179         u8 packets[0x40];
1180         u8 octets[0x40];
1181 };
1182
1183 struct mlx5_ifc_query_flow_counter_out_bits {
1184         u8 status[0x8];
1185         u8 reserved_at_8[0x18];
1186         u8 syndrome[0x20];
1187         u8 reserved_at_40[0x40];
1188         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
1189 };
1190
1191 struct mlx5_ifc_query_flow_counter_in_bits {
1192         u8 opcode[0x10];
1193         u8 reserved_at_10[0x10];
1194         u8 reserved_at_20[0x10];
1195         u8 op_mod[0x10];
1196         u8 reserved_at_40[0x20];
1197         u8 mkey[0x20];
1198         u8 address[0x40];
1199         u8 clear[0x1];
1200         u8 dump_to_memory[0x1];
1201         u8 num_of_counters[0x1e];
1202         u8 flow_counter_id[0x20];
1203 };
1204
1205 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u
1206 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u
1207
1208 struct mlx5_ifc_klm_bits {
1209         u8 byte_count[0x20];
1210         u8 mkey[0x20];
1211         u8 address[0x40];
1212 };
1213
1214 struct mlx5_ifc_mkc_bits {
1215         u8 reserved_at_0[0x1];
1216         u8 free[0x1];
1217         u8 reserved_at_2[0x1];
1218         u8 access_mode_4_2[0x3];
1219         u8 reserved_at_6[0x7];
1220         u8 relaxed_ordering_write[0x1];
1221         u8 reserved_at_e[0x1];
1222         u8 small_fence_on_rdma_read_response[0x1];
1223         u8 umr_en[0x1];
1224         u8 a[0x1];
1225         u8 rw[0x1];
1226         u8 rr[0x1];
1227         u8 lw[0x1];
1228         u8 lr[0x1];
1229         u8 access_mode_1_0[0x2];
1230         u8 reserved_at_18[0x8];
1231         u8 qpn[0x18];
1232         u8 mkey_7_0[0x8];
1233         u8 reserved_at_40[0x20];
1234         u8 length64[0x1];
1235         u8 bsf_en[0x1];
1236         u8 sync_umr[0x1];
1237         u8 reserved_at_63[0x2];
1238         u8 expected_sigerr_count[0x1];
1239         u8 reserved_at_66[0x1];
1240         u8 en_rinval[0x1];
1241         u8 pd[0x18];
1242         u8 start_addr[0x40];
1243         u8 len[0x40];
1244         u8 bsf_octword_size[0x20];
1245         u8 reserved_at_120[0x80];
1246         u8 translations_octword_size[0x20];
1247         u8 reserved_at_1c0[0x19];
1248         u8 relaxed_ordering_read[0x1];
1249         u8 reserved_at_1da[0x1];
1250         u8 log_page_size[0x5];
1251         u8 reserved_at_1e0[0x3];
1252         u8 crypto_en[0x2];
1253         u8 reserved_at_1e5[0x1b];
1254 };
1255
1256 /* Range of values for MKEY context crypto_en field. */
1257 enum {
1258         MLX5_MKEY_CRYPTO_DISABLED = 0x0,
1259         MLX5_MKEY_CRYPTO_ENABLED = 0x1,
1260 };
1261
1262 struct mlx5_ifc_create_mkey_out_bits {
1263         u8 status[0x8];
1264         u8 reserved_at_8[0x18];
1265         u8 syndrome[0x20];
1266         u8 reserved_at_40[0x8];
1267         u8 mkey_index[0x18];
1268         u8 reserved_at_60[0x20];
1269 };
1270
1271 struct mlx5_ifc_create_mkey_in_bits {
1272         u8 opcode[0x10];
1273         u8 reserved_at_10[0x10];
1274         u8 reserved_at_20[0x10];
1275         u8 op_mod[0x10];
1276         u8 reserved_at_40[0x20];
1277         u8 pg_access[0x1];
1278         u8 reserved_at_61[0x1f];
1279         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
1280         u8 reserved_at_280[0x80];
1281         u8 translations_octword_actual_size[0x20];
1282         u8 mkey_umem_id[0x20];
1283         u8 mkey_umem_offset[0x40];
1284         u8 reserved_at_380[0x500];
1285         u8 klm_pas_mtt[][0x20];
1286 };
1287
1288 enum {
1289         MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
1290         MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
1291         MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
1292         MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1,
1293         MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,
1294         MLX5_SET_HCA_CAP_OP_MOD_ESW = 0x9 << 1,
1295         MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
1296         MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP = 0x1C << 1,
1297         MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1,
1298 };
1299
1300 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \
1301                         (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ)
1302 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \
1303                         (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS)
1304 #define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \
1305                         (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH)
1306 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \
1307                         (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO)
1308 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO \
1309                         (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO)
1310 #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \
1311                         (1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT)
1312 #define MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD \
1313                         (1ULL << MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD)
1314 #define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \
1315                         (1ULL << MLX5_GENERAL_OBJ_TYPE_DEK)
1316 #define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \
1317                         (1ULL << MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK)
1318 #define MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL \
1319                         (1ULL << MLX5_GENERAL_OBJ_TYPE_CREDENTIAL)
1320 #define MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN \
1321                         (1ULL << MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN)
1322
1323 enum {
1324         MLX5_HCA_CAP_OPMOD_GET_MAX   = 0,
1325         MLX5_HCA_CAP_OPMOD_GET_CUR   = 1,
1326 };
1327
1328 enum {
1329         MLX5_CAP_INLINE_MODE_L2,
1330         MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
1331         MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
1332 };
1333
1334 enum {
1335         MLX5_INLINE_MODE_NONE,
1336         MLX5_INLINE_MODE_L2,
1337         MLX5_INLINE_MODE_IP,
1338         MLX5_INLINE_MODE_TCP_UDP,
1339         MLX5_INLINE_MODE_RESERVED4,
1340         MLX5_INLINE_MODE_INNER_L2,
1341         MLX5_INLINE_MODE_INNER_IP,
1342         MLX5_INLINE_MODE_INNER_TCP_UDP,
1343 };
1344
1345 /* The supported timestamp formats reported in HCA attributes. */
1346 enum {
1347         MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR = 0x0,
1348         MLX5_HCA_CAP_TIMESTAMP_FORMAT_RT = 0x1,
1349         MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR_RT = 0x2,
1350 };
1351
1352 /* The timestamp format attributes to configure queues (RQ/SQ/QP). */
1353 enum {
1354         MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
1355         MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
1356         MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
1357 };
1358
1359 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
1360 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
1361 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
1362 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
1363 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
1364 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
1365 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
1366 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
1367 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
1368 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
1369 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
1370
1371 /* The device steering logic format. */
1372 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 0x0
1373 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX 0x1
1374
1375 struct mlx5_ifc_cmd_hca_cap_bits {
1376         u8 reserved_at_0[0x20];
1377         u8 hca_cap_2[0x1];
1378         u8 reserved_at_21[0xf];
1379         u8 vhca_id[0x10];
1380         u8 reserved_at_40[0x20];
1381         u8 reserved_at_60[0x3];
1382         u8 log_regexp_scatter_gather_size[0x5];
1383         u8 reserved_at_68[0x3];
1384         u8 log_dma_mmo_size[0x5];
1385         u8 reserved_at_70[0x3];
1386         u8 log_compress_mmo_size[0x5];
1387         u8 reserved_at_78[0x3];
1388         u8 log_decompress_mmo_size[0x5];
1389         u8 log_max_srq_sz[0x8];
1390         u8 log_max_qp_sz[0x8];
1391         u8 reserved_at_90[0x9];
1392         u8 wqe_index_ignore_cap[0x1];
1393         u8 dynamic_qp_allocation[0x1];
1394         u8 log_max_qp[0x5];
1395         u8 reserved_at_a0[0x4];
1396         u8 regexp_num_of_engines[0x4];
1397         u8 reserved_at_a8[0x1];
1398         u8 reg_c_preserve[0x1];
1399         u8 reserved_at_aa[0x1];
1400         u8 log_max_srq[0x5];
1401         u8 reserved_at_b0[0xb];
1402         u8 scatter_fcs_w_decap_disable[0x1];
1403         u8 reserved_at_bc[0x4];
1404         u8 reserved_at_c0[0x8];
1405         u8 log_max_cq_sz[0x8];
1406         u8 reserved_at_d0[0x2];
1407         u8 access_register_user[0x1];
1408         u8 reserved_at_d3[0x8];
1409         u8 log_max_cq[0x5];
1410         u8 log_max_eq_sz[0x8];
1411         u8 relaxed_ordering_write[0x1];
1412         u8 relaxed_ordering_read[0x1];
1413         u8 log_max_mkey[0x6];
1414         u8 reserved_at_f0[0x8];
1415         u8 dump_fill_mkey[0x1];
1416         u8 reserved_at_f9[0x3];
1417         u8 log_max_eq[0x4];
1418         u8 max_indirection[0x8];
1419         u8 fixed_buffer_size[0x1];
1420         u8 log_max_mrw_sz[0x7];
1421         u8 force_teardown[0x1];
1422         u8 reserved_at_111[0x1];
1423         u8 log_max_bsf_list_size[0x6];
1424         u8 umr_extended_translation_offset[0x1];
1425         u8 null_mkey[0x1];
1426         u8 log_max_klm_list_size[0x6];
1427         u8 non_wire_sq[0x1];
1428         u8 reserved_at_121[0x9];
1429         u8 log_max_ra_req_dc[0x6];
1430         u8 reserved_at_130[0x3];
1431         u8 log_max_static_sq_wq[0x5];
1432         u8 reserved_at_138[0x2];
1433         u8 log_max_ra_res_dc[0x6];
1434         u8 reserved_at_140[0xa];
1435         u8 log_max_ra_req_qp[0x6];
1436         u8 rtr2rts_qp_counters_set_id[0x1];
1437         u8 rts2rts_udp_sport[0x1];
1438         u8 rts2rts_lag_tx_port_affinity[0x1];
1439         u8 dma_mmo_sq[0x1];
1440         u8 compress_min_block_size[0x4];
1441         u8 compress_mmo_sq[0x1];
1442         u8 decompress_mmo_sq[0x1];
1443         u8 log_max_ra_res_qp[0x6];
1444         u8 end_pad[0x1];
1445         u8 cc_query_allowed[0x1];
1446         u8 cc_modify_allowed[0x1];
1447         u8 start_pad[0x1];
1448         u8 cache_line_128byte[0x1];
1449         u8 reserved_at_165[0xa];
1450         u8 qcam_reg[0x1];
1451         u8 gid_table_size[0x10];
1452         u8 out_of_seq_cnt[0x1];
1453         u8 vport_counters[0x1];
1454         u8 retransmission_q_counters[0x1];
1455         u8 debug[0x1];
1456         u8 modify_rq_counter_set_id[0x1];
1457         u8 rq_delay_drop[0x1];
1458         u8 max_qp_cnt[0xa];
1459         u8 pkey_table_size[0x10];
1460         u8 vport_group_manager[0x1];
1461         u8 vhca_group_manager[0x1];
1462         u8 ib_virt[0x1];
1463         u8 eth_virt[0x1];
1464         u8 vnic_env_queue_counters[0x1];
1465         u8 ets[0x1];
1466         u8 nic_flow_table[0x1];
1467         u8 eswitch_manager[0x1];
1468         u8 device_memory[0x1];
1469         u8 mcam_reg[0x1];
1470         u8 pcam_reg[0x1];
1471         u8 local_ca_ack_delay[0x5];
1472         u8 port_module_event[0x1];
1473         u8 enhanced_error_q_counters[0x1];
1474         u8 ports_check[0x1];
1475         u8 reserved_at_1b3[0x1];
1476         u8 disable_link_up[0x1];
1477         u8 beacon_led[0x1];
1478         u8 port_type[0x2];
1479         u8 num_ports[0x8];
1480         u8 reserved_at_1c0[0x1];
1481         u8 pps[0x1];
1482         u8 pps_modify[0x1];
1483         u8 log_max_msg[0x5];
1484         u8 reserved_at_1c8[0x4];
1485         u8 max_tc[0x4];
1486         u8 temp_warn_event[0x1];
1487         u8 dcbx[0x1];
1488         u8 general_notification_event[0x1];
1489         u8 reserved_at_1d3[0x2];
1490         u8 fpga[0x1];
1491         u8 rol_s[0x1];
1492         u8 rol_g[0x1];
1493         u8 reserved_at_1d8[0x1];
1494         u8 wol_s[0x1];
1495         u8 wol_g[0x1];
1496         u8 wol_a[0x1];
1497         u8 wol_b[0x1];
1498         u8 wol_m[0x1];
1499         u8 wol_u[0x1];
1500         u8 wol_p[0x1];
1501         u8 stat_rate_support[0x10];
1502         u8 reserved_at_1f0[0xc];
1503         u8 cqe_version[0x4];
1504         u8 compact_address_vector[0x1];
1505         u8 striding_rq[0x1];
1506         u8 reserved_at_202[0x1];
1507         u8 ipoib_enhanced_offloads[0x1];
1508         u8 ipoib_basic_offloads[0x1];
1509         u8 reserved_at_205[0x1];
1510         u8 repeated_block_disabled[0x1];
1511         u8 umr_modify_entity_size_disabled[0x1];
1512         u8 umr_modify_atomic_disabled[0x1];
1513         u8 umr_indirect_mkey_disabled[0x1];
1514         u8 umr_fence[0x2];
1515         u8 reserved_at_20c[0x3];
1516         u8 drain_sigerr[0x1];
1517         u8 cmdif_checksum[0x2];
1518         u8 sigerr_cqe[0x1];
1519         u8 reserved_at_213[0x1];
1520         u8 wq_signature[0x1];
1521         u8 sctr_data_cqe[0x1];
1522         u8 reserved_at_216[0x1];
1523         u8 sho[0x1];
1524         u8 tph[0x1];
1525         u8 rf[0x1];
1526         u8 dct[0x1];
1527         u8 qos[0x1];
1528         u8 eth_net_offloads[0x1];
1529         u8 roce[0x1];
1530         u8 atomic[0x1];
1531         u8 reserved_at_21f[0x1];
1532         u8 cq_oi[0x1];
1533         u8 cq_resize[0x1];
1534         u8 cq_moderation[0x1];
1535         u8 reserved_at_223[0x3];
1536         u8 cq_eq_remap[0x1];
1537         u8 pg[0x1];
1538         u8 block_lb_mc[0x1];
1539         u8 reserved_at_229[0x1];
1540         u8 scqe_break_moderation[0x1];
1541         u8 cq_period_start_from_cqe[0x1];
1542         u8 cd[0x1];
1543         u8 reserved_at_22d[0x1];
1544         u8 apm[0x1];
1545         u8 vector_calc[0x1];
1546         u8 umr_ptr_rlky[0x1];
1547         u8 imaicl[0x1];
1548         u8 reserved_at_232[0x4];
1549         u8 qkv[0x1];
1550         u8 pkv[0x1];
1551         u8 set_deth_sqpn[0x1];
1552         u8 reserved_at_239[0x3];
1553         u8 xrc[0x1];
1554         u8 ud[0x1];
1555         u8 uc[0x1];
1556         u8 rc[0x1];
1557         u8 uar_4k[0x1];
1558         u8 reserved_at_241[0x8];
1559         u8 regexp_params[0x1];
1560         u8 uar_sz[0x6];
1561         u8 port_selection_cap[0x1];
1562         u8 reserved_at_251[0x7];
1563         u8 log_pg_sz[0x8];
1564         u8 bf[0x1];
1565         u8 driver_version[0x1];
1566         u8 pad_tx_eth_packet[0x1];
1567         u8 reserved_at_263[0x8];
1568         u8 log_bf_reg_size[0x5];
1569         u8 reserved_at_270[0xb];
1570         u8 lag_master[0x1];
1571         u8 num_lag_ports[0x4];
1572         u8 reserved_at_280[0x10];
1573         u8 max_wqe_sz_sq[0x10];
1574         u8 reserved_at_2a0[0xc];
1575         u8 regexp_mmo_sq[0x1];
1576         u8 regexp_version[0x3];
1577         u8 max_wqe_sz_rq[0x10];
1578         u8 max_flow_counter_31_16[0x10];
1579         u8 max_wqe_sz_sq_dc[0x10];
1580         u8 reserved_at_2e0[0x7];
1581         u8 max_qp_mcg[0x19];
1582         u8 reserved_at_300[0x10];
1583         u8 flow_counter_bulk_alloc[0x08];
1584         u8 log_max_mcg[0x8];
1585         u8 reserved_at_320[0x3];
1586         u8 log_max_transport_domain[0x5];
1587         u8 reserved_at_328[0x3];
1588         u8 log_max_pd[0x5];
1589         u8 reserved_at_330[0xb];
1590         u8 log_max_xrcd[0x5];
1591         u8 nic_receive_steering_discard[0x1];
1592         u8 receive_discard_vport_down[0x1];
1593         u8 transmit_discard_vport_down[0x1];
1594         u8 reserved_at_343[0x5];
1595         u8 log_max_flow_counter_bulk[0x8];
1596         u8 max_flow_counter_15_0[0x10];
1597         u8 modify_tis[0x1];
1598         u8 flow_counters_dump[0x1];
1599         u8 reserved_at_360[0x1];
1600         u8 log_max_rq[0x5];
1601         u8 reserved_at_368[0x3];
1602         u8 log_max_sq[0x5];
1603         u8 reserved_at_370[0x3];
1604         u8 log_max_tir[0x5];
1605         u8 reserved_at_378[0x3];
1606         u8 log_max_tis[0x5];
1607         u8 basic_cyclic_rcv_wqe[0x1];
1608         u8 reserved_at_381[0x1];
1609         u8 mem_rq_rmp[0x1];
1610         u8 log_max_rmp[0x5];
1611         u8 reserved_at_388[0x3];
1612         u8 log_max_rqt[0x5];
1613         u8 reserved_at_390[0x3];
1614         u8 log_max_rqt_size[0x5];
1615         u8 reserved_at_398[0x3];
1616         u8 log_max_tis_per_sq[0x5];
1617         u8 ext_stride_num_range[0x1];
1618         u8 reserved_at_3a1[0x2];
1619         u8 log_max_stride_sz_rq[0x5];
1620         u8 reserved_at_3a8[0x3];
1621         u8 log_min_stride_sz_rq[0x5];
1622         u8 reserved_at_3b0[0x3];
1623         u8 log_max_stride_sz_sq[0x5];
1624         u8 reserved_at_3b8[0x3];
1625         u8 log_min_stride_sz_sq[0x5];
1626         u8 hairpin[0x1];
1627         u8 reserved_at_3c1[0x2];
1628         u8 log_max_hairpin_queues[0x5];
1629         u8 reserved_at_3c8[0x3];
1630         u8 log_max_hairpin_wq_data_sz[0x5];
1631         u8 reserved_at_3d0[0x3];
1632         u8 log_max_hairpin_num_packets[0x5];
1633         u8 reserved_at_3d8[0x3];
1634         u8 log_max_wq_sz[0x5];
1635         u8 nic_vport_change_event[0x1];
1636         u8 disable_local_lb_uc[0x1];
1637         u8 disable_local_lb_mc[0x1];
1638         u8 log_min_hairpin_wq_data_sz[0x5];
1639         u8 reserved_at_3e8[0x3];
1640         u8 log_max_vlan_list[0x5];
1641         u8 reserved_at_3f0[0x3];
1642         u8 log_max_current_mc_list[0x5];
1643         u8 reserved_at_3f8[0x3];
1644         u8 log_max_current_uc_list[0x5];
1645         u8 general_obj_types[0x40];
1646         u8 sq_ts_format[0x2];
1647         u8 rq_ts_format[0x2];
1648         u8 steering_format_version[0x4];
1649         u8 reserved_at_448[0x18];
1650         u8 reserved_at_460[0x8];
1651         u8 aes_xts[0x1];
1652         u8 crypto[0x1];
1653         u8 reserved_at_46a[0x6];
1654         u8 max_num_eqs[0x10];
1655         u8 reserved_at_480[0x3];
1656         u8 log_max_l2_table[0x5];
1657         u8 reserved_at_488[0x8];
1658         u8 log_uar_page_sz[0x10];
1659         u8 reserved_at_4a0[0x20];
1660         u8 device_frequency_mhz[0x20];
1661         u8 device_frequency_khz[0x20];
1662         u8 reserved_at_500[0x20];
1663         u8 num_of_uars_per_page[0x20];
1664         u8 flex_parser_protocols[0x20];
1665         u8 max_geneve_tlv_options[0x8];
1666         u8 reserved_at_568[0x3];
1667         u8 max_geneve_tlv_option_data_len[0x5];
1668         u8 reserved_at_570[0x49];
1669         u8 mini_cqe_resp_l3_l4_tag[0x1];
1670         u8 mini_cqe_resp_flow_tag[0x1];
1671         u8 enhanced_cqe_compression[0x1];
1672         u8 mini_cqe_resp_stride_index[0x1];
1673         u8 cqe_128_always[0x1];
1674         u8 cqe_compression_128[0x1];
1675         u8 cqe_compression[0x1];
1676         u8 cqe_compression_timeout[0x10];
1677         u8 cqe_compression_max_num[0x10];
1678         u8 reserved_at_5e0[0x10];
1679         u8 tag_matching[0x1];
1680         u8 rndv_offload_rc[0x1];
1681         u8 rndv_offload_dc[0x1];
1682         u8 log_tag_matching_list_sz[0x5];
1683         u8 reserved_at_5f8[0x3];
1684         u8 log_max_xrq[0x5];
1685         u8 affiliate_nic_vport_criteria[0x8];
1686         u8 native_port_num[0x8];
1687         u8 num_vhca_ports[0x8];
1688         u8 reserved_at_618[0x6];
1689         u8 sw_owner_id[0x1];
1690         u8 reserved_at_61f[0x6C];
1691         u8 wait_on_data[0x1];
1692         u8 wait_on_time[0x1];
1693         u8 reserved_at_68d[0xBB];
1694         u8 dma_mmo_qp[0x1];
1695         u8 regexp_mmo_qp[0x1];
1696         u8 compress_mmo_qp[0x1];
1697         u8 decompress_mmo_qp[0x1];
1698         u8 reserved_at_624[0xd4];
1699 };
1700
1701 struct mlx5_ifc_qos_cap_bits {
1702         u8 packet_pacing[0x1];
1703         u8 esw_scheduling[0x1];
1704         u8 esw_bw_share[0x1];
1705         u8 esw_rate_limit[0x1];
1706         u8 reserved_at_4[0x1];
1707         u8 packet_pacing_burst_bound[0x1];
1708         u8 packet_pacing_typical_size[0x1];
1709         u8 flow_meter_old[0x1];
1710         u8 reserved_at_8[0x8];
1711         u8 log_max_flow_meter[0x8];
1712         u8 flow_meter_reg_id[0x8];
1713         u8 wqe_rate_pp[0x1];
1714         u8 reserved_at_25[0x7];
1715         u8 flow_meter[0x1];
1716         u8 reserved_at_2e[0x17];
1717         u8 packet_pacing_max_rate[0x20];
1718         u8 packet_pacing_min_rate[0x20];
1719         u8 reserved_at_80[0x10];
1720         u8 packet_pacing_rate_table_size[0x10];
1721         u8 esw_element_type[0x10];
1722         u8 esw_tsar_type[0x10];
1723         u8 reserved_at_c0[0x10];
1724         u8 max_qos_para_vport[0x10];
1725         u8 max_tsar_bw_share[0x20];
1726         u8 nic_element_type[0x10];
1727         u8 nic_tsar_type[0x10];
1728         u8 reserved_at_120[0x3];
1729         u8 log_meter_aso_granularity[0x5];
1730         u8 reserved_at_128[0x3];
1731         u8 log_meter_aso_max_alloc[0x5];
1732         u8 reserved_at_130[0x3];
1733         u8 log_max_num_meter_aso[0x5];
1734         u8 reserved_at_138[0x6b0];
1735 };
1736
1737 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1738         u8 csum_cap[0x1];
1739         u8 vlan_cap[0x1];
1740         u8 lro_cap[0x1];
1741         u8 lro_psh_flag[0x1];
1742         u8 lro_time_stamp[0x1];
1743         u8 lro_max_msg_sz_mode[0x2];
1744         u8 wqe_vlan_insert[0x1];
1745         u8 self_lb_en_modifiable[0x1];
1746         u8 self_lb_mc[0x1];
1747         u8 self_lb_uc[0x1];
1748         u8 max_lso_cap[0x5];
1749         u8 multi_pkt_send_wqe[0x2];
1750         u8 wqe_inline_mode[0x2];
1751         u8 rss_ind_tbl_cap[0x4];
1752         u8 reg_umr_sq[0x1];
1753         u8 scatter_fcs[0x1];
1754         u8 enhanced_multi_pkt_send_wqe[0x1];
1755         u8 tunnel_lso_const_out_ip_id[0x1];
1756         u8 tunnel_lro_gre[0x1];
1757         u8 tunnel_lro_vxlan[0x1];
1758         u8 tunnel_stateless_gre[0x1];
1759         u8 tunnel_stateless_vxlan[0x1];
1760         u8 swp[0x1];
1761         u8 swp_csum[0x1];
1762         u8 swp_lso[0x1];
1763         u8 reserved_at_23[0x8];
1764         u8 tunnel_stateless_gtp[0x1];
1765         u8 reserved_at_25[0x4];
1766         u8 max_vxlan_udp_ports[0x8];
1767         u8 reserved_at_38[0x6];
1768         u8 max_geneve_opt_len[0x1];
1769         u8 tunnel_stateless_geneve_rx[0x1];
1770         u8 reserved_at_40[0x10];
1771         u8 lro_min_mss_size[0x10];
1772         u8 reserved_at_60[0x120];
1773         u8 lro_timer_supported_periods[4][0x20];
1774         u8 reserved_at_200[0x600];
1775 };
1776
1777 enum {
1778         MLX5_VIRTQ_TYPE_SPLIT = 0,
1779         MLX5_VIRTQ_TYPE_PACKED = 1,
1780 };
1781
1782 enum {
1783         MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0,
1784         MLX5_VIRTQ_EVENT_MODE_QP = 1,
1785         MLX5_VIRTQ_EVENT_MODE_MSIX = 2,
1786 };
1787
1788 struct mlx5_ifc_virtio_emulation_cap_bits {
1789         u8 desc_tunnel_offload_type[0x1];
1790         u8 eth_frame_offload_type[0x1];
1791         u8 virtio_version_1_0[0x1];
1792         u8 tso_ipv4[0x1];
1793         u8 tso_ipv6[0x1];
1794         u8 tx_csum[0x1];
1795         u8 rx_csum[0x1];
1796         u8 reserved_at_7[0x1][0x9];
1797         u8 event_mode[0x8];
1798         u8 virtio_queue_type[0x8];
1799         u8 reserved_at_20[0x13];
1800         u8 log_doorbell_stride[0x5];
1801         u8 reserved_at_3b[0x3];
1802         u8 log_doorbell_bar_size[0x5];
1803         u8 doorbell_bar_offset[0x40];
1804         u8 reserved_at_80[0x8];
1805         u8 max_num_virtio_queues[0x18];
1806         u8 reserved_at_a0[0x60];
1807         u8 umem_1_buffer_param_a[0x20];
1808         u8 umem_1_buffer_param_b[0x20];
1809         u8 umem_2_buffer_param_a[0x20];
1810         u8 umem_2_buffer_param_b[0x20];
1811         u8 umem_3_buffer_param_a[0x20];
1812         u8 umem_3_buffer_param_b[0x20];
1813         u8 reserved_at_1c0[0x620];
1814 };
1815
1816 /**
1817  * PARSE_GRAPH_NODE Capabilities Field Descriptions
1818  */
1819 struct mlx5_ifc_parse_graph_node_cap_bits {
1820         u8 node_in[0x20];
1821         u8 node_out[0x20];
1822         u8 header_length_mode[0x10];
1823         u8 sample_offset_mode[0x10];
1824         u8 max_num_arc_in[0x08];
1825         u8 max_num_arc_out[0x08];
1826         u8 max_num_sample[0x08];
1827         u8 reserved_at_78[0x07];
1828         u8 sample_id_in_out[0x1];
1829         u8 max_base_header_length[0x10];
1830         u8 reserved_at_90[0x08];
1831         u8 max_sample_base_offset[0x08];
1832         u8 max_next_header_offset[0x10];
1833         u8 reserved_at_b0[0x08];
1834         u8 header_length_mask_width[0x08];
1835 };
1836
1837 struct mlx5_ifc_flow_table_prop_layout_bits {
1838         u8 ft_support[0x1];
1839         u8 flow_tag[0x1];
1840         u8 flow_counter[0x1];
1841         u8 flow_modify_en[0x1];
1842         u8 modify_root[0x1];
1843         u8 identified_miss_table[0x1];
1844         u8 flow_table_modify[0x1];
1845         u8 reformat[0x1];
1846         u8 decap[0x1];
1847         u8 reset_root_to_default[0x1];
1848         u8 pop_vlan[0x1];
1849         u8 push_vlan[0x1];
1850         u8 fpga_vendor_acceleration[0x1];
1851         u8 pop_vlan_2[0x1];
1852         u8 push_vlan_2[0x1];
1853         u8 reformat_and_vlan_action[0x1];
1854         u8 modify_and_vlan_action[0x1];
1855         u8 sw_owner[0x1];
1856         u8 reformat_l3_tunnel_to_l2[0x1];
1857         u8 reformat_l2_to_l3_tunnel[0x1];
1858         u8 reformat_and_modify_action[0x1];
1859         u8 reserved_at_15[0x9];
1860         u8 sw_owner_v2[0x1];
1861         u8 reserved_at_1f[0x1];
1862         u8 reserved_at_20[0x2];
1863         u8 log_max_ft_size[0x6];
1864         u8 log_max_modify_header_context[0x8];
1865         u8 max_modify_header_actions[0x8];
1866         u8 max_ft_level[0x8];
1867         u8 reserved_at_40[0x8];
1868         u8 log_max_ft_sampler_num[8];
1869         u8 metadata_reg_b_width[0x8];
1870         u8 metadata_reg_a_width[0x8];
1871         u8 reserved_at_60[0x18];
1872         u8 log_max_ft_num[0x8];
1873         u8 reserved_at_80[0x10];
1874         u8 log_max_flow_counter[0x8];
1875         u8 log_max_destination[0x8];
1876         u8 reserved_at_a0[0x18];
1877         u8 log_max_flow[0x8];
1878         u8 reserved_at_c0[0x140];
1879 };
1880
1881 struct mlx5_ifc_roce_caps_bits {
1882         u8 reserved_0[0x1e];
1883         u8 qp_ts_format[0x2];
1884         u8 reserved_at_20[0x7e0];
1885 };
1886
1887 /*
1888  * Table 1872 - Flow Table Fields Supported 2 Format
1889  */
1890 struct mlx5_ifc_ft_fields_support_2_bits {
1891         u8 reserved_at_0[0xf];
1892         u8 tunnel_header_2_3[0x1];
1893         u8 tunnel_header_0_1[0x1];
1894         u8 macsec_syndrome[0x1];
1895         u8 macsec_tag[0x1];
1896         u8 outer_lrh_sl[0x1];
1897         u8 inner_ipv4_ihl[0x1];
1898         u8 outer_ipv4_ihl[0x1];
1899         u8 psp_syndrome[0x1];
1900         u8 inner_l3_ok[0x1];
1901         u8 inner_l4_ok[0x1];
1902         u8 outer_l3_ok[0x1];
1903         u8 outer_l4_ok[0x1];
1904         u8 psp_header[0x1];
1905         u8 inner_ipv4_checksum_ok[0x1];
1906         u8 inner_l4_checksum_ok[0x1];
1907         u8 outer_ipv4_checksum_ok[0x1];
1908         u8 outer_l4_checksum_ok[0x1];
1909         u8 reserved_at_20[0x60];
1910 };
1911
1912 struct mlx5_ifc_flow_table_nic_cap_bits {
1913         u8 reserved_at_0[0x200];
1914         struct mlx5_ifc_flow_table_prop_layout_bits
1915                 flow_table_properties_nic_receive;
1916         struct mlx5_ifc_flow_table_prop_layout_bits
1917                 flow_table_properties_nic_receive_rdma;
1918         struct mlx5_ifc_flow_table_prop_layout_bits
1919                 flow_table_properties_nic_receive_sniffer;
1920         struct mlx5_ifc_flow_table_prop_layout_bits
1921                 flow_table_properties_nic_transmit;
1922         struct mlx5_ifc_flow_table_prop_layout_bits
1923                 flow_table_properties_nic_transmit_rdma;
1924         struct mlx5_ifc_flow_table_prop_layout_bits
1925                 flow_table_properties_nic_transmit_sniffer;
1926         u8 reserved_at_e00[0x600];
1927         struct mlx5_ifc_ft_fields_support_2_bits
1928                 ft_field_support_2_nic_receive;
1929 };
1930
1931 /*
1932  *  HCA Capabilities 2
1933  */
1934 struct mlx5_ifc_cmd_hca_cap_2_bits {
1935         u8 reserved_at_0[0x80]; /* End of DW4. */
1936         u8 reserved_at_80[0x3];
1937         u8 max_num_prog_sample_field[0x5];
1938         u8 reserved_at_88[0x3];
1939         u8 log_max_num_reserved_qpn[0x5];
1940         u8 reserved_at_90[0x3];
1941         u8 log_reserved_qpn_granularity[0x5];
1942         u8 reserved_at_98[0x3];
1943         u8 log_reserved_qpn_max_alloc[0x5]; /* End of DW5. */
1944         u8 max_reformat_insert_size[0x8];
1945         u8 max_reformat_insert_offset[0x8];
1946         u8 max_reformat_remove_size[0x8];
1947         u8 max_reformat_remove_offset[0x8]; /* End of DW6. */
1948         u8 reserved_at_c0[0x3];
1949         u8 log_min_stride_wqe_sz[0x5];
1950         u8 reserved_at_c8[0x3];
1951         u8 log_conn_track_granularity[0x5];
1952         u8 reserved_at_d0[0x3];
1953         u8 log_conn_track_max_alloc[0x5];
1954         u8 reserved_at_d8[0x3];
1955         u8 log_max_conn_track_offload[0x5];
1956         u8 reserved_at_e0[0x20]; /* End of DW7. */
1957         u8 reserved_at_100[0x700];
1958 };
1959
1960 struct mlx5_ifc_esw_cap_bits {
1961         u8 reserved_at_0[0x60];
1962
1963         u8 esw_manager_vport_number_valid[0x1];
1964         u8 reserved_at_61[0xf];
1965         u8 esw_manager_vport_number[0x10];
1966
1967         u8 reserved_at_80[0x780];
1968 };
1969
1970 union mlx5_ifc_hca_cap_union_bits {
1971         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1972         struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
1973         struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1974                per_protocol_networking_offload_caps;
1975         struct mlx5_ifc_qos_cap_bits qos_cap;
1976         struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
1977         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1978         struct mlx5_ifc_esw_cap_bits esw_cap;
1979         struct mlx5_ifc_roce_caps_bits roce_caps;
1980         u8 reserved_at_0[0x8000];
1981 };
1982
1983 struct mlx5_ifc_set_action_in_bits {
1984         u8 action_type[0x4];
1985         u8 field[0xc];
1986         u8 reserved_at_10[0x3];
1987         u8 offset[0x5];
1988         u8 reserved_at_18[0x3];
1989         u8 length[0x5];
1990         u8 data[0x20];
1991 };
1992
1993 struct mlx5_ifc_query_hca_cap_out_bits {
1994         u8 status[0x8];
1995         u8 reserved_at_8[0x18];
1996         u8 syndrome[0x20];
1997         u8 reserved_at_40[0x40];
1998         union mlx5_ifc_hca_cap_union_bits capability;
1999 };
2000
2001 struct mlx5_ifc_query_hca_cap_in_bits {
2002         u8 opcode[0x10];
2003         u8 reserved_at_10[0x10];
2004         u8 reserved_at_20[0x10];
2005         u8 op_mod[0x10];
2006         u8 reserved_at_40[0x40];
2007 };
2008
2009 struct mlx5_ifc_mac_address_layout_bits {
2010         u8 reserved_at_0[0x10];
2011         u8 mac_addr_47_32[0x10];
2012         u8 mac_addr_31_0[0x20];
2013 };
2014
2015 struct mlx5_ifc_nic_vport_context_bits {
2016         u8 reserved_at_0[0x5];
2017         u8 min_wqe_inline_mode[0x3];
2018         u8 reserved_at_8[0x15];
2019         u8 disable_mc_local_lb[0x1];
2020         u8 disable_uc_local_lb[0x1];
2021         u8 roce_en[0x1];
2022         u8 arm_change_event[0x1];
2023         u8 reserved_at_21[0x1a];
2024         u8 event_on_mtu[0x1];
2025         u8 event_on_promisc_change[0x1];
2026         u8 event_on_vlan_change[0x1];
2027         u8 event_on_mc_address_change[0x1];
2028         u8 event_on_uc_address_change[0x1];
2029         u8 reserved_at_40[0xc];
2030         u8 affiliation_criteria[0x4];
2031         u8 affiliated_vhca_id[0x10];
2032         u8 reserved_at_60[0xd0];
2033         u8 mtu[0x10];
2034         u8 system_image_guid[0x40];
2035         u8 port_guid[0x40];
2036         u8 node_guid[0x40];
2037         u8 reserved_at_200[0x140];
2038         u8 qkey_violation_counter[0x10];
2039         u8 reserved_at_350[0x430];
2040         u8 promisc_uc[0x1];
2041         u8 promisc_mc[0x1];
2042         u8 promisc_all[0x1];
2043         u8 reserved_at_783[0x2];
2044         u8 allowed_list_type[0x3];
2045         u8 reserved_at_788[0xc];
2046         u8 allowed_list_size[0xc];
2047         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2048         u8 reserved_at_7e0[0x20];
2049 };
2050
2051 struct mlx5_ifc_query_nic_vport_context_out_bits {
2052         u8 status[0x8];
2053         u8 reserved_at_8[0x18];
2054         u8 syndrome[0x20];
2055         u8 reserved_at_40[0x40];
2056         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
2057 };
2058
2059 struct mlx5_ifc_query_nic_vport_context_in_bits {
2060         u8 opcode[0x10];
2061         u8 reserved_at_10[0x10];
2062         u8 reserved_at_20[0x10];
2063         u8 op_mod[0x10];
2064         u8 other_vport[0x1];
2065         u8 reserved_at_41[0xf];
2066         u8 vport_number[0x10];
2067         u8 reserved_at_60[0x5];
2068         u8 allowed_list_type[0x3];
2069         u8 reserved_at_68[0x18];
2070 };
2071
2072 /*
2073  * lag_tx_port_affinity: 0 auto-selection, 1 PF1, 2 PF2 vice versa.
2074  * Each TIS binds to one PF by setting lag_tx_port_affinity (>0).
2075  * Once LAG enabled, we create multiple TISs and bind each one to
2076  * different PFs, then TIS[i] gets affinity i+1 and goes to PF i+1.
2077  */
2078 #define MLX5_IFC_LAG_MAP_TIS_AFFINITY(index, num) ((num) ? \
2079                                                     (index) % (num) + 1 : 0)
2080 struct mlx5_ifc_tisc_bits {
2081         u8 strict_lag_tx_port_affinity[0x1];
2082         u8 reserved_at_1[0x3];
2083         u8 lag_tx_port_affinity[0x04];
2084         u8 reserved_at_8[0x4];
2085         u8 prio[0x4];
2086         u8 reserved_at_10[0x10];
2087         u8 reserved_at_20[0x100];
2088         u8 reserved_at_120[0x8];
2089         u8 transport_domain[0x18];
2090         u8 reserved_at_140[0x8];
2091         u8 underlay_qpn[0x18];
2092         u8 reserved_at_160[0x3a0];
2093 };
2094
2095 struct mlx5_ifc_query_tis_out_bits {
2096         u8 status[0x8];
2097         u8 reserved_at_8[0x18];
2098         u8 syndrome[0x20];
2099         u8 reserved_at_40[0x40];
2100         struct mlx5_ifc_tisc_bits tis_context;
2101 };
2102
2103 struct mlx5_ifc_query_tis_in_bits {
2104         u8 opcode[0x10];
2105         u8 reserved_at_10[0x10];
2106         u8 reserved_at_20[0x10];
2107         u8 op_mod[0x10];
2108         u8 reserved_at_40[0x8];
2109         u8 tisn[0x18];
2110         u8 reserved_at_60[0x20];
2111 };
2112
2113 /* port_select_mode definition. */
2114 enum mlx5_lag_mode_type {
2115         MLX5_LAG_MODE_TIS = 0,
2116         MLX5_LAG_MODE_HASH = 1,
2117 };
2118
2119 struct mlx5_ifc_lag_context_bits {
2120         u8 fdb_selection_mode[0x1];
2121         u8 reserved_at_1[0x14];
2122         u8 port_select_mode[0x3];
2123         u8 reserved_at_18[0x5];
2124         u8 lag_state[0x3];
2125         u8 reserved_at_20[0x14];
2126         u8 tx_remap_affinity_2[0x4];
2127         u8 reserved_at_38[0x4];
2128         u8 tx_remap_affinity_1[0x4];
2129 };
2130
2131 struct mlx5_ifc_query_lag_in_bits {
2132         u8 opcode[0x10];
2133         u8 uid[0x10];
2134         u8 reserved_at_20[0x10];
2135         u8 op_mod[0x10];
2136         u8 reserved_at_40[0x40];
2137 };
2138
2139 struct mlx5_ifc_query_lag_out_bits {
2140         u8 status[0x8];
2141         u8 reserved_at_8[0x18];
2142         u8 syndrome[0x20];
2143         struct mlx5_ifc_lag_context_bits context;
2144 };
2145
2146 struct mlx5_ifc_alloc_transport_domain_out_bits {
2147         u8 status[0x8];
2148         u8 reserved_at_8[0x18];
2149         u8 syndrome[0x20];
2150         u8 reserved_at_40[0x8];
2151         u8 transport_domain[0x18];
2152         u8 reserved_at_60[0x20];
2153 };
2154
2155 struct mlx5_ifc_alloc_transport_domain_in_bits {
2156         u8 opcode[0x10];
2157         u8 reserved_at_10[0x10];
2158         u8 reserved_at_20[0x10];
2159         u8 op_mod[0x10];
2160         u8 reserved_at_40[0x40];
2161 };
2162
2163 enum {
2164         MLX5_WQ_TYPE_LINKED_LIST                = 0x0,
2165         MLX5_WQ_TYPE_CYCLIC                     = 0x1,
2166         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ    = 0x2,
2167         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ         = 0x3,
2168 };
2169
2170 enum {
2171         MLX5_WQ_END_PAD_MODE_NONE  = 0x0,
2172         MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
2173 };
2174
2175 struct mlx5_ifc_wq_bits {
2176         u8 wq_type[0x4];
2177         u8 wq_signature[0x1];
2178         u8 end_padding_mode[0x2];
2179         u8 cd_slave[0x1];
2180         u8 reserved_at_8[0x18];
2181         u8 hds_skip_first_sge[0x1];
2182         u8 log2_hds_buf_size[0x3];
2183         u8 reserved_at_24[0x7];
2184         u8 page_offset[0x5];
2185         u8 lwm[0x10];
2186         u8 reserved_at_40[0x8];
2187         u8 pd[0x18];
2188         u8 reserved_at_60[0x8];
2189         u8 uar_page[0x18];
2190         u8 dbr_addr[0x40];
2191         u8 hw_counter[0x20];
2192         u8 sw_counter[0x20];
2193         u8 reserved_at_100[0xc];
2194         u8 log_wq_stride[0x4];
2195         u8 reserved_at_110[0x3];
2196         u8 log_wq_pg_sz[0x5];
2197         u8 reserved_at_118[0x3];
2198         u8 log_wq_sz[0x5];
2199         u8 dbr_umem_valid[0x1];
2200         u8 wq_umem_valid[0x1];
2201         u8 reserved_at_122[0x1];
2202         u8 log_hairpin_num_packets[0x5];
2203         u8 reserved_at_128[0x3];
2204         u8 log_hairpin_data_sz[0x5];
2205         u8 reserved_at_130[0x4];
2206         u8 single_wqe_log_num_of_strides[0x4];
2207         u8 two_byte_shift_en[0x1];
2208         u8 reserved_at_139[0x4];
2209         u8 single_stride_log_num_of_bytes[0x3];
2210         u8 dbr_umem_id[0x20];
2211         u8 wq_umem_id[0x20];
2212         u8 wq_umem_offset[0x40];
2213         u8 reserved_at_1c0[0x440];
2214 };
2215
2216 enum {
2217         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2218         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2219 };
2220
2221 enum {
2222         MLX5_RQC_STATE_RST  = 0x0,
2223         MLX5_RQC_STATE_RDY  = 0x1,
2224         MLX5_RQC_STATE_ERR  = 0x3,
2225 };
2226
2227 struct mlx5_ifc_rqc_bits {
2228         u8 rlky[0x1];
2229         u8 delay_drop_en[0x1];
2230         u8 scatter_fcs[0x1];
2231         u8 vsd[0x1];
2232         u8 mem_rq_type[0x4];
2233         u8 state[0x4];
2234         u8 reserved_at_c[0x1];
2235         u8 flush_in_error_en[0x1];
2236         u8 hairpin[0x1];
2237         u8 reserved_at_f[0xB];
2238         u8 ts_format[0x02];
2239         u8 reserved_at_1c[0x4];
2240         u8 reserved_at_20[0x8];
2241         u8 user_index[0x18];
2242         u8 reserved_at_40[0x8];
2243         u8 cqn[0x18];
2244         u8 counter_set_id[0x8];
2245         u8 reserved_at_68[0x18];
2246         u8 reserved_at_80[0x8];
2247         u8 rmpn[0x18];
2248         u8 reserved_at_a0[0x8];
2249         u8 hairpin_peer_sq[0x18];
2250         u8 reserved_at_c0[0x10];
2251         u8 hairpin_peer_vhca[0x10];
2252         u8 reserved_at_e0[0xa0];
2253         struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
2254 };
2255
2256 struct mlx5_ifc_create_rq_out_bits {
2257         u8 status[0x8];
2258         u8 reserved_at_8[0x18];
2259         u8 syndrome[0x20];
2260         u8 reserved_at_40[0x8];
2261         u8 rqn[0x18];
2262         u8 reserved_at_60[0x20];
2263 };
2264
2265 struct mlx5_ifc_create_rq_in_bits {
2266         u8 opcode[0x10];
2267         u8 uid[0x10];
2268         u8 reserved_at_20[0x10];
2269         u8 op_mod[0x10];
2270         u8 reserved_at_40[0xc0];
2271         struct mlx5_ifc_rqc_bits ctx;
2272 };
2273
2274 struct mlx5_ifc_modify_rq_out_bits {
2275         u8 status[0x8];
2276         u8 reserved_at_8[0x18];
2277         u8 syndrome[0x20];
2278         u8 reserved_at_40[0x40];
2279 };
2280
2281 struct mlx5_ifc_query_rq_out_bits {
2282         u8 status[0x8];
2283         u8 reserved_at_8[0x18];
2284         u8 syndrome[0x20];
2285         u8 reserved_at_40[0xc0];
2286         struct mlx5_ifc_rqc_bits rq_context;
2287 };
2288
2289 struct mlx5_ifc_query_rq_in_bits {
2290         u8 opcode[0x10];
2291         u8 reserved_at_10[0x10];
2292         u8 reserved_at_20[0x10];
2293         u8 op_mod[0x10];
2294         u8 reserved_at_40[0x8];
2295         u8 rqn[0x18];
2296         u8 reserved_at_60[0x20];
2297 };
2298
2299 enum {
2300         MLX5_RMPC_STATE_RDY = 0x1,
2301         MLX5_RMPC_STATE_ERR = 0x3,
2302 };
2303
2304 struct mlx5_ifc_rmpc_bits {
2305         u8 reserved_at_0[0x8];
2306         u8 state[0x4];
2307         u8 reserved_at_c[0x14];
2308         u8 basic_cyclic_rcv_wqe[0x1];
2309         u8 reserved_at_21[0x1f];
2310         u8 reserved_at_40[0x140];
2311         struct mlx5_ifc_wq_bits wq;
2312 };
2313
2314 struct mlx5_ifc_query_rmp_out_bits {
2315         u8 status[0x8];
2316         u8 reserved_at_8[0x18];
2317         u8 syndrome[0x20];
2318         u8 reserved_at_40[0xc0];
2319         struct mlx5_ifc_rmpc_bits rmp_context;
2320 };
2321
2322 struct mlx5_ifc_query_rmp_in_bits {
2323         u8 opcode[0x10];
2324         u8 reserved_at_10[0x10];
2325         u8 reserved_at_20[0x10];
2326         u8 op_mod[0x10];
2327         u8 reserved_at_40[0x8];
2328         u8 rmpn[0x18];
2329         u8 reserved_at_60[0x20];
2330 };
2331
2332 struct mlx5_ifc_modify_rmp_out_bits {
2333         u8 status[0x8];
2334         u8 reserved_at_8[0x18];
2335         u8 syndrome[0x20];
2336         u8 reserved_at_40[0x40];
2337 };
2338
2339 struct mlx5_ifc_rmp_bitmask_bits {
2340         u8 reserved_at_0[0x20];
2341         u8 reserved_at_20[0x1f];
2342         u8 lwm[0x1];
2343 };
2344
2345 struct mlx5_ifc_modify_rmp_in_bits {
2346         u8 opcode[0x10];
2347         u8 uid[0x10];
2348         u8 reserved_at_20[0x10];
2349         u8 op_mod[0x10];
2350         u8 rmp_state[0x4];
2351         u8 reserved_at_44[0x4];
2352         u8 rmpn[0x18];
2353         u8 reserved_at_60[0x20];
2354         struct mlx5_ifc_rmp_bitmask_bits bitmask;
2355         u8 reserved_at_c0[0x40];
2356         struct mlx5_ifc_rmpc_bits ctx;
2357 };
2358
2359 struct mlx5_ifc_create_rmp_out_bits {
2360         u8 status[0x8];
2361         u8 reserved_at_8[0x18];
2362         u8 syndrome[0x20];
2363         u8 reserved_at_40[0x8];
2364         u8 rmpn[0x18];
2365         u8 reserved_at_60[0x20];
2366 };
2367
2368 struct mlx5_ifc_create_rmp_in_bits {
2369         u8 opcode[0x10];
2370         u8 uid[0x10];
2371         u8 reserved_at_20[0x10];
2372         u8 op_mod[0x10];
2373         u8 reserved_at_40[0xc0];
2374         struct mlx5_ifc_rmpc_bits ctx;
2375 };
2376
2377 struct mlx5_ifc_create_tis_out_bits {
2378         u8 status[0x8];
2379         u8 reserved_at_8[0x18];
2380         u8 syndrome[0x20];
2381         u8 reserved_at_40[0x8];
2382         u8 tisn[0x18];
2383         u8 reserved_at_60[0x20];
2384 };
2385
2386 struct mlx5_ifc_create_tis_in_bits {
2387         u8 opcode[0x10];
2388         u8 uid[0x10];
2389         u8 reserved_at_20[0x10];
2390         u8 op_mod[0x10];
2391         u8 reserved_at_40[0xc0];
2392         struct mlx5_ifc_tisc_bits ctx;
2393 };
2394
2395 enum {
2396         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
2397         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
2398         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
2399         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
2400 };
2401
2402 struct mlx5_ifc_modify_rq_in_bits {
2403         u8 opcode[0x10];
2404         u8 uid[0x10];
2405         u8 reserved_at_20[0x10];
2406         u8 op_mod[0x10];
2407         u8 rq_state[0x4];
2408         u8 reserved_at_44[0x4];
2409         u8 rqn[0x18];
2410         u8 reserved_at_60[0x20];
2411         u8 modify_bitmask[0x40];
2412         u8 reserved_at_c0[0x40];
2413         struct mlx5_ifc_rqc_bits ctx;
2414 };
2415
2416 enum {
2417         MLX5_L3_PROT_TYPE_IPV4 = 0,
2418         MLX5_L3_PROT_TYPE_IPV6 = 1,
2419 };
2420
2421 enum {
2422         MLX5_L4_PROT_TYPE_TCP = 0,
2423         MLX5_L4_PROT_TYPE_UDP = 1,
2424 };
2425
2426 enum {
2427         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
2428         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
2429         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
2430         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
2431         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
2432 };
2433
2434 struct mlx5_ifc_rx_hash_field_select_bits {
2435         u8 l3_prot_type[0x1];
2436         u8 l4_prot_type[0x1];
2437         u8 selected_fields[0x1e];
2438 };
2439
2440 enum {
2441         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2442         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2443 };
2444
2445 enum {
2446         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2447         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2448 };
2449
2450 enum {
2451         MLX5_RX_HASH_FN_NONE           = 0x0,
2452         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2453         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2454 };
2455
2456 enum {
2457         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
2458         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
2459 };
2460
2461 enum {
2462         MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4    = 0x0,
2463         MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2  = 0x1,
2464 };
2465
2466 struct mlx5_ifc_tirc_bits {
2467         u8 reserved_at_0[0x20];
2468         u8 disp_type[0x4];
2469         u8 reserved_at_24[0x1c];
2470         u8 reserved_at_40[0x40];
2471         u8 reserved_at_80[0x4];
2472         u8 lro_timeout_period_usecs[0x10];
2473         u8 lro_enable_mask[0x4];
2474         u8 lro_max_msg_sz[0x8];
2475         u8 reserved_at_a0[0x40];
2476         u8 reserved_at_e0[0x8];
2477         u8 inline_rqn[0x18];
2478         u8 rx_hash_symmetric[0x1];
2479         u8 reserved_at_101[0x1];
2480         u8 tunneled_offload_en[0x1];
2481         u8 reserved_at_103[0x5];
2482         u8 indirect_table[0x18];
2483         u8 rx_hash_fn[0x4];
2484         u8 reserved_at_124[0x2];
2485         u8 self_lb_block[0x2];
2486         u8 transport_domain[0x18];
2487         u8 rx_hash_toeplitz_key[10][0x20];
2488         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2489         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2490         u8 reserved_at_2c0[0x4c0];
2491 };
2492
2493 struct mlx5_ifc_create_tir_out_bits {
2494         u8 status[0x8];
2495         u8 reserved_at_8[0x18];
2496         u8 syndrome[0x20];
2497         u8 reserved_at_40[0x8];
2498         u8 tirn[0x18];
2499         u8 reserved_at_60[0x20];
2500 };
2501
2502 struct mlx5_ifc_create_tir_in_bits {
2503         u8 opcode[0x10];
2504         u8 uid[0x10];
2505         u8 reserved_at_20[0x10];
2506         u8 op_mod[0x10];
2507         u8 reserved_at_40[0xc0];
2508         struct mlx5_ifc_tirc_bits ctx;
2509 };
2510
2511 enum {
2512         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0,
2513         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1,
2514         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2,
2515         /* bit 3 - tunneled_offload_en modify not supported. */
2516         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4,
2517 };
2518
2519 struct mlx5_ifc_modify_tir_out_bits {
2520         u8 status[0x8];
2521         u8 reserved_at_8[0x18];
2522         u8 syndrome[0x20];
2523         u8 reserved_at_40[0x40];
2524 };
2525
2526 struct mlx5_ifc_modify_tir_in_bits {
2527         u8 opcode[0x10];
2528         u8 uid[0x10];
2529         u8 reserved_at_20[0x10];
2530         u8 op_mod[0x10];
2531         u8 reserved_at_40[0x8];
2532         u8 tirn[0x18];
2533         u8 reserved_at_60[0x20];
2534         u8 modify_bitmask[0x40];
2535         u8 reserved_at_c0[0x40];
2536         struct mlx5_ifc_tirc_bits ctx;
2537 };
2538
2539 enum {
2540         MLX5_INLINE_Q_TYPE_RQ = 0x0,
2541         MLX5_INLINE_Q_TYPE_VIRTQ = 0x1,
2542 };
2543
2544 struct mlx5_ifc_rq_num_bits {
2545         u8 reserved_at_0[0x8];
2546         u8 rq_num[0x18];
2547 };
2548
2549 struct mlx5_ifc_rqtc_bits {
2550         u8 reserved_at_0[0xa5];
2551         u8 list_q_type[0x3];
2552         u8 reserved_at_a8[0x8];
2553         u8 rqt_max_size[0x10];
2554         u8 reserved_at_c0[0x10];
2555         u8 rqt_actual_size[0x10];
2556         u8 reserved_at_e0[0x6a0];
2557         struct mlx5_ifc_rq_num_bits rq_num[];
2558 };
2559
2560 struct mlx5_ifc_create_rqt_out_bits {
2561         u8 status[0x8];
2562         u8 reserved_at_8[0x18];
2563         u8 syndrome[0x20];
2564         u8 reserved_at_40[0x8];
2565         u8 rqtn[0x18];
2566         u8 reserved_at_60[0x20];
2567 };
2568
2569 #ifdef PEDANTIC
2570 #pragma GCC diagnostic ignored "-Wpedantic"
2571 #endif
2572 struct mlx5_ifc_create_rqt_in_bits {
2573         u8 opcode[0x10];
2574         u8 uid[0x10];
2575         u8 reserved_at_20[0x10];
2576         u8 op_mod[0x10];
2577         u8 reserved_at_40[0xc0];
2578         struct mlx5_ifc_rqtc_bits rqt_context;
2579 };
2580
2581 struct mlx5_ifc_modify_rqt_in_bits {
2582         u8 opcode[0x10];
2583         u8 uid[0x10];
2584         u8 reserved_at_20[0x10];
2585         u8 op_mod[0x10];
2586         u8 reserved_at_40[0x8];
2587         u8 rqtn[0x18];
2588         u8 reserved_at_60[0x20];
2589         u8 modify_bitmask[0x40];
2590         u8 reserved_at_c0[0x40];
2591         struct mlx5_ifc_rqtc_bits rqt_context;
2592 };
2593 #ifdef PEDANTIC
2594 #pragma GCC diagnostic error "-Wpedantic"
2595 #endif
2596
2597 struct mlx5_ifc_modify_rqt_out_bits {
2598         u8 status[0x8];
2599         u8 reserved_at_8[0x18];
2600         u8 syndrome[0x20];
2601         u8 reserved_at_40[0x40];
2602 };
2603
2604 enum {
2605         MLX5_SQC_STATE_RST  = 0x0,
2606         MLX5_SQC_STATE_RDY  = 0x1,
2607         MLX5_SQC_STATE_ERR  = 0x3,
2608 };
2609
2610 struct mlx5_ifc_sqc_bits {
2611         u8 rlky[0x1];
2612         u8 cd_master[0x1];
2613         u8 fre[0x1];
2614         u8 flush_in_error_en[0x1];
2615         u8 allow_multi_pkt_send_wqe[0x1];
2616         u8 min_wqe_inline_mode[0x3];
2617         u8 state[0x4];
2618         u8 reg_umr[0x1];
2619         u8 allow_swp[0x1];
2620         u8 hairpin[0x1];
2621         u8 non_wire[0x1];
2622         u8 static_sq_wq[0x1];
2623         u8 reserved_at_11[0x9];
2624         u8 ts_format[0x02];
2625         u8 reserved_at_1c[0x4];
2626         u8 reserved_at_20[0x8];
2627         u8 user_index[0x18];
2628         u8 reserved_at_40[0x8];
2629         u8 cqn[0x18];
2630         u8 reserved_at_60[0x8];
2631         u8 hairpin_peer_rq[0x18];
2632         u8 reserved_at_80[0x10];
2633         u8 hairpin_peer_vhca[0x10];
2634         u8 reserved_at_a0[0x50];
2635         u8 packet_pacing_rate_limit_index[0x10];
2636         u8 tis_lst_sz[0x10];
2637         u8 reserved_at_110[0x10];
2638         u8 reserved_at_120[0x40];
2639         u8 reserved_at_160[0x8];
2640         u8 tis_num_0[0x18];
2641         struct mlx5_ifc_wq_bits wq;
2642 };
2643
2644 struct mlx5_ifc_query_sq_in_bits {
2645         u8 opcode[0x10];
2646         u8 reserved_at_10[0x10];
2647         u8 reserved_at_20[0x10];
2648         u8 op_mod[0x10];
2649         u8 reserved_at_40[0x8];
2650         u8 sqn[0x18];
2651         u8 reserved_at_60[0x20];
2652 };
2653
2654 struct mlx5_ifc_modify_sq_out_bits {
2655         u8 status[0x8];
2656         u8 reserved_at_8[0x18];
2657         u8 syndrome[0x20];
2658         u8 reserved_at_40[0x40];
2659 };
2660
2661 struct mlx5_ifc_modify_sq_in_bits {
2662         u8 opcode[0x10];
2663         u8 uid[0x10];
2664         u8 reserved_at_20[0x10];
2665         u8 op_mod[0x10];
2666         u8 sq_state[0x4];
2667         u8 reserved_at_44[0x4];
2668         u8 sqn[0x18];
2669         u8 reserved_at_60[0x20];
2670         u8 modify_bitmask[0x40];
2671         u8 reserved_at_c0[0x40];
2672         struct mlx5_ifc_sqc_bits ctx;
2673 };
2674
2675 struct mlx5_ifc_create_sq_out_bits {
2676         u8 status[0x8];
2677         u8 reserved_at_8[0x18];
2678         u8 syndrome[0x20];
2679         u8 reserved_at_40[0x8];
2680         u8 sqn[0x18];
2681         u8 reserved_at_60[0x20];
2682 };
2683
2684 struct mlx5_ifc_create_sq_in_bits {
2685         u8 opcode[0x10];
2686         u8 uid[0x10];
2687         u8 reserved_at_20[0x10];
2688         u8 op_mod[0x10];
2689         u8 reserved_at_40[0xc0];
2690         struct mlx5_ifc_sqc_bits ctx;
2691 };
2692
2693 enum {
2694         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
2695         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
2696         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
2697         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
2698         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
2699 };
2700
2701 struct mlx5_ifc_flow_meter_parameters_bits {
2702         u8 valid[0x1];
2703         u8 bucket_overflow[0x1];
2704         u8 start_color[0x2];
2705         u8 both_buckets_on_green[0x1];
2706         u8 meter_mode[0x2];
2707         u8 reserved_at_1[0x19];
2708         u8 reserved_at_2[0x20];
2709         u8 reserved_at_3[0x3];
2710         u8 cbs_exponent[0x5];
2711         u8 cbs_mantissa[0x8];
2712         u8 reserved_at_4[0x3];
2713         u8 cir_exponent[0x5];
2714         u8 cir_mantissa[0x8];
2715         u8 reserved_at_5[0x20];
2716         u8 reserved_at_6[0x3];
2717         u8 ebs_exponent[0x5];
2718         u8 ebs_mantissa[0x8];
2719         u8 reserved_at_7[0x3];
2720         u8 eir_exponent[0x5];
2721         u8 eir_mantissa[0x8];
2722         u8 reserved_at_8[0x60];
2723 };
2724 #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF)
2725 #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8
2726
2727 enum {
2728         MLX5_METER_MODE_IP_LEN = 0x0,
2729         MLX5_METER_MODE_L2_LEN = 0x1,
2730         MLX5_METER_MODE_L2_IPG_LEN = 0x2,
2731         MLX5_METER_MODE_PKT = 0x3,
2732 };
2733
2734 enum {
2735         MLX5_CQE_SIZE_64B = 0x0,
2736         MLX5_CQE_SIZE_128B = 0x1,
2737 };
2738
2739 struct mlx5_ifc_cqc_bits {
2740         u8 status[0x4];
2741         u8 as_notify[0x1];
2742         u8 initiator_src_dct[0x1];
2743         u8 dbr_umem_valid[0x1];
2744         u8 reserved_at_7[0x1];
2745         u8 cqe_sz[0x3];
2746         u8 cc[0x1];
2747         u8 reserved_at_c[0x1];
2748         u8 scqe_break_moderation_en[0x1];
2749         u8 oi[0x1];
2750         u8 cq_period_mode[0x2];
2751         u8 cqe_comp_en[0x1];
2752         u8 mini_cqe_res_format[0x2];
2753         u8 st[0x4];
2754         u8 reserved_at_18[0x1];
2755         u8 cqe_comp_layout[0x7];
2756         u8 dbr_umem_id[0x20];
2757         u8 reserved_at_40[0x14];
2758         u8 page_offset[0x6];
2759         u8 reserved_at_5a[0x2];
2760         u8 mini_cqe_res_format_ext[0x2];
2761         u8 cq_timestamp_format[0x2];
2762         u8 reserved_at_60[0x3];
2763         u8 log_cq_size[0x5];
2764         u8 uar_page[0x18];
2765         u8 reserved_at_80[0x4];
2766         u8 cq_period[0xc];
2767         u8 cq_max_count[0x10];
2768         u8 reserved_at_a0[0x18];
2769         u8 c_eqn[0x8];
2770         u8 reserved_at_c0[0x3];
2771         u8 log_page_size[0x5];
2772         u8 reserved_at_c8[0x18];
2773         u8 reserved_at_e0[0x20];
2774         u8 reserved_at_100[0x8];
2775         u8 last_notified_index[0x18];
2776         u8 reserved_at_120[0x8];
2777         u8 last_solicit_index[0x18];
2778         u8 reserved_at_140[0x8];
2779         u8 consumer_counter[0x18];
2780         u8 reserved_at_160[0x8];
2781         u8 producer_counter[0x18];
2782         u8 local_partition_id[0xc];
2783         u8 process_id[0x14];
2784         u8 reserved_at_1A0[0x20];
2785         u8 dbr_addr[0x40];
2786 };
2787
2788 struct mlx5_ifc_health_buffer_bits {
2789         u8 reserved_0[0x100];
2790         u8 assert_existptr[0x20];
2791         u8 assert_callra[0x20];
2792         u8 reserved_1[0x40];
2793         u8 fw_version[0x20];
2794         u8 hw_id[0x20];
2795         u8 reserved_2[0x20];
2796         u8 irisc_index[0x8];
2797         u8 synd[0x8];
2798         u8 ext_synd[0x10];
2799 };
2800
2801 struct mlx5_ifc_initial_seg_bits {
2802         u8 fw_rev_minor[0x10];
2803         u8 fw_rev_major[0x10];
2804         u8 cmd_interface_rev[0x10];
2805         u8 fw_rev_subminor[0x10];
2806         u8 reserved_0[0x40];
2807         u8 cmdq_phy_addr_63_32[0x20];
2808         u8 cmdq_phy_addr_31_12[0x14];
2809         u8 reserved_1[0x2];
2810         u8 nic_interface[0x2];
2811         u8 log_cmdq_size[0x4];
2812         u8 log_cmdq_stride[0x4];
2813         u8 command_doorbell_vector[0x20];
2814         u8 reserved_2[0xf00];
2815         u8 initializing[0x1];
2816         u8 nic_interface_supported[0x7];
2817         u8 reserved_4[0x18];
2818         struct mlx5_ifc_health_buffer_bits health_buffer;
2819         u8 no_dram_nic_offset[0x20];
2820         u8 reserved_5[0x6de0];
2821         u8 internal_timer_h[0x20];
2822         u8 internal_timer_l[0x20];
2823         u8 reserved_6[0x20];
2824         u8 reserved_7[0x1f];
2825         u8 clear_int[0x1];
2826         u8 health_syndrome[0x8];
2827         u8 health_counter[0x18];
2828         u8 reserved_8[0x17fc0];
2829 };
2830
2831 struct mlx5_ifc_create_cq_out_bits {
2832         u8 status[0x8];
2833         u8 reserved_at_8[0x18];
2834         u8 syndrome[0x20];
2835         u8 reserved_at_40[0x8];
2836         u8 cqn[0x18];
2837         u8 reserved_at_60[0x20];
2838 };
2839
2840 struct mlx5_ifc_create_cq_in_bits {
2841         u8 opcode[0x10];
2842         u8 uid[0x10];
2843         u8 reserved_at_20[0x10];
2844         u8 op_mod[0x10];
2845         u8 reserved_at_40[0x40];
2846         struct mlx5_ifc_cqc_bits cq_context;
2847         u8 cq_umem_offset[0x40];
2848         u8 cq_umem_id[0x20];
2849         u8 cq_umem_valid[0x1];
2850         u8 reserved_at_2e1[0x1f];
2851         u8 reserved_at_300[0x580];
2852         u8 pas[];
2853 };
2854
2855 enum {
2856         MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
2857         MLX5_GENERAL_OBJ_TYPE_DEK = 0x000c,
2858         MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
2859         MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
2860         MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d,
2861         MLX5_GENERAL_OBJ_TYPE_CREDENTIAL = 0x001e,
2862         MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN = 0x001f,
2863         MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,
2864         MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024,
2865         MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025,
2866         MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031,
2867 };
2868
2869 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
2870         u8 opcode[0x10];
2871         u8 reserved_at_10[0x20];
2872         u8 obj_type[0x10];
2873         u8 obj_id[0x20];
2874         u8 reserved_at_60[0x3];
2875         u8 log_obj_range[0x5];
2876         u8 reserved_at_58[0x18];
2877 };
2878
2879 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
2880         u8 status[0x8];
2881         u8 reserved_at_8[0x18];
2882         u8 syndrome[0x20];
2883         u8 obj_id[0x20];
2884         u8 reserved_at_60[0x20];
2885 };
2886
2887 struct mlx5_ifc_virtio_q_counters_bits {
2888         u8 modify_field_select[0x40];
2889         u8 reserved_at_40[0x40];
2890         u8 received_desc[0x40];
2891         u8 completed_desc[0x40];
2892         u8 error_cqes[0x20];
2893         u8 bad_desc_errors[0x20];
2894         u8 exceed_max_chain[0x20];
2895         u8 invalid_buffer[0x20];
2896         u8 reserved_at_180[0x50];
2897 };
2898
2899 struct mlx5_ifc_geneve_tlv_option_bits {
2900         u8 modify_field_select[0x40];
2901         u8 reserved_at_40[0x18];
2902         u8 geneve_option_fte_index[0x8];
2903         u8 option_class[0x10];
2904         u8 option_type[0x8];
2905         u8 reserved_at_78[0x3];
2906         u8 option_data_length[0x5];
2907         u8 reserved_at_80[0x180];
2908 };
2909
2910 struct mlx5_ifc_create_virtio_q_counters_in_bits {
2911         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2912         struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2913 };
2914
2915 struct mlx5_ifc_query_virtio_q_counters_out_bits {
2916         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2917         struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2918 };
2919
2920 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
2921         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2922         struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
2923 };
2924
2925 enum {
2926         MLX5_CRYPTO_KEY_SIZE_128b = 0x0,
2927         MLX5_CRYPTO_KEY_SIZE_256b = 0x1,
2928 };
2929
2930 enum {
2931         MLX5_CRYPTO_KEY_PURPOSE_TLS     = 0x1,
2932         MLX5_CRYPTO_KEY_PURPOSE_IPSEC   = 0x2,
2933         MLX5_CRYPTO_KEY_PURPOSE_AES_XTS = 0x3,
2934         MLX5_CRYPTO_KEY_PURPOSE_MACSEC  = 0x4,
2935         MLX5_CRYPTO_KEY_PURPOSE_GCM     = 0x5,
2936         MLX5_CRYPTO_KEY_PURPOSE_PSP     = 0x6,
2937 };
2938
2939 struct mlx5_ifc_dek_bits {
2940         u8 modify_field_select[0x40];
2941         u8 state[0x8];
2942         u8 reserved_at_48[0xc];
2943         u8 key_size[0x4];
2944         u8 has_keytag[0x1];
2945         u8 reserved_at_59[0x3];
2946         u8 key_purpose[0x4];
2947         u8 reserved_at_60[0x8];
2948         u8 pd[0x18];
2949         u8 reserved_at_80[0x100];
2950         u8 opaque[0x40];
2951         u8 reserved_at_1c0[0x40];
2952         u8 key[0x400];
2953         u8 reserved_at_600[0x200];
2954 };
2955
2956 struct mlx5_ifc_create_dek_in_bits {
2957         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2958         struct mlx5_ifc_dek_bits dek;
2959 };
2960
2961 struct mlx5_ifc_import_kek_bits {
2962         u8 modify_field_select[0x40];
2963         u8 state[0x8];
2964         u8 reserved_at_48[0xc];
2965         u8 key_size[0x4];
2966         u8 reserved_at_58[0x1a8];
2967         u8 key[0x400];
2968         u8 reserved_at_600[0x200];
2969 };
2970
2971 struct mlx5_ifc_create_import_kek_in_bits {
2972         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2973         struct mlx5_ifc_import_kek_bits import_kek;
2974 };
2975
2976 enum {
2977         MLX5_CREDENTIAL_ROLE_OFFICER = 0x0,
2978         MLX5_CREDENTIAL_ROLE_USER = 0x1,
2979 };
2980
2981 struct mlx5_ifc_credential_bits {
2982         u8 modify_field_select[0x40];
2983         u8 state[0x8];
2984         u8 reserved_at_48[0x10];
2985         u8 credential_role[0x8];
2986         u8 reserved_at_60[0x1a0];
2987         u8 credential[0x180];
2988         u8 reserved_at_380[0x480];
2989 };
2990
2991 struct mlx5_ifc_create_credential_in_bits {
2992         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2993         struct mlx5_ifc_credential_bits credential;
2994 };
2995
2996 struct mlx5_ifc_crypto_login_bits {
2997         u8 modify_field_select[0x40];
2998         u8 reserved_at_40[0x48];
2999         u8 credential_pointer[0x18];
3000         u8 reserved_at_a0[0x8];
3001         u8 session_import_kek_ptr[0x18];
3002         u8 reserved_at_c0[0x140];
3003         u8 credential[0x180];
3004         u8 reserved_at_380[0x480];
3005 };
3006
3007 struct mlx5_ifc_create_crypto_login_in_bits {
3008         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3009         struct mlx5_ifc_crypto_login_bits crypto_login;
3010 };
3011
3012 enum {
3013         MLX5_VIRTQ_STATE_INIT = 0,
3014         MLX5_VIRTQ_STATE_RDY = 1,
3015         MLX5_VIRTQ_STATE_SUSPEND = 2,
3016         MLX5_VIRTQ_STATE_ERROR = 3,
3017 };
3018
3019 enum {
3020         MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),
3021         MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),
3022         MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),
3023 };
3024
3025 struct mlx5_ifc_virtio_q_bits {
3026         u8 virtio_q_type[0x8];
3027         u8 reserved_at_8[0x5];
3028         u8 event_mode[0x3];
3029         u8 queue_index[0x10];
3030         u8 full_emulation[0x1];
3031         u8 virtio_version_1_0[0x1];
3032         u8 reserved_at_22[0x2];
3033         u8 offload_type[0x4];
3034         u8 event_qpn_or_msix[0x18];
3035         u8 doorbell_stride_idx[0x10];
3036         u8 queue_size[0x10];
3037         u8 device_emulation_id[0x20];
3038         u8 desc_addr[0x40];
3039         u8 used_addr[0x40];
3040         u8 available_addr[0x40];
3041         u8 virtio_q_mkey[0x20];
3042         u8 reserved_at_160[0x18];
3043         u8 error_type[0x8];
3044         u8 umem_1_id[0x20];
3045         u8 umem_1_size[0x20];
3046         u8 umem_1_offset[0x40];
3047         u8 umem_2_id[0x20];
3048         u8 umem_2_size[0x20];
3049         u8 umem_2_offset[0x40];
3050         u8 umem_3_id[0x20];
3051         u8 umem_3_size[0x20];
3052         u8 umem_3_offset[0x40];
3053         u8 counter_set_id[0x20];
3054         u8 reserved_at_320[0x8];
3055         u8 pd[0x18];
3056         u8 reserved_at_340[0x2];
3057         u8 queue_period_mode[0x2];
3058         u8 queue_period_us[0xc];
3059         u8 queue_max_count[0x10];
3060         u8 reserved_at_360[0xa0];
3061 };
3062
3063 struct mlx5_ifc_virtio_net_q_bits {
3064         u8 modify_field_select[0x40];
3065         u8 reserved_at_40[0x40];
3066         u8 tso_ipv4[0x1];
3067         u8 tso_ipv6[0x1];
3068         u8 tx_csum[0x1];
3069         u8 rx_csum[0x1];
3070         u8 reserved_at_84[0x6];
3071         u8 dirty_bitmap_dump_enable[0x1];
3072         u8 vhost_log_page[0x5];
3073         u8 reserved_at_90[0xc];
3074         u8 state[0x4];
3075         u8 reserved_at_a0[0x8];
3076         u8 tisn_or_qpn[0x18];
3077         u8 dirty_bitmap_mkey[0x20];
3078         u8 dirty_bitmap_size[0x20];
3079         u8 dirty_bitmap_addr[0x40];
3080         u8 hw_available_index[0x10];
3081         u8 hw_used_index[0x10];
3082         u8 reserved_at_160[0xa0];
3083         struct mlx5_ifc_virtio_q_bits virtio_q_context;
3084 };
3085
3086 struct mlx5_ifc_create_virtq_in_bits {
3087         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3088         struct mlx5_ifc_virtio_net_q_bits virtq;
3089 };
3090
3091 struct mlx5_ifc_query_virtq_out_bits {
3092         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3093         struct mlx5_ifc_virtio_net_q_bits virtq;
3094 };
3095
3096 struct mlx5_ifc_flow_hit_aso_bits {
3097         u8 modify_field_select[0x40];
3098         u8 reserved_at_40[0x48];
3099         u8 access_pd[0x18];
3100         u8 reserved_at_a0[0x160];
3101         u8 flag[0x200];
3102 };
3103
3104 struct mlx5_ifc_create_flow_hit_aso_in_bits {
3105         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3106         struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso;
3107 };
3108
3109 struct mlx5_ifc_flow_meter_aso_bits {
3110         u8 modify_field_select[0x40];
3111         u8 reserved_at_40[0x48];
3112         u8 access_pd[0x18];
3113         u8 reserved_at_a0[0x160];
3114         u8 parameters[0x200];
3115 };
3116
3117 struct mlx5_ifc_create_flow_meter_aso_in_bits {
3118         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3119         struct mlx5_ifc_flow_meter_aso_bits flow_meter_aso;
3120 };
3121
3122 struct mlx5_ifc_tcp_window_params_bits {
3123         u8 max_ack[0x20];
3124         u8 max_win[0x20];
3125         u8 reply_end[0x20];
3126         u8 sent_end[0x20];
3127 };
3128
3129 struct mlx5_ifc_conn_track_aso_bits {
3130         struct mlx5_ifc_tcp_window_params_bits reply_dir; /* End of DW3. */
3131         struct mlx5_ifc_tcp_window_params_bits original_dir; /* End of DW7. */
3132         u8 last_end[0x20]; /* End of DW8. */
3133         u8 last_ack[0x20]; /* End of DW9. */
3134         u8 last_seq[0x20]; /* End of DW10. */
3135         u8 last_win[0x10];
3136         u8 reserved_at_170[0xa];
3137         u8 last_dir[0x1];
3138         u8 last_index[0x5]; /* End of DW11. */
3139         u8 reserved_at_180[0x40]; /* End of DW13. */
3140         u8 reply_direction_tcp_scale[0x4];
3141         u8 reply_direction_tcp_close_initiated[0x1];
3142         u8 reply_direction_tcp_liberal_enabled[0x1];
3143         u8 reply_direction_tcp_data_unacked[0x1];
3144         u8 reply_direction_tcp_max_ack[0x1];
3145         u8 reserved_at_1c8[0x8];
3146         u8 original_direction_tcp_scale[0x4];
3147         u8 original_direction_tcp_close_initiated[0x1];
3148         u8 original_direction_tcp_liberal_enabled[0x1];
3149         u8 original_direction_tcp_data_unacked[0x1];
3150         u8 original_direction_tcp_max_ack[0x1];
3151         u8 reserved_at_1d8[0x8]; /* End of DW14. */
3152         u8 valid[0x1];
3153         u8 state[0x3];
3154         u8 freeze_track[0x1];
3155         u8 reserved_at_1e5[0xb];
3156         u8 reserved_at_1f0[0x1];
3157         u8 connection_assured[0x1];
3158         u8 sack_permitted[0x1];
3159         u8 challenged_acked[0x1];
3160         u8 heartbeat[0x1];
3161         u8 max_ack_window[0x3];
3162         u8 reserved_at_1f8[0x1];
3163         u8 retransmission_counter[0x3];
3164         u8 retranmission_limit_exceeded[0x1];
3165         u8 retranmission_limit[0x3]; /* End of DW15. */
3166 };
3167
3168 struct mlx5_ifc_conn_track_offload_bits {
3169         u8 modify_field_select[0x40];
3170         u8 reserved_at_40[0x40];
3171         u8 reserved_at_80[0x8];
3172         u8 conn_track_aso_access_pd[0x18];
3173         u8 reserved_at_a0[0x160];
3174         struct mlx5_ifc_conn_track_aso_bits conn_track_aso;
3175 };
3176
3177 struct mlx5_ifc_create_conn_track_aso_in_bits {
3178         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3179         struct mlx5_ifc_conn_track_offload_bits conn_track_offload;
3180 };
3181
3182 enum mlx5_access_aso_opc_mod {
3183         ASO_OPC_MOD_IPSEC = 0x0,
3184         ASO_OPC_MOD_CONNECTION_TRACKING = 0x1,
3185         ASO_OPC_MOD_POLICER = 0x2,
3186         ASO_OPC_MOD_RACE_AVOIDANCE = 0x3,
3187         ASO_OPC_MOD_FLOW_HIT = 0x4,
3188 };
3189
3190 #define ASO_CSEG_DATA_MASK_MODE_OFFSET  30
3191
3192 enum mlx5_aso_data_mask_mode {
3193         BITWISE_64BIT = 0x0,
3194         BYTEWISE_64BYTE = 0x1,
3195         CALCULATED_64BYTE = 0x2,
3196 };
3197
3198 #define ASO_CSEG_COND_0_OPER_OFFSET     20
3199 #define ASO_CSEG_COND_1_OPER_OFFSET     16
3200
3201 enum mlx5_aso_pre_cond_op {
3202         ASO_OP_ALWAYS_FALSE = 0x0,
3203         ASO_OP_ALWAYS_TRUE = 0x1,
3204         ASO_OP_EQUAL = 0x2,
3205         ASO_OP_NOT_EQUAL = 0x3,
3206         ASO_OP_GREATER_OR_EQUAL = 0x4,
3207         ASO_OP_LESSER_OR_EQUAL = 0x5,
3208         ASO_OP_LESSER = 0x6,
3209         ASO_OP_GREATER = 0x7,
3210         ASO_OP_CYCLIC_GREATER = 0x8,
3211         ASO_OP_CYCLIC_LESSER = 0x9,
3212 };
3213
3214 #define ASO_CSEG_COND_OPER_OFFSET       6
3215
3216 enum mlx5_aso_op {
3217         ASO_OPER_LOGICAL_AND = 0x0,
3218         ASO_OPER_LOGICAL_OR = 0x1,
3219 };
3220
3221 /* ASO WQE CTRL segment. */
3222 struct mlx5_aso_cseg {
3223         uint32_t va_h;
3224         uint32_t va_l_r;
3225         uint32_t lkey;
3226         uint32_t operand_masks;
3227         uint32_t condition_0_data;
3228         uint32_t condition_0_mask;
3229         uint32_t condition_1_data;
3230         uint32_t condition_1_mask;
3231         uint64_t bitwise_data;
3232         uint64_t data_mask;
3233 } __rte_packed;
3234
3235 /* A meter data segment - 2 per ASO WQE. */
3236 struct mlx5_aso_mtr_dseg {
3237         uint32_t v_bo_sc_bbog_mm;
3238         /*
3239          * bit 31: valid, 30: bucket overflow, 28-29: start color,
3240          * 27: both buckets on green, 24-25: meter mode.
3241          */
3242         uint32_t reserved;
3243         uint32_t cbs_cir;
3244         /*
3245          * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa,
3246          * bit 8-12: cir_exponent, bit 0-7 cir_mantissa.
3247          */
3248         uint32_t c_tokens;
3249         uint32_t ebs_eir;
3250         /*
3251          * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa,
3252          * bit 8-12: eir_exponent, bit 0-7 eir_mantissa.
3253          */
3254         uint32_t e_tokens;
3255         uint64_t timestamp;
3256 } __rte_packed;
3257
3258 #define ASO_DSEG_VALID_OFFSET 31
3259 #define ASO_DSEG_BO_OFFSET 30
3260 #define ASO_DSEG_SC_OFFSET 28
3261 #define ASO_DSEG_BBOG_OFFSET 27
3262 #define ASO_DSEG_MTR_MODE 24
3263 #define ASO_DSEG_CBS_EXP_OFFSET 24
3264 #define ASO_DSEG_CBS_MAN_OFFSET 16
3265 #define ASO_DSEG_XIR_EXP_MASK 0x1F
3266 #define ASO_DSEG_XIR_EXP_OFFSET 8
3267 #define ASO_DSEG_EBS_EXP_OFFSET 24
3268 #define ASO_DSEG_EBS_MAN_OFFSET 16
3269 #define ASO_DSEG_EXP_MASK 0x1F
3270 #define ASO_DSEG_MAN_MASK 0xFF
3271
3272 #define MLX5_ASO_WQE_DSEG_SIZE  0x40
3273 #define MLX5_ASO_METERS_PER_WQE 2
3274 #define MLX5_ASO_MTRS_PER_POOL 128
3275
3276 /* ASO WQE data segment. */
3277 struct mlx5_aso_dseg {
3278         union {
3279                 uint8_t data[MLX5_ASO_WQE_DSEG_SIZE];
3280                 struct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE];
3281         };
3282 } __rte_packed;
3283
3284 /* ASO WQE. */
3285 struct mlx5_aso_wqe {
3286         struct mlx5_wqe_cseg general_cseg;
3287         struct mlx5_aso_cseg aso_cseg;
3288         struct mlx5_aso_dseg aso_dseg;
3289 } __rte_packed;
3290
3291 enum {
3292         MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
3293 };
3294
3295 enum {
3296         MLX5_QP_ST_RC = 0x0,
3297 };
3298
3299 enum {
3300         MLX5_QP_PM_MIGRATED = 0x3,
3301 };
3302
3303 enum {
3304         MLX5_NON_ZERO_RQ = 0x0,
3305         MLX5_SRQ_RQ = 0x1,
3306         MLX5_CRQ_RQ = 0x2,
3307         MLX5_ZERO_LEN_RQ = 0x3,
3308 };
3309
3310 struct mlx5_ifc_ads_bits {
3311         u8 fl[0x1];
3312         u8 free_ar[0x1];
3313         u8 reserved_at_2[0xe];
3314         u8 pkey_index[0x10];
3315         u8 reserved_at_20[0x8];
3316         u8 grh[0x1];
3317         u8 mlid[0x7];
3318         u8 rlid[0x10];
3319         u8 ack_timeout[0x5];
3320         u8 reserved_at_45[0x3];
3321         u8 src_addr_index[0x8];
3322         u8 reserved_at_50[0x4];
3323         u8 stat_rate[0x4];
3324         u8 hop_limit[0x8];
3325         u8 reserved_at_60[0x4];
3326         u8 tclass[0x8];
3327         u8 flow_label[0x14];
3328         u8 rgid_rip[16][0x8];
3329         u8 reserved_at_100[0x4];
3330         u8 f_dscp[0x1];
3331         u8 f_ecn[0x1];
3332         u8 reserved_at_106[0x1];
3333         u8 f_eth_prio[0x1];
3334         u8 ecn[0x2];
3335         u8 dscp[0x6];
3336         u8 udp_sport[0x10];
3337         u8 dei_cfi[0x1];
3338         u8 eth_prio[0x3];
3339         u8 sl[0x4];
3340         u8 vhca_port_num[0x8];
3341         u8 rmac_47_32[0x10];
3342         u8 rmac_31_0[0x20];
3343 };
3344
3345 struct mlx5_ifc_qpc_bits {
3346         u8 state[0x4];
3347         u8 lag_tx_port_affinity[0x4];
3348         u8 st[0x8];
3349         u8 reserved_at_10[0x3];
3350         u8 pm_state[0x2];
3351         u8 reserved_at_15[0x1];
3352         u8 req_e2e_credit_mode[0x2];
3353         u8 offload_type[0x4];
3354         u8 end_padding_mode[0x2];
3355         u8 reserved_at_1e[0x2];
3356         u8 wq_signature[0x1];
3357         u8 block_lb_mc[0x1];
3358         u8 atomic_like_write_en[0x1];
3359         u8 latency_sensitive[0x1];
3360         u8 reserved_at_24[0x1];
3361         u8 drain_sigerr[0x1];
3362         u8 reserved_at_26[0x2];
3363         u8 pd[0x18];
3364         u8 mtu[0x3];
3365         u8 log_msg_max[0x5];
3366         u8 reserved_at_48[0x1];
3367         u8 log_rq_size[0x4];
3368         u8 log_rq_stride[0x3];
3369         u8 no_sq[0x1];
3370         u8 log_sq_size[0x4];
3371         u8 reserved_at_55[0x3];
3372         u8 ts_format[0x2];
3373         u8 reserved_at_5a[0x1];
3374         u8 rlky[0x1];
3375         u8 ulp_stateless_offload_mode[0x4];
3376         u8 counter_set_id[0x8];
3377         u8 uar_page[0x18];
3378         u8 reserved_at_80[0x8];
3379         u8 user_index[0x18];
3380         u8 reserved_at_a0[0x3];
3381         u8 log_page_size[0x5];
3382         u8 remote_qpn[0x18];
3383         struct mlx5_ifc_ads_bits primary_address_path;
3384         struct mlx5_ifc_ads_bits secondary_address_path;
3385         u8 log_ack_req_freq[0x4];
3386         u8 reserved_at_384[0x4];
3387         u8 log_sra_max[0x3];
3388         u8 reserved_at_38b[0x2];
3389         u8 retry_count[0x3];
3390         u8 rnr_retry[0x3];
3391         u8 reserved_at_393[0x1];
3392         u8 fre[0x1];
3393         u8 cur_rnr_retry[0x3];
3394         u8 cur_retry_count[0x3];
3395         u8 reserved_at_39b[0x5];
3396         u8 reserved_at_3a0[0x20];
3397         u8 reserved_at_3c0[0x8];
3398         u8 next_send_psn[0x18];
3399         u8 reserved_at_3e0[0x8];
3400         u8 cqn_snd[0x18];
3401         u8 reserved_at_400[0x8];
3402         u8 deth_sqpn[0x18];
3403         u8 reserved_at_420[0x20];
3404         u8 reserved_at_440[0x8];
3405         u8 last_acked_psn[0x18];
3406         u8 reserved_at_460[0x8];
3407         u8 ssn[0x18];
3408         u8 reserved_at_480[0x8];
3409         u8 log_rra_max[0x3];
3410         u8 reserved_at_48b[0x1];
3411         u8 atomic_mode[0x4];
3412         u8 rre[0x1];
3413         u8 rwe[0x1];
3414         u8 rae[0x1];
3415         u8 reserved_at_493[0x1];
3416         u8 page_offset[0x6];
3417         u8 reserved_at_49a[0x3];
3418         u8 cd_slave_receive[0x1];
3419         u8 cd_slave_send[0x1];
3420         u8 cd_master[0x1];
3421         u8 reserved_at_4a0[0x3];
3422         u8 min_rnr_nak[0x5];
3423         u8 next_rcv_psn[0x18];
3424         u8 reserved_at_4c0[0x8];
3425         u8 xrcd[0x18];
3426         u8 reserved_at_4e0[0x8];
3427         u8 cqn_rcv[0x18];
3428         u8 dbr_addr[0x40];
3429         u8 q_key[0x20];
3430         u8 reserved_at_560[0x5];
3431         u8 rq_type[0x3];
3432         u8 srqn_rmpn_xrqn[0x18];
3433         u8 reserved_at_580[0x8];
3434         u8 rmsn[0x18];
3435         u8 hw_sq_wqebb_counter[0x10];
3436         u8 sw_sq_wqebb_counter[0x10];
3437         u8 hw_rq_counter[0x20];
3438         u8 sw_rq_counter[0x20];
3439         u8 reserved_at_600[0x20];
3440         u8 reserved_at_620[0xf];
3441         u8 cgs[0x1];
3442         u8 cs_req[0x8];
3443         u8 cs_res[0x8];
3444         u8 dc_access_key[0x40];
3445         u8 reserved_at_680[0x3];
3446         u8 dbr_umem_valid[0x1];
3447         u8 reserved_at_684[0x9c];
3448         u8 dbr_umem_id[0x20];
3449 };
3450
3451 struct mlx5_ifc_create_qp_out_bits {
3452         u8 status[0x8];
3453         u8 reserved_at_8[0x18];
3454         u8 syndrome[0x20];
3455         u8 reserved_at_40[0x8];
3456         u8 qpn[0x18];
3457         u8 reserved_at_60[0x20];
3458 };
3459
3460 struct mlx5_ifc_qpc_extension_bits {
3461         u8 reserved_at_0[0x2];
3462         u8 mmo[0x1];
3463         u8 reserved_at_3[0x5fd];
3464 };
3465
3466 #ifdef PEDANTIC
3467 #pragma GCC diagnostic ignored "-Wpedantic"
3468 #endif
3469 struct mlx5_ifc_qpc_pas_list_bits {
3470         u8 pas[0][0x40];
3471 };
3472
3473 #ifdef PEDANTIC
3474 #pragma GCC diagnostic ignored "-Wpedantic"
3475 #endif
3476 struct mlx5_ifc_qpc_extension_and_pas_list_bits {
3477         struct mlx5_ifc_qpc_extension_bits qpc_data_extension;
3478         u8 pas[0][0x40];
3479 };
3480
3481
3482 #ifdef PEDANTIC
3483 #pragma GCC diagnostic ignored "-Wpedantic"
3484 #endif
3485 struct mlx5_ifc_create_qp_in_bits {
3486         u8 opcode[0x10];
3487         u8 uid[0x10];
3488         u8 reserved_at_20[0x10];
3489         u8 op_mod[0x10];
3490         u8 qpc_ext[0x1];
3491         u8 reserved_at_41[0x3f];
3492         u8 opt_param_mask[0x20];
3493         u8 reserved_at_a0[0x20];
3494         struct mlx5_ifc_qpc_bits qpc;
3495         u8 wq_umem_offset[0x40];
3496         u8 wq_umem_id[0x20];
3497         u8 wq_umem_valid[0x1];
3498         u8 reserved_at_861[0x1f];
3499         union {
3500                 struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list;
3501                 struct mlx5_ifc_qpc_extension_and_pas_list_bits
3502                                         qpc_extension_and_pas_list;
3503         };
3504 };
3505 #ifdef PEDANTIC
3506 #pragma GCC diagnostic error "-Wpedantic"
3507 #endif
3508
3509 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3510         u8 status[0x8];
3511         u8 reserved_at_8[0x18];
3512         u8 syndrome[0x20];
3513         u8 reserved_at_40[0x40];
3514 };
3515
3516 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3517         u8 opcode[0x10];
3518         u8 uid[0x10];
3519         u8 reserved_at_20[0x10];
3520         u8 op_mod[0x10];
3521         u8 reserved_at_40[0x8];
3522         u8 qpn[0x18];
3523         u8 reserved_at_60[0x20];
3524         u8 opt_param_mask[0x20];
3525         u8 reserved_at_a0[0x20];
3526         struct mlx5_ifc_qpc_bits qpc;
3527         u8 reserved_at_800[0x80];
3528 };
3529
3530 struct mlx5_ifc_sqd2rts_qp_out_bits {
3531         u8 status[0x8];
3532         u8 reserved_at_8[0x18];
3533         u8 syndrome[0x20];
3534         u8 reserved_at_40[0x40];
3535 };
3536
3537 struct mlx5_ifc_sqd2rts_qp_in_bits {
3538         u8 opcode[0x10];
3539         u8 uid[0x10];
3540         u8 reserved_at_20[0x10];
3541         u8 op_mod[0x10];
3542         u8 reserved_at_40[0x8];
3543         u8 qpn[0x18];
3544         u8 reserved_at_60[0x20];
3545         u8 opt_param_mask[0x20];
3546         u8 reserved_at_a0[0x20];
3547         struct mlx5_ifc_qpc_bits qpc;
3548         u8 reserved_at_800[0x80];
3549 };
3550
3551 struct mlx5_ifc_rts2rts_qp_out_bits {
3552         u8 status[0x8];
3553         u8 reserved_at_8[0x18];
3554         u8 syndrome[0x20];
3555         u8 reserved_at_40[0x40];
3556 };
3557
3558 struct mlx5_ifc_rts2rts_qp_in_bits {
3559         u8 opcode[0x10];
3560         u8 uid[0x10];
3561         u8 reserved_at_20[0x10];
3562         u8 op_mod[0x10];
3563         u8 reserved_at_40[0x8];
3564         u8 qpn[0x18];
3565         u8 reserved_at_60[0x20];
3566         u8 opt_param_mask[0x20];
3567         u8 reserved_at_a0[0x20];
3568         struct mlx5_ifc_qpc_bits qpc;
3569         u8 reserved_at_800[0x80];
3570 };
3571
3572 struct mlx5_ifc_rtr2rts_qp_out_bits {
3573         u8 status[0x8];
3574         u8 reserved_at_8[0x18];
3575         u8 syndrome[0x20];
3576         u8 reserved_at_40[0x40];
3577 };
3578
3579 struct mlx5_ifc_rtr2rts_qp_in_bits {
3580         u8 opcode[0x10];
3581         u8 uid[0x10];
3582         u8 reserved_at_20[0x10];
3583         u8 op_mod[0x10];
3584         u8 reserved_at_40[0x8];
3585         u8 qpn[0x18];
3586         u8 reserved_at_60[0x20];
3587         u8 opt_param_mask[0x20];
3588         u8 reserved_at_a0[0x20];
3589         struct mlx5_ifc_qpc_bits qpc;
3590         u8 reserved_at_800[0x80];
3591 };
3592
3593 struct mlx5_ifc_rst2init_qp_out_bits {
3594         u8 status[0x8];
3595         u8 reserved_at_8[0x18];
3596         u8 syndrome[0x20];
3597         u8 reserved_at_40[0x40];
3598 };
3599
3600 struct mlx5_ifc_rst2init_qp_in_bits {
3601         u8 opcode[0x10];
3602         u8 uid[0x10];
3603         u8 reserved_at_20[0x10];
3604         u8 op_mod[0x10];
3605         u8 reserved_at_40[0x8];
3606         u8 qpn[0x18];
3607         u8 reserved_at_60[0x20];
3608         u8 opt_param_mask[0x20];
3609         u8 reserved_at_a0[0x20];
3610         struct mlx5_ifc_qpc_bits qpc;
3611         u8 reserved_at_800[0x80];
3612 };
3613
3614 struct mlx5_ifc_init2rtr_qp_out_bits {
3615         u8 status[0x8];
3616         u8 reserved_at_8[0x18];
3617         u8 syndrome[0x20];
3618         u8 reserved_at_40[0x40];
3619 };
3620
3621 struct mlx5_ifc_init2rtr_qp_in_bits {
3622         u8 opcode[0x10];
3623         u8 uid[0x10];
3624         u8 reserved_at_20[0x10];
3625         u8 op_mod[0x10];
3626         u8 reserved_at_40[0x8];
3627         u8 qpn[0x18];
3628         u8 reserved_at_60[0x20];
3629         u8 opt_param_mask[0x20];
3630         u8 reserved_at_a0[0x20];
3631         struct mlx5_ifc_qpc_bits qpc;
3632         u8 reserved_at_800[0x80];
3633 };
3634
3635 struct mlx5_ifc_init2init_qp_out_bits {
3636         u8 status[0x8];
3637         u8 reserved_at_8[0x18];
3638         u8 syndrome[0x20];
3639         u8 reserved_at_40[0x40];
3640 };
3641
3642 struct mlx5_ifc_init2init_qp_in_bits {
3643         u8 opcode[0x10];
3644         u8 uid[0x10];
3645         u8 reserved_at_20[0x10];
3646         u8 op_mod[0x10];
3647         u8 reserved_at_40[0x8];
3648         u8 qpn[0x18];
3649         u8 reserved_at_60[0x20];
3650         u8 opt_param_mask[0x20];
3651         u8 reserved_at_a0[0x20];
3652         struct mlx5_ifc_qpc_bits qpc;
3653         u8 reserved_at_800[0x80];
3654 };
3655
3656 struct mlx5_ifc_dealloc_pd_out_bits {
3657         u8 status[0x8];
3658         u8 reserved_0[0x18];
3659         u8 syndrome[0x20];
3660         u8 reserved_1[0x40];
3661 };
3662
3663 struct mlx5_ifc_dealloc_pd_in_bits {
3664         u8 opcode[0x10];
3665         u8 reserved_0[0x10];
3666         u8 reserved_1[0x10];
3667         u8 op_mod[0x10];
3668         u8 reserved_2[0x8];
3669         u8 pd[0x18];
3670         u8 reserved_3[0x20];
3671 };
3672
3673 struct mlx5_ifc_alloc_pd_out_bits {
3674         u8 status[0x8];
3675         u8 reserved_0[0x18];
3676         u8 syndrome[0x20];
3677         u8 reserved_1[0x8];
3678         u8 pd[0x18];
3679         u8 reserved_2[0x20];
3680 };
3681
3682 struct mlx5_ifc_alloc_pd_in_bits {
3683         u8 opcode[0x10];
3684         u8 reserved_0[0x10];
3685         u8 reserved_1[0x10];
3686         u8 op_mod[0x10];
3687         u8 reserved_2[0x40];
3688 };
3689
3690 #ifdef PEDANTIC
3691 #pragma GCC diagnostic ignored "-Wpedantic"
3692 #endif
3693 struct mlx5_ifc_query_qp_out_bits {
3694         u8 status[0x8];
3695         u8 reserved_at_8[0x18];
3696         u8 syndrome[0x20];
3697         u8 reserved_at_40[0x40];
3698         u8 opt_param_mask[0x20];
3699         u8 reserved_at_a0[0x20];
3700         struct mlx5_ifc_qpc_bits qpc;
3701         u8 reserved_at_800[0x80];
3702         u8 pas[0][0x40];
3703 };
3704 #ifdef PEDANTIC
3705 #pragma GCC diagnostic error "-Wpedantic"
3706 #endif
3707
3708 struct mlx5_ifc_query_qp_in_bits {
3709         u8 opcode[0x10];
3710         u8 reserved_at_10[0x10];
3711         u8 reserved_at_20[0x10];
3712         u8 op_mod[0x10];
3713         u8 reserved_at_40[0x8];
3714         u8 qpn[0x18];
3715         u8 reserved_at_60[0x20];
3716 };
3717
3718 enum {
3719         MLX5_DATA_RATE = 0x0,
3720         MLX5_WQE_RATE = 0x1,
3721 };
3722
3723 struct mlx5_ifc_set_pp_rate_limit_context_bits {
3724         u8 rate_limit[0x20];
3725         u8 burst_upper_bound[0x20];
3726         u8 reserved_at_40[0xC];
3727         u8 rate_mode[0x4];
3728         u8 typical_packet_size[0x10];
3729         u8 reserved_at_60[0x120];
3730 };
3731
3732 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u
3733
3734 #ifdef PEDANTIC
3735 #pragma GCC diagnostic ignored "-Wpedantic"
3736 #endif
3737 struct mlx5_ifc_access_register_out_bits {
3738         u8 status[0x8];
3739         u8 reserved_at_8[0x18];
3740         u8 syndrome[0x20];
3741         u8 reserved_at_40[0x40];
3742         u8 register_data[0][0x20];
3743 };
3744
3745 struct mlx5_ifc_access_register_in_bits {
3746         u8 opcode[0x10];
3747         u8 reserved_at_10[0x10];
3748         u8 reserved_at_20[0x10];
3749         u8 op_mod[0x10];
3750         u8 reserved_at_40[0x10];
3751         u8 register_id[0x10];
3752         u8 argument[0x20];
3753         u8 register_data[0][0x20];
3754 };
3755 #ifdef PEDANTIC
3756 #pragma GCC diagnostic error "-Wpedantic"
3757 #endif
3758
3759 enum {
3760         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
3761         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
3762 };
3763
3764 enum {
3765         MLX5_REGISTER_ID_MTUTC  = 0x9055,
3766         MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002,
3767         MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003,
3768         MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004,
3769         MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005,
3770 };
3771
3772 struct mlx5_ifc_register_mtutc_bits {
3773         u8 time_stamp_mode[0x2];
3774         u8 time_stamp_state[0x2];
3775         u8 reserved_at_4[0x18];
3776         u8 operation[0x4];
3777         u8 freq_adjustment[0x20];
3778         u8 reserved_at_40[0x40];
3779         u8 utc_sec[0x20];
3780         u8 utc_nsec[0x20];
3781         u8 time_adjustment[0x20];
3782 };
3783
3784 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0
3785 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1
3786
3787 struct mlx5_ifc_crypto_operational_register_bits {
3788         u8 wrapped_crypto_operational[0x1];
3789         u8 reserved_at_1[0x1b];
3790         u8 kek_size[0x4];
3791         u8 reserved_at_20[0x20];
3792         u8 credential[0x140];
3793         u8 kek[0x100];
3794         u8 reserved_at_280[0x180];
3795 };
3796
3797 struct mlx5_ifc_crypto_commissioning_register_bits {
3798         u8 token[0x1]; /* TODO: add size after PRM update */
3799 };
3800
3801 struct mlx5_ifc_import_kek_handle_register_bits {
3802         struct mlx5_ifc_crypto_login_bits crypto_login_object;
3803         struct mlx5_ifc_import_kek_bits import_kek_object;
3804         u8 reserved_at_200[0x4];
3805         u8 write_operation[0x4];
3806         u8 import_kek_id[0x18];
3807         u8 reserved_at_220[0xe0];
3808 };
3809
3810 struct mlx5_ifc_credential_handle_register_bits {
3811         struct mlx5_ifc_crypto_login_bits crypto_login_object;
3812         struct mlx5_ifc_credential_bits credential_object;
3813         u8 reserved_at_200[0x4];
3814         u8 write_operation[0x4];
3815         u8 credential_id[0x18];
3816         u8 reserved_at_220[0xe0];
3817 };
3818
3819 enum {
3820         MLX5_REGISTER_ADD_OPERATION = 0x1,
3821         MLX5_REGISTER_DELETE_OPERATION = 0x2,
3822 };
3823
3824 struct mlx5_ifc_parse_graph_arc_bits {
3825         u8 start_inner_tunnel[0x1];
3826         u8 reserved_at_1[0x7];
3827         u8 arc_parse_graph_node[0x8];
3828         u8 compare_condition_value[0x10];
3829         u8 parse_graph_node_handle[0x20];
3830         u8 reserved_at_40[0x40];
3831 };
3832
3833 struct mlx5_ifc_parse_graph_flow_match_sample_bits {
3834         u8 flow_match_sample_en[0x1];
3835         u8 reserved_at_1[0x3];
3836         u8 flow_match_sample_offset_mode[0x4];
3837         u8 reserved_at_5[0x8];
3838         u8 flow_match_sample_field_offset[0x10];
3839         u8 reserved_at_32[0x4];
3840         u8 flow_match_sample_field_offset_shift[0x4];
3841         u8 flow_match_sample_field_base_offset[0x8];
3842         u8 reserved_at_48[0xd];
3843         u8 flow_match_sample_tunnel_mode[0x3];
3844         u8 flow_match_sample_field_offset_mask[0x20];
3845         u8 flow_match_sample_field_id[0x20];
3846 };
3847
3848 struct mlx5_ifc_parse_graph_flex_bits {
3849         u8 modify_field_select[0x40];
3850         u8 reserved_at_64[0x20];
3851         u8 header_length_base_value[0x10];
3852         u8 reserved_at_112[0x4];
3853         u8 header_length_field_shift[0x4];
3854         u8 reserved_at_120[0x4];
3855         u8 header_length_mode[0x4];
3856         u8 header_length_field_offset[0x10];
3857         u8 next_header_field_offset[0x10];
3858         u8 reserved_at_160[0x1b];
3859         u8 next_header_field_size[0x5];
3860         u8 header_length_field_mask[0x20];
3861         u8 reserved_at_224[0x20];
3862         struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8];
3863         struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8];
3864         struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8];
3865 };
3866
3867 struct mlx5_ifc_create_flex_parser_in_bits {
3868         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3869         struct mlx5_ifc_parse_graph_flex_bits flex;
3870 };
3871
3872 struct mlx5_ifc_create_flex_parser_out_bits {
3873         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3874         struct mlx5_ifc_parse_graph_flex_bits flex;
3875 };
3876
3877 struct mlx5_ifc_parse_graph_flex_out_bits {
3878         u8 status[0x8];
3879         u8 reserved_at_8[0x18];
3880         u8 syndrome[0x20];
3881         u8 reserved_at_40[0x40];
3882         struct mlx5_ifc_parse_graph_flex_bits capability;
3883 };
3884
3885 struct regexp_params_field_select_bits {
3886         u8 reserved_at_0[0x1d];
3887         u8 rof_mkey[0x1];
3888         u8 stop_engine[0x1];
3889         u8 reserved_at_1f[0x1];
3890 };
3891
3892 struct mlx5_ifc_regexp_params_bits {
3893         u8 reserved_at_0[0x1f];
3894         u8 stop_engine[0x1];
3895         u8 reserved_at_20[0x60];
3896         u8 rof_mkey[0x20];
3897         u8 rof_size[0x20];
3898         u8 rof_mkey_va[0x40];
3899         u8 reserved_at_100[0x80];
3900 };
3901
3902 struct mlx5_ifc_set_regexp_params_in_bits {
3903         u8 opcode[0x10];
3904         u8 uid[0x10];
3905         u8 reserved_at_20[0x10];
3906         u8 op_mod[0x10];
3907         u8 reserved_at_40[0x18];
3908         u8 engine_id[0x8];
3909         struct regexp_params_field_select_bits field_select;
3910         struct mlx5_ifc_regexp_params_bits regexp_params;
3911 };
3912
3913 struct mlx5_ifc_set_regexp_params_out_bits {
3914         u8 status[0x8];
3915         u8 reserved_at_8[0x18];
3916         u8 syndrome[0x20];
3917         u8 reserved_at_18[0x40];
3918 };
3919
3920 struct mlx5_ifc_query_regexp_params_in_bits {
3921         u8 opcode[0x10];
3922         u8 uid[0x10];
3923         u8 reserved_at_20[0x10];
3924         u8 op_mod[0x10];
3925         u8 reserved_at_40[0x18];
3926         u8 engine_id[0x8];
3927         u8 reserved[0x20];
3928 };
3929
3930 struct mlx5_ifc_query_regexp_params_out_bits {
3931         u8 status[0x8];
3932         u8 reserved_at_8[0x18];
3933         u8 syndrome[0x20];
3934         u8 reserved[0x40];
3935         struct mlx5_ifc_regexp_params_bits regexp_params;
3936 };
3937
3938 struct mlx5_ifc_set_regexp_register_in_bits {
3939         u8 opcode[0x10];
3940         u8 uid[0x10];
3941         u8 reserved_at_20[0x10];
3942         u8 op_mod[0x10];
3943         u8 reserved_at_40[0x18];
3944         u8 engine_id[0x8];
3945         u8 register_address[0x20];
3946         u8 register_data[0x20];
3947         u8 reserved[0x60];
3948 };
3949
3950 struct mlx5_ifc_set_regexp_register_out_bits {
3951         u8 status[0x8];
3952         u8 reserved_at_8[0x18];
3953         u8 syndrome[0x20];
3954         u8 reserved[0x40];
3955 };
3956
3957 struct mlx5_ifc_query_regexp_register_in_bits {
3958         u8 opcode[0x10];
3959         u8 uid[0x10];
3960         u8 reserved_at_20[0x10];
3961         u8 op_mod[0x10];
3962         u8 reserved_at_40[0x18];
3963         u8 engine_id[0x8];
3964         u8 register_address[0x20];
3965 };
3966
3967 struct mlx5_ifc_query_regexp_register_out_bits {
3968         u8 status[0x8];
3969         u8 reserved_at_8[0x18];
3970         u8 syndrome[0x20];
3971         u8 reserved[0x20];
3972         u8 register_data[0x20];
3973 };
3974
3975 /* Queue counters. */
3976 struct mlx5_ifc_alloc_q_counter_out_bits {
3977         u8 status[0x8];
3978         u8 reserved_at_8[0x18];
3979         u8 syndrome[0x20];
3980         u8 reserved_at_40[0x18];
3981         u8 counter_set_id[0x8];
3982         u8 reserved_at_60[0x20];
3983 };
3984
3985 struct mlx5_ifc_alloc_q_counter_in_bits {
3986         u8 opcode[0x10];
3987         u8 uid[0x10];
3988         u8 reserved_at_20[0x10];
3989         u8 op_mod[0x10];
3990         u8 reserved_at_40[0x40];
3991 };
3992
3993 struct mlx5_ifc_query_q_counter_out_bits {
3994         u8 status[0x8];
3995         u8 reserved_at_8[0x18];
3996         u8 syndrome[0x20];
3997         u8 reserved_at_40[0x40];
3998         u8 rx_write_requests[0x20];
3999         u8 reserved_at_a0[0x20];
4000         u8 rx_read_requests[0x20];
4001         u8 reserved_at_e0[0x20];
4002         u8 rx_atomic_requests[0x20];
4003         u8 reserved_at_120[0x20];
4004         u8 rx_dct_connect[0x20];
4005         u8 reserved_at_160[0x20];
4006         u8 out_of_buffer[0x20];
4007         u8 reserved_at_1a0[0x20];
4008         u8 out_of_sequence[0x20];
4009         u8 reserved_at_1e0[0x20];
4010         u8 duplicate_request[0x20];
4011         u8 reserved_at_220[0x20];
4012         u8 rnr_nak_retry_err[0x20];
4013         u8 reserved_at_260[0x20];
4014         u8 packet_seq_err[0x20];
4015         u8 reserved_at_2a0[0x20];
4016         u8 implied_nak_seq_err[0x20];
4017         u8 reserved_at_2e0[0x20];
4018         u8 local_ack_timeout_err[0x20];
4019         u8 reserved_at_320[0xa0];
4020         u8 resp_local_length_error[0x20];
4021         u8 req_local_length_error[0x20];
4022         u8 resp_local_qp_error[0x20];
4023         u8 local_operation_error[0x20];
4024         u8 resp_local_protection[0x20];
4025         u8 req_local_protection[0x20];
4026         u8 resp_cqe_error[0x20];
4027         u8 req_cqe_error[0x20];
4028         u8 req_mw_binding[0x20];
4029         u8 req_bad_response[0x20];
4030         u8 req_remote_invalid_request[0x20];
4031         u8 resp_remote_invalid_request[0x20];
4032         u8 req_remote_access_errors[0x20];
4033         u8 resp_remote_access_errors[0x20];
4034         u8 req_remote_operation_errors[0x20];
4035         u8 req_transport_retries_exceeded[0x20];
4036         u8 cq_overflow[0x20];
4037         u8 resp_cqe_flush_error[0x20];
4038         u8 req_cqe_flush_error[0x20];
4039         u8 reserved_at_620[0x1e0];
4040 };
4041
4042 struct mlx5_ifc_query_q_counter_in_bits {
4043         u8 opcode[0x10];
4044         u8 uid[0x10];
4045         u8 reserved_at_20[0x10];
4046         u8 op_mod[0x10];
4047         u8 reserved_at_40[0x80];
4048         u8 clear[0x1];
4049         u8 reserved_at_c1[0x1f];
4050         u8 reserved_at_e0[0x18];
4051         u8 counter_set_id[0x8];
4052 };
4053
4054 /* CQE format mask. */
4055 #define MLX5E_CQE_FORMAT_MASK 0xc
4056
4057 /* MPW opcode. */
4058 #define MLX5_OPC_MOD_MPW 0x01
4059
4060 /* Compressed Rx CQE structure. */
4061 struct mlx5_mini_cqe8 {
4062         union {
4063                 uint32_t rx_hash_result;
4064                 struct {
4065                         union {
4066                                 uint16_t checksum;
4067                                 uint16_t flow_tag_high;
4068                                 struct {
4069                                         uint8_t reserved;
4070                                         uint8_t hdr_type;
4071                                 };
4072                         };
4073                         uint16_t stride_idx;
4074                 };
4075                 struct {
4076                         uint16_t wqe_counter;
4077                         uint8_t  s_wqe_opcode;
4078                         uint8_t  reserved;
4079                 } s_wqe_info;
4080         };
4081         union {
4082                 uint32_t byte_cnt_flow;
4083                 uint32_t byte_cnt;
4084         };
4085 };
4086
4087 /* Mini CQE responder format. */
4088 enum {
4089         MLX5_CQE_RESP_FORMAT_HASH = 0x0,
4090         MLX5_CQE_RESP_FORMAT_CSUM = 0x1,
4091         MLX5_CQE_RESP_FORMAT_FTAG_STRIDX = 0x2,
4092         MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3,
4093         MLX5_CQE_RESP_FORMAT_L34H_STRIDX = 0x4,
4094 };
4095
4096 /* srTCM PRM flow meter parameters. */
4097 enum {
4098         MLX5_FLOW_COLOR_RED = 0,
4099         MLX5_FLOW_COLOR_YELLOW,
4100         MLX5_FLOW_COLOR_GREEN,
4101         MLX5_FLOW_COLOR_UNDEFINED,
4102 };
4103
4104 /* Maximum value of srTCM & trTCM metering parameters. */
4105 #define MLX5_SRTCM_XBS_MAX (0xFF * (1ULL << 0x1F))
4106 #define MLX5_SRTCM_XIR_MAX (8 * (1ULL << 30) * 0xFF)
4107
4108 /* The bits meter color use. */
4109 #define MLX5_MTR_COLOR_BITS 8
4110
4111 /* The bit size of one register. */
4112 #define MLX5_REG_BITS 32
4113
4114 /* Idle bits for non-color usage in color register. */
4115 #define MLX5_MTR_IDLE_BITS_IN_COLOR_REG (MLX5_REG_BITS - MLX5_MTR_COLOR_BITS)
4116
4117 /* Length mode of dynamic flex parser graph node. */
4118 enum mlx5_parse_graph_node_len_mode {
4119         MLX5_GRAPH_NODE_LEN_FIXED = 0x0,
4120         MLX5_GRAPH_NODE_LEN_FIELD = 0x1,
4121         MLX5_GRAPH_NODE_LEN_BITMASK = 0x2,
4122 };
4123
4124 /* Offset mode of the samples of flex parser. */
4125 enum mlx5_parse_graph_flow_match_sample_offset_mode {
4126         MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0,
4127         MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1,
4128         MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2,
4129 };
4130
4131 enum mlx5_parse_graph_flow_match_sample_tunnel_mode {
4132         MLX5_GRAPH_SAMPLE_TUNNEL_OUTER = 0x0,
4133         MLX5_GRAPH_SAMPLE_TUNNEL_INNER = 0x1,
4134         MLX5_GRAPH_SAMPLE_TUNNEL_FIRST = 0x2
4135 };
4136
4137 /* Node index for an input / output arc of the flex parser graph. */
4138 enum mlx5_parse_graph_arc_node_index {
4139         MLX5_GRAPH_ARC_NODE_NULL = 0x0,
4140         MLX5_GRAPH_ARC_NODE_HEAD = 0x1,
4141         MLX5_GRAPH_ARC_NODE_MAC = 0x2,
4142         MLX5_GRAPH_ARC_NODE_IP = 0x3,
4143         MLX5_GRAPH_ARC_NODE_GRE = 0x4,
4144         MLX5_GRAPH_ARC_NODE_UDP = 0x5,
4145         MLX5_GRAPH_ARC_NODE_MPLS = 0x6,
4146         MLX5_GRAPH_ARC_NODE_TCP = 0x7,
4147         MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8,
4148         MLX5_GRAPH_ARC_NODE_GENEVE = 0x9,
4149         MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa,
4150         MLX5_GRAPH_ARC_NODE_IPV4 = 0xb,
4151         MLX5_GRAPH_ARC_NODE_IPV6 = 0xc,
4152         MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f,
4153 };
4154
4155 #define MLX5_PARSE_GRAPH_FLOW_SAMPLE_MAX 8
4156 #define MLX5_PARSE_GRAPH_IN_ARC_MAX 8
4157 #define MLX5_PARSE_GRAPH_OUT_ARC_MAX 8
4158
4159 /**
4160  * Convert a user mark to flow mark.
4161  *
4162  * @param val
4163  *   Mark value to convert.
4164  *
4165  * @return
4166  *   Converted mark value.
4167  */
4168 static inline uint32_t
4169 mlx5_flow_mark_set(uint32_t val)
4170 {
4171         uint32_t ret;
4172
4173         /*
4174          * Add one to the user value to differentiate un-marked flows from
4175          * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
4176          * remains untouched.
4177          */
4178         if (val != MLX5_FLOW_MARK_DEFAULT)
4179                 ++val;
4180 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
4181         /*
4182          * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
4183          * word, byte-swapped by the kernel on little-endian systems. In this
4184          * case, left-shifting the resulting big-endian value ensures the
4185          * least significant 24 bits are retained when converting it back.
4186          */
4187         ret = rte_cpu_to_be_32(val) >> 8;
4188 #else
4189         ret = val;
4190 #endif
4191         return ret;
4192 }
4193
4194 /**
4195  * Convert a mark to user mark.
4196  *
4197  * @param val
4198  *   Mark value to convert.
4199  *
4200  * @return
4201  *   Converted mark value.
4202  */
4203 static inline uint32_t
4204 mlx5_flow_mark_get(uint32_t val)
4205 {
4206         /*
4207          * Subtract one from the retrieved value. It was added by
4208          * mlx5_flow_mark_set() to distinguish unmarked flows.
4209          */
4210 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
4211         return (val >> 8) - 1;
4212 #else
4213         return val - 1;
4214 #endif
4215 }
4216
4217 /**
4218  * Convert a timestamp format to configure settings in the queue context.
4219  *
4220  * @param val
4221  *   timestamp format supported by the queue.
4222  *
4223  * @return
4224  *   Converted timestamp format settings.
4225  */
4226 static inline uint32_t
4227 mlx5_ts_format_conv(uint32_t ts_format)
4228 {
4229         return ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ?
4230                         MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
4231                         MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
4232 }
4233
4234 #endif /* RTE_PMD_MLX5_PRM_H_ */