1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2016 6WIND S.A.
3 * Copyright 2016 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_PRM_H_
7 #define RTE_PMD_MLX5_PRM_H_
12 #include <rte_byteorder.h>
14 #include <mlx5_glue.h>
15 #include "mlx5_autoconf.h"
17 /* RSS hash key size. */
18 #define MLX5_RSS_HASH_KEY_LEN 40
20 /* Get CQE owner bit. */
21 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
24 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
27 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
29 /* Get CQE solicited event. */
30 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
32 /* Invalidate a CQE. */
33 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
35 /* Hardware index widths. */
36 #define MLX5_CQ_INDEX_WIDTH 24
37 #define MLX5_WQ_INDEX_WIDTH 16
39 /* WQE Segment sizes in bytes. */
40 #define MLX5_WSEG_SIZE 16u
41 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
42 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
43 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
45 /* WQE/WQEBB size in bytes. */
46 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
49 * Max size of a WQE session.
50 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
51 * the WQE size field in Control Segment is 6 bits wide.
53 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
56 * Default minimum number of Tx queues for inlining packets.
57 * If there are less queues as specified we assume we have
58 * no enough CPU resources (cycles) to perform inlining,
59 * the PCIe throughput is not supposed as bottleneck and
60 * inlining is disabled.
62 #define MLX5_INLINE_MAX_TXQS 8u
63 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
66 * Default packet length threshold to be inlined with
67 * enhanced MPW. If packet length exceeds the threshold
68 * the data are not inlined. Should be aligned in WQEBB
69 * boundary with accounting the title Control and Ethernet
72 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
73 MLX5_DSEG_MIN_INLINE_SIZE)
75 * Maximal inline data length sent with enhanced MPW.
76 * Is based on maximal WQE size.
78 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
79 MLX5_WQE_CSEG_SIZE - \
80 MLX5_WQE_ESEG_SIZE - \
81 MLX5_WQE_DSEG_SIZE + \
82 MLX5_DSEG_MIN_INLINE_SIZE)
84 * Minimal amount of packets to be sent with EMPW.
85 * This limits the minimal required size of sent EMPW.
86 * If there are no enough resources to built minimal
87 * EMPW the sending loop exits.
89 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
91 * Maximal amount of packets to be sent with EMPW.
92 * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
93 * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
94 * without CQE generation request, being multiplied by
95 * MLX5_TX_COMP_MAX_CQE it may cause significant latency
96 * in tx burst routine at the moment of freeing multiple mbufs.
98 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
99 #define MLX5_MPW_MAX_PACKETS 6
100 #define MLX5_MPW_INLINE_MAX_PACKETS 6
103 * Default packet length threshold to be inlined with
104 * ordinary SEND. Inlining saves the MR key search
105 * and extra PCIe data fetch transaction, but eats the
108 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
109 MLX5_ESEG_MIN_INLINE_SIZE - \
110 MLX5_WQE_CSEG_SIZE - \
111 MLX5_WQE_ESEG_SIZE - \
114 * Maximal inline data length sent with ordinary SEND.
115 * Is based on maximal WQE size.
117 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
118 MLX5_WQE_CSEG_SIZE - \
119 MLX5_WQE_ESEG_SIZE - \
120 MLX5_WQE_DSEG_SIZE + \
121 MLX5_ESEG_MIN_INLINE_SIZE)
123 /* Missed in mlx5dv.h, should define here. */
124 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW
125 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
128 #ifndef HAVE_MLX5_OPCODE_SEND_EN
129 #define MLX5_OPCODE_SEND_EN 0x17u
132 #ifndef HAVE_MLX5_OPCODE_WAIT
133 #define MLX5_OPCODE_WAIT 0x0fu
136 #ifndef HAVE_MLX5_OPCODE_ACCESS_ASO
137 #define MLX5_OPCODE_ACCESS_ASO 0x2du
140 /* CQE value to inform that VLAN is stripped. */
141 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
144 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
147 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
150 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
153 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
156 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
158 /* IP is fragmented. */
159 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
161 /* L2 header is valid. */
162 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
164 /* L3 header is valid. */
165 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
167 /* L4 header is valid. */
168 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
170 /* Outer packet, 0 IPv4, 1 IPv6. */
171 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
173 /* Tunnel packet bit in the CQE. */
174 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
176 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
177 #define MLX5_CQE_LRO_PUSH_MASK 0x40
179 /* Mask for L4 type in the CQE hdr_type_etc field. */
180 #define MLX5_CQE_L4_TYPE_MASK 0x70
182 /* The bit index of L4 type in CQE hdr_type_etc field. */
183 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
185 /* L4 type to indicate TCP packet without acknowledgment. */
186 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
188 /* L4 type to indicate TCP packet with acknowledgment. */
189 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
191 /* Inner L3 checksum offload (Tunneled packets only). */
192 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
194 /* Inner L4 checksum offload (Tunneled packets only). */
195 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
197 /* Outer L4 type is TCP. */
198 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5)
200 /* Outer L4 type is UDP. */
201 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5)
203 /* Outer L3 type is IPV4. */
204 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
206 /* Outer L3 type is IPV6. */
207 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
209 /* Inner L4 type is TCP. */
210 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
212 /* Inner L4 type is UDP. */
213 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
215 /* Inner L3 type is IPV4. */
216 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
218 /* Inner L3 type is IPV6. */
219 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
221 /* VLAN insertion flag. */
222 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
224 /* Data inline segment flag. */
225 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
227 /* Is flow mark valid. */
228 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
229 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
231 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
234 /* INVALID is used by packets matching no flow rules. */
235 #define MLX5_FLOW_MARK_INVALID 0
237 /* Maximum allowed value to mark a packet. */
238 #define MLX5_FLOW_MARK_MAX 0xfffff0
240 /* Default mark value used when none is provided. */
241 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
243 /* Default mark mask for metadata legacy mode. */
244 #define MLX5_FLOW_MARK_MASK 0xffffff
246 /* Byte length mask when mark is enable in miniCQE */
247 #define MLX5_LEN_WITH_MARK_MASK 0xffffff00
249 /* Maximum number of DS in WQE. Limited by 6-bit field. */
250 #define MLX5_DSEG_MAX 63
252 /* The completion mode offset in the WQE control segment line 2. */
253 #define MLX5_COMP_MODE_OFFSET 2
255 /* Amount of data bytes in minimal inline data segment. */
256 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
258 /* Amount of data bytes in minimal inline eth segment. */
259 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
261 /* Amount of data bytes after eth data segment. */
262 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
264 /* The maximum log value of segments per RQ WQE. */
265 #define MLX5_MAX_LOG_RQ_SEGS 5u
267 /* The alignment needed for WQ buffer. */
268 #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size()
270 /* The alignment needed for CQ buffer. */
271 #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size()
273 /* Completion mode. */
274 enum mlx5_completion_mode {
275 MLX5_COMP_ONLY_ERR = 0x0,
276 MLX5_COMP_ONLY_FIRST_ERR = 0x1,
277 MLX5_COMP_ALWAYS = 0x2,
278 MLX5_COMP_CQE_AND_EQE = 0x3,
285 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
288 /* WQE Control segment. */
289 struct mlx5_wqe_cseg {
294 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
297 * WQE CSEG opcode field size is 32 bits, divided:
299 * Bits 23:8 wqe_index
302 #define WQE_CSEG_OPC_MOD_OFFSET 24
303 #define WQE_CSEG_WQE_INDEX_OFFSET 8
305 /* Header of data segment. Minimal size Data Segment */
306 struct mlx5_wqe_dseg {
309 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
317 /* Subset of struct WQE Ethernet Segment. */
318 struct mlx5_wqe_eseg {
326 uint16_t inline_hdr_sz;
328 uint16_t inline_data;
335 uint32_t flow_metadata;
341 struct mlx5_wqe_qseg {
348 /* The title WQEBB, header of WQE. */
351 struct mlx5_wqe_cseg cseg;
354 struct mlx5_wqe_eseg eseg;
356 struct mlx5_wqe_dseg dseg[2];
357 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
361 /* WQE for Multi-Packet RQ. */
362 struct mlx5_wqe_mprq {
363 struct mlx5_wqe_srq_next_seg next_seg;
364 struct mlx5_wqe_data_seg dseg;
367 #define MLX5_MPRQ_LEN_MASK 0x000ffff
368 #define MLX5_MPRQ_LEN_SHIFT 0
369 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
370 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
371 #define MLX5_MPRQ_FILLER_MASK 0x80000000
372 #define MLX5_MPRQ_FILLER_SHIFT 31
374 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
376 /* CQ element structure - should be equal to the cache line size */
378 #if (RTE_CACHE_LINE_SIZE == 128)
384 uint8_t lro_tcppsh_abort_dupack;
386 uint16_t lro_tcp_win;
387 uint32_t lro_ack_seq_num;
388 uint32_t rx_hash_res;
389 uint8_t rx_hash_type;
393 uint16_t hdr_type_etc;
397 uint32_t flow_table_metadata;
401 uint32_t sop_drop_qpn;
402 uint16_t wqe_counter;
409 uint32_t sop_drop_qpn;
410 uint16_t wqe_counter;
415 struct mlx5_wqe_rseg {
421 #define MLX5_UMRC_IF_OFFSET 31u
422 #define MLX5_UMRC_KO_OFFSET 16u
423 #define MLX5_UMRC_TO_BS_OFFSET 0u
425 struct mlx5_wqe_umr_cseg {
426 uint32_t if_cf_toe_cq_res;
432 struct mlx5_wqe_mkey_cseg {
433 uint32_t fr_res_af_sf;
439 uint32_t bsf_octword_size;
440 uint32_t reserved3[4];
441 uint32_t translations_octword_size;
447 MLX5_BSF_SIZE_16B = 0x0,
448 MLX5_BSF_SIZE_32B = 0x1,
449 MLX5_BSF_SIZE_64B = 0x2,
450 MLX5_BSF_SIZE_128B = 0x3,
454 MLX5_BSF_P_TYPE_SIGNATURE = 0x0,
455 MLX5_BSF_P_TYPE_CRYPTO = 0x1,
459 MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0,
460 MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1,
461 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2,
462 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3,
466 MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0,
470 MLX5_BLOCK_SIZE_512B = 0x1,
471 MLX5_BLOCK_SIZE_520B = 0x2,
472 MLX5_BLOCK_SIZE_4096B = 0x3,
473 MLX5_BLOCK_SIZE_4160B = 0x4,
474 MLX5_BLOCK_SIZE_1MB = 0x5,
475 MLX5_BLOCK_SIZE_4048B = 0x6,
478 #define MLX5_BSF_SIZE_OFFSET 30
479 #define MLX5_BSF_P_TYPE_OFFSET 24
480 #define MLX5_ENCRYPTION_ORDER_OFFSET 16
481 #define MLX5_BLOCK_SIZE_OFFSET 24
483 struct mlx5_wqe_umr_bsf_seg {
485 * bs_bpt_eo_es contains:
486 * bs bsf_size 2 bits at MLX5_BSF_SIZE_OFFSET
487 * bpt bsf_p_type 2 bits at MLX5_BSF_P_TYPE_OFFSET
488 * eo encryption_order 4 bits at MLX5_ENCRYPTION_ORDER_OFFSET
489 * es encryption_standard 4 bits at offset 0
491 uint32_t bs_bpt_eo_es;
492 uint32_t raw_data_size;
495 * bsp crypto_block_size_pointer 8 bits at MLX5_BLOCK_SIZE_OFFSET
496 * res reserved 24 bits
500 uint8_t xts_initial_tweak[16];
503 * res reserved 8 bits
504 * dp dek_pointer 24 bits at offset 0
509 uint32_t reserved2[4];
513 #pragma GCC diagnostic ignored "-Wpedantic"
516 struct mlx5_umr_wqe {
517 struct mlx5_wqe_cseg ctr;
518 struct mlx5_wqe_umr_cseg ucseg;
519 struct mlx5_wqe_mkey_cseg mkc;
521 struct mlx5_wqe_dseg kseg[0];
522 struct mlx5_wqe_umr_bsf_seg bsf[0];
526 struct mlx5_rdma_write_wqe {
527 struct mlx5_wqe_cseg ctr;
528 struct mlx5_wqe_rseg rseg;
529 struct mlx5_wqe_dseg dseg[0];
533 #pragma GCC diagnostic error "-Wpedantic"
537 /* MMO metadata segment */
539 #define MLX5_OPCODE_MMO 0x2fu
540 #define MLX5_OPC_MOD_MMO_REGEX 0x4u
541 #define MLX5_OPC_MOD_MMO_COMP 0x2u
542 #define MLX5_OPC_MOD_MMO_DECOMP 0x3u
543 #define MLX5_OPC_MOD_MMO_DMA 0x1u
545 #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u
546 #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u
547 #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u
548 #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u
549 #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS)
550 #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u
551 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u
552 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u
554 struct mlx5_wqe_metadata_seg {
555 uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */
560 struct mlx5_gga_wqe {
564 uint32_t gga_ctrl1; /* ws 12-15, bs 16-19, dyns 20-23. */
566 uint32_t opaque_lkey;
567 uint64_t opaque_vaddr;
568 struct mlx5_wqe_dseg gather;
569 struct mlx5_wqe_dseg scatter;
572 struct mlx5_gga_compress_opaque {
575 uint32_t scattered_length;
576 uint32_t gathered_length;
577 uint64_t scatter_crc;
581 uint8_t reserved1[216];
584 struct mlx5_ifc_regexp_mmo_control_bits {
585 uint8_t reserved_at_31[0x2];
587 uint8_t reserved_at_28[0x1];
588 uint8_t subset_id_0[0xc];
589 uint8_t reserved_at_16[0x4];
590 uint8_t subset_id_1[0xc];
592 uint8_t subset_id_2[0xc];
593 uint8_t reserved_at_16_1[0x4];
594 uint8_t subset_id_3[0xc];
597 struct mlx5_ifc_regexp_metadata_bits {
598 uint8_t rof_version[0x10];
599 uint8_t latency_count[0x10];
600 uint8_t instruction_count[0x10];
601 uint8_t primary_thread_count[0x10];
602 uint8_t match_count[0x8];
603 uint8_t detected_match_count[0x8];
604 uint8_t status[0x10];
605 uint8_t job_id[0x20];
606 uint8_t reserved[0x80];
609 struct mlx5_ifc_regexp_match_tuple_bits {
610 uint8_t length[0x10];
611 uint8_t start_ptr[0x10];
612 uint8_t rule_id[0x20];
615 /* Adding direct verbs to data-path. */
617 /* CQ sequence number mask. */
618 #define MLX5_CQ_SQN_MASK 0x3
620 /* CQ sequence number index. */
621 #define MLX5_CQ_SQN_OFFSET 28
623 /* CQ doorbell index mask. */
624 #define MLX5_CI_MASK 0xffffff
626 /* CQ doorbell offset. */
627 #define MLX5_CQ_ARM_DB 1
629 /* CQ doorbell offset*/
630 #define MLX5_CQ_DOORBELL 0x20
632 /* CQE format value. */
633 #define MLX5_COMPRESSED 0x3
635 /* CQ doorbell cmd types. */
636 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24)
637 #define MLX5_CQ_DBR_CMD_ALL (0 << 24)
639 /* Action type of header modification. */
641 MLX5_MODIFICATION_TYPE_SET = 0x1,
642 MLX5_MODIFICATION_TYPE_ADD = 0x2,
643 MLX5_MODIFICATION_TYPE_COPY = 0x3,
646 /* The field of packet to be modified. */
647 enum mlx5_modification_field {
648 MLX5_MODI_OUT_NONE = -1,
649 MLX5_MODI_OUT_SMAC_47_16 = 1,
650 MLX5_MODI_OUT_SMAC_15_0,
651 MLX5_MODI_OUT_ETHERTYPE,
652 MLX5_MODI_OUT_DMAC_47_16,
653 MLX5_MODI_OUT_DMAC_15_0,
654 MLX5_MODI_OUT_IP_DSCP,
655 MLX5_MODI_OUT_TCP_FLAGS,
656 MLX5_MODI_OUT_TCP_SPORT,
657 MLX5_MODI_OUT_TCP_DPORT,
658 MLX5_MODI_OUT_IPV4_TTL,
659 MLX5_MODI_OUT_UDP_SPORT,
660 MLX5_MODI_OUT_UDP_DPORT,
661 MLX5_MODI_OUT_SIPV6_127_96,
662 MLX5_MODI_OUT_SIPV6_95_64,
663 MLX5_MODI_OUT_SIPV6_63_32,
664 MLX5_MODI_OUT_SIPV6_31_0,
665 MLX5_MODI_OUT_DIPV6_127_96,
666 MLX5_MODI_OUT_DIPV6_95_64,
667 MLX5_MODI_OUT_DIPV6_63_32,
668 MLX5_MODI_OUT_DIPV6_31_0,
671 MLX5_MODI_OUT_FIRST_VID,
672 MLX5_MODI_IN_SMAC_47_16 = 0x31,
673 MLX5_MODI_IN_SMAC_15_0,
674 MLX5_MODI_IN_ETHERTYPE,
675 MLX5_MODI_IN_DMAC_47_16,
676 MLX5_MODI_IN_DMAC_15_0,
677 MLX5_MODI_IN_IP_DSCP,
678 MLX5_MODI_IN_TCP_FLAGS,
679 MLX5_MODI_IN_TCP_SPORT,
680 MLX5_MODI_IN_TCP_DPORT,
681 MLX5_MODI_IN_IPV4_TTL,
682 MLX5_MODI_IN_UDP_SPORT,
683 MLX5_MODI_IN_UDP_DPORT,
684 MLX5_MODI_IN_SIPV6_127_96,
685 MLX5_MODI_IN_SIPV6_95_64,
686 MLX5_MODI_IN_SIPV6_63_32,
687 MLX5_MODI_IN_SIPV6_31_0,
688 MLX5_MODI_IN_DIPV6_127_96,
689 MLX5_MODI_IN_DIPV6_95_64,
690 MLX5_MODI_IN_DIPV6_63_32,
691 MLX5_MODI_IN_DIPV6_31_0,
694 MLX5_MODI_OUT_IPV6_HOPLIMIT,
695 MLX5_MODI_IN_IPV6_HOPLIMIT,
696 MLX5_MODI_META_DATA_REG_A,
697 MLX5_MODI_META_DATA_REG_B = 0x50,
698 MLX5_MODI_META_REG_C_0,
699 MLX5_MODI_META_REG_C_1,
700 MLX5_MODI_META_REG_C_2,
701 MLX5_MODI_META_REG_C_3,
702 MLX5_MODI_META_REG_C_4,
703 MLX5_MODI_META_REG_C_5,
704 MLX5_MODI_META_REG_C_6,
705 MLX5_MODI_META_REG_C_7,
706 MLX5_MODI_OUT_TCP_SEQ_NUM,
707 MLX5_MODI_IN_TCP_SEQ_NUM,
708 MLX5_MODI_OUT_TCP_ACK_NUM,
709 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
710 MLX5_MODI_GTP_TEID = 0x6E,
713 /* Total number of metadata reg_c's. */
714 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1)
730 /* Modification sub command. */
731 struct mlx5_modification_cmd {
735 unsigned int length:5;
736 unsigned int rsvd0:3;
737 unsigned int offset:5;
738 unsigned int rsvd1:3;
739 unsigned int field:12;
740 unsigned int action_type:4;
747 unsigned int rsvd2:8;
748 unsigned int dst_offset:5;
749 unsigned int rsvd3:3;
750 unsigned int dst_field:12;
751 unsigned int rsvd4:4;
756 typedef uint64_t u64;
757 typedef uint32_t u32;
758 typedef uint16_t u16;
761 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
762 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
763 #define __mlx5_bit_off(typ, fld) ((unsigned int)(uintptr_t) \
764 (&(__mlx5_nullp(typ)->fld)))
765 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
766 (__mlx5_bit_off(typ, fld) & 0x1f))
767 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
768 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
769 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
770 __mlx5_dw_bit_off(typ, fld))
771 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
772 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
773 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
774 (__mlx5_bit_off(typ, fld) & 0xf))
775 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
776 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \
777 __mlx5_16_bit_off(typ, fld))
778 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
779 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
780 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
781 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
783 /* insert a value to a struct */
784 #define MLX5_SET(typ, p, fld, v) \
787 *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \
788 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
789 __mlx5_dw_off(typ, fld))) & \
790 (~__mlx5_dw_mask(typ, fld))) | \
791 (((_v) & __mlx5_mask(typ, fld)) << \
792 __mlx5_dw_bit_off(typ, fld))); \
795 #define MLX5_SET64(typ, p, fld, v) \
797 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \
798 *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \
799 rte_cpu_to_be_64(v); \
802 #define MLX5_SET16(typ, p, fld, v) \
805 *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \
806 rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
807 __mlx5_16_off(typ, fld))) & \
808 (~__mlx5_16_mask(typ, fld))) | \
809 (((_v) & __mlx5_mask16(typ, fld)) << \
810 __mlx5_16_bit_off(typ, fld))); \
813 #define MLX5_GET_VOLATILE(typ, p, fld) \
814 ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\
815 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
816 __mlx5_mask(typ, fld))
817 #define MLX5_GET(typ, p, fld) \
818 ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\
819 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
820 __mlx5_mask(typ, fld))
821 #define MLX5_GET16(typ, p, fld) \
822 ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
823 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
824 __mlx5_mask16(typ, fld))
825 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \
826 __mlx5_64_off(typ, fld)))
827 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
828 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
830 struct mlx5_ifc_fte_match_set_misc_bits {
831 u8 gre_c_present[0x1];
832 u8 reserved_at_1[0x1];
833 u8 gre_k_present[0x1];
834 u8 gre_s_present[0x1];
835 u8 source_vhci_port[0x4];
837 u8 reserved_at_20[0x10];
838 u8 source_port[0x10];
839 u8 outer_second_prio[0x3];
840 u8 outer_second_cfi[0x1];
841 u8 outer_second_vid[0xc];
842 u8 inner_second_prio[0x3];
843 u8 inner_second_cfi[0x1];
844 u8 inner_second_vid[0xc];
845 u8 outer_second_cvlan_tag[0x1];
846 u8 inner_second_cvlan_tag[0x1];
847 u8 outer_second_svlan_tag[0x1];
848 u8 inner_second_svlan_tag[0x1];
849 u8 reserved_at_64[0xc];
850 u8 gre_protocol[0x10];
854 u8 reserved_at_b8[0x8];
856 u8 reserved_at_e4[0x6];
857 u8 geneve_tlv_option_0_exist[0x1];
859 u8 reserved_at_e0[0xc];
860 u8 outer_ipv6_flow_label[0x14];
861 u8 reserved_at_100[0xc];
862 u8 inner_ipv6_flow_label[0x14];
863 u8 reserved_at_120[0xa];
864 u8 geneve_opt_len[0x6];
865 u8 geneve_protocol_type[0x10];
866 u8 reserved_at_140[0xc0];
869 struct mlx5_ifc_ipv4_layout_bits {
870 u8 reserved_at_0[0x60];
874 struct mlx5_ifc_ipv6_layout_bits {
878 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
879 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
880 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
881 u8 reserved_at_0[0x80];
884 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
903 u8 reserved_at_c0[0x10];
907 u8 ipv4_checksum_ok[0x1];
908 u8 l4_checksum_ok[0x1];
909 u8 ip_ttl_hoplimit[0x8];
912 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
913 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
916 struct mlx5_ifc_fte_match_mpls_bits {
923 struct mlx5_ifc_fte_match_set_misc2_bits {
924 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
925 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
926 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
927 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
928 u8 metadata_reg_c_7[0x20];
929 u8 metadata_reg_c_6[0x20];
930 u8 metadata_reg_c_5[0x20];
931 u8 metadata_reg_c_4[0x20];
932 u8 metadata_reg_c_3[0x20];
933 u8 metadata_reg_c_2[0x20];
934 u8 metadata_reg_c_1[0x20];
935 u8 metadata_reg_c_0[0x20];
936 u8 metadata_reg_a[0x20];
937 u8 metadata_reg_b[0x20];
938 u8 reserved_at_1c0[0x40];
941 struct mlx5_ifc_fte_match_set_misc3_bits {
942 u8 inner_tcp_seq_num[0x20];
943 u8 outer_tcp_seq_num[0x20];
944 u8 inner_tcp_ack_num[0x20];
945 u8 outer_tcp_ack_num[0x20];
946 u8 reserved_at_auto1[0x8];
947 u8 outer_vxlan_gpe_vni[0x18];
948 u8 outer_vxlan_gpe_next_protocol[0x8];
949 u8 outer_vxlan_gpe_flags[0x8];
950 u8 reserved_at_a8[0x10];
951 u8 icmp_header_data[0x20];
952 u8 icmpv6_header_data[0x20];
957 u8 geneve_tlv_option_0_data[0x20];
959 u8 gtpu_msg_type[0x08];
960 u8 gtpu_msg_flags[0x08];
961 u8 reserved_at_170[0x10];
963 u8 gtpu_first_ext_dw_0[0x20];
965 u8 reserved_at_240[0x20];
969 struct mlx5_ifc_fte_match_set_misc4_bits {
970 u8 prog_sample_field_value_0[0x20];
971 u8 prog_sample_field_id_0[0x20];
972 u8 prog_sample_field_value_1[0x20];
973 u8 prog_sample_field_id_1[0x20];
974 u8 prog_sample_field_value_2[0x20];
975 u8 prog_sample_field_id_2[0x20];
976 u8 prog_sample_field_value_3[0x20];
977 u8 prog_sample_field_id_3[0x20];
978 u8 prog_sample_field_value_4[0x20];
979 u8 prog_sample_field_id_4[0x20];
980 u8 prog_sample_field_value_5[0x20];
981 u8 prog_sample_field_id_5[0x20];
982 u8 prog_sample_field_value_6[0x20];
983 u8 prog_sample_field_id_6[0x20];
984 u8 prog_sample_field_value_7[0x20];
985 u8 prog_sample_field_id_7[0x20];
988 struct mlx5_ifc_fte_match_set_misc5_bits {
989 u8 macsec_tag_0[0x20];
990 u8 macsec_tag_1[0x20];
991 u8 macsec_tag_2[0x20];
992 u8 macsec_tag_3[0x20];
993 u8 tunnel_header_0[0x20];
994 u8 tunnel_header_1[0x20];
995 u8 tunnel_header_2[0x20];
996 u8 tunnel_header_3[0x20];
1001 struct mlx5_ifc_fte_match_param_bits {
1002 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1003 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1004 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1005 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1006 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1007 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1008 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
1010 * Add reserved bit to match the struct size with the size defined in PRM.
1011 * This extension is not required in Linux.
1013 #ifndef HAVE_INFINIBAND_VERBS_H
1014 u8 reserved_0[0x200];
1018 struct mlx5_ifc_dest_format_struct_bits {
1019 u8 destination_type[0x8];
1020 u8 destination_id[0x18];
1021 u8 reserved_0[0x20];
1025 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
1026 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
1027 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
1028 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
1029 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT,
1030 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT,
1031 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT,
1035 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
1036 MLX5_CMD_OP_CREATE_MKEY = 0x200,
1037 MLX5_CMD_OP_CREATE_CQ = 0x400,
1038 MLX5_CMD_OP_CREATE_QP = 0x500,
1039 MLX5_CMD_OP_RST2INIT_QP = 0x502,
1040 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
1041 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
1042 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
1043 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
1044 MLX5_CMD_OP_QP_2ERR = 0x507,
1045 MLX5_CMD_OP_QP_2RST = 0x50A,
1046 MLX5_CMD_OP_QUERY_QP = 0x50B,
1047 MLX5_CMD_OP_SQD2RTS_QP = 0x50C,
1048 MLX5_CMD_OP_INIT2INIT_QP = 0x50E,
1049 MLX5_CMD_OP_SUSPEND_QP = 0x50F,
1050 MLX5_CMD_OP_RESUME_QP = 0x510,
1051 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
1052 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
1053 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
1054 MLX5_CMD_OP_ALLOC_PD = 0x800,
1055 MLX5_CMD_OP_DEALLOC_PD = 0x801,
1056 MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
1057 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
1058 MLX5_CMD_OP_QUERY_LAG = 0x842,
1059 MLX5_CMD_OP_CREATE_TIR = 0x900,
1060 MLX5_CMD_OP_MODIFY_TIR = 0x901,
1061 MLX5_CMD_OP_CREATE_SQ = 0X904,
1062 MLX5_CMD_OP_MODIFY_SQ = 0X905,
1063 MLX5_CMD_OP_CREATE_RQ = 0x908,
1064 MLX5_CMD_OP_MODIFY_RQ = 0x909,
1065 MLX5_CMD_OP_QUERY_RQ = 0x90b,
1066 MLX5_CMD_OP_CREATE_TIS = 0x912,
1067 MLX5_CMD_OP_QUERY_TIS = 0x915,
1068 MLX5_CMD_OP_CREATE_RQT = 0x916,
1069 MLX5_CMD_OP_MODIFY_RQT = 0x917,
1070 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
1071 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
1072 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
1073 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
1074 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
1075 MLX5_CMD_SET_REGEX_PARAMS = 0xb04,
1076 MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,
1077 MLX5_CMD_SET_REGEX_REGISTERS = 0xb06,
1078 MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
1079 MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c,
1083 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
1084 MLX5_MKC_ACCESS_MODE_KLM = 0x2,
1085 MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3,
1088 #define MLX5_ADAPTER_PAGE_SHIFT 12
1089 #define MLX5_LOG_RQ_STRIDE_SHIFT 4
1091 * The batch counter dcs id starts from 0x800000 and none batch counter
1092 * starts from 0. As currently, the counter is changed to be indexed by
1093 * pool index and the offset of the counter in the pool counters_raw array.
1094 * It means now the counter index is same for batch and none batch counter.
1095 * Add the 0x800000 batch counter offset to the batch counter index helps
1096 * indicate the counter index is from batch or none batch container pool.
1098 #define MLX5_CNT_BATCH_OFFSET 0x800000
1100 /* The counter batch query requires ID align with 4. */
1101 #define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4
1103 /* Flow counters. */
1104 struct mlx5_ifc_alloc_flow_counter_out_bits {
1106 u8 reserved_at_8[0x18];
1108 u8 flow_counter_id[0x20];
1109 u8 reserved_at_60[0x20];
1112 struct mlx5_ifc_alloc_flow_counter_in_bits {
1114 u8 reserved_at_10[0x10];
1115 u8 reserved_at_20[0x10];
1117 u8 flow_counter_id[0x20];
1118 u8 reserved_at_40[0x18];
1119 u8 flow_counter_bulk[0x8];
1122 struct mlx5_ifc_dealloc_flow_counter_out_bits {
1124 u8 reserved_at_8[0x18];
1126 u8 reserved_at_40[0x40];
1129 struct mlx5_ifc_dealloc_flow_counter_in_bits {
1131 u8 reserved_at_10[0x10];
1132 u8 reserved_at_20[0x10];
1134 u8 flow_counter_id[0x20];
1135 u8 reserved_at_60[0x20];
1138 struct mlx5_ifc_traffic_counter_bits {
1143 struct mlx5_ifc_query_flow_counter_out_bits {
1145 u8 reserved_at_8[0x18];
1147 u8 reserved_at_40[0x40];
1148 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
1151 struct mlx5_ifc_query_flow_counter_in_bits {
1153 u8 reserved_at_10[0x10];
1154 u8 reserved_at_20[0x10];
1156 u8 reserved_at_40[0x20];
1160 u8 dump_to_memory[0x1];
1161 u8 num_of_counters[0x1e];
1162 u8 flow_counter_id[0x20];
1165 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u
1166 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u
1168 struct mlx5_ifc_klm_bits {
1169 u8 byte_count[0x20];
1174 struct mlx5_ifc_mkc_bits {
1175 u8 reserved_at_0[0x1];
1177 u8 reserved_at_2[0x1];
1178 u8 access_mode_4_2[0x3];
1179 u8 reserved_at_6[0x7];
1180 u8 relaxed_ordering_write[0x1];
1181 u8 reserved_at_e[0x1];
1182 u8 small_fence_on_rdma_read_response[0x1];
1189 u8 access_mode_1_0[0x2];
1190 u8 reserved_at_18[0x8];
1193 u8 reserved_at_40[0x20];
1197 u8 reserved_at_63[0x2];
1198 u8 expected_sigerr_count[0x1];
1199 u8 reserved_at_66[0x1];
1202 u8 start_addr[0x40];
1204 u8 bsf_octword_size[0x20];
1205 u8 reserved_at_120[0x80];
1206 u8 translations_octword_size[0x20];
1207 u8 reserved_at_1c0[0x19];
1208 u8 relaxed_ordering_read[0x1];
1209 u8 reserved_at_1da[0x1];
1210 u8 log_page_size[0x5];
1211 u8 reserved_at_1e0[0x3];
1213 u8 reserved_at_1e5[0x1b];
1216 /* Range of values for MKEY context crypto_en field. */
1218 MLX5_MKEY_CRYPTO_DISABLED = 0x0,
1219 MLX5_MKEY_CRYPTO_ENABLED = 0x1,
1222 struct mlx5_ifc_create_mkey_out_bits {
1224 u8 reserved_at_8[0x18];
1226 u8 reserved_at_40[0x8];
1227 u8 mkey_index[0x18];
1228 u8 reserved_at_60[0x20];
1231 struct mlx5_ifc_create_mkey_in_bits {
1233 u8 reserved_at_10[0x10];
1234 u8 reserved_at_20[0x10];
1236 u8 reserved_at_40[0x20];
1238 u8 reserved_at_61[0x1f];
1239 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
1240 u8 reserved_at_280[0x80];
1241 u8 translations_octword_actual_size[0x20];
1242 u8 mkey_umem_id[0x20];
1243 u8 mkey_umem_offset[0x40];
1244 u8 reserved_at_380[0x500];
1245 u8 klm_pas_mtt[][0x20];
1249 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
1250 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
1251 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
1252 MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1,
1253 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,
1254 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
1255 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP = 0x1C << 1,
1256 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1,
1259 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \
1260 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ)
1261 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \
1262 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS)
1263 #define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \
1264 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH)
1265 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \
1266 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO)
1267 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO \
1268 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO)
1269 #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \
1270 (1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT)
1271 #define MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD \
1272 (1ULL << MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD)
1273 #define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \
1274 (1ULL << MLX5_GENERAL_OBJ_TYPE_DEK)
1275 #define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \
1276 (1ULL << MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK)
1277 #define MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL \
1278 (1ULL << MLX5_GENERAL_OBJ_TYPE_CREDENTIAL)
1279 #define MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN \
1280 (1ULL << MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN)
1283 MLX5_HCA_CAP_OPMOD_GET_MAX = 0,
1284 MLX5_HCA_CAP_OPMOD_GET_CUR = 1,
1288 MLX5_CAP_INLINE_MODE_L2,
1289 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
1290 MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
1294 MLX5_INLINE_MODE_NONE,
1295 MLX5_INLINE_MODE_L2,
1296 MLX5_INLINE_MODE_IP,
1297 MLX5_INLINE_MODE_TCP_UDP,
1298 MLX5_INLINE_MODE_RESERVED4,
1299 MLX5_INLINE_MODE_INNER_L2,
1300 MLX5_INLINE_MODE_INNER_IP,
1301 MLX5_INLINE_MODE_INNER_TCP_UDP,
1304 /* The supported timestamp formats reported in HCA attributes. */
1306 MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR = 0x0,
1307 MLX5_HCA_CAP_TIMESTAMP_FORMAT_RT = 0x1,
1308 MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR_RT = 0x2,
1311 /* The timestamp format attributes to configure queues (RQ/SQ/QP). */
1313 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
1314 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1,
1315 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
1318 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
1319 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
1320 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
1321 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
1322 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
1323 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
1324 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
1325 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
1326 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
1327 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
1328 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
1330 /* The device steering logic format. */
1331 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 0x0
1332 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX 0x1
1334 struct mlx5_ifc_cmd_hca_cap_bits {
1335 u8 reserved_at_0[0x30];
1337 u8 reserved_at_40[0x20];
1338 u8 reserved_at_60[0x3];
1339 u8 log_regexp_scatter_gather_size[0x5];
1340 u8 reserved_at_68[0x3];
1341 u8 log_dma_mmo_size[0x5];
1342 u8 reserved_at_70[0x3];
1343 u8 log_compress_mmo_size[0x5];
1344 u8 reserved_at_78[0x3];
1345 u8 log_decompress_mmo_size[0x5];
1346 u8 log_max_srq_sz[0x8];
1347 u8 log_max_qp_sz[0x8];
1348 u8 reserved_at_90[0x9];
1349 u8 wqe_index_ignore_cap[0x1];
1350 u8 dynamic_qp_allocation[0x1];
1352 u8 reserved_at_a0[0x4];
1353 u8 regexp_num_of_engines[0x4];
1354 u8 reserved_at_a8[0x1];
1355 u8 reg_c_preserve[0x1];
1356 u8 reserved_at_aa[0x1];
1357 u8 log_max_srq[0x5];
1358 u8 reserved_at_b0[0xb];
1359 u8 scatter_fcs_w_decap_disable[0x1];
1360 u8 reserved_at_bc[0x4];
1361 u8 reserved_at_c0[0x8];
1362 u8 log_max_cq_sz[0x8];
1363 u8 reserved_at_d0[0xb];
1365 u8 log_max_eq_sz[0x8];
1366 u8 relaxed_ordering_write[0x1];
1367 u8 relaxed_ordering_read[0x1];
1368 u8 access_register_user[0x1];
1369 u8 log_max_mkey[0x5];
1370 u8 reserved_at_f0[0x8];
1371 u8 dump_fill_mkey[0x1];
1372 u8 reserved_at_f9[0x3];
1374 u8 max_indirection[0x8];
1375 u8 fixed_buffer_size[0x1];
1376 u8 log_max_mrw_sz[0x7];
1377 u8 force_teardown[0x1];
1378 u8 reserved_at_111[0x1];
1379 u8 log_max_bsf_list_size[0x6];
1380 u8 umr_extended_translation_offset[0x1];
1382 u8 log_max_klm_list_size[0x6];
1383 u8 non_wire_sq[0x1];
1384 u8 reserved_at_121[0x9];
1385 u8 log_max_ra_req_dc[0x6];
1386 u8 reserved_at_130[0x3];
1387 u8 log_max_static_sq_wq[0x5];
1388 u8 reserved_at_138[0x2];
1389 u8 log_max_ra_res_dc[0x6];
1390 u8 reserved_at_140[0xa];
1391 u8 log_max_ra_req_qp[0x6];
1392 u8 rtr2rts_qp_counters_set_id[0x1];
1393 u8 rts2rts_udp_sport[0x1];
1394 u8 rts2rts_lag_tx_port_affinity[0x1];
1396 u8 compress_min_block_size[0x4];
1397 u8 compress_mmo_sq[0x1];
1398 u8 decompress_mmo_sq[0x1];
1399 u8 log_max_ra_res_qp[0x6];
1401 u8 cc_query_allowed[0x1];
1402 u8 cc_modify_allowed[0x1];
1404 u8 cache_line_128byte[0x1];
1405 u8 reserved_at_165[0xa];
1407 u8 gid_table_size[0x10];
1408 u8 out_of_seq_cnt[0x1];
1409 u8 vport_counters[0x1];
1410 u8 retransmission_q_counters[0x1];
1412 u8 modify_rq_counter_set_id[0x1];
1413 u8 rq_delay_drop[0x1];
1415 u8 pkey_table_size[0x10];
1416 u8 vport_group_manager[0x1];
1417 u8 vhca_group_manager[0x1];
1420 u8 vnic_env_queue_counters[0x1];
1422 u8 nic_flow_table[0x1];
1423 u8 eswitch_manager[0x1];
1424 u8 device_memory[0x1];
1427 u8 local_ca_ack_delay[0x5];
1428 u8 port_module_event[0x1];
1429 u8 enhanced_error_q_counters[0x1];
1430 u8 ports_check[0x1];
1431 u8 reserved_at_1b3[0x1];
1432 u8 disable_link_up[0x1];
1436 u8 reserved_at_1c0[0x1];
1439 u8 log_max_msg[0x5];
1440 u8 reserved_at_1c8[0x4];
1442 u8 temp_warn_event[0x1];
1444 u8 general_notification_event[0x1];
1445 u8 reserved_at_1d3[0x2];
1449 u8 reserved_at_1d8[0x1];
1457 u8 stat_rate_support[0x10];
1458 u8 reserved_at_1f0[0xc];
1459 u8 cqe_version[0x4];
1460 u8 compact_address_vector[0x1];
1461 u8 striding_rq[0x1];
1462 u8 reserved_at_202[0x1];
1463 u8 ipoib_enhanced_offloads[0x1];
1464 u8 ipoib_basic_offloads[0x1];
1465 u8 reserved_at_205[0x1];
1466 u8 repeated_block_disabled[0x1];
1467 u8 umr_modify_entity_size_disabled[0x1];
1468 u8 umr_modify_atomic_disabled[0x1];
1469 u8 umr_indirect_mkey_disabled[0x1];
1471 u8 reserved_at_20c[0x3];
1472 u8 drain_sigerr[0x1];
1473 u8 cmdif_checksum[0x2];
1475 u8 reserved_at_213[0x1];
1476 u8 wq_signature[0x1];
1477 u8 sctr_data_cqe[0x1];
1478 u8 reserved_at_216[0x1];
1484 u8 eth_net_offloads[0x1];
1487 u8 reserved_at_21f[0x1];
1490 u8 cq_moderation[0x1];
1491 u8 reserved_at_223[0x3];
1492 u8 cq_eq_remap[0x1];
1494 u8 block_lb_mc[0x1];
1495 u8 reserved_at_229[0x1];
1496 u8 scqe_break_moderation[0x1];
1497 u8 cq_period_start_from_cqe[0x1];
1499 u8 reserved_at_22d[0x1];
1501 u8 vector_calc[0x1];
1502 u8 umr_ptr_rlky[0x1];
1504 u8 reserved_at_232[0x4];
1507 u8 set_deth_sqpn[0x1];
1508 u8 reserved_at_239[0x3];
1514 u8 reserved_at_241[0x8];
1515 u8 regexp_params[0x1];
1517 u8 port_selection_cap[0x1];
1518 u8 reserved_at_251[0x7];
1521 u8 driver_version[0x1];
1522 u8 pad_tx_eth_packet[0x1];
1523 u8 reserved_at_263[0x8];
1524 u8 log_bf_reg_size[0x5];
1525 u8 reserved_at_270[0xb];
1527 u8 num_lag_ports[0x4];
1528 u8 reserved_at_280[0x10];
1529 u8 max_wqe_sz_sq[0x10];
1530 u8 reserved_at_2a0[0xc];
1531 u8 regexp_mmo_sq[0x1];
1532 u8 regexp_version[0x3];
1533 u8 max_wqe_sz_rq[0x10];
1534 u8 max_flow_counter_31_16[0x10];
1535 u8 max_wqe_sz_sq_dc[0x10];
1536 u8 reserved_at_2e0[0x7];
1537 u8 max_qp_mcg[0x19];
1538 u8 reserved_at_300[0x10];
1539 u8 flow_counter_bulk_alloc[0x08];
1540 u8 log_max_mcg[0x8];
1541 u8 reserved_at_320[0x3];
1542 u8 log_max_transport_domain[0x5];
1543 u8 reserved_at_328[0x3];
1545 u8 reserved_at_330[0xb];
1546 u8 log_max_xrcd[0x5];
1547 u8 nic_receive_steering_discard[0x1];
1548 u8 receive_discard_vport_down[0x1];
1549 u8 transmit_discard_vport_down[0x1];
1550 u8 reserved_at_343[0x5];
1551 u8 log_max_flow_counter_bulk[0x8];
1552 u8 max_flow_counter_15_0[0x10];
1554 u8 flow_counters_dump[0x1];
1555 u8 reserved_at_360[0x1];
1557 u8 reserved_at_368[0x3];
1559 u8 reserved_at_370[0x3];
1560 u8 log_max_tir[0x5];
1561 u8 reserved_at_378[0x3];
1562 u8 log_max_tis[0x5];
1563 u8 basic_cyclic_rcv_wqe[0x1];
1564 u8 reserved_at_381[0x2];
1565 u8 log_max_rmp[0x5];
1566 u8 reserved_at_388[0x3];
1567 u8 log_max_rqt[0x5];
1568 u8 reserved_at_390[0x3];
1569 u8 log_max_rqt_size[0x5];
1570 u8 reserved_at_398[0x3];
1571 u8 log_max_tis_per_sq[0x5];
1572 u8 ext_stride_num_range[0x1];
1573 u8 reserved_at_3a1[0x2];
1574 u8 log_max_stride_sz_rq[0x5];
1575 u8 reserved_at_3a8[0x3];
1576 u8 log_min_stride_sz_rq[0x5];
1577 u8 reserved_at_3b0[0x3];
1578 u8 log_max_stride_sz_sq[0x5];
1579 u8 reserved_at_3b8[0x3];
1580 u8 log_min_stride_sz_sq[0x5];
1582 u8 reserved_at_3c1[0x2];
1583 u8 log_max_hairpin_queues[0x5];
1584 u8 reserved_at_3c8[0x3];
1585 u8 log_max_hairpin_wq_data_sz[0x5];
1586 u8 reserved_at_3d0[0x3];
1587 u8 log_max_hairpin_num_packets[0x5];
1588 u8 reserved_at_3d8[0x3];
1589 u8 log_max_wq_sz[0x5];
1590 u8 nic_vport_change_event[0x1];
1591 u8 disable_local_lb_uc[0x1];
1592 u8 disable_local_lb_mc[0x1];
1593 u8 log_min_hairpin_wq_data_sz[0x5];
1594 u8 reserved_at_3e8[0x3];
1595 u8 log_max_vlan_list[0x5];
1596 u8 reserved_at_3f0[0x3];
1597 u8 log_max_current_mc_list[0x5];
1598 u8 reserved_at_3f8[0x3];
1599 u8 log_max_current_uc_list[0x5];
1600 u8 general_obj_types[0x40];
1601 u8 sq_ts_format[0x2];
1602 u8 rq_ts_format[0x2];
1603 u8 steering_format_version[0x4];
1604 u8 reserved_at_448[0x18];
1605 u8 reserved_at_460[0x8];
1608 u8 reserved_at_46a[0x6];
1609 u8 max_num_eqs[0x10];
1610 u8 reserved_at_480[0x3];
1611 u8 log_max_l2_table[0x5];
1612 u8 reserved_at_488[0x8];
1613 u8 log_uar_page_sz[0x10];
1614 u8 reserved_at_4a0[0x20];
1615 u8 device_frequency_mhz[0x20];
1616 u8 device_frequency_khz[0x20];
1617 u8 reserved_at_500[0x20];
1618 u8 num_of_uars_per_page[0x20];
1619 u8 flex_parser_protocols[0x20];
1620 u8 max_geneve_tlv_options[0x8];
1621 u8 reserved_at_568[0x3];
1622 u8 max_geneve_tlv_option_data_len[0x5];
1623 u8 reserved_at_570[0x49];
1624 u8 mini_cqe_resp_l3_l4_tag[0x1];
1625 u8 mini_cqe_resp_flow_tag[0x1];
1626 u8 enhanced_cqe_compression[0x1];
1627 u8 mini_cqe_resp_stride_index[0x1];
1628 u8 cqe_128_always[0x1];
1629 u8 cqe_compression_128[0x1];
1630 u8 cqe_compression[0x1];
1631 u8 cqe_compression_timeout[0x10];
1632 u8 cqe_compression_max_num[0x10];
1633 u8 reserved_at_5e0[0x10];
1634 u8 tag_matching[0x1];
1635 u8 rndv_offload_rc[0x1];
1636 u8 rndv_offload_dc[0x1];
1637 u8 log_tag_matching_list_sz[0x5];
1638 u8 reserved_at_5f8[0x3];
1639 u8 log_max_xrq[0x5];
1640 u8 affiliate_nic_vport_criteria[0x8];
1641 u8 native_port_num[0x8];
1642 u8 num_vhca_ports[0x8];
1643 u8 reserved_at_618[0x6];
1644 u8 sw_owner_id[0x1];
1645 u8 reserved_at_61f[0x109];
1647 u8 regexp_mmo_qp[0x1];
1648 u8 compress_mmo_qp[0x1];
1649 u8 decompress_mmo_qp[0x1];
1650 u8 reserved_at_624[0xd4];
1653 struct mlx5_ifc_qos_cap_bits {
1654 u8 packet_pacing[0x1];
1655 u8 esw_scheduling[0x1];
1656 u8 esw_bw_share[0x1];
1657 u8 esw_rate_limit[0x1];
1658 u8 reserved_at_4[0x1];
1659 u8 packet_pacing_burst_bound[0x1];
1660 u8 packet_pacing_typical_size[0x1];
1661 u8 flow_meter_old[0x1];
1662 u8 reserved_at_8[0x8];
1663 u8 log_max_flow_meter[0x8];
1664 u8 flow_meter_reg_id[0x8];
1665 u8 wqe_rate_pp[0x1];
1666 u8 reserved_at_25[0x7];
1668 u8 reserved_at_2e[0x17];
1669 u8 packet_pacing_max_rate[0x20];
1670 u8 packet_pacing_min_rate[0x20];
1671 u8 reserved_at_80[0x10];
1672 u8 packet_pacing_rate_table_size[0x10];
1673 u8 esw_element_type[0x10];
1674 u8 esw_tsar_type[0x10];
1675 u8 reserved_at_c0[0x10];
1676 u8 max_qos_para_vport[0x10];
1677 u8 max_tsar_bw_share[0x20];
1678 u8 nic_element_type[0x10];
1679 u8 nic_tsar_type[0x10];
1680 u8 reserved_at_120[0x3];
1681 u8 log_meter_aso_granularity[0x5];
1682 u8 reserved_at_128[0x3];
1683 u8 log_meter_aso_max_alloc[0x5];
1684 u8 reserved_at_130[0x3];
1685 u8 log_max_num_meter_aso[0x5];
1686 u8 reserved_at_138[0x6b0];
1689 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1693 u8 lro_psh_flag[0x1];
1694 u8 lro_time_stamp[0x1];
1695 u8 lro_max_msg_sz_mode[0x2];
1696 u8 wqe_vlan_insert[0x1];
1697 u8 self_lb_en_modifiable[0x1];
1700 u8 max_lso_cap[0x5];
1701 u8 multi_pkt_send_wqe[0x2];
1702 u8 wqe_inline_mode[0x2];
1703 u8 rss_ind_tbl_cap[0x4];
1705 u8 scatter_fcs[0x1];
1706 u8 enhanced_multi_pkt_send_wqe[0x1];
1707 u8 tunnel_lso_const_out_ip_id[0x1];
1708 u8 tunnel_lro_gre[0x1];
1709 u8 tunnel_lro_vxlan[0x1];
1710 u8 tunnel_stateless_gre[0x1];
1711 u8 tunnel_stateless_vxlan[0x1];
1715 u8 reserved_at_23[0x8];
1716 u8 tunnel_stateless_gtp[0x1];
1717 u8 reserved_at_25[0x4];
1718 u8 max_vxlan_udp_ports[0x8];
1719 u8 reserved_at_38[0x6];
1720 u8 max_geneve_opt_len[0x1];
1721 u8 tunnel_stateless_geneve_rx[0x1];
1722 u8 reserved_at_40[0x10];
1723 u8 lro_min_mss_size[0x10];
1724 u8 reserved_at_60[0x120];
1725 u8 lro_timer_supported_periods[4][0x20];
1726 u8 reserved_at_200[0x600];
1730 MLX5_VIRTQ_TYPE_SPLIT = 0,
1731 MLX5_VIRTQ_TYPE_PACKED = 1,
1735 MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0,
1736 MLX5_VIRTQ_EVENT_MODE_QP = 1,
1737 MLX5_VIRTQ_EVENT_MODE_MSIX = 2,
1740 struct mlx5_ifc_virtio_emulation_cap_bits {
1741 u8 desc_tunnel_offload_type[0x1];
1742 u8 eth_frame_offload_type[0x1];
1743 u8 virtio_version_1_0[0x1];
1748 u8 reserved_at_7[0x1][0x9];
1750 u8 virtio_queue_type[0x8];
1751 u8 reserved_at_20[0x13];
1752 u8 log_doorbell_stride[0x5];
1753 u8 reserved_at_3b[0x3];
1754 u8 log_doorbell_bar_size[0x5];
1755 u8 doorbell_bar_offset[0x40];
1756 u8 reserved_at_80[0x8];
1757 u8 max_num_virtio_queues[0x18];
1758 u8 reserved_at_a0[0x60];
1759 u8 umem_1_buffer_param_a[0x20];
1760 u8 umem_1_buffer_param_b[0x20];
1761 u8 umem_2_buffer_param_a[0x20];
1762 u8 umem_2_buffer_param_b[0x20];
1763 u8 umem_3_buffer_param_a[0x20];
1764 u8 umem_3_buffer_param_b[0x20];
1765 u8 reserved_at_1c0[0x620];
1769 * PARSE_GRAPH_NODE Capabilities Field Descriptions
1771 struct mlx5_ifc_parse_graph_node_cap_bits {
1774 u8 header_length_mode[0x10];
1775 u8 sample_offset_mode[0x10];
1776 u8 max_num_arc_in[0x08];
1777 u8 max_num_arc_out[0x08];
1778 u8 max_num_sample[0x08];
1779 u8 reserved_at_78[0x07];
1780 u8 sample_id_in_out[0x1];
1781 u8 max_base_header_length[0x10];
1782 u8 reserved_at_90[0x08];
1783 u8 max_sample_base_offset[0x08];
1784 u8 max_next_header_offset[0x10];
1785 u8 reserved_at_b0[0x08];
1786 u8 header_length_mask_width[0x08];
1789 struct mlx5_ifc_flow_table_prop_layout_bits {
1792 u8 flow_counter[0x1];
1793 u8 flow_modify_en[0x1];
1794 u8 modify_root[0x1];
1795 u8 identified_miss_table[0x1];
1796 u8 flow_table_modify[0x1];
1799 u8 reset_root_to_default[0x1];
1802 u8 fpga_vendor_acceleration[0x1];
1804 u8 push_vlan_2[0x1];
1805 u8 reformat_and_vlan_action[0x1];
1806 u8 modify_and_vlan_action[0x1];
1808 u8 reformat_l3_tunnel_to_l2[0x1];
1809 u8 reformat_l2_to_l3_tunnel[0x1];
1810 u8 reformat_and_modify_action[0x1];
1811 u8 reserved_at_15[0x9];
1812 u8 sw_owner_v2[0x1];
1813 u8 reserved_at_1f[0x1];
1814 u8 reserved_at_20[0x2];
1815 u8 log_max_ft_size[0x6];
1816 u8 log_max_modify_header_context[0x8];
1817 u8 max_modify_header_actions[0x8];
1818 u8 max_ft_level[0x8];
1819 u8 reserved_at_40[0x8];
1820 u8 log_max_ft_sampler_num[8];
1821 u8 metadata_reg_b_width[0x8];
1822 u8 metadata_reg_a_width[0x8];
1823 u8 reserved_at_60[0x18];
1824 u8 log_max_ft_num[0x8];
1825 u8 reserved_at_80[0x10];
1826 u8 log_max_flow_counter[0x8];
1827 u8 log_max_destination[0x8];
1828 u8 reserved_at_a0[0x18];
1829 u8 log_max_flow[0x8];
1830 u8 reserved_at_c0[0x140];
1833 struct mlx5_ifc_roce_caps_bits {
1834 u8 reserved_0[0x1e];
1835 u8 qp_ts_format[0x2];
1836 u8 reserved_at_20[0x7e0];
1840 * Table 1872 - Flow Table Fields Supported 2 Format
1842 struct mlx5_ifc_ft_fields_support_2_bits {
1843 u8 reserved_at_0[0xf];
1844 u8 tunnel_header_2_3[0x1];
1845 u8 tunnel_header_0_1[0x1];
1846 u8 macsec_syndrome[0x1];
1848 u8 outer_lrh_sl[0x1];
1849 u8 inner_ipv4_ihl[0x1];
1850 u8 outer_ipv4_ihl[0x1];
1851 u8 psp_syndrome[0x1];
1852 u8 inner_l3_ok[0x1];
1853 u8 inner_l4_ok[0x1];
1854 u8 outer_l3_ok[0x1];
1855 u8 outer_l4_ok[0x1];
1857 u8 inner_ipv4_checksum_ok[0x1];
1858 u8 inner_l4_checksum_ok[0x1];
1859 u8 outer_ipv4_checksum_ok[0x1];
1860 u8 outer_l4_checksum_ok[0x1];
1861 u8 reserved_at_20[0x60];
1864 struct mlx5_ifc_flow_table_nic_cap_bits {
1865 u8 reserved_at_0[0x200];
1866 struct mlx5_ifc_flow_table_prop_layout_bits
1867 flow_table_properties_nic_receive;
1868 struct mlx5_ifc_flow_table_prop_layout_bits
1869 flow_table_properties_nic_receive_rdma;
1870 struct mlx5_ifc_flow_table_prop_layout_bits
1871 flow_table_properties_nic_receive_sniffer;
1872 struct mlx5_ifc_flow_table_prop_layout_bits
1873 flow_table_properties_nic_transmit;
1874 struct mlx5_ifc_flow_table_prop_layout_bits
1875 flow_table_properties_nic_transmit_rdma;
1876 struct mlx5_ifc_flow_table_prop_layout_bits
1877 flow_table_properties_nic_transmit_sniffer;
1878 u8 reserved_at_e00[0x600];
1879 struct mlx5_ifc_ft_fields_support_2_bits
1880 ft_field_support_2_nic_receive;
1884 * HCA Capabilities 2
1886 struct mlx5_ifc_cmd_hca_cap_2_bits {
1887 u8 reserved_at_0[0x80]; /* End of DW4. */
1888 u8 reserved_at_80[0x3];
1889 u8 max_num_prog_sample_field[0x5];
1890 u8 reserved_at_88[0x3];
1891 u8 log_max_num_reserved_qpn[0x5];
1892 u8 reserved_at_90[0x3];
1893 u8 log_reserved_qpn_granularity[0x5];
1894 u8 reserved_at_98[0x3];
1895 u8 log_reserved_qpn_max_alloc[0x5]; /* End of DW5. */
1896 u8 max_reformat_insert_size[0x8];
1897 u8 max_reformat_insert_offset[0x8];
1898 u8 max_reformat_remove_size[0x8];
1899 u8 max_reformat_remove_offset[0x8]; /* End of DW6. */
1900 u8 aso_conntrack_reg_id[0x8];
1901 u8 reserved_at_c8[0x3];
1902 u8 log_conn_track_granularity[0x5];
1903 u8 reserved_at_d0[0x3];
1904 u8 log_conn_track_max_alloc[0x5];
1905 u8 reserved_at_d8[0x3];
1906 u8 log_max_conn_track_offload[0x5];
1907 u8 reserved_at_e0[0x20]; /* End of DW7. */
1908 u8 reserved_at_100[0x700];
1911 union mlx5_ifc_hca_cap_union_bits {
1912 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1913 struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1914 per_protocol_networking_offload_caps;
1915 struct mlx5_ifc_qos_cap_bits qos_cap;
1916 struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
1917 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1918 struct mlx5_ifc_roce_caps_bits roce_caps;
1919 u8 reserved_at_0[0x8000];
1922 struct mlx5_ifc_set_action_in_bits {
1923 u8 action_type[0x4];
1925 u8 reserved_at_10[0x3];
1927 u8 reserved_at_18[0x3];
1932 struct mlx5_ifc_query_hca_cap_out_bits {
1934 u8 reserved_at_8[0x18];
1936 u8 reserved_at_40[0x40];
1937 union mlx5_ifc_hca_cap_union_bits capability;
1940 struct mlx5_ifc_query_hca_cap_in_bits {
1942 u8 reserved_at_10[0x10];
1943 u8 reserved_at_20[0x10];
1945 u8 reserved_at_40[0x40];
1948 struct mlx5_ifc_mac_address_layout_bits {
1949 u8 reserved_at_0[0x10];
1950 u8 mac_addr_47_32[0x10];
1951 u8 mac_addr_31_0[0x20];
1954 struct mlx5_ifc_nic_vport_context_bits {
1955 u8 reserved_at_0[0x5];
1956 u8 min_wqe_inline_mode[0x3];
1957 u8 reserved_at_8[0x15];
1958 u8 disable_mc_local_lb[0x1];
1959 u8 disable_uc_local_lb[0x1];
1961 u8 arm_change_event[0x1];
1962 u8 reserved_at_21[0x1a];
1963 u8 event_on_mtu[0x1];
1964 u8 event_on_promisc_change[0x1];
1965 u8 event_on_vlan_change[0x1];
1966 u8 event_on_mc_address_change[0x1];
1967 u8 event_on_uc_address_change[0x1];
1968 u8 reserved_at_40[0xc];
1969 u8 affiliation_criteria[0x4];
1970 u8 affiliated_vhca_id[0x10];
1971 u8 reserved_at_60[0xd0];
1973 u8 system_image_guid[0x40];
1976 u8 reserved_at_200[0x140];
1977 u8 qkey_violation_counter[0x10];
1978 u8 reserved_at_350[0x430];
1981 u8 promisc_all[0x1];
1982 u8 reserved_at_783[0x2];
1983 u8 allowed_list_type[0x3];
1984 u8 reserved_at_788[0xc];
1985 u8 allowed_list_size[0xc];
1986 struct mlx5_ifc_mac_address_layout_bits permanent_address;
1987 u8 reserved_at_7e0[0x20];
1990 struct mlx5_ifc_query_nic_vport_context_out_bits {
1992 u8 reserved_at_8[0x18];
1994 u8 reserved_at_40[0x40];
1995 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
1998 struct mlx5_ifc_query_nic_vport_context_in_bits {
2000 u8 reserved_at_10[0x10];
2001 u8 reserved_at_20[0x10];
2003 u8 other_vport[0x1];
2004 u8 reserved_at_41[0xf];
2005 u8 vport_number[0x10];
2006 u8 reserved_at_60[0x5];
2007 u8 allowed_list_type[0x3];
2008 u8 reserved_at_68[0x18];
2012 * lag_tx_port_affinity: 0 auto-selection, 1 PF1, 2 PF2 vice versa.
2013 * Each TIS binds to one PF by setting lag_tx_port_affinity (>0).
2014 * Once LAG enabled, we create multiple TISs and bind each one to
2015 * different PFs, then TIS[i] gets affinity i+1 and goes to PF i+1.
2017 #define MLX5_IFC_LAG_MAP_TIS_AFFINITY(index, num) ((num) ? \
2018 (index) % (num) + 1 : 0)
2019 struct mlx5_ifc_tisc_bits {
2020 u8 strict_lag_tx_port_affinity[0x1];
2021 u8 reserved_at_1[0x3];
2022 u8 lag_tx_port_affinity[0x04];
2023 u8 reserved_at_8[0x4];
2025 u8 reserved_at_10[0x10];
2026 u8 reserved_at_20[0x100];
2027 u8 reserved_at_120[0x8];
2028 u8 transport_domain[0x18];
2029 u8 reserved_at_140[0x8];
2030 u8 underlay_qpn[0x18];
2031 u8 reserved_at_160[0x3a0];
2034 struct mlx5_ifc_query_tis_out_bits {
2036 u8 reserved_at_8[0x18];
2038 u8 reserved_at_40[0x40];
2039 struct mlx5_ifc_tisc_bits tis_context;
2042 struct mlx5_ifc_query_tis_in_bits {
2044 u8 reserved_at_10[0x10];
2045 u8 reserved_at_20[0x10];
2047 u8 reserved_at_40[0x8];
2049 u8 reserved_at_60[0x20];
2052 /* port_select_mode definition. */
2053 enum mlx5_lag_mode_type {
2054 MLX5_LAG_MODE_TIS = 0,
2055 MLX5_LAG_MODE_HASH = 1,
2058 struct mlx5_ifc_lag_context_bits {
2059 u8 fdb_selection_mode[0x1];
2060 u8 reserved_at_1[0x14];
2061 u8 port_select_mode[0x3];
2062 u8 reserved_at_18[0x5];
2064 u8 reserved_at_20[0x14];
2065 u8 tx_remap_affinity_2[0x4];
2066 u8 reserved_at_38[0x4];
2067 u8 tx_remap_affinity_1[0x4];
2070 struct mlx5_ifc_query_lag_in_bits {
2073 u8 reserved_at_20[0x10];
2075 u8 reserved_at_40[0x40];
2078 struct mlx5_ifc_query_lag_out_bits {
2080 u8 reserved_at_8[0x18];
2082 struct mlx5_ifc_lag_context_bits context;
2085 struct mlx5_ifc_alloc_transport_domain_out_bits {
2087 u8 reserved_at_8[0x18];
2089 u8 reserved_at_40[0x8];
2090 u8 transport_domain[0x18];
2091 u8 reserved_at_60[0x20];
2094 struct mlx5_ifc_alloc_transport_domain_in_bits {
2096 u8 reserved_at_10[0x10];
2097 u8 reserved_at_20[0x10];
2099 u8 reserved_at_40[0x40];
2103 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
2104 MLX5_WQ_TYPE_CYCLIC = 0x1,
2105 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
2106 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
2110 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
2111 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
2114 struct mlx5_ifc_wq_bits {
2116 u8 wq_signature[0x1];
2117 u8 end_padding_mode[0x2];
2119 u8 reserved_at_8[0x18];
2120 u8 hds_skip_first_sge[0x1];
2121 u8 log2_hds_buf_size[0x3];
2122 u8 reserved_at_24[0x7];
2123 u8 page_offset[0x5];
2125 u8 reserved_at_40[0x8];
2127 u8 reserved_at_60[0x8];
2130 u8 hw_counter[0x20];
2131 u8 sw_counter[0x20];
2132 u8 reserved_at_100[0xc];
2133 u8 log_wq_stride[0x4];
2134 u8 reserved_at_110[0x3];
2135 u8 log_wq_pg_sz[0x5];
2136 u8 reserved_at_118[0x3];
2138 u8 dbr_umem_valid[0x1];
2139 u8 wq_umem_valid[0x1];
2140 u8 reserved_at_122[0x1];
2141 u8 log_hairpin_num_packets[0x5];
2142 u8 reserved_at_128[0x3];
2143 u8 log_hairpin_data_sz[0x5];
2144 u8 reserved_at_130[0x4];
2145 u8 single_wqe_log_num_of_strides[0x4];
2146 u8 two_byte_shift_en[0x1];
2147 u8 reserved_at_139[0x4];
2148 u8 single_stride_log_num_of_bytes[0x3];
2149 u8 dbr_umem_id[0x20];
2150 u8 wq_umem_id[0x20];
2151 u8 wq_umem_offset[0x40];
2152 u8 reserved_at_1c0[0x440];
2156 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2157 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2161 MLX5_RQC_STATE_RST = 0x0,
2162 MLX5_RQC_STATE_RDY = 0x1,
2163 MLX5_RQC_STATE_ERR = 0x3,
2166 struct mlx5_ifc_rqc_bits {
2168 u8 delay_drop_en[0x1];
2169 u8 scatter_fcs[0x1];
2171 u8 mem_rq_type[0x4];
2173 u8 reserved_at_c[0x1];
2174 u8 flush_in_error_en[0x1];
2176 u8 reserved_at_f[0xB];
2178 u8 reserved_at_1c[0x4];
2179 u8 reserved_at_20[0x8];
2180 u8 user_index[0x18];
2181 u8 reserved_at_40[0x8];
2183 u8 counter_set_id[0x8];
2184 u8 reserved_at_68[0x18];
2185 u8 reserved_at_80[0x8];
2187 u8 reserved_at_a0[0x8];
2188 u8 hairpin_peer_sq[0x18];
2189 u8 reserved_at_c0[0x10];
2190 u8 hairpin_peer_vhca[0x10];
2191 u8 reserved_at_e0[0xa0];
2192 struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
2195 struct mlx5_ifc_create_rq_out_bits {
2197 u8 reserved_at_8[0x18];
2199 u8 reserved_at_40[0x8];
2201 u8 reserved_at_60[0x20];
2204 struct mlx5_ifc_create_rq_in_bits {
2207 u8 reserved_at_20[0x10];
2209 u8 reserved_at_40[0xc0];
2210 struct mlx5_ifc_rqc_bits ctx;
2213 struct mlx5_ifc_modify_rq_out_bits {
2215 u8 reserved_at_8[0x18];
2217 u8 reserved_at_40[0x40];
2220 struct mlx5_ifc_query_rq_out_bits {
2222 u8 reserved_at_8[0x18];
2224 u8 reserved_at_40[0xc0];
2225 struct mlx5_ifc_rqc_bits rq_context;
2228 struct mlx5_ifc_query_rq_in_bits {
2230 u8 reserved_at_10[0x10];
2231 u8 reserved_at_20[0x10];
2233 u8 reserved_at_40[0x8];
2235 u8 reserved_at_60[0x20];
2238 struct mlx5_ifc_create_tis_out_bits {
2240 u8 reserved_at_8[0x18];
2242 u8 reserved_at_40[0x8];
2244 u8 reserved_at_60[0x20];
2247 struct mlx5_ifc_create_tis_in_bits {
2250 u8 reserved_at_20[0x10];
2252 u8 reserved_at_40[0xc0];
2253 struct mlx5_ifc_tisc_bits ctx;
2257 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
2258 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
2259 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
2260 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
2263 struct mlx5_ifc_modify_rq_in_bits {
2266 u8 reserved_at_20[0x10];
2269 u8 reserved_at_44[0x4];
2271 u8 reserved_at_60[0x20];
2272 u8 modify_bitmask[0x40];
2273 u8 reserved_at_c0[0x40];
2274 struct mlx5_ifc_rqc_bits ctx;
2278 MLX5_L3_PROT_TYPE_IPV4 = 0,
2279 MLX5_L3_PROT_TYPE_IPV6 = 1,
2283 MLX5_L4_PROT_TYPE_TCP = 0,
2284 MLX5_L4_PROT_TYPE_UDP = 1,
2288 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
2289 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
2290 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
2291 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
2292 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
2295 struct mlx5_ifc_rx_hash_field_select_bits {
2296 u8 l3_prot_type[0x1];
2297 u8 l4_prot_type[0x1];
2298 u8 selected_fields[0x1e];
2302 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2303 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2307 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2308 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2312 MLX5_RX_HASH_FN_NONE = 0x0,
2313 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2314 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2318 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
2319 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
2323 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 = 0x0,
2324 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2 = 0x1,
2327 struct mlx5_ifc_tirc_bits {
2328 u8 reserved_at_0[0x20];
2330 u8 reserved_at_24[0x1c];
2331 u8 reserved_at_40[0x40];
2332 u8 reserved_at_80[0x4];
2333 u8 lro_timeout_period_usecs[0x10];
2334 u8 lro_enable_mask[0x4];
2335 u8 lro_max_msg_sz[0x8];
2336 u8 reserved_at_a0[0x40];
2337 u8 reserved_at_e0[0x8];
2338 u8 inline_rqn[0x18];
2339 u8 rx_hash_symmetric[0x1];
2340 u8 reserved_at_101[0x1];
2341 u8 tunneled_offload_en[0x1];
2342 u8 reserved_at_103[0x5];
2343 u8 indirect_table[0x18];
2345 u8 reserved_at_124[0x2];
2346 u8 self_lb_block[0x2];
2347 u8 transport_domain[0x18];
2348 u8 rx_hash_toeplitz_key[10][0x20];
2349 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2350 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2351 u8 reserved_at_2c0[0x4c0];
2354 struct mlx5_ifc_create_tir_out_bits {
2356 u8 reserved_at_8[0x18];
2358 u8 reserved_at_40[0x8];
2360 u8 reserved_at_60[0x20];
2363 struct mlx5_ifc_create_tir_in_bits {
2366 u8 reserved_at_20[0x10];
2368 u8 reserved_at_40[0xc0];
2369 struct mlx5_ifc_tirc_bits ctx;
2373 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0,
2374 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1,
2375 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2,
2376 /* bit 3 - tunneled_offload_en modify not supported. */
2377 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4,
2380 struct mlx5_ifc_modify_tir_out_bits {
2382 u8 reserved_at_8[0x18];
2384 u8 reserved_at_40[0x40];
2387 struct mlx5_ifc_modify_tir_in_bits {
2390 u8 reserved_at_20[0x10];
2392 u8 reserved_at_40[0x8];
2394 u8 reserved_at_60[0x20];
2395 u8 modify_bitmask[0x40];
2396 u8 reserved_at_c0[0x40];
2397 struct mlx5_ifc_tirc_bits ctx;
2401 MLX5_INLINE_Q_TYPE_RQ = 0x0,
2402 MLX5_INLINE_Q_TYPE_VIRTQ = 0x1,
2405 struct mlx5_ifc_rq_num_bits {
2406 u8 reserved_at_0[0x8];
2410 struct mlx5_ifc_rqtc_bits {
2411 u8 reserved_at_0[0xa5];
2412 u8 list_q_type[0x3];
2413 u8 reserved_at_a8[0x8];
2414 u8 rqt_max_size[0x10];
2415 u8 reserved_at_c0[0x10];
2416 u8 rqt_actual_size[0x10];
2417 u8 reserved_at_e0[0x6a0];
2418 struct mlx5_ifc_rq_num_bits rq_num[];
2421 struct mlx5_ifc_create_rqt_out_bits {
2423 u8 reserved_at_8[0x18];
2425 u8 reserved_at_40[0x8];
2427 u8 reserved_at_60[0x20];
2431 #pragma GCC diagnostic ignored "-Wpedantic"
2433 struct mlx5_ifc_create_rqt_in_bits {
2436 u8 reserved_at_20[0x10];
2438 u8 reserved_at_40[0xc0];
2439 struct mlx5_ifc_rqtc_bits rqt_context;
2442 struct mlx5_ifc_modify_rqt_in_bits {
2445 u8 reserved_at_20[0x10];
2447 u8 reserved_at_40[0x8];
2449 u8 reserved_at_60[0x20];
2450 u8 modify_bitmask[0x40];
2451 u8 reserved_at_c0[0x40];
2452 struct mlx5_ifc_rqtc_bits rqt_context;
2455 #pragma GCC diagnostic error "-Wpedantic"
2458 struct mlx5_ifc_modify_rqt_out_bits {
2460 u8 reserved_at_8[0x18];
2462 u8 reserved_at_40[0x40];
2466 MLX5_SQC_STATE_RST = 0x0,
2467 MLX5_SQC_STATE_RDY = 0x1,
2468 MLX5_SQC_STATE_ERR = 0x3,
2471 struct mlx5_ifc_sqc_bits {
2475 u8 flush_in_error_en[0x1];
2476 u8 allow_multi_pkt_send_wqe[0x1];
2477 u8 min_wqe_inline_mode[0x3];
2483 u8 static_sq_wq[0x1];
2484 u8 reserved_at_11[0x9];
2486 u8 reserved_at_1c[0x4];
2487 u8 reserved_at_20[0x8];
2488 u8 user_index[0x18];
2489 u8 reserved_at_40[0x8];
2491 u8 reserved_at_60[0x8];
2492 u8 hairpin_peer_rq[0x18];
2493 u8 reserved_at_80[0x10];
2494 u8 hairpin_peer_vhca[0x10];
2495 u8 reserved_at_a0[0x50];
2496 u8 packet_pacing_rate_limit_index[0x10];
2497 u8 tis_lst_sz[0x10];
2498 u8 reserved_at_110[0x10];
2499 u8 reserved_at_120[0x40];
2500 u8 reserved_at_160[0x8];
2502 struct mlx5_ifc_wq_bits wq;
2505 struct mlx5_ifc_query_sq_in_bits {
2507 u8 reserved_at_10[0x10];
2508 u8 reserved_at_20[0x10];
2510 u8 reserved_at_40[0x8];
2512 u8 reserved_at_60[0x20];
2515 struct mlx5_ifc_modify_sq_out_bits {
2517 u8 reserved_at_8[0x18];
2519 u8 reserved_at_40[0x40];
2522 struct mlx5_ifc_modify_sq_in_bits {
2525 u8 reserved_at_20[0x10];
2528 u8 reserved_at_44[0x4];
2530 u8 reserved_at_60[0x20];
2531 u8 modify_bitmask[0x40];
2532 u8 reserved_at_c0[0x40];
2533 struct mlx5_ifc_sqc_bits ctx;
2536 struct mlx5_ifc_create_sq_out_bits {
2538 u8 reserved_at_8[0x18];
2540 u8 reserved_at_40[0x8];
2542 u8 reserved_at_60[0x20];
2545 struct mlx5_ifc_create_sq_in_bits {
2548 u8 reserved_at_20[0x10];
2550 u8 reserved_at_40[0xc0];
2551 struct mlx5_ifc_sqc_bits ctx;
2555 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
2556 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
2557 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
2558 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
2559 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
2562 struct mlx5_ifc_flow_meter_parameters_bits {
2564 u8 bucket_overflow[0x1];
2565 u8 start_color[0x2];
2566 u8 both_buckets_on_green[0x1];
2568 u8 reserved_at_1[0x19];
2569 u8 reserved_at_2[0x20];
2570 u8 reserved_at_3[0x3];
2571 u8 cbs_exponent[0x5];
2572 u8 cbs_mantissa[0x8];
2573 u8 reserved_at_4[0x3];
2574 u8 cir_exponent[0x5];
2575 u8 cir_mantissa[0x8];
2576 u8 reserved_at_5[0x20];
2577 u8 reserved_at_6[0x3];
2578 u8 ebs_exponent[0x5];
2579 u8 ebs_mantissa[0x8];
2580 u8 reserved_at_7[0x3];
2581 u8 eir_exponent[0x5];
2582 u8 eir_mantissa[0x8];
2583 u8 reserved_at_8[0x60];
2585 #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF)
2586 #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8
2589 MLX5_METER_MODE_IP_LEN = 0x0,
2590 MLX5_METER_MODE_L2_LEN = 0x1,
2591 MLX5_METER_MODE_L2_IPG_LEN = 0x2,
2592 MLX5_METER_MODE_PKT = 0x3,
2596 MLX5_CQE_SIZE_64B = 0x0,
2597 MLX5_CQE_SIZE_128B = 0x1,
2600 struct mlx5_ifc_cqc_bits {
2603 u8 initiator_src_dct[0x1];
2604 u8 dbr_umem_valid[0x1];
2605 u8 reserved_at_7[0x1];
2608 u8 reserved_at_c[0x1];
2609 u8 scqe_break_moderation_en[0x1];
2611 u8 cq_period_mode[0x2];
2612 u8 cqe_comp_en[0x1];
2613 u8 mini_cqe_res_format[0x2];
2615 u8 reserved_at_18[0x1];
2616 u8 cqe_comp_layout[0x7];
2617 u8 dbr_umem_id[0x20];
2618 u8 reserved_at_40[0x14];
2619 u8 page_offset[0x6];
2620 u8 reserved_at_5a[0x2];
2621 u8 mini_cqe_res_format_ext[0x2];
2622 u8 cq_timestamp_format[0x2];
2623 u8 reserved_at_60[0x3];
2624 u8 log_cq_size[0x5];
2626 u8 reserved_at_80[0x4];
2628 u8 cq_max_count[0x10];
2629 u8 reserved_at_a0[0x18];
2631 u8 reserved_at_c0[0x3];
2632 u8 log_page_size[0x5];
2633 u8 reserved_at_c8[0x18];
2634 u8 reserved_at_e0[0x20];
2635 u8 reserved_at_100[0x8];
2636 u8 last_notified_index[0x18];
2637 u8 reserved_at_120[0x8];
2638 u8 last_solicit_index[0x18];
2639 u8 reserved_at_140[0x8];
2640 u8 consumer_counter[0x18];
2641 u8 reserved_at_160[0x8];
2642 u8 producer_counter[0x18];
2643 u8 local_partition_id[0xc];
2644 u8 process_id[0x14];
2645 u8 reserved_at_1A0[0x20];
2649 struct mlx5_ifc_health_buffer_bits {
2650 u8 reserved_0[0x100];
2651 u8 assert_existptr[0x20];
2652 u8 assert_callra[0x20];
2653 u8 reserved_1[0x40];
2654 u8 fw_version[0x20];
2656 u8 reserved_2[0x20];
2657 u8 irisc_index[0x8];
2662 struct mlx5_ifc_initial_seg_bits {
2663 u8 fw_rev_minor[0x10];
2664 u8 fw_rev_major[0x10];
2665 u8 cmd_interface_rev[0x10];
2666 u8 fw_rev_subminor[0x10];
2667 u8 reserved_0[0x40];
2668 u8 cmdq_phy_addr_63_32[0x20];
2669 u8 cmdq_phy_addr_31_12[0x14];
2671 u8 nic_interface[0x2];
2672 u8 log_cmdq_size[0x4];
2673 u8 log_cmdq_stride[0x4];
2674 u8 command_doorbell_vector[0x20];
2675 u8 reserved_2[0xf00];
2676 u8 initializing[0x1];
2677 u8 nic_interface_supported[0x7];
2678 u8 reserved_4[0x18];
2679 struct mlx5_ifc_health_buffer_bits health_buffer;
2680 u8 no_dram_nic_offset[0x20];
2681 u8 reserved_5[0x6de0];
2682 u8 internal_timer_h[0x20];
2683 u8 internal_timer_l[0x20];
2684 u8 reserved_6[0x20];
2685 u8 reserved_7[0x1f];
2687 u8 health_syndrome[0x8];
2688 u8 health_counter[0x18];
2689 u8 reserved_8[0x17fc0];
2692 struct mlx5_ifc_create_cq_out_bits {
2694 u8 reserved_at_8[0x18];
2696 u8 reserved_at_40[0x8];
2698 u8 reserved_at_60[0x20];
2701 struct mlx5_ifc_create_cq_in_bits {
2704 u8 reserved_at_20[0x10];
2706 u8 reserved_at_40[0x40];
2707 struct mlx5_ifc_cqc_bits cq_context;
2708 u8 cq_umem_offset[0x40];
2709 u8 cq_umem_id[0x20];
2710 u8 cq_umem_valid[0x1];
2711 u8 reserved_at_2e1[0x1f];
2712 u8 reserved_at_300[0x580];
2717 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
2718 MLX5_GENERAL_OBJ_TYPE_DEK = 0x000c,
2719 MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
2720 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
2721 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d,
2722 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL = 0x001e,
2723 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN = 0x001f,
2724 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,
2725 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024,
2726 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025,
2727 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031,
2730 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
2732 u8 reserved_at_10[0x20];
2735 u8 reserved_at_60[0x3];
2736 u8 log_obj_range[0x5];
2737 u8 reserved_at_58[0x18];
2740 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
2742 u8 reserved_at_8[0x18];
2745 u8 reserved_at_60[0x20];
2748 struct mlx5_ifc_virtio_q_counters_bits {
2749 u8 modify_field_select[0x40];
2750 u8 reserved_at_40[0x40];
2751 u8 received_desc[0x40];
2752 u8 completed_desc[0x40];
2753 u8 error_cqes[0x20];
2754 u8 bad_desc_errors[0x20];
2755 u8 exceed_max_chain[0x20];
2756 u8 invalid_buffer[0x20];
2757 u8 reserved_at_180[0x50];
2760 struct mlx5_ifc_geneve_tlv_option_bits {
2761 u8 modify_field_select[0x40];
2762 u8 reserved_at_40[0x18];
2763 u8 geneve_option_fte_index[0x8];
2764 u8 option_class[0x10];
2765 u8 option_type[0x8];
2766 u8 reserved_at_78[0x3];
2767 u8 option_data_length[0x5];
2768 u8 reserved_at_80[0x180];
2771 struct mlx5_ifc_create_virtio_q_counters_in_bits {
2772 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2773 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2776 struct mlx5_ifc_query_virtio_q_counters_out_bits {
2777 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2778 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2781 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
2782 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2783 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
2787 MLX5_CRYPTO_KEY_SIZE_128b = 0x0,
2788 MLX5_CRYPTO_KEY_SIZE_256b = 0x1,
2792 MLX5_CRYPTO_KEY_PURPOSE_TLS = 0x1,
2793 MLX5_CRYPTO_KEY_PURPOSE_IPSEC = 0x2,
2794 MLX5_CRYPTO_KEY_PURPOSE_AES_XTS = 0x3,
2795 MLX5_CRYPTO_KEY_PURPOSE_MACSEC = 0x4,
2796 MLX5_CRYPTO_KEY_PURPOSE_GCM = 0x5,
2797 MLX5_CRYPTO_KEY_PURPOSE_PSP = 0x6,
2800 struct mlx5_ifc_dek_bits {
2801 u8 modify_field_select[0x40];
2803 u8 reserved_at_48[0xc];
2806 u8 reserved_at_59[0x3];
2807 u8 key_purpose[0x4];
2808 u8 reserved_at_60[0x8];
2810 u8 reserved_at_80[0x100];
2812 u8 reserved_at_1c0[0x40];
2814 u8 reserved_at_600[0x200];
2817 struct mlx5_ifc_create_dek_in_bits {
2818 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2819 struct mlx5_ifc_dek_bits dek;
2822 struct mlx5_ifc_import_kek_bits {
2823 u8 modify_field_select[0x40];
2825 u8 reserved_at_48[0xc];
2827 u8 reserved_at_58[0x1a8];
2829 u8 reserved_at_600[0x200];
2832 struct mlx5_ifc_create_import_kek_in_bits {
2833 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2834 struct mlx5_ifc_import_kek_bits import_kek;
2838 MLX5_CREDENTIAL_ROLE_OFFICER = 0x0,
2839 MLX5_CREDENTIAL_ROLE_USER = 0x1,
2842 struct mlx5_ifc_credential_bits {
2843 u8 modify_field_select[0x40];
2845 u8 reserved_at_48[0x10];
2846 u8 credential_role[0x8];
2847 u8 reserved_at_60[0x1a0];
2848 u8 credential[0x180];
2849 u8 reserved_at_380[0x480];
2852 struct mlx5_ifc_create_credential_in_bits {
2853 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2854 struct mlx5_ifc_credential_bits credential;
2857 struct mlx5_ifc_crypto_login_bits {
2858 u8 modify_field_select[0x40];
2859 u8 reserved_at_40[0x48];
2860 u8 credential_pointer[0x18];
2861 u8 reserved_at_a0[0x8];
2862 u8 session_import_kek_ptr[0x18];
2863 u8 reserved_at_c0[0x140];
2864 u8 credential[0x180];
2865 u8 reserved_at_380[0x480];
2868 struct mlx5_ifc_create_crypto_login_in_bits {
2869 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2870 struct mlx5_ifc_crypto_login_bits crypto_login;
2874 MLX5_VIRTQ_STATE_INIT = 0,
2875 MLX5_VIRTQ_STATE_RDY = 1,
2876 MLX5_VIRTQ_STATE_SUSPEND = 2,
2877 MLX5_VIRTQ_STATE_ERROR = 3,
2881 MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),
2882 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),
2883 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),
2886 struct mlx5_ifc_virtio_q_bits {
2887 u8 virtio_q_type[0x8];
2888 u8 reserved_at_8[0x5];
2890 u8 queue_index[0x10];
2891 u8 full_emulation[0x1];
2892 u8 virtio_version_1_0[0x1];
2893 u8 reserved_at_22[0x2];
2894 u8 offload_type[0x4];
2895 u8 event_qpn_or_msix[0x18];
2896 u8 doorbell_stride_idx[0x10];
2897 u8 queue_size[0x10];
2898 u8 device_emulation_id[0x20];
2901 u8 available_addr[0x40];
2902 u8 virtio_q_mkey[0x20];
2903 u8 reserved_at_160[0x18];
2906 u8 umem_1_size[0x20];
2907 u8 umem_1_offset[0x40];
2909 u8 umem_2_size[0x20];
2910 u8 umem_2_offset[0x40];
2912 u8 umem_3_size[0x20];
2913 u8 umem_3_offset[0x40];
2914 u8 counter_set_id[0x20];
2915 u8 reserved_at_320[0x8];
2917 u8 reserved_at_340[0x2];
2918 u8 queue_period_mode[0x2];
2919 u8 queue_period_us[0xc];
2920 u8 queue_max_count[0x10];
2921 u8 reserved_at_360[0xa0];
2924 struct mlx5_ifc_virtio_net_q_bits {
2925 u8 modify_field_select[0x40];
2926 u8 reserved_at_40[0x40];
2931 u8 reserved_at_84[0x6];
2932 u8 dirty_bitmap_dump_enable[0x1];
2933 u8 vhost_log_page[0x5];
2934 u8 reserved_at_90[0xc];
2936 u8 reserved_at_a0[0x8];
2937 u8 tisn_or_qpn[0x18];
2938 u8 dirty_bitmap_mkey[0x20];
2939 u8 dirty_bitmap_size[0x20];
2940 u8 dirty_bitmap_addr[0x40];
2941 u8 hw_available_index[0x10];
2942 u8 hw_used_index[0x10];
2943 u8 reserved_at_160[0xa0];
2944 struct mlx5_ifc_virtio_q_bits virtio_q_context;
2947 struct mlx5_ifc_create_virtq_in_bits {
2948 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2949 struct mlx5_ifc_virtio_net_q_bits virtq;
2952 struct mlx5_ifc_query_virtq_out_bits {
2953 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2954 struct mlx5_ifc_virtio_net_q_bits virtq;
2957 struct mlx5_ifc_flow_hit_aso_bits {
2958 u8 modify_field_select[0x40];
2959 u8 reserved_at_40[0x48];
2961 u8 reserved_at_a0[0x160];
2965 struct mlx5_ifc_create_flow_hit_aso_in_bits {
2966 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2967 struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso;
2970 struct mlx5_ifc_flow_meter_aso_bits {
2971 u8 modify_field_select[0x40];
2972 u8 reserved_at_40[0x48];
2974 u8 reserved_at_a0[0x160];
2975 u8 parameters[0x200];
2978 struct mlx5_ifc_create_flow_meter_aso_in_bits {
2979 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2980 struct mlx5_ifc_flow_meter_aso_bits flow_meter_aso;
2983 struct mlx5_ifc_tcp_window_params_bits {
2990 struct mlx5_ifc_conn_track_aso_bits {
2991 struct mlx5_ifc_tcp_window_params_bits reply_dir; /* End of DW3. */
2992 struct mlx5_ifc_tcp_window_params_bits original_dir; /* End of DW7. */
2993 u8 last_end[0x20]; /* End of DW8. */
2994 u8 last_ack[0x20]; /* End of DW9. */
2995 u8 last_seq[0x20]; /* End of DW10. */
2997 u8 reserved_at_170[0xa];
2999 u8 last_index[0x5]; /* End of DW11. */
3000 u8 reserved_at_180[0x40]; /* End of DW13. */
3001 u8 reply_direction_tcp_scale[0x4];
3002 u8 reply_direction_tcp_close_initiated[0x1];
3003 u8 reply_direction_tcp_liberal_enabled[0x1];
3004 u8 reply_direction_tcp_data_unacked[0x1];
3005 u8 reply_direction_tcp_max_ack[0x1];
3006 u8 reserved_at_1c8[0x8];
3007 u8 original_direction_tcp_scale[0x4];
3008 u8 original_direction_tcp_close_initiated[0x1];
3009 u8 original_direction_tcp_liberal_enabled[0x1];
3010 u8 original_direction_tcp_data_unacked[0x1];
3011 u8 original_direction_tcp_max_ack[0x1];
3012 u8 reserved_at_1d8[0x8]; /* End of DW14. */
3015 u8 freeze_track[0x1];
3016 u8 reserved_at_1e5[0xb];
3017 u8 reserved_at_1f0[0x1];
3018 u8 connection_assured[0x1];
3019 u8 sack_permitted[0x1];
3020 u8 challenged_acked[0x1];
3022 u8 max_ack_window[0x3];
3023 u8 reserved_at_1f8[0x1];
3024 u8 retransmission_counter[0x3];
3025 u8 retranmission_limit_exceeded[0x1];
3026 u8 retranmission_limit[0x3]; /* End of DW15. */
3029 struct mlx5_ifc_conn_track_offload_bits {
3030 u8 modify_field_select[0x40];
3031 u8 reserved_at_40[0x40];
3032 u8 reserved_at_80[0x8];
3033 u8 conn_track_aso_access_pd[0x18];
3034 u8 reserved_at_a0[0x160];
3035 struct mlx5_ifc_conn_track_aso_bits conn_track_aso;
3038 struct mlx5_ifc_create_conn_track_aso_in_bits {
3039 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3040 struct mlx5_ifc_conn_track_offload_bits conn_track_offload;
3043 enum mlx5_access_aso_opc_mod {
3044 ASO_OPC_MOD_IPSEC = 0x0,
3045 ASO_OPC_MOD_CONNECTION_TRACKING = 0x1,
3046 ASO_OPC_MOD_POLICER = 0x2,
3047 ASO_OPC_MOD_RACE_AVOIDANCE = 0x3,
3048 ASO_OPC_MOD_FLOW_HIT = 0x4,
3051 #define ASO_CSEG_DATA_MASK_MODE_OFFSET 30
3053 enum mlx5_aso_data_mask_mode {
3054 BITWISE_64BIT = 0x0,
3055 BYTEWISE_64BYTE = 0x1,
3056 CALCULATED_64BYTE = 0x2,
3059 #define ASO_CSEG_COND_0_OPER_OFFSET 20
3060 #define ASO_CSEG_COND_1_OPER_OFFSET 16
3062 enum mlx5_aso_pre_cond_op {
3063 ASO_OP_ALWAYS_FALSE = 0x0,
3064 ASO_OP_ALWAYS_TRUE = 0x1,
3066 ASO_OP_NOT_EQUAL = 0x3,
3067 ASO_OP_GREATER_OR_EQUAL = 0x4,
3068 ASO_OP_LESSER_OR_EQUAL = 0x5,
3069 ASO_OP_LESSER = 0x6,
3070 ASO_OP_GREATER = 0x7,
3071 ASO_OP_CYCLIC_GREATER = 0x8,
3072 ASO_OP_CYCLIC_LESSER = 0x9,
3075 #define ASO_CSEG_COND_OPER_OFFSET 6
3078 ASO_OPER_LOGICAL_AND = 0x0,
3079 ASO_OPER_LOGICAL_OR = 0x1,
3082 /* ASO WQE CTRL segment. */
3083 struct mlx5_aso_cseg {
3087 uint32_t operand_masks;
3088 uint32_t condition_0_data;
3089 uint32_t condition_0_mask;
3090 uint32_t condition_1_data;
3091 uint32_t condition_1_mask;
3092 uint64_t bitwise_data;
3096 /* A meter data segment - 2 per ASO WQE. */
3097 struct mlx5_aso_mtr_dseg {
3098 uint32_t v_bo_sc_bbog_mm;
3100 * bit 31: valid, 30: bucket overflow, 28-29: start color,
3101 * 27: both buckets on green, 24-25: meter mode.
3106 * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa,
3107 * bit 8-12: cir_exponent, bit 0-7 cir_mantissa.
3112 * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa,
3113 * bit 8-12: eir_exponent, bit 0-7 eir_mantissa.
3119 #define ASO_DSEG_VALID_OFFSET 31
3120 #define ASO_DSEG_BO_OFFSET 30
3121 #define ASO_DSEG_SC_OFFSET 28
3122 #define ASO_DSEG_BBOG_OFFSET 27
3123 #define ASO_DSEG_MTR_MODE 24
3124 #define ASO_DSEG_CBS_EXP_OFFSET 24
3125 #define ASO_DSEG_CBS_MAN_OFFSET 16
3126 #define ASO_DSEG_XIR_EXP_MASK 0x1F
3127 #define ASO_DSEG_XIR_EXP_OFFSET 8
3128 #define ASO_DSEG_EBS_EXP_OFFSET 24
3129 #define ASO_DSEG_EBS_MAN_OFFSET 16
3130 #define ASO_DSEG_EXP_MASK 0x1F
3131 #define ASO_DSEG_MAN_MASK 0xFF
3133 #define MLX5_ASO_WQE_DSEG_SIZE 0x40
3134 #define MLX5_ASO_METERS_PER_WQE 2
3135 #define MLX5_ASO_MTRS_PER_POOL 128
3137 /* ASO WQE data segment. */
3138 struct mlx5_aso_dseg {
3140 uint8_t data[MLX5_ASO_WQE_DSEG_SIZE];
3141 struct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE];
3146 struct mlx5_aso_wqe {
3147 struct mlx5_wqe_cseg general_cseg;
3148 struct mlx5_aso_cseg aso_cseg;
3149 struct mlx5_aso_dseg aso_dseg;
3153 MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
3157 MLX5_QP_ST_RC = 0x0,
3161 MLX5_QP_PM_MIGRATED = 0x3,
3165 MLX5_NON_ZERO_RQ = 0x0,
3168 MLX5_ZERO_LEN_RQ = 0x3,
3171 struct mlx5_ifc_ads_bits {
3174 u8 reserved_at_2[0xe];
3175 u8 pkey_index[0x10];
3176 u8 reserved_at_20[0x8];
3180 u8 ack_timeout[0x5];
3181 u8 reserved_at_45[0x3];
3182 u8 src_addr_index[0x8];
3183 u8 reserved_at_50[0x4];
3186 u8 reserved_at_60[0x4];
3188 u8 flow_label[0x14];
3189 u8 rgid_rip[16][0x8];
3190 u8 reserved_at_100[0x4];
3193 u8 reserved_at_106[0x1];
3201 u8 vhca_port_num[0x8];
3202 u8 rmac_47_32[0x10];
3206 struct mlx5_ifc_qpc_bits {
3208 u8 lag_tx_port_affinity[0x4];
3210 u8 reserved_at_10[0x3];
3212 u8 reserved_at_15[0x1];
3213 u8 req_e2e_credit_mode[0x2];
3214 u8 offload_type[0x4];
3215 u8 end_padding_mode[0x2];
3216 u8 reserved_at_1e[0x2];
3217 u8 wq_signature[0x1];
3218 u8 block_lb_mc[0x1];
3219 u8 atomic_like_write_en[0x1];
3220 u8 latency_sensitive[0x1];
3221 u8 reserved_at_24[0x1];
3222 u8 drain_sigerr[0x1];
3223 u8 reserved_at_26[0x2];
3226 u8 log_msg_max[0x5];
3227 u8 reserved_at_48[0x1];
3228 u8 log_rq_size[0x4];
3229 u8 log_rq_stride[0x3];
3231 u8 log_sq_size[0x4];
3232 u8 reserved_at_55[0x3];
3234 u8 reserved_at_5a[0x1];
3236 u8 ulp_stateless_offload_mode[0x4];
3237 u8 counter_set_id[0x8];
3239 u8 reserved_at_80[0x8];
3240 u8 user_index[0x18];
3241 u8 reserved_at_a0[0x3];
3242 u8 log_page_size[0x5];
3243 u8 remote_qpn[0x18];
3244 struct mlx5_ifc_ads_bits primary_address_path;
3245 struct mlx5_ifc_ads_bits secondary_address_path;
3246 u8 log_ack_req_freq[0x4];
3247 u8 reserved_at_384[0x4];
3248 u8 log_sra_max[0x3];
3249 u8 reserved_at_38b[0x2];
3250 u8 retry_count[0x3];
3252 u8 reserved_at_393[0x1];
3254 u8 cur_rnr_retry[0x3];
3255 u8 cur_retry_count[0x3];
3256 u8 reserved_at_39b[0x5];
3257 u8 reserved_at_3a0[0x20];
3258 u8 reserved_at_3c0[0x8];
3259 u8 next_send_psn[0x18];
3260 u8 reserved_at_3e0[0x8];
3262 u8 reserved_at_400[0x8];
3264 u8 reserved_at_420[0x20];
3265 u8 reserved_at_440[0x8];
3266 u8 last_acked_psn[0x18];
3267 u8 reserved_at_460[0x8];
3269 u8 reserved_at_480[0x8];
3270 u8 log_rra_max[0x3];
3271 u8 reserved_at_48b[0x1];
3272 u8 atomic_mode[0x4];
3276 u8 reserved_at_493[0x1];
3277 u8 page_offset[0x6];
3278 u8 reserved_at_49a[0x3];
3279 u8 cd_slave_receive[0x1];
3280 u8 cd_slave_send[0x1];
3282 u8 reserved_at_4a0[0x3];
3283 u8 min_rnr_nak[0x5];
3284 u8 next_rcv_psn[0x18];
3285 u8 reserved_at_4c0[0x8];
3287 u8 reserved_at_4e0[0x8];
3291 u8 reserved_at_560[0x5];
3293 u8 srqn_rmpn_xrqn[0x18];
3294 u8 reserved_at_580[0x8];
3296 u8 hw_sq_wqebb_counter[0x10];
3297 u8 sw_sq_wqebb_counter[0x10];
3298 u8 hw_rq_counter[0x20];
3299 u8 sw_rq_counter[0x20];
3300 u8 reserved_at_600[0x20];
3301 u8 reserved_at_620[0xf];
3305 u8 dc_access_key[0x40];
3306 u8 reserved_at_680[0x3];
3307 u8 dbr_umem_valid[0x1];
3308 u8 reserved_at_684[0x9c];
3309 u8 dbr_umem_id[0x20];
3312 struct mlx5_ifc_create_qp_out_bits {
3314 u8 reserved_at_8[0x18];
3316 u8 reserved_at_40[0x8];
3318 u8 reserved_at_60[0x20];
3321 struct mlx5_ifc_qpc_extension_bits {
3322 u8 reserved_at_0[0x2];
3324 u8 reserved_at_3[0x5fd];
3328 #pragma GCC diagnostic ignored "-Wpedantic"
3330 struct mlx5_ifc_qpc_pas_list_bits {
3335 #pragma GCC diagnostic ignored "-Wpedantic"
3337 struct mlx5_ifc_qpc_extension_and_pas_list_bits {
3338 struct mlx5_ifc_qpc_extension_bits qpc_data_extension;
3344 #pragma GCC diagnostic ignored "-Wpedantic"
3346 struct mlx5_ifc_create_qp_in_bits {
3349 u8 reserved_at_20[0x10];
3352 u8 reserved_at_41[0x3f];
3353 u8 opt_param_mask[0x20];
3354 u8 reserved_at_a0[0x20];
3355 struct mlx5_ifc_qpc_bits qpc;
3356 u8 wq_umem_offset[0x40];
3357 u8 wq_umem_id[0x20];
3358 u8 wq_umem_valid[0x1];
3359 u8 reserved_at_861[0x1f];
3361 struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list;
3362 struct mlx5_ifc_qpc_extension_and_pas_list_bits
3363 qpc_extension_and_pas_list;
3367 #pragma GCC diagnostic error "-Wpedantic"
3370 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3372 u8 reserved_at_8[0x18];
3374 u8 reserved_at_40[0x40];
3377 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3380 u8 reserved_at_20[0x10];
3382 u8 reserved_at_40[0x8];
3384 u8 reserved_at_60[0x20];
3385 u8 opt_param_mask[0x20];
3386 u8 reserved_at_a0[0x20];
3387 struct mlx5_ifc_qpc_bits qpc;
3388 u8 reserved_at_800[0x80];
3391 struct mlx5_ifc_sqd2rts_qp_out_bits {
3393 u8 reserved_at_8[0x18];
3395 u8 reserved_at_40[0x40];
3398 struct mlx5_ifc_sqd2rts_qp_in_bits {
3401 u8 reserved_at_20[0x10];
3403 u8 reserved_at_40[0x8];
3405 u8 reserved_at_60[0x20];
3406 u8 opt_param_mask[0x20];
3407 u8 reserved_at_a0[0x20];
3408 struct mlx5_ifc_qpc_bits qpc;
3409 u8 reserved_at_800[0x80];
3412 struct mlx5_ifc_rts2rts_qp_out_bits {
3414 u8 reserved_at_8[0x18];
3416 u8 reserved_at_40[0x40];
3419 struct mlx5_ifc_rts2rts_qp_in_bits {
3422 u8 reserved_at_20[0x10];
3424 u8 reserved_at_40[0x8];
3426 u8 reserved_at_60[0x20];
3427 u8 opt_param_mask[0x20];
3428 u8 reserved_at_a0[0x20];
3429 struct mlx5_ifc_qpc_bits qpc;
3430 u8 reserved_at_800[0x80];
3433 struct mlx5_ifc_rtr2rts_qp_out_bits {
3435 u8 reserved_at_8[0x18];
3437 u8 reserved_at_40[0x40];
3440 struct mlx5_ifc_rtr2rts_qp_in_bits {
3443 u8 reserved_at_20[0x10];
3445 u8 reserved_at_40[0x8];
3447 u8 reserved_at_60[0x20];
3448 u8 opt_param_mask[0x20];
3449 u8 reserved_at_a0[0x20];
3450 struct mlx5_ifc_qpc_bits qpc;
3451 u8 reserved_at_800[0x80];
3454 struct mlx5_ifc_rst2init_qp_out_bits {
3456 u8 reserved_at_8[0x18];
3458 u8 reserved_at_40[0x40];
3461 struct mlx5_ifc_rst2init_qp_in_bits {
3464 u8 reserved_at_20[0x10];
3466 u8 reserved_at_40[0x8];
3468 u8 reserved_at_60[0x20];
3469 u8 opt_param_mask[0x20];
3470 u8 reserved_at_a0[0x20];
3471 struct mlx5_ifc_qpc_bits qpc;
3472 u8 reserved_at_800[0x80];
3475 struct mlx5_ifc_init2rtr_qp_out_bits {
3477 u8 reserved_at_8[0x18];
3479 u8 reserved_at_40[0x40];
3482 struct mlx5_ifc_init2rtr_qp_in_bits {
3485 u8 reserved_at_20[0x10];
3487 u8 reserved_at_40[0x8];
3489 u8 reserved_at_60[0x20];
3490 u8 opt_param_mask[0x20];
3491 u8 reserved_at_a0[0x20];
3492 struct mlx5_ifc_qpc_bits qpc;
3493 u8 reserved_at_800[0x80];
3496 struct mlx5_ifc_init2init_qp_out_bits {
3498 u8 reserved_at_8[0x18];
3500 u8 reserved_at_40[0x40];
3503 struct mlx5_ifc_init2init_qp_in_bits {
3506 u8 reserved_at_20[0x10];
3508 u8 reserved_at_40[0x8];
3510 u8 reserved_at_60[0x20];
3511 u8 opt_param_mask[0x20];
3512 u8 reserved_at_a0[0x20];
3513 struct mlx5_ifc_qpc_bits qpc;
3514 u8 reserved_at_800[0x80];
3517 struct mlx5_ifc_dealloc_pd_out_bits {
3519 u8 reserved_0[0x18];
3521 u8 reserved_1[0x40];
3524 struct mlx5_ifc_dealloc_pd_in_bits {
3526 u8 reserved_0[0x10];
3527 u8 reserved_1[0x10];
3531 u8 reserved_3[0x20];
3534 struct mlx5_ifc_alloc_pd_out_bits {
3536 u8 reserved_0[0x18];
3540 u8 reserved_2[0x20];
3543 struct mlx5_ifc_alloc_pd_in_bits {
3545 u8 reserved_0[0x10];
3546 u8 reserved_1[0x10];
3548 u8 reserved_2[0x40];
3552 #pragma GCC diagnostic ignored "-Wpedantic"
3554 struct mlx5_ifc_query_qp_out_bits {
3556 u8 reserved_at_8[0x18];
3558 u8 reserved_at_40[0x40];
3559 u8 opt_param_mask[0x20];
3560 u8 reserved_at_a0[0x20];
3561 struct mlx5_ifc_qpc_bits qpc;
3562 u8 reserved_at_800[0x80];
3566 #pragma GCC diagnostic error "-Wpedantic"
3569 struct mlx5_ifc_query_qp_in_bits {
3571 u8 reserved_at_10[0x10];
3572 u8 reserved_at_20[0x10];
3574 u8 reserved_at_40[0x8];
3576 u8 reserved_at_60[0x20];
3580 MLX5_DATA_RATE = 0x0,
3581 MLX5_WQE_RATE = 0x1,
3584 struct mlx5_ifc_set_pp_rate_limit_context_bits {
3585 u8 rate_limit[0x20];
3586 u8 burst_upper_bound[0x20];
3587 u8 reserved_at_40[0xC];
3589 u8 typical_packet_size[0x10];
3590 u8 reserved_at_60[0x120];
3593 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u
3596 #pragma GCC diagnostic ignored "-Wpedantic"
3598 struct mlx5_ifc_access_register_out_bits {
3600 u8 reserved_at_8[0x18];
3602 u8 reserved_at_40[0x40];
3603 u8 register_data[0][0x20];
3606 struct mlx5_ifc_access_register_in_bits {
3608 u8 reserved_at_10[0x10];
3609 u8 reserved_at_20[0x10];
3611 u8 reserved_at_40[0x10];
3612 u8 register_id[0x10];
3614 u8 register_data[0][0x20];
3617 #pragma GCC diagnostic error "-Wpedantic"
3621 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
3622 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
3626 MLX5_REGISTER_ID_MTUTC = 0x9055,
3627 MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002,
3628 MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003,
3629 MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004,
3630 MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005,
3633 struct mlx5_ifc_register_mtutc_bits {
3634 u8 time_stamp_mode[0x2];
3635 u8 time_stamp_state[0x2];
3636 u8 reserved_at_4[0x18];
3638 u8 freq_adjustment[0x20];
3639 u8 reserved_at_40[0x40];
3642 u8 time_adjustment[0x20];
3645 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0
3646 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1
3648 struct mlx5_ifc_crypto_operational_register_bits {
3649 u8 wrapped_crypto_operational[0x1];
3650 u8 reserved_at_1[0x1b];
3652 u8 reserved_at_20[0x20];
3653 u8 credential[0x140];
3655 u8 reserved_at_280[0x180];
3658 struct mlx5_ifc_crypto_commissioning_register_bits {
3659 u8 token[0x1]; /* TODO: add size after PRM update */
3662 struct mlx5_ifc_import_kek_handle_register_bits {
3663 struct mlx5_ifc_crypto_login_bits crypto_login_object;
3664 struct mlx5_ifc_import_kek_bits import_kek_object;
3665 u8 reserved_at_200[0x4];
3666 u8 write_operation[0x4];
3667 u8 import_kek_id[0x18];
3668 u8 reserved_at_220[0xe0];
3671 struct mlx5_ifc_credential_handle_register_bits {
3672 struct mlx5_ifc_crypto_login_bits crypto_login_object;
3673 struct mlx5_ifc_credential_bits credential_object;
3674 u8 reserved_at_200[0x4];
3675 u8 write_operation[0x4];
3676 u8 credential_id[0x18];
3677 u8 reserved_at_220[0xe0];
3681 MLX5_REGISTER_ADD_OPERATION = 0x1,
3682 MLX5_REGISTER_DELETE_OPERATION = 0x2,
3685 struct mlx5_ifc_parse_graph_arc_bits {
3686 u8 start_inner_tunnel[0x1];
3687 u8 reserved_at_1[0x7];
3688 u8 arc_parse_graph_node[0x8];
3689 u8 compare_condition_value[0x10];
3690 u8 parse_graph_node_handle[0x20];
3691 u8 reserved_at_40[0x40];
3694 struct mlx5_ifc_parse_graph_flow_match_sample_bits {
3695 u8 flow_match_sample_en[0x1];
3696 u8 reserved_at_1[0x3];
3697 u8 flow_match_sample_offset_mode[0x4];
3698 u8 reserved_at_5[0x8];
3699 u8 flow_match_sample_field_offset[0x10];
3700 u8 reserved_at_32[0x4];
3701 u8 flow_match_sample_field_offset_shift[0x4];
3702 u8 flow_match_sample_field_base_offset[0x8];
3703 u8 reserved_at_48[0xd];
3704 u8 flow_match_sample_tunnel_mode[0x3];
3705 u8 flow_match_sample_field_offset_mask[0x20];
3706 u8 flow_match_sample_field_id[0x20];
3709 struct mlx5_ifc_parse_graph_flex_bits {
3710 u8 modify_field_select[0x40];
3711 u8 reserved_at_64[0x20];
3712 u8 header_length_base_value[0x10];
3713 u8 reserved_at_112[0x4];
3714 u8 header_length_field_shift[0x4];
3715 u8 reserved_at_120[0x4];
3716 u8 header_length_mode[0x4];
3717 u8 header_length_field_offset[0x10];
3718 u8 next_header_field_offset[0x10];
3719 u8 reserved_at_160[0x1b];
3720 u8 next_header_field_size[0x5];
3721 u8 header_length_field_mask[0x20];
3722 u8 reserved_at_224[0x20];
3723 struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8];
3724 struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8];
3725 struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8];
3728 struct mlx5_ifc_create_flex_parser_in_bits {
3729 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3730 struct mlx5_ifc_parse_graph_flex_bits flex;
3733 struct mlx5_ifc_create_flex_parser_out_bits {
3734 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3735 struct mlx5_ifc_parse_graph_flex_bits flex;
3738 struct mlx5_ifc_parse_graph_flex_out_bits {
3740 u8 reserved_at_8[0x18];
3742 u8 reserved_at_40[0x40];
3743 struct mlx5_ifc_parse_graph_flex_bits capability;
3746 struct regexp_params_field_select_bits {
3747 u8 reserved_at_0[0x1d];
3749 u8 stop_engine[0x1];
3750 u8 reserved_at_1f[0x1];
3753 struct mlx5_ifc_regexp_params_bits {
3754 u8 reserved_at_0[0x1f];
3755 u8 stop_engine[0x1];
3756 u8 reserved_at_20[0x60];
3759 u8 rof_mkey_va[0x40];
3760 u8 reserved_at_100[0x80];
3763 struct mlx5_ifc_set_regexp_params_in_bits {
3766 u8 reserved_at_20[0x10];
3768 u8 reserved_at_40[0x18];
3770 struct regexp_params_field_select_bits field_select;
3771 struct mlx5_ifc_regexp_params_bits regexp_params;
3774 struct mlx5_ifc_set_regexp_params_out_bits {
3776 u8 reserved_at_8[0x18];
3778 u8 reserved_at_18[0x40];
3781 struct mlx5_ifc_query_regexp_params_in_bits {
3784 u8 reserved_at_20[0x10];
3786 u8 reserved_at_40[0x18];
3791 struct mlx5_ifc_query_regexp_params_out_bits {
3793 u8 reserved_at_8[0x18];
3796 struct mlx5_ifc_regexp_params_bits regexp_params;
3799 struct mlx5_ifc_set_regexp_register_in_bits {
3802 u8 reserved_at_20[0x10];
3804 u8 reserved_at_40[0x18];
3806 u8 register_address[0x20];
3807 u8 register_data[0x20];
3811 struct mlx5_ifc_set_regexp_register_out_bits {
3813 u8 reserved_at_8[0x18];
3818 struct mlx5_ifc_query_regexp_register_in_bits {
3821 u8 reserved_at_20[0x10];
3823 u8 reserved_at_40[0x18];
3825 u8 register_address[0x20];
3828 struct mlx5_ifc_query_regexp_register_out_bits {
3830 u8 reserved_at_8[0x18];
3833 u8 register_data[0x20];
3836 /* Queue counters. */
3837 struct mlx5_ifc_alloc_q_counter_out_bits {
3839 u8 reserved_at_8[0x18];
3841 u8 reserved_at_40[0x18];
3842 u8 counter_set_id[0x8];
3843 u8 reserved_at_60[0x20];
3846 struct mlx5_ifc_alloc_q_counter_in_bits {
3849 u8 reserved_at_20[0x10];
3851 u8 reserved_at_40[0x40];
3854 struct mlx5_ifc_query_q_counter_out_bits {
3856 u8 reserved_at_8[0x18];
3858 u8 reserved_at_40[0x40];
3859 u8 rx_write_requests[0x20];
3860 u8 reserved_at_a0[0x20];
3861 u8 rx_read_requests[0x20];
3862 u8 reserved_at_e0[0x20];
3863 u8 rx_atomic_requests[0x20];
3864 u8 reserved_at_120[0x20];
3865 u8 rx_dct_connect[0x20];
3866 u8 reserved_at_160[0x20];
3867 u8 out_of_buffer[0x20];
3868 u8 reserved_at_1a0[0x20];
3869 u8 out_of_sequence[0x20];
3870 u8 reserved_at_1e0[0x20];
3871 u8 duplicate_request[0x20];
3872 u8 reserved_at_220[0x20];
3873 u8 rnr_nak_retry_err[0x20];
3874 u8 reserved_at_260[0x20];
3875 u8 packet_seq_err[0x20];
3876 u8 reserved_at_2a0[0x20];
3877 u8 implied_nak_seq_err[0x20];
3878 u8 reserved_at_2e0[0x20];
3879 u8 local_ack_timeout_err[0x20];
3880 u8 reserved_at_320[0xa0];
3881 u8 resp_local_length_error[0x20];
3882 u8 req_local_length_error[0x20];
3883 u8 resp_local_qp_error[0x20];
3884 u8 local_operation_error[0x20];
3885 u8 resp_local_protection[0x20];
3886 u8 req_local_protection[0x20];
3887 u8 resp_cqe_error[0x20];
3888 u8 req_cqe_error[0x20];
3889 u8 req_mw_binding[0x20];
3890 u8 req_bad_response[0x20];
3891 u8 req_remote_invalid_request[0x20];
3892 u8 resp_remote_invalid_request[0x20];
3893 u8 req_remote_access_errors[0x20];
3894 u8 resp_remote_access_errors[0x20];
3895 u8 req_remote_operation_errors[0x20];
3896 u8 req_transport_retries_exceeded[0x20];
3897 u8 cq_overflow[0x20];
3898 u8 resp_cqe_flush_error[0x20];
3899 u8 req_cqe_flush_error[0x20];
3900 u8 reserved_at_620[0x1e0];
3903 struct mlx5_ifc_query_q_counter_in_bits {
3906 u8 reserved_at_20[0x10];
3908 u8 reserved_at_40[0x80];
3910 u8 reserved_at_c1[0x1f];
3911 u8 reserved_at_e0[0x18];
3912 u8 counter_set_id[0x8];
3915 /* CQE format mask. */
3916 #define MLX5E_CQE_FORMAT_MASK 0xc
3919 #define MLX5_OPC_MOD_MPW 0x01
3921 /* Compressed Rx CQE structure. */
3922 struct mlx5_mini_cqe8 {
3924 uint32_t rx_hash_result;
3928 uint16_t flow_tag_high;
3934 uint16_t stride_idx;
3937 uint16_t wqe_counter;
3938 uint8_t s_wqe_opcode;
3943 uint32_t byte_cnt_flow;
3948 /* Mini CQE responder format. */
3950 MLX5_CQE_RESP_FORMAT_HASH = 0x0,
3951 MLX5_CQE_RESP_FORMAT_CSUM = 0x1,
3952 MLX5_CQE_RESP_FORMAT_FTAG_STRIDX = 0x2,
3953 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3,
3954 MLX5_CQE_RESP_FORMAT_L34H_STRIDX = 0x4,
3957 /* srTCM PRM flow meter parameters. */
3959 MLX5_FLOW_COLOR_RED = 0,
3960 MLX5_FLOW_COLOR_YELLOW,
3961 MLX5_FLOW_COLOR_GREEN,
3962 MLX5_FLOW_COLOR_UNDEFINED,
3965 /* Maximum value of srTCM & trTCM metering parameters. */
3966 #define MLX5_SRTCM_XBS_MAX (0xFF * (1ULL << 0x1F))
3967 #define MLX5_SRTCM_XIR_MAX (8 * (1ULL << 30) * 0xFF)
3969 /* The bits meter color use. */
3970 #define MLX5_MTR_COLOR_BITS 8
3972 /* The bit size of one register. */
3973 #define MLX5_REG_BITS 32
3975 /* Idle bits for non-color usage in color register. */
3976 #define MLX5_MTR_IDLE_BITS_IN_COLOR_REG (MLX5_REG_BITS - MLX5_MTR_COLOR_BITS)
3978 /* Length mode of dynamic flex parser graph node. */
3979 enum mlx5_parse_graph_node_len_mode {
3980 MLX5_GRAPH_NODE_LEN_FIXED = 0x0,
3981 MLX5_GRAPH_NODE_LEN_FIELD = 0x1,
3982 MLX5_GRAPH_NODE_LEN_BITMASK = 0x2,
3985 /* Offset mode of the samples of flex parser. */
3986 enum mlx5_parse_graph_flow_match_sample_offset_mode {
3987 MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0,
3988 MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1,
3989 MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2,
3992 enum mlx5_parse_graph_flow_match_sample_tunnel_mode {
3993 MLX5_GRAPH_SAMPLE_TUNNEL_OUTER = 0x0,
3994 MLX5_GRAPH_SAMPLE_TUNNEL_INNER = 0x1,
3995 MLX5_GRAPH_SAMPLE_TUNNEL_FIRST = 0x2
3998 /* Node index for an input / output arc of the flex parser graph. */
3999 enum mlx5_parse_graph_arc_node_index {
4000 MLX5_GRAPH_ARC_NODE_NULL = 0x0,
4001 MLX5_GRAPH_ARC_NODE_HEAD = 0x1,
4002 MLX5_GRAPH_ARC_NODE_MAC = 0x2,
4003 MLX5_GRAPH_ARC_NODE_IP = 0x3,
4004 MLX5_GRAPH_ARC_NODE_GRE = 0x4,
4005 MLX5_GRAPH_ARC_NODE_UDP = 0x5,
4006 MLX5_GRAPH_ARC_NODE_MPLS = 0x6,
4007 MLX5_GRAPH_ARC_NODE_TCP = 0x7,
4008 MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8,
4009 MLX5_GRAPH_ARC_NODE_GENEVE = 0x9,
4010 MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa,
4011 MLX5_GRAPH_ARC_NODE_IPV4 = 0xb,
4012 MLX5_GRAPH_ARC_NODE_IPV6 = 0xc,
4013 MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f,
4016 #define MLX5_PARSE_GRAPH_FLOW_SAMPLE_MAX 8
4017 #define MLX5_PARSE_GRAPH_IN_ARC_MAX 8
4018 #define MLX5_PARSE_GRAPH_OUT_ARC_MAX 8
4021 * Convert a user mark to flow mark.
4024 * Mark value to convert.
4027 * Converted mark value.
4029 static inline uint32_t
4030 mlx5_flow_mark_set(uint32_t val)
4035 * Add one to the user value to differentiate un-marked flows from
4036 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
4037 * remains untouched.
4039 if (val != MLX5_FLOW_MARK_DEFAULT)
4041 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
4043 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
4044 * word, byte-swapped by the kernel on little-endian systems. In this
4045 * case, left-shifting the resulting big-endian value ensures the
4046 * least significant 24 bits are retained when converting it back.
4048 ret = rte_cpu_to_be_32(val) >> 8;
4056 * Convert a mark to user mark.
4059 * Mark value to convert.
4062 * Converted mark value.
4064 static inline uint32_t
4065 mlx5_flow_mark_get(uint32_t val)
4068 * Subtract one from the retrieved value. It was added by
4069 * mlx5_flow_mark_set() to distinguish unmarked flows.
4071 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
4072 return (val >> 8) - 1;
4079 * Convert a timestamp format to configure settings in the queue context.
4082 * timestamp format supported by the queue.
4085 * Converted timstamp format settings.
4087 static inline uint32_t
4088 mlx5_ts_format_conv(uint32_t ts_format)
4090 return ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ?
4091 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
4092 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
4095 #endif /* RTE_PMD_MLX5_PRM_H_ */