drivers/common/mlx5/mlx5_prm.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2016 6WIND S.A.
   3  * Copyright 2016 Mellanox Technologies, Ltd
   4  */
   5
   6 #ifndef RTE_PMD_MLX5_PRM_H_
   7 #define RTE_PMD_MLX5_PRM_H_
   8
   9 #include <unistd.h>
  10
  11 #include <rte_vect.h>
  12 #include <rte_byteorder.h>
  13
  14 #include <mlx5_glue.h>
  15 #include "mlx5_autoconf.h"
  16
  17 /* RSS hash key size. */
  18 #define MLX5_RSS_HASH_KEY_LEN 40
  19
  20 /* Get CQE owner bit. */
  21 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
  22
  23 /* Get CQE format. */
  24 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
  25
  26 /* Get CQE opcode. */
  27 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
  28
  29 /* Get CQE solicited event. */
  30 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
  31
  32 /* Invalidate a CQE. */
  33 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
  34
  35 /* Hardware index widths. */
  36 #define MLX5_CQ_INDEX_WIDTH 24
  37 #define MLX5_WQ_INDEX_WIDTH 16
  38
  39 /* WQE Segment sizes in bytes. */
  40 #define MLX5_WSEG_SIZE 16u
  41 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
  42 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
  43 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
  44
  45 /* WQE/WQEBB size in bytes. */
  46 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
  47
  48 /*
  49  * Max size of a WQE session.
  50  * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
  51  * the WQE size field in Control Segment is 6 bits wide.
  52  */
  53 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
  54
  55 /*
  56  * Default minimum number of Tx queues for inlining packets.
  57  * If there are less queues as specified we assume we have
  58  * no enough CPU resources (cycles) to perform inlining,
  59  * the PCIe throughput is not supposed as bottleneck and
  60  * inlining is disabled.
  61  */
  62 #define MLX5_INLINE_MAX_TXQS 8u
  63 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
  64
  65 /*
  66  * Default packet length threshold to be inlined with
  67  * enhanced MPW. If packet length exceeds the threshold
  68  * the data are not inlined. Should be aligned in WQEBB
  69  * boundary with accounting the title Control and Ethernet
  70  * segments.
  71  */
  72 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
  73                                   MLX5_DSEG_MIN_INLINE_SIZE)
  74 /*
  75  * Maximal inline data length sent with enhanced MPW.
  76  * Is based on maximal WQE size.
  77  */
  78 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
  79                                   MLX5_WQE_CSEG_SIZE - \
  80                                   MLX5_WQE_ESEG_SIZE - \
  81                                   MLX5_WQE_DSEG_SIZE + \
  82                                   MLX5_DSEG_MIN_INLINE_SIZE)
  83 /*
  84  * Minimal amount of packets to be sent with EMPW.
  85  * This limits the minimal required size of sent EMPW.
  86  * If there are no enough resources to built minimal
  87  * EMPW the sending loop exits.
  88  */
  89 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
  90 /*
  91  * Maximal amount of packets to be sent with EMPW.
  92  * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
  93  * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
  94  * without CQE generation request, being multiplied by
  95  * MLX5_TX_COMP_MAX_CQE it may cause significant latency
  96  * in tx burst routine at the moment of freeing multiple mbufs.
  97  */
  98 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
  99 #define MLX5_MPW_MAX_PACKETS 6
 100 #define MLX5_MPW_INLINE_MAX_PACKETS 6
 101
 102 /*
 103  * Default packet length threshold to be inlined with
 104  * ordinary SEND. Inlining saves the MR key search
 105  * and extra PCIe data fetch transaction, but eats the
 106  * CPU cycles.
 107  */
 108 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
 109                                   MLX5_ESEG_MIN_INLINE_SIZE - \
 110                                   MLX5_WQE_CSEG_SIZE - \
 111                                   MLX5_WQE_ESEG_SIZE - \
 112                                   MLX5_WQE_DSEG_SIZE)
 113 /*
 114  * Maximal inline data length sent with ordinary SEND.
 115  * Is based on maximal WQE size.
 116  */
 117 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
 118                                   MLX5_WQE_CSEG_SIZE - \
 119                                   MLX5_WQE_ESEG_SIZE - \
 120                                   MLX5_WQE_DSEG_SIZE + \
 121                                   MLX5_ESEG_MIN_INLINE_SIZE)
 122
 123 /* Missed in mlx5dv.h, should define here. */
 124 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW
 125 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
 126 #endif
 127
 128 #ifndef HAVE_MLX5_OPCODE_SEND_EN
 129 #define MLX5_OPCODE_SEND_EN 0x17u
 130 #endif
 131
 132 #ifndef HAVE_MLX5_OPCODE_WAIT
 133 #define MLX5_OPCODE_WAIT 0x0fu
 134 #endif
 135
 136 #ifndef HAVE_MLX5_OPCODE_ACCESS_ASO
 137 #define MLX5_OPCODE_ACCESS_ASO 0x2du
 138 #endif
 139
 140 /* CQE value to inform that VLAN is stripped. */
 141 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
 142
 143 /* IPv4 options. */
 144 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
 145
 146 /* IPv6 packet. */
 147 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
 148
 149 /* IPv4 packet. */
 150 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
 151
 152 /* TCP packet. */
 153 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
 154
 155 /* UDP packet. */
 156 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
 157
 158 /* IP is fragmented. */
 159 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
 160
 161 /* L2 header is valid. */
 162 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
 163
 164 /* L3 header is valid. */
 165 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
 166
 167 /* L4 header is valid. */
 168 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
 169
 170 /* Outer packet, 0 IPv4, 1 IPv6. */
 171 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
 172
 173 /* Tunnel packet bit in the CQE. */
 174 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
 175
 176 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
 177 #define MLX5_CQE_LRO_PUSH_MASK 0x40
 178
 179 /* Mask for L4 type in the CQE hdr_type_etc field. */
 180 #define MLX5_CQE_L4_TYPE_MASK 0x70
 181
 182 /* The bit index of L4 type in CQE hdr_type_etc field. */
 183 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
 184
 185 /* L4 type to indicate TCP packet without acknowledgment. */
 186 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
 187
 188 /* L4 type to indicate TCP packet with acknowledgment. */
 189 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
 190
 191 /* Inner L3 checksum offload (Tunneled packets only). */
 192 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
 193
 194 /* Inner L4 checksum offload (Tunneled packets only). */
 195 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
 196
 197 /* Outer L4 type is TCP. */
 198 #define MLX5_ETH_WQE_L4_OUTER_TCP  (0u << 5)
 199
 200 /* Outer L4 type is UDP. */
 201 #define MLX5_ETH_WQE_L4_OUTER_UDP  (1u << 5)
 202
 203 /* Outer L3 type is IPV4. */
 204 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
 205
 206 /* Outer L3 type is IPV6. */
 207 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
 208
 209 /* Inner L4 type is TCP. */
 210 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
 211
 212 /* Inner L4 type is UDP. */
 213 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
 214
 215 /* Inner L3 type is IPV4. */
 216 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
 217
 218 /* Inner L3 type is IPV6. */
 219 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
 220
 221 /* VLAN insertion flag. */
 222 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
 223
 224 /* Data inline segment flag. */
 225 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
 226
 227 /* Is flow mark valid. */
 228 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
 229 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
 230 #else
 231 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
 232 #endif
 233
 234 /* INVALID is used by packets matching no flow rules. */
 235 #define MLX5_FLOW_MARK_INVALID 0
 236
 237 /* Maximum allowed value to mark a packet. */
 238 #define MLX5_FLOW_MARK_MAX 0xfffff0
 239
 240 /* Default mark value used when none is provided. */
 241 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
 242
 243 /* Default mark mask for metadata legacy mode. */
 244 #define MLX5_FLOW_MARK_MASK 0xffffff
 245
 246 /* Byte length mask when mark is enable in miniCQE */
 247 #define MLX5_LEN_WITH_MARK_MASK 0xffffff00
 248
 249 /* Maximum number of DS in WQE. Limited by 6-bit field. */
 250 #define MLX5_DSEG_MAX 63
 251
 252 /* The completion mode offset in the WQE control segment line 2. */
 253 #define MLX5_COMP_MODE_OFFSET 2
 254
 255 /* Amount of data bytes in minimal inline data segment. */
 256 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
 257
 258 /* Amount of data bytes in minimal inline eth segment. */
 259 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
 260
 261 /* Amount of data bytes after eth data segment. */
 262 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
 263
 264 /* The maximum log value of segments per RQ WQE. */
 265 #define MLX5_MAX_LOG_RQ_SEGS 5u
 266
 267 /* The alignment needed for WQ buffer. */
 268 #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size()
 269
 270 /* The alignment needed for CQ buffer. */
 271 #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size()
 272
 273 /* Completion mode. */
 274 enum mlx5_completion_mode {
 275         MLX5_COMP_ONLY_ERR = 0x0,
 276         MLX5_COMP_ONLY_FIRST_ERR = 0x1,
 277         MLX5_COMP_ALWAYS = 0x2,
 278         MLX5_COMP_CQE_AND_EQE = 0x3,
 279 };
 280
 281 /* MPW mode. */
 282 enum mlx5_mpw_mode {
 283         MLX5_MPW_DISABLED,
 284         MLX5_MPW,
 285         MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
 286 };
 287
 288 /* WQE Control segment. */
 289 struct mlx5_wqe_cseg {
 290         uint32_t opcode;
 291         uint32_t sq_ds;
 292         uint32_t flags;
 293         uint32_t misc;
 294 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
 295
 296 /*
 297  * WQE CSEG opcode field size is 32 bits, divided:
 298  * Bits 31:24 OPC_MOD
 299  * Bits 23:8 wqe_index
 300  * Bits 7:0 OPCODE
 301  */
 302 #define WQE_CSEG_OPC_MOD_OFFSET         24
 303 #define WQE_CSEG_WQE_INDEX_OFFSET        8
 304
 305 /* Header of data segment. Minimal size Data Segment */
 306 struct mlx5_wqe_dseg {
 307         uint32_t bcount;
 308         union {
 309                 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
 310                 struct {
 311                         uint32_t lkey;
 312                         uint64_t pbuf;
 313                 } __rte_packed;
 314         };
 315 } __rte_packed;
 316
 317 /* Subset of struct WQE Ethernet Segment. */
 318 struct mlx5_wqe_eseg {
 319         union {
 320                 struct {
 321                         uint32_t swp_offs;
 322                         uint8_t cs_flags;
 323                         uint8_t swp_flags;
 324                         uint16_t mss;
 325                         uint32_t metadata;
 326                         uint16_t inline_hdr_sz;
 327                         union {
 328                                 uint16_t inline_data;
 329                                 uint16_t vlan_tag;
 330                         };
 331                 } __rte_packed;
 332                 struct {
 333                         uint32_t offsets;
 334                         uint32_t flags;
 335                         uint32_t flow_metadata;
 336                         uint32_t inline_hdr;
 337                 } __rte_packed;
 338         };
 339 } __rte_packed;
 340
 341 struct mlx5_wqe_qseg {
 342         uint32_t reserved0;
 343         uint32_t reserved1;
 344         uint32_t max_index;
 345         uint32_t qpn_cqn;
 346 } __rte_packed;
 347
 348 /* The title WQEBB, header of WQE. */
 349 struct mlx5_wqe {
 350         union {
 351                 struct mlx5_wqe_cseg cseg;
 352                 uint32_t ctrl[4];
 353         };
 354         struct mlx5_wqe_eseg eseg;
 355         union {
 356                 struct mlx5_wqe_dseg dseg[2];
 357                 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
 358         };
 359 } __rte_packed;
 360
 361 /* WQE for Multi-Packet RQ. */
 362 struct mlx5_wqe_mprq {
 363         struct mlx5_wqe_srq_next_seg next_seg;
 364         struct mlx5_wqe_data_seg dseg;
 365 };
 366
 367 #define MLX5_MPRQ_LEN_MASK 0x000ffff
 368 #define MLX5_MPRQ_LEN_SHIFT 0
 369 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
 370 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
 371 #define MLX5_MPRQ_FILLER_MASK 0x80000000
 372 #define MLX5_MPRQ_FILLER_SHIFT 31
 373
 374 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
 375
 376 /* CQ element structure - should be equal to the cache line size */
 377 struct mlx5_cqe {
 378 #if (RTE_CACHE_LINE_SIZE == 128)
 379         uint8_t padding[64];
 380 #endif
 381         uint8_t pkt_info;
 382         uint8_t rsvd0;
 383         uint16_t wqe_id;
 384         uint8_t lro_tcppsh_abort_dupack;
 385         uint8_t lro_min_ttl;
 386         uint16_t lro_tcp_win;
 387         uint32_t lro_ack_seq_num;
 388         uint32_t rx_hash_res;
 389         uint8_t rx_hash_type;
 390         uint8_t rsvd1[3];
 391         uint16_t csum;
 392         uint8_t rsvd2[6];
 393         uint16_t hdr_type_etc;
 394         uint16_t vlan_info;
 395         uint8_t lro_num_seg;
 396         uint8_t rsvd3[3];
 397         uint32_t flow_table_metadata;
 398         uint8_t rsvd4[4];
 399         uint32_t byte_cnt;
 400         uint64_t timestamp;
 401         uint32_t sop_drop_qpn;
 402         uint16_t wqe_counter;
 403         uint8_t rsvd5;
 404         uint8_t op_own;
 405 };
 406
 407 struct mlx5_cqe_ts {
 408         uint64_t timestamp;
 409         uint32_t sop_drop_qpn;
 410         uint16_t wqe_counter;
 411         uint8_t rsvd5;
 412         uint8_t op_own;
 413 };
 414
 415 struct mlx5_wqe_rseg {
 416         uint64_t raddr;
 417         uint32_t rkey;
 418         uint32_t reserved;
 419 } __rte_packed;
 420
 421 #define MLX5_UMRC_IF_OFFSET 31u
 422 #define MLX5_UMRC_KO_OFFSET 16u
 423 #define MLX5_UMRC_TO_BS_OFFSET 0u
 424
 425 struct mlx5_wqe_umr_cseg {
 426         uint32_t if_cf_toe_cq_res;
 427         uint32_t ko_to_bs;
 428         uint64_t mkey_mask;
 429         uint32_t rsvd1[8];
 430 } __rte_packed;
 431
 432 struct mlx5_wqe_mkey_cseg {
 433         uint32_t fr_res_af_sf;
 434         uint32_t qpn_mkey;
 435         uint32_t reserved2;
 436         uint32_t flags_pd;
 437         uint64_t start_addr;
 438         uint64_t len;
 439         uint32_t bsf_octword_size;
 440         uint32_t reserved3[4];
 441         uint32_t translations_octword_size;
 442         uint32_t res4_lps;
 443         uint32_t reserved;
 444 } __rte_packed;
 445
 446 enum {
 447         MLX5_BSF_SIZE_16B = 0x0,
 448         MLX5_BSF_SIZE_32B = 0x1,
 449         MLX5_BSF_SIZE_64B = 0x2,
 450         MLX5_BSF_SIZE_128B = 0x3,
 451 };
 452
 453 enum {
 454         MLX5_BSF_P_TYPE_SIGNATURE = 0x0,
 455         MLX5_BSF_P_TYPE_CRYPTO = 0x1,
 456 };
 457
 458 enum {
 459         MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0,
 460         MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1,
 461         MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2,
 462         MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3,
 463 };
 464
 465 enum {
 466         MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0,
 467 };
 468
 469 enum {
 470         MLX5_BLOCK_SIZE_512B    = 0x1,
 471         MLX5_BLOCK_SIZE_520B    = 0x2,
 472         MLX5_BLOCK_SIZE_4096B   = 0x3,
 473         MLX5_BLOCK_SIZE_4160B   = 0x4,
 474         MLX5_BLOCK_SIZE_1MB     = 0x5,
 475         MLX5_BLOCK_SIZE_4048B   = 0x6,
 476 };
 477
 478 #define MLX5_BSF_SIZE_OFFSET            30
 479 #define MLX5_BSF_P_TYPE_OFFSET          24
 480 #define MLX5_ENCRYPTION_ORDER_OFFSET    16
 481 #define MLX5_BLOCK_SIZE_OFFSET          24
 482
 483 struct mlx5_wqe_umr_bsf_seg {
 484         /*
 485          * bs_bpt_eo_es contains:
 486          * bs   bsf_size                2 bits at MLX5_BSF_SIZE_OFFSET
 487          * bpt  bsf_p_type              2 bits at MLX5_BSF_P_TYPE_OFFSET
 488          * eo   encryption_order        4 bits at MLX5_ENCRYPTION_ORDER_OFFSET
 489          * es   encryption_standard     4 bits at offset 0
 490          */
 491         uint32_t bs_bpt_eo_es;
 492         uint32_t raw_data_size;
 493         /*
 494          * bsp_res contains:
 495          * bsp  crypto_block_size_pointer       8 bits at MLX5_BLOCK_SIZE_OFFSET
 496          * res  reserved 24 bits
 497          */
 498         uint32_t bsp_res;
 499         uint32_t reserved0;
 500         uint8_t xts_initial_tweak[16];
 501         /*
 502          * res_dp contains:
 503          * res  reserved 8 bits
 504          * dp   dek_pointer             24 bits at offset 0
 505          */
 506         uint32_t res_dp;
 507         uint32_t reserved1;
 508         uint64_t keytag;
 509         uint32_t reserved2[4];
 510 } __rte_packed;
 511
 512 #ifdef PEDANTIC
 513 #pragma GCC diagnostic ignored "-Wpedantic"
 514 #endif
 515
 516 struct mlx5_umr_wqe {
 517         struct mlx5_wqe_cseg ctr;
 518         struct mlx5_wqe_umr_cseg ucseg;
 519         struct mlx5_wqe_mkey_cseg mkc;
 520         union {
 521                 struct mlx5_wqe_dseg kseg[0];
 522                 struct mlx5_wqe_umr_bsf_seg bsf[0];
 523         };
 524 } __rte_packed;
 525
 526 struct mlx5_rdma_write_wqe {
 527         struct mlx5_wqe_cseg ctr;
 528         struct mlx5_wqe_rseg rseg;
 529         struct mlx5_wqe_dseg dseg[0];
 530 } __rte_packed;
 531
 532 #ifdef PEDANTIC
 533 #pragma GCC diagnostic error "-Wpedantic"
 534 #endif
 535
 536 /* GGA */
 537 /* MMO metadata segment */
 538
 539 #define MLX5_OPCODE_MMO 0x2fu
 540 #define MLX5_OPC_MOD_MMO_REGEX 0x4u
 541 #define MLX5_OPC_MOD_MMO_COMP 0x2u
 542 #define MLX5_OPC_MOD_MMO_DECOMP 0x3u
 543 #define MLX5_OPC_MOD_MMO_DMA 0x1u
 544
 545 #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u
 546 #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u
 547 #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u
 548 #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u
 549 #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS)
 550 #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u
 551 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u
 552 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u
 553
 554 struct mlx5_wqe_metadata_seg {
 555         uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */
 556         uint32_t lkey;
 557         uint64_t addr;
 558 };
 559
 560 struct mlx5_gga_wqe {
 561         uint32_t opcode;
 562         uint32_t sq_ds;
 563         uint32_t flags;
 564         uint32_t gga_ctrl1;  /* ws 12-15, bs 16-19, dyns 20-23. */
 565         uint32_t gga_ctrl2;
 566         uint32_t opaque_lkey;
 567         uint64_t opaque_vaddr;
 568         struct mlx5_wqe_dseg gather;
 569         struct mlx5_wqe_dseg scatter;
 570 } __rte_packed;
 571
 572 struct mlx5_gga_compress_opaque {
 573         uint32_t syndrom;
 574         uint32_t reserved0;
 575         uint32_t scattered_length;
 576         uint32_t gathered_length;
 577         uint64_t scatter_crc;
 578         uint64_t gather_crc;
 579         uint32_t crc32;
 580         uint32_t adler32;
 581         uint8_t reserved1[216];
 582 } __rte_packed;
 583
 584 struct mlx5_ifc_regexp_mmo_control_bits {
 585         uint8_t reserved_at_31[0x2];
 586         uint8_t le[0x1];
 587         uint8_t reserved_at_28[0x1];
 588         uint8_t subset_id_0[0xc];
 589         uint8_t reserved_at_16[0x4];
 590         uint8_t subset_id_1[0xc];
 591         uint8_t ctrl[0x4];
 592         uint8_t subset_id_2[0xc];
 593         uint8_t reserved_at_16_1[0x4];
 594         uint8_t subset_id_3[0xc];
 595 };
 596
 597 struct mlx5_ifc_regexp_metadata_bits {
 598         uint8_t rof_version[0x10];
 599         uint8_t latency_count[0x10];
 600         uint8_t instruction_count[0x10];
 601         uint8_t primary_thread_count[0x10];
 602         uint8_t match_count[0x8];
 603         uint8_t detected_match_count[0x8];
 604         uint8_t status[0x10];
 605         uint8_t job_id[0x20];
 606         uint8_t reserved[0x80];
 607 };
 608
 609 struct mlx5_ifc_regexp_match_tuple_bits {
 610         uint8_t length[0x10];
 611         uint8_t start_ptr[0x10];
 612         uint8_t rule_id[0x20];
 613 };
 614
 615 /* Adding direct verbs to data-path. */
 616
 617 /* CQ sequence number mask. */
 618 #define MLX5_CQ_SQN_MASK 0x3
 619
 620 /* CQ sequence number index. */
 621 #define MLX5_CQ_SQN_OFFSET 28
 622
 623 /* CQ doorbell index mask. */
 624 #define MLX5_CI_MASK 0xffffff
 625
 626 /* CQ doorbell offset. */
 627 #define MLX5_CQ_ARM_DB 1
 628
 629 /* CQ doorbell offset*/
 630 #define MLX5_CQ_DOORBELL 0x20
 631
 632 /* CQE format value. */
 633 #define MLX5_COMPRESSED 0x3
 634
 635 /* CQ doorbell cmd types. */
 636 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24)
 637 #define MLX5_CQ_DBR_CMD_ALL (0 << 24)
 638
 639 /* Action type of header modification. */
 640 enum {
 641         MLX5_MODIFICATION_TYPE_SET = 0x1,
 642         MLX5_MODIFICATION_TYPE_ADD = 0x2,
 643         MLX5_MODIFICATION_TYPE_COPY = 0x3,
 644 };
 645
 646 /* The field of packet to be modified. */
 647 enum mlx5_modification_field {
 648         MLX5_MODI_OUT_NONE = -1,
 649         MLX5_MODI_OUT_SMAC_47_16 = 1,
 650         MLX5_MODI_OUT_SMAC_15_0,
 651         MLX5_MODI_OUT_ETHERTYPE,
 652         MLX5_MODI_OUT_DMAC_47_16,
 653         MLX5_MODI_OUT_DMAC_15_0,
 654         MLX5_MODI_OUT_IP_DSCP,
 655         MLX5_MODI_OUT_TCP_FLAGS,
 656         MLX5_MODI_OUT_TCP_SPORT,
 657         MLX5_MODI_OUT_TCP_DPORT,
 658         MLX5_MODI_OUT_IPV4_TTL,
 659         MLX5_MODI_OUT_UDP_SPORT,
 660         MLX5_MODI_OUT_UDP_DPORT,
 661         MLX5_MODI_OUT_SIPV6_127_96,
 662         MLX5_MODI_OUT_SIPV6_95_64,
 663         MLX5_MODI_OUT_SIPV6_63_32,
 664         MLX5_MODI_OUT_SIPV6_31_0,
 665         MLX5_MODI_OUT_DIPV6_127_96,
 666         MLX5_MODI_OUT_DIPV6_95_64,
 667         MLX5_MODI_OUT_DIPV6_63_32,
 668         MLX5_MODI_OUT_DIPV6_31_0,
 669         MLX5_MODI_OUT_SIPV4,
 670         MLX5_MODI_OUT_DIPV4,
 671         MLX5_MODI_OUT_FIRST_VID,
 672         MLX5_MODI_IN_SMAC_47_16 = 0x31,
 673         MLX5_MODI_IN_SMAC_15_0,
 674         MLX5_MODI_IN_ETHERTYPE,
 675         MLX5_MODI_IN_DMAC_47_16,
 676         MLX5_MODI_IN_DMAC_15_0,
 677         MLX5_MODI_IN_IP_DSCP,
 678         MLX5_MODI_IN_TCP_FLAGS,
 679         MLX5_MODI_IN_TCP_SPORT,
 680         MLX5_MODI_IN_TCP_DPORT,
 681         MLX5_MODI_IN_IPV4_TTL,
 682         MLX5_MODI_IN_UDP_SPORT,
 683         MLX5_MODI_IN_UDP_DPORT,
 684         MLX5_MODI_IN_SIPV6_127_96,
 685         MLX5_MODI_IN_SIPV6_95_64,
 686         MLX5_MODI_IN_SIPV6_63_32,
 687         MLX5_MODI_IN_SIPV6_31_0,
 688         MLX5_MODI_IN_DIPV6_127_96,
 689         MLX5_MODI_IN_DIPV6_95_64,
 690         MLX5_MODI_IN_DIPV6_63_32,
 691         MLX5_MODI_IN_DIPV6_31_0,
 692         MLX5_MODI_IN_SIPV4,
 693         MLX5_MODI_IN_DIPV4,
 694         MLX5_MODI_OUT_IPV6_HOPLIMIT,
 695         MLX5_MODI_IN_IPV6_HOPLIMIT,
 696         MLX5_MODI_META_DATA_REG_A,
 697         MLX5_MODI_META_DATA_REG_B = 0x50,
 698         MLX5_MODI_META_REG_C_0,
 699         MLX5_MODI_META_REG_C_1,
 700         MLX5_MODI_META_REG_C_2,
 701         MLX5_MODI_META_REG_C_3,
 702         MLX5_MODI_META_REG_C_4,
 703         MLX5_MODI_META_REG_C_5,
 704         MLX5_MODI_META_REG_C_6,
 705         MLX5_MODI_META_REG_C_7,
 706         MLX5_MODI_OUT_TCP_SEQ_NUM,
 707         MLX5_MODI_IN_TCP_SEQ_NUM,
 708         MLX5_MODI_OUT_TCP_ACK_NUM,
 709         MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
 710         MLX5_MODI_GTP_TEID = 0x6E,
 711 };
 712
 713 /* Total number of metadata reg_c's. */
 714 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1)
 715
 716 enum modify_reg {
 717         REG_NON = 0,
 718         REG_A,
 719         REG_B,
 720         REG_C_0,
 721         REG_C_1,
 722         REG_C_2,
 723         REG_C_3,
 724         REG_C_4,
 725         REG_C_5,
 726         REG_C_6,
 727         REG_C_7,
 728 };
 729
 730 /* Modification sub command. */
 731 struct mlx5_modification_cmd {
 732         union {
 733                 uint32_t data0;
 734                 struct {
 735                         unsigned int length:5;
 736                         unsigned int rsvd0:3;
 737                         unsigned int offset:5;
 738                         unsigned int rsvd1:3;
 739                         unsigned int field:12;
 740                         unsigned int action_type:4;
 741                 };
 742         };
 743         union {
 744                 uint32_t data1;
 745                 uint8_t data[4];
 746                 struct {
 747                         unsigned int rsvd2:8;
 748                         unsigned int dst_offset:5;
 749                         unsigned int rsvd3:3;
 750                         unsigned int dst_field:12;
 751                         unsigned int rsvd4:4;
 752                 };
 753         };
 754 };
 755
 756 typedef uint64_t u64;
 757 typedef uint32_t u32;
 758 typedef uint16_t u16;
 759 typedef uint8_t u8;
 760
 761 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
 762 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
 763 #define __mlx5_bit_off(typ, fld) ((unsigned int)(uintptr_t) \
 764                                   (&(__mlx5_nullp(typ)->fld)))
 765 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
 766                                     (__mlx5_bit_off(typ, fld) & 0x1f))
 767 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
 768 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
 769 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
 770                                   __mlx5_dw_bit_off(typ, fld))
 771 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
 772 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
 773 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
 774                                     (__mlx5_bit_off(typ, fld) & 0xf))
 775 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
 776 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \
 777                                   __mlx5_16_bit_off(typ, fld))
 778 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
 779 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
 780 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
 781 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
 782
 783 /* insert a value to a struct */
 784 #define MLX5_SET(typ, p, fld, v) \
 785         do { \
 786                 u32 _v = v; \
 787                 *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \
 788                 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
 789                                   __mlx5_dw_off(typ, fld))) & \
 790                                   (~__mlx5_dw_mask(typ, fld))) | \
 791                                  (((_v) & __mlx5_mask(typ, fld)) << \
 792                                    __mlx5_dw_bit_off(typ, fld))); \
 793         } while (0)
 794
 795 #define MLX5_SET64(typ, p, fld, v) \
 796         do { \
 797                 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \
 798                 *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \
 799                         rte_cpu_to_be_64(v); \
 800         } while (0)
 801
 802 #define MLX5_SET16(typ, p, fld, v) \
 803         do { \
 804                 u16 _v = v; \
 805                 *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \
 806                 rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
 807                                   __mlx5_16_off(typ, fld))) & \
 808                                   (~__mlx5_16_mask(typ, fld))) | \
 809                                  (((_v) & __mlx5_mask16(typ, fld)) << \
 810                                   __mlx5_16_bit_off(typ, fld))); \
 811         } while (0)
 812
 813 #define MLX5_GET_VOLATILE(typ, p, fld) \
 814         ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\
 815         __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
 816         __mlx5_mask(typ, fld))
 817 #define MLX5_GET(typ, p, fld) \
 818         ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\
 819         __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
 820         __mlx5_mask(typ, fld))
 821 #define MLX5_GET16(typ, p, fld) \
 822         ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
 823           __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
 824          __mlx5_mask16(typ, fld))
 825 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \
 826                                                    __mlx5_64_off(typ, fld)))
 827 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
 828 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
 829
 830 struct mlx5_ifc_fte_match_set_misc_bits {
 831         u8 gre_c_present[0x1];
 832         u8 reserved_at_1[0x1];
 833         u8 gre_k_present[0x1];
 834         u8 gre_s_present[0x1];
 835         u8 source_vhci_port[0x4];
 836         u8 source_sqn[0x18];
 837         u8 reserved_at_20[0x10];
 838         u8 source_port[0x10];
 839         u8 outer_second_prio[0x3];
 840         u8 outer_second_cfi[0x1];
 841         u8 outer_second_vid[0xc];
 842         u8 inner_second_prio[0x3];
 843         u8 inner_second_cfi[0x1];
 844         u8 inner_second_vid[0xc];
 845         u8 outer_second_cvlan_tag[0x1];
 846         u8 inner_second_cvlan_tag[0x1];
 847         u8 outer_second_svlan_tag[0x1];
 848         u8 inner_second_svlan_tag[0x1];
 849         u8 reserved_at_64[0xc];
 850         u8 gre_protocol[0x10];
 851         u8 gre_key_h[0x18];
 852         u8 gre_key_l[0x8];
 853         u8 vxlan_vni[0x18];
 854         u8 reserved_at_b8[0x8];
 855         u8 geneve_vni[0x18];
 856         u8 reserved_at_e4[0x7];
 857         u8 geneve_oam[0x1];
 858         u8 reserved_at_e0[0xc];
 859         u8 outer_ipv6_flow_label[0x14];
 860         u8 reserved_at_100[0xc];
 861         u8 inner_ipv6_flow_label[0x14];
 862         u8 reserved_at_120[0xa];
 863         u8 geneve_opt_len[0x6];
 864         u8 geneve_protocol_type[0x10];
 865         u8 reserved_at_140[0xc0];
 866 };
 867
 868 struct mlx5_ifc_ipv4_layout_bits {
 869         u8 reserved_at_0[0x60];
 870         u8 ipv4[0x20];
 871 };
 872
 873 struct mlx5_ifc_ipv6_layout_bits {
 874         u8 ipv6[16][0x8];
 875 };
 876
 877 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 878         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 879         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 880         u8 reserved_at_0[0x80];
 881 };
 882
 883 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 884         u8 smac_47_16[0x20];
 885         u8 smac_15_0[0x10];
 886         u8 ethertype[0x10];
 887         u8 dmac_47_16[0x20];
 888         u8 dmac_15_0[0x10];
 889         u8 first_prio[0x3];
 890         u8 first_cfi[0x1];
 891         u8 first_vid[0xc];
 892         u8 ip_protocol[0x8];
 893         u8 ip_dscp[0x6];
 894         u8 ip_ecn[0x2];
 895         u8 cvlan_tag[0x1];
 896         u8 svlan_tag[0x1];
 897         u8 frag[0x1];
 898         u8 ip_version[0x4];
 899         u8 tcp_flags[0x9];
 900         u8 tcp_sport[0x10];
 901         u8 tcp_dport[0x10];
 902         u8 reserved_at_c0[0x10];
 903         u8 ipv4_ihl[0x4];
 904         u8 l3_ok[0x1];
 905         u8 l4_ok[0x1];
 906         u8 ipv4_checksum_ok[0x1];
 907         u8 l4_checksum_ok[0x1];
 908         u8 ip_ttl_hoplimit[0x8];
 909         u8 udp_sport[0x10];
 910         u8 udp_dport[0x10];
 911         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 912         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 913 };
 914
 915 struct mlx5_ifc_fte_match_mpls_bits {
 916         u8 mpls_label[0x14];
 917         u8 mpls_exp[0x3];
 918         u8 mpls_s_bos[0x1];
 919         u8 mpls_ttl[0x8];
 920 };
 921
 922 struct mlx5_ifc_fte_match_set_misc2_bits {
 923         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 924         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 925         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 926         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 927         u8 metadata_reg_c_7[0x20];
 928         u8 metadata_reg_c_6[0x20];
 929         u8 metadata_reg_c_5[0x20];
 930         u8 metadata_reg_c_4[0x20];
 931         u8 metadata_reg_c_3[0x20];
 932         u8 metadata_reg_c_2[0x20];
 933         u8 metadata_reg_c_1[0x20];
 934         u8 metadata_reg_c_0[0x20];
 935         u8 metadata_reg_a[0x20];
 936         u8 metadata_reg_b[0x20];
 937         u8 reserved_at_1c0[0x40];
 938 };
 939
 940 struct mlx5_ifc_fte_match_set_misc3_bits {
 941         u8 inner_tcp_seq_num[0x20];
 942         u8 outer_tcp_seq_num[0x20];
 943         u8 inner_tcp_ack_num[0x20];
 944         u8 outer_tcp_ack_num[0x20];
 945         u8 reserved_at_auto1[0x8];
 946         u8 outer_vxlan_gpe_vni[0x18];
 947         u8 outer_vxlan_gpe_next_protocol[0x8];
 948         u8 outer_vxlan_gpe_flags[0x8];
 949         u8 reserved_at_a8[0x10];
 950         u8 icmp_header_data[0x20];
 951         u8 icmpv6_header_data[0x20];
 952         u8 icmp_type[0x8];
 953         u8 icmp_code[0x8];
 954         u8 icmpv6_type[0x8];
 955         u8 icmpv6_code[0x8];
 956         u8 geneve_tlv_option_0_data[0x20];
 957         u8 gtpu_teid[0x20];
 958         u8 gtpu_msg_type[0x08];
 959         u8 gtpu_msg_flags[0x08];
 960         u8 reserved_at_170[0x10];
 961         u8 gtpu_dw_2[0x20];
 962         u8 gtpu_first_ext_dw_0[0x20];
 963         u8 gtpu_dw_0[0x20];
 964         u8 reserved_at_240[0x20];
 965
 966 };
 967
 968 struct mlx5_ifc_fte_match_set_misc4_bits {
 969         u8 prog_sample_field_value_0[0x20];
 970         u8 prog_sample_field_id_0[0x20];
 971         u8 prog_sample_field_value_1[0x20];
 972         u8 prog_sample_field_id_1[0x20];
 973         u8 prog_sample_field_value_2[0x20];
 974         u8 prog_sample_field_id_2[0x20];
 975         u8 prog_sample_field_value_3[0x20];
 976         u8 prog_sample_field_id_3[0x20];
 977         u8 reserved_at_100[0x100];
 978 };
 979
 980 struct mlx5_ifc_fte_match_set_misc5_bits {
 981         u8 macsec_tag_0[0x20];
 982         u8 macsec_tag_1[0x20];
 983         u8 macsec_tag_2[0x20];
 984         u8 macsec_tag_3[0x20];
 985         u8 tunnel_header_0[0x20];
 986         u8 tunnel_header_1[0x20];
 987         u8 tunnel_header_2[0x20];
 988         u8 tunnel_header_3[0x20];
 989         u8 reserved[0x100];
 990 };
 991
 992 /* Flow matcher. */
 993 struct mlx5_ifc_fte_match_param_bits {
 994         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
 995         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
 996         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
 997         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
 998         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
 999         struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1000         struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
1001 /*
1002  * Add reserved bit to match the struct size with the size defined in PRM.
1003  * This extension is not required in Linux.
1004  */
1005 #ifndef HAVE_INFINIBAND_VERBS_H
1006         u8 reserved_0[0x200];
1007 #endif
1008 };
1009
1010 struct mlx5_ifc_dest_format_struct_bits {
1011         u8 destination_type[0x8];
1012         u8 destination_id[0x18];
1013         u8 reserved_0[0x20];
1014 };
1015
1016 enum {
1017         MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
1018         MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
1019         MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
1020         MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
1021         MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT,
1022         MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT,
1023         MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT,
1024 };
1025
1026 enum {
1027         MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
1028         MLX5_CMD_OP_CREATE_MKEY = 0x200,
1029         MLX5_CMD_OP_CREATE_CQ = 0x400,
1030         MLX5_CMD_OP_CREATE_QP = 0x500,
1031         MLX5_CMD_OP_RST2INIT_QP = 0x502,
1032         MLX5_CMD_OP_INIT2RTR_QP = 0x503,
1033         MLX5_CMD_OP_RTR2RTS_QP = 0x504,
1034         MLX5_CMD_OP_RTS2RTS_QP = 0x505,
1035         MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
1036         MLX5_CMD_OP_QP_2ERR = 0x507,
1037         MLX5_CMD_OP_QP_2RST = 0x50A,
1038         MLX5_CMD_OP_QUERY_QP = 0x50B,
1039         MLX5_CMD_OP_SQD2RTS_QP = 0x50C,
1040         MLX5_CMD_OP_INIT2INIT_QP = 0x50E,
1041         MLX5_CMD_OP_SUSPEND_QP = 0x50F,
1042         MLX5_CMD_OP_RESUME_QP = 0x510,
1043         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
1044         MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
1045         MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
1046         MLX5_CMD_OP_ALLOC_PD = 0x800,
1047         MLX5_CMD_OP_DEALLOC_PD = 0x801,
1048         MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
1049         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
1050         MLX5_CMD_OP_CREATE_TIR = 0x900,
1051         MLX5_CMD_OP_MODIFY_TIR = 0x901,
1052         MLX5_CMD_OP_CREATE_SQ = 0X904,
1053         MLX5_CMD_OP_MODIFY_SQ = 0X905,
1054         MLX5_CMD_OP_CREATE_RQ = 0x908,
1055         MLX5_CMD_OP_MODIFY_RQ = 0x909,
1056         MLX5_CMD_OP_QUERY_RQ = 0x90b,
1057         MLX5_CMD_OP_CREATE_TIS = 0x912,
1058         MLX5_CMD_OP_QUERY_TIS = 0x915,
1059         MLX5_CMD_OP_CREATE_RQT = 0x916,
1060         MLX5_CMD_OP_MODIFY_RQT = 0x917,
1061         MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
1062         MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
1063         MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
1064         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
1065         MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
1066         MLX5_CMD_SET_REGEX_PARAMS = 0xb04,
1067         MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,
1068         MLX5_CMD_SET_REGEX_REGISTERS = 0xb06,
1069         MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
1070         MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c,
1071 };
1072
1073 enum {
1074         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
1075         MLX5_MKC_ACCESS_MODE_KLM   = 0x2,
1076         MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3,
1077 };
1078
1079 #define MLX5_ADAPTER_PAGE_SHIFT 12
1080 #define MLX5_LOG_RQ_STRIDE_SHIFT 4
1081 /**
1082  * The batch counter dcs id starts from 0x800000 and none batch counter
1083  * starts from 0. As currently, the counter is changed to be indexed by
1084  * pool index and the offset of the counter in the pool counters_raw array.
1085  * It means now the counter index is same for batch and none batch counter.
1086  * Add the 0x800000 batch counter offset to the batch counter index helps
1087  * indicate the counter index is from batch or none batch container pool.
1088  */
1089 #define MLX5_CNT_BATCH_OFFSET 0x800000
1090
1091 /* The counter batch query requires ID align with 4. */
1092 #define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4
1093
1094 /* Flow counters. */
1095 struct mlx5_ifc_alloc_flow_counter_out_bits {
1096         u8 status[0x8];
1097         u8 reserved_at_8[0x18];
1098         u8 syndrome[0x20];
1099         u8 flow_counter_id[0x20];
1100         u8 reserved_at_60[0x20];
1101 };
1102
1103 struct mlx5_ifc_alloc_flow_counter_in_bits {
1104         u8 opcode[0x10];
1105         u8 reserved_at_10[0x10];
1106         u8 reserved_at_20[0x10];
1107         u8 op_mod[0x10];
1108         u8 flow_counter_id[0x20];
1109         u8 reserved_at_40[0x18];
1110         u8 flow_counter_bulk[0x8];
1111 };
1112
1113 struct mlx5_ifc_dealloc_flow_counter_out_bits {
1114         u8 status[0x8];
1115         u8 reserved_at_8[0x18];
1116         u8 syndrome[0x20];
1117         u8 reserved_at_40[0x40];
1118 };
1119
1120 struct mlx5_ifc_dealloc_flow_counter_in_bits {
1121         u8 opcode[0x10];
1122         u8 reserved_at_10[0x10];
1123         u8 reserved_at_20[0x10];
1124         u8 op_mod[0x10];
1125         u8 flow_counter_id[0x20];
1126         u8 reserved_at_60[0x20];
1127 };
1128
1129 struct mlx5_ifc_traffic_counter_bits {
1130         u8 packets[0x40];
1131         u8 octets[0x40];
1132 };
1133
1134 struct mlx5_ifc_query_flow_counter_out_bits {
1135         u8 status[0x8];
1136         u8 reserved_at_8[0x18];
1137         u8 syndrome[0x20];
1138         u8 reserved_at_40[0x40];
1139         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
1140 };
1141
1142 struct mlx5_ifc_query_flow_counter_in_bits {
1143         u8 opcode[0x10];
1144         u8 reserved_at_10[0x10];
1145         u8 reserved_at_20[0x10];
1146         u8 op_mod[0x10];
1147         u8 reserved_at_40[0x20];
1148         u8 mkey[0x20];
1149         u8 address[0x40];
1150         u8 clear[0x1];
1151         u8 dump_to_memory[0x1];
1152         u8 num_of_counters[0x1e];
1153         u8 flow_counter_id[0x20];
1154 };
1155
1156 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u
1157 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u
1158
1159 struct mlx5_ifc_klm_bits {
1160         u8 byte_count[0x20];
1161         u8 mkey[0x20];
1162         u8 address[0x40];
1163 };
1164
1165 struct mlx5_ifc_mkc_bits {
1166         u8 reserved_at_0[0x1];
1167         u8 free[0x1];
1168         u8 reserved_at_2[0x1];
1169         u8 access_mode_4_2[0x3];
1170         u8 reserved_at_6[0x7];
1171         u8 relaxed_ordering_write[0x1];
1172         u8 reserved_at_e[0x1];
1173         u8 small_fence_on_rdma_read_response[0x1];
1174         u8 umr_en[0x1];
1175         u8 a[0x1];
1176         u8 rw[0x1];
1177         u8 rr[0x1];
1178         u8 lw[0x1];
1179         u8 lr[0x1];
1180         u8 access_mode_1_0[0x2];
1181         u8 reserved_at_18[0x8];
1182         u8 qpn[0x18];
1183         u8 mkey_7_0[0x8];
1184         u8 reserved_at_40[0x20];
1185         u8 length64[0x1];
1186         u8 bsf_en[0x1];
1187         u8 sync_umr[0x1];
1188         u8 reserved_at_63[0x2];
1189         u8 expected_sigerr_count[0x1];
1190         u8 reserved_at_66[0x1];
1191         u8 en_rinval[0x1];
1192         u8 pd[0x18];
1193         u8 start_addr[0x40];
1194         u8 len[0x40];
1195         u8 bsf_octword_size[0x20];
1196         u8 reserved_at_120[0x80];
1197         u8 translations_octword_size[0x20];
1198         u8 reserved_at_1c0[0x19];
1199         u8 relaxed_ordering_read[0x1];
1200         u8 reserved_at_1da[0x1];
1201         u8 log_page_size[0x5];
1202         u8 reserved_at_1e0[0x3];
1203         u8 crypto_en[0x2];
1204         u8 reserved_at_1e5[0x1b];
1205 };
1206
1207 /* Range of values for MKEY context crypto_en field. */
1208 enum {
1209         MLX5_MKEY_CRYPTO_DISABLED = 0x0,
1210         MLX5_MKEY_CRYPTO_ENABLED = 0x1,
1211 };
1212
1213 struct mlx5_ifc_create_mkey_out_bits {
1214         u8 status[0x8];
1215         u8 reserved_at_8[0x18];
1216         u8 syndrome[0x20];
1217         u8 reserved_at_40[0x8];
1218         u8 mkey_index[0x18];
1219         u8 reserved_at_60[0x20];
1220 };
1221
1222 struct mlx5_ifc_create_mkey_in_bits {
1223         u8 opcode[0x10];
1224         u8 reserved_at_10[0x10];
1225         u8 reserved_at_20[0x10];
1226         u8 op_mod[0x10];
1227         u8 reserved_at_40[0x20];
1228         u8 pg_access[0x1];
1229         u8 reserved_at_61[0x1f];
1230         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
1231         u8 reserved_at_280[0x80];
1232         u8 translations_octword_actual_size[0x20];
1233         u8 mkey_umem_id[0x20];
1234         u8 mkey_umem_offset[0x40];
1235         u8 reserved_at_380[0x500];
1236         u8 klm_pas_mtt[][0x20];
1237 };
1238
1239 enum {
1240         MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
1241         MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
1242         MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
1243         MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1,
1244         MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,
1245         MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
1246         MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1,
1247 };
1248
1249 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \
1250                         (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ)
1251 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \
1252                         (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS)
1253 #define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \
1254                         (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH)
1255 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \
1256                         (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO)
1257 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO \
1258                         (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO)
1259 #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \
1260                         (1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT)
1261 #define MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD \
1262                         (1ULL << MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD)
1263 #define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \
1264                         (1ULL << MLX5_GENERAL_OBJ_TYPE_DEK)
1265 #define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \
1266                         (1ULL << MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK)
1267 #define MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL \
1268                         (1ULL << MLX5_GENERAL_OBJ_TYPE_CREDENTIAL)
1269 #define MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN \
1270                         (1ULL << MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN)
1271
1272 enum {
1273         MLX5_HCA_CAP_OPMOD_GET_MAX   = 0,
1274         MLX5_HCA_CAP_OPMOD_GET_CUR   = 1,
1275 };
1276
1277 enum {
1278         MLX5_CAP_INLINE_MODE_L2,
1279         MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
1280         MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
1281 };
1282
1283 enum {
1284         MLX5_INLINE_MODE_NONE,
1285         MLX5_INLINE_MODE_L2,
1286         MLX5_INLINE_MODE_IP,
1287         MLX5_INLINE_MODE_TCP_UDP,
1288         MLX5_INLINE_MODE_RESERVED4,
1289         MLX5_INLINE_MODE_INNER_L2,
1290         MLX5_INLINE_MODE_INNER_IP,
1291         MLX5_INLINE_MODE_INNER_TCP_UDP,
1292 };
1293
1294 /* The supported timestamp formats reported in HCA attributes. */
1295 enum {
1296         MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR = 0x0,
1297         MLX5_HCA_CAP_TIMESTAMP_FORMAT_RT = 0x1,
1298         MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR_RT = 0x2,
1299 };
1300
1301 /* The timestamp format attributes to configure queues (RQ/SQ/QP). */
1302 enum {
1303         MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
1304         MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
1305         MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
1306 };
1307
1308 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
1309 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
1310 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
1311 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
1312 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
1313 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
1314 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
1315 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
1316 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
1317 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
1318 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
1319
1320 struct mlx5_ifc_cmd_hca_cap_bits {
1321         u8 reserved_at_0[0x30];
1322         u8 vhca_id[0x10];
1323         u8 reserved_at_40[0x20];
1324         u8 reserved_at_60[0x3];
1325         u8 log_regexp_scatter_gather_size[0x5];
1326         u8 reserved_at_68[0x3];
1327         u8 log_dma_mmo_size[0x5];
1328         u8 reserved_at_70[0x3];
1329         u8 log_compress_mmo_size[0x5];
1330         u8 reserved_at_78[0x3];
1331         u8 log_decompress_mmo_size[0x5];
1332         u8 log_max_srq_sz[0x8];
1333         u8 log_max_qp_sz[0x8];
1334         u8 reserved_at_90[0x9];
1335         u8 wqe_index_ignore_cap[0x1];
1336         u8 dynamic_qp_allocation[0x1];
1337         u8 log_max_qp[0x5];
1338         u8 regexp[0x1];
1339         u8 reserved_at_a1[0x3];
1340         u8 regexp_num_of_engines[0x4];
1341         u8 reserved_at_a8[0x1];
1342         u8 reg_c_preserve[0x1];
1343         u8 reserved_at_aa[0x1];
1344         u8 log_max_srq[0x5];
1345         u8 reserved_at_b0[0x3];
1346         u8 regexp_log_crspace_size[0x5];
1347         u8 reserved_at_b8[0x3];
1348         u8 scatter_fcs_w_decap_disable[0x1];
1349         u8 reserved_at_bc[0x4];
1350         u8 reserved_at_c0[0x8];
1351         u8 log_max_cq_sz[0x8];
1352         u8 reserved_at_d0[0xb];
1353         u8 log_max_cq[0x5];
1354         u8 log_max_eq_sz[0x8];
1355         u8 relaxed_ordering_write[0x1];
1356         u8 relaxed_ordering_read[0x1];
1357         u8 access_register_user[0x1];
1358         u8 log_max_mkey[0x5];
1359         u8 reserved_at_f0[0x8];
1360         u8 dump_fill_mkey[0x1];
1361         u8 reserved_at_f9[0x3];
1362         u8 log_max_eq[0x4];
1363         u8 max_indirection[0x8];
1364         u8 fixed_buffer_size[0x1];
1365         u8 log_max_mrw_sz[0x7];
1366         u8 force_teardown[0x1];
1367         u8 reserved_at_111[0x1];
1368         u8 log_max_bsf_list_size[0x6];
1369         u8 umr_extended_translation_offset[0x1];
1370         u8 null_mkey[0x1];
1371         u8 log_max_klm_list_size[0x6];
1372         u8 non_wire_sq[0x1];
1373         u8 reserved_at_121[0x9];
1374         u8 log_max_ra_req_dc[0x6];
1375         u8 reserved_at_130[0x3];
1376         u8 log_max_static_sq_wq[0x5];
1377         u8 reserved_at_138[0x2];
1378         u8 log_max_ra_res_dc[0x6];
1379         u8 reserved_at_140[0xa];
1380         u8 log_max_ra_req_qp[0x6];
1381         u8 rtr2rts_qp_counters_set_id[0x1];
1382         u8 rts2rts_udp_sport[0x1];
1383         u8 rts2rts_lag_tx_port_affinity[0x1];
1384         u8 dma_mmo[0x1];
1385         u8 compress_min_block_size[0x4];
1386         u8 compress[0x1];
1387         u8 decompress[0x1];
1388         u8 log_max_ra_res_qp[0x6];
1389         u8 end_pad[0x1];
1390         u8 cc_query_allowed[0x1];
1391         u8 cc_modify_allowed[0x1];
1392         u8 start_pad[0x1];
1393         u8 cache_line_128byte[0x1];
1394         u8 reserved_at_165[0xa];
1395         u8 qcam_reg[0x1];
1396         u8 gid_table_size[0x10];
1397         u8 out_of_seq_cnt[0x1];
1398         u8 vport_counters[0x1];
1399         u8 retransmission_q_counters[0x1];
1400         u8 debug[0x1];
1401         u8 modify_rq_counter_set_id[0x1];
1402         u8 rq_delay_drop[0x1];
1403         u8 max_qp_cnt[0xa];
1404         u8 pkey_table_size[0x10];
1405         u8 vport_group_manager[0x1];
1406         u8 vhca_group_manager[0x1];
1407         u8 ib_virt[0x1];
1408         u8 eth_virt[0x1];
1409         u8 vnic_env_queue_counters[0x1];
1410         u8 ets[0x1];
1411         u8 nic_flow_table[0x1];
1412         u8 eswitch_manager[0x1];
1413         u8 device_memory[0x1];
1414         u8 mcam_reg[0x1];
1415         u8 pcam_reg[0x1];
1416         u8 local_ca_ack_delay[0x5];
1417         u8 port_module_event[0x1];
1418         u8 enhanced_error_q_counters[0x1];
1419         u8 ports_check[0x1];
1420         u8 reserved_at_1b3[0x1];
1421         u8 disable_link_up[0x1];
1422         u8 beacon_led[0x1];
1423         u8 port_type[0x2];
1424         u8 num_ports[0x8];
1425         u8 reserved_at_1c0[0x1];
1426         u8 pps[0x1];
1427         u8 pps_modify[0x1];
1428         u8 log_max_msg[0x5];
1429         u8 reserved_at_1c8[0x4];
1430         u8 max_tc[0x4];
1431         u8 temp_warn_event[0x1];
1432         u8 dcbx[0x1];
1433         u8 general_notification_event[0x1];
1434         u8 reserved_at_1d3[0x2];
1435         u8 fpga[0x1];
1436         u8 rol_s[0x1];
1437         u8 rol_g[0x1];
1438         u8 reserved_at_1d8[0x1];
1439         u8 wol_s[0x1];
1440         u8 wol_g[0x1];
1441         u8 wol_a[0x1];
1442         u8 wol_b[0x1];
1443         u8 wol_m[0x1];
1444         u8 wol_u[0x1];
1445         u8 wol_p[0x1];
1446         u8 stat_rate_support[0x10];
1447         u8 reserved_at_1f0[0xc];
1448         u8 cqe_version[0x4];
1449         u8 compact_address_vector[0x1];
1450         u8 striding_rq[0x1];
1451         u8 reserved_at_202[0x1];
1452         u8 ipoib_enhanced_offloads[0x1];
1453         u8 ipoib_basic_offloads[0x1];
1454         u8 reserved_at_205[0x1];
1455         u8 repeated_block_disabled[0x1];
1456         u8 umr_modify_entity_size_disabled[0x1];
1457         u8 umr_modify_atomic_disabled[0x1];
1458         u8 umr_indirect_mkey_disabled[0x1];
1459         u8 umr_fence[0x2];
1460         u8 reserved_at_20c[0x3];
1461         u8 drain_sigerr[0x1];
1462         u8 cmdif_checksum[0x2];
1463         u8 sigerr_cqe[0x1];
1464         u8 reserved_at_213[0x1];
1465         u8 wq_signature[0x1];
1466         u8 sctr_data_cqe[0x1];
1467         u8 reserved_at_216[0x1];
1468         u8 sho[0x1];
1469         u8 tph[0x1];
1470         u8 rf[0x1];
1471         u8 dct[0x1];
1472         u8 qos[0x1];
1473         u8 eth_net_offloads[0x1];
1474         u8 roce[0x1];
1475         u8 atomic[0x1];
1476         u8 reserved_at_21f[0x1];
1477         u8 cq_oi[0x1];
1478         u8 cq_resize[0x1];
1479         u8 cq_moderation[0x1];
1480         u8 reserved_at_223[0x3];
1481         u8 cq_eq_remap[0x1];
1482         u8 pg[0x1];
1483         u8 block_lb_mc[0x1];
1484         u8 reserved_at_229[0x1];
1485         u8 scqe_break_moderation[0x1];
1486         u8 cq_period_start_from_cqe[0x1];
1487         u8 cd[0x1];
1488         u8 reserved_at_22d[0x1];
1489         u8 apm[0x1];
1490         u8 vector_calc[0x1];
1491         u8 umr_ptr_rlky[0x1];
1492         u8 imaicl[0x1];
1493         u8 reserved_at_232[0x4];
1494         u8 qkv[0x1];
1495         u8 pkv[0x1];
1496         u8 set_deth_sqpn[0x1];
1497         u8 reserved_at_239[0x3];
1498         u8 xrc[0x1];
1499         u8 ud[0x1];
1500         u8 uc[0x1];
1501         u8 rc[0x1];
1502         u8 uar_4k[0x1];
1503         u8 reserved_at_241[0x9];
1504         u8 uar_sz[0x6];
1505         u8 reserved_at_250[0x8];
1506         u8 log_pg_sz[0x8];
1507         u8 bf[0x1];
1508         u8 driver_version[0x1];
1509         u8 pad_tx_eth_packet[0x1];
1510         u8 reserved_at_263[0x8];
1511         u8 log_bf_reg_size[0x5];
1512         u8 reserved_at_270[0xb];
1513         u8 lag_master[0x1];
1514         u8 num_lag_ports[0x4];
1515         u8 reserved_at_280[0x10];
1516         u8 max_wqe_sz_sq[0x10];
1517         u8 reserved_at_2a0[0x10];
1518         u8 max_wqe_sz_rq[0x10];
1519         u8 max_flow_counter_31_16[0x10];
1520         u8 max_wqe_sz_sq_dc[0x10];
1521         u8 reserved_at_2e0[0x7];
1522         u8 max_qp_mcg[0x19];
1523         u8 reserved_at_300[0x10];
1524         u8 flow_counter_bulk_alloc[0x08];
1525         u8 log_max_mcg[0x8];
1526         u8 reserved_at_320[0x3];
1527         u8 log_max_transport_domain[0x5];
1528         u8 reserved_at_328[0x3];
1529         u8 log_max_pd[0x5];
1530         u8 reserved_at_330[0xb];
1531         u8 log_max_xrcd[0x5];
1532         u8 nic_receive_steering_discard[0x1];
1533         u8 receive_discard_vport_down[0x1];
1534         u8 transmit_discard_vport_down[0x1];
1535         u8 reserved_at_343[0x5];
1536         u8 log_max_flow_counter_bulk[0x8];
1537         u8 max_flow_counter_15_0[0x10];
1538         u8 modify_tis[0x1];
1539         u8 flow_counters_dump[0x1];
1540         u8 reserved_at_360[0x1];
1541         u8 log_max_rq[0x5];
1542         u8 reserved_at_368[0x3];
1543         u8 log_max_sq[0x5];
1544         u8 reserved_at_370[0x3];
1545         u8 log_max_tir[0x5];
1546         u8 reserved_at_378[0x3];
1547         u8 log_max_tis[0x5];
1548         u8 basic_cyclic_rcv_wqe[0x1];
1549         u8 reserved_at_381[0x2];
1550         u8 log_max_rmp[0x5];
1551         u8 reserved_at_388[0x3];
1552         u8 log_max_rqt[0x5];
1553         u8 reserved_at_390[0x3];
1554         u8 log_max_rqt_size[0x5];
1555         u8 reserved_at_398[0x3];
1556         u8 log_max_tis_per_sq[0x5];
1557         u8 ext_stride_num_range[0x1];
1558         u8 reserved_at_3a1[0x2];
1559         u8 log_max_stride_sz_rq[0x5];
1560         u8 reserved_at_3a8[0x3];
1561         u8 log_min_stride_sz_rq[0x5];
1562         u8 reserved_at_3b0[0x3];
1563         u8 log_max_stride_sz_sq[0x5];
1564         u8 reserved_at_3b8[0x3];
1565         u8 log_min_stride_sz_sq[0x5];
1566         u8 hairpin[0x1];
1567         u8 reserved_at_3c1[0x2];
1568         u8 log_max_hairpin_queues[0x5];
1569         u8 reserved_at_3c8[0x3];
1570         u8 log_max_hairpin_wq_data_sz[0x5];
1571         u8 reserved_at_3d0[0x3];
1572         u8 log_max_hairpin_num_packets[0x5];
1573         u8 reserved_at_3d8[0x3];
1574         u8 log_max_wq_sz[0x5];
1575         u8 nic_vport_change_event[0x1];
1576         u8 disable_local_lb_uc[0x1];
1577         u8 disable_local_lb_mc[0x1];
1578         u8 log_min_hairpin_wq_data_sz[0x5];
1579         u8 reserved_at_3e8[0x3];
1580         u8 log_max_vlan_list[0x5];
1581         u8 reserved_at_3f0[0x3];
1582         u8 log_max_current_mc_list[0x5];
1583         u8 reserved_at_3f8[0x3];
1584         u8 log_max_current_uc_list[0x5];
1585         u8 general_obj_types[0x40];
1586         u8 sq_ts_format[0x2];
1587         u8 rq_ts_format[0x2];
1588         u8 reserved_at_444[0x1C];
1589         u8 reserved_at_460[0x8];
1590         u8 aes_xts[0x1];
1591         u8 crypto[0x1];
1592         u8 reserved_at_46a[0x6];
1593         u8 max_num_eqs[0x10];
1594         u8 reserved_at_480[0x3];
1595         u8 log_max_l2_table[0x5];
1596         u8 reserved_at_488[0x8];
1597         u8 log_uar_page_sz[0x10];
1598         u8 reserved_at_4a0[0x20];
1599         u8 device_frequency_mhz[0x20];
1600         u8 device_frequency_khz[0x20];
1601         u8 reserved_at_500[0x20];
1602         u8 num_of_uars_per_page[0x20];
1603         u8 flex_parser_protocols[0x20];
1604         u8 max_geneve_tlv_options[0x8];
1605         u8 reserved_at_568[0x3];
1606         u8 max_geneve_tlv_option_data_len[0x5];
1607         u8 reserved_at_570[0x49];
1608         u8 mini_cqe_resp_l3_l4_tag[0x1];
1609         u8 mini_cqe_resp_flow_tag[0x1];
1610         u8 enhanced_cqe_compression[0x1];
1611         u8 mini_cqe_resp_stride_index[0x1];
1612         u8 cqe_128_always[0x1];
1613         u8 cqe_compression_128[0x1];
1614         u8 cqe_compression[0x1];
1615         u8 cqe_compression_timeout[0x10];
1616         u8 cqe_compression_max_num[0x10];
1617         u8 reserved_at_5e0[0x10];
1618         u8 tag_matching[0x1];
1619         u8 rndv_offload_rc[0x1];
1620         u8 rndv_offload_dc[0x1];
1621         u8 log_tag_matching_list_sz[0x5];
1622         u8 reserved_at_5f8[0x3];
1623         u8 log_max_xrq[0x5];
1624         u8 affiliate_nic_vport_criteria[0x8];
1625         u8 native_port_num[0x8];
1626         u8 num_vhca_ports[0x8];
1627         u8 reserved_at_618[0x6];
1628         u8 sw_owner_id[0x1];
1629         u8 reserved_at_61f[0x1e1];
1630 };
1631
1632 struct mlx5_ifc_qos_cap_bits {
1633         u8 packet_pacing[0x1];
1634         u8 esw_scheduling[0x1];
1635         u8 esw_bw_share[0x1];
1636         u8 esw_rate_limit[0x1];
1637         u8 reserved_at_4[0x1];
1638         u8 packet_pacing_burst_bound[0x1];
1639         u8 packet_pacing_typical_size[0x1];
1640         u8 flow_meter_old[0x1];
1641         u8 reserved_at_8[0x8];
1642         u8 log_max_flow_meter[0x8];
1643         u8 flow_meter_reg_id[0x8];
1644         u8 wqe_rate_pp[0x1];
1645         u8 reserved_at_25[0x7];
1646         u8 flow_meter[0x1];
1647         u8 reserved_at_2e[0x17];
1648         u8 packet_pacing_max_rate[0x20];
1649         u8 packet_pacing_min_rate[0x20];
1650         u8 reserved_at_80[0x10];
1651         u8 packet_pacing_rate_table_size[0x10];
1652         u8 esw_element_type[0x10];
1653         u8 esw_tsar_type[0x10];
1654         u8 reserved_at_c0[0x10];
1655         u8 max_qos_para_vport[0x10];
1656         u8 max_tsar_bw_share[0x20];
1657         u8 nic_element_type[0x10];
1658         u8 nic_tsar_type[0x10];
1659         u8 reserved_at_120[0x3];
1660         u8 log_meter_aso_granularity[0x5];
1661         u8 reserved_at_128[0x3];
1662         u8 log_meter_aso_max_alloc[0x5];
1663         u8 reserved_at_130[0x3];
1664         u8 log_max_num_meter_aso[0x5];
1665         u8 reserved_at_138[0x6b0];
1666 };
1667
1668 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1669         u8 csum_cap[0x1];
1670         u8 vlan_cap[0x1];
1671         u8 lro_cap[0x1];
1672         u8 lro_psh_flag[0x1];
1673         u8 lro_time_stamp[0x1];
1674         u8 lro_max_msg_sz_mode[0x2];
1675         u8 wqe_vlan_insert[0x1];
1676         u8 self_lb_en_modifiable[0x1];
1677         u8 self_lb_mc[0x1];
1678         u8 self_lb_uc[0x1];
1679         u8 max_lso_cap[0x5];
1680         u8 multi_pkt_send_wqe[0x2];
1681         u8 wqe_inline_mode[0x2];
1682         u8 rss_ind_tbl_cap[0x4];
1683         u8 reg_umr_sq[0x1];
1684         u8 scatter_fcs[0x1];
1685         u8 enhanced_multi_pkt_send_wqe[0x1];
1686         u8 tunnel_lso_const_out_ip_id[0x1];
1687         u8 tunnel_lro_gre[0x1];
1688         u8 tunnel_lro_vxlan[0x1];
1689         u8 tunnel_stateless_gre[0x1];
1690         u8 tunnel_stateless_vxlan[0x1];
1691         u8 swp[0x1];
1692         u8 swp_csum[0x1];
1693         u8 swp_lso[0x1];
1694         u8 reserved_at_23[0x8];
1695         u8 tunnel_stateless_gtp[0x1];
1696         u8 reserved_at_25[0x4];
1697         u8 max_vxlan_udp_ports[0x8];
1698         u8 reserved_at_38[0x6];
1699         u8 max_geneve_opt_len[0x1];
1700         u8 tunnel_stateless_geneve_rx[0x1];
1701         u8 reserved_at_40[0x10];
1702         u8 lro_min_mss_size[0x10];
1703         u8 reserved_at_60[0x120];
1704         u8 lro_timer_supported_periods[4][0x20];
1705         u8 reserved_at_200[0x600];
1706 };
1707
1708 enum {
1709         MLX5_VIRTQ_TYPE_SPLIT = 0,
1710         MLX5_VIRTQ_TYPE_PACKED = 1,
1711 };
1712
1713 enum {
1714         MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0,
1715         MLX5_VIRTQ_EVENT_MODE_QP = 1,
1716         MLX5_VIRTQ_EVENT_MODE_MSIX = 2,
1717 };
1718
1719 struct mlx5_ifc_virtio_emulation_cap_bits {
1720         u8 desc_tunnel_offload_type[0x1];
1721         u8 eth_frame_offload_type[0x1];
1722         u8 virtio_version_1_0[0x1];
1723         u8 tso_ipv4[0x1];
1724         u8 tso_ipv6[0x1];
1725         u8 tx_csum[0x1];
1726         u8 rx_csum[0x1];
1727         u8 reserved_at_7[0x1][0x9];
1728         u8 event_mode[0x8];
1729         u8 virtio_queue_type[0x8];
1730         u8 reserved_at_20[0x13];
1731         u8 log_doorbell_stride[0x5];
1732         u8 reserved_at_3b[0x3];
1733         u8 log_doorbell_bar_size[0x5];
1734         u8 doorbell_bar_offset[0x40];
1735         u8 reserved_at_80[0x8];
1736         u8 max_num_virtio_queues[0x18];
1737         u8 reserved_at_a0[0x60];
1738         u8 umem_1_buffer_param_a[0x20];
1739         u8 umem_1_buffer_param_b[0x20];
1740         u8 umem_2_buffer_param_a[0x20];
1741         u8 umem_2_buffer_param_b[0x20];
1742         u8 umem_3_buffer_param_a[0x20];
1743         u8 umem_3_buffer_param_b[0x20];
1744         u8 reserved_at_1c0[0x620];
1745 };
1746
1747 struct mlx5_ifc_flow_table_prop_layout_bits {
1748         u8 ft_support[0x1];
1749         u8 flow_tag[0x1];
1750         u8 flow_counter[0x1];
1751         u8 flow_modify_en[0x1];
1752         u8 modify_root[0x1];
1753         u8 identified_miss_table[0x1];
1754         u8 flow_table_modify[0x1];
1755         u8 reformat[0x1];
1756         u8 decap[0x1];
1757         u8 reset_root_to_default[0x1];
1758         u8 pop_vlan[0x1];
1759         u8 push_vlan[0x1];
1760         u8 fpga_vendor_acceleration[0x1];
1761         u8 pop_vlan_2[0x1];
1762         u8 push_vlan_2[0x1];
1763         u8 reformat_and_vlan_action[0x1];
1764         u8 modify_and_vlan_action[0x1];
1765         u8 sw_owner[0x1];
1766         u8 reformat_l3_tunnel_to_l2[0x1];
1767         u8 reformat_l2_to_l3_tunnel[0x1];
1768         u8 reformat_and_modify_action[0x1];
1769         u8 reserved_at_15[0x9];
1770         u8 sw_owner_v2[0x1];
1771         u8 reserved_at_1f[0x1];
1772         u8 reserved_at_20[0x2];
1773         u8 log_max_ft_size[0x6];
1774         u8 log_max_modify_header_context[0x8];
1775         u8 max_modify_header_actions[0x8];
1776         u8 max_ft_level[0x8];
1777         u8 reserved_at_40[0x8];
1778         u8 log_max_ft_sampler_num[8];
1779         u8 metadata_reg_b_width[0x8];
1780         u8 metadata_reg_a_width[0x8];
1781         u8 reserved_at_60[0x18];
1782         u8 log_max_ft_num[0x8];
1783         u8 reserved_at_80[0x10];
1784         u8 log_max_flow_counter[0x8];
1785         u8 log_max_destination[0x8];
1786         u8 reserved_at_a0[0x18];
1787         u8 log_max_flow[0x8];
1788         u8 reserved_at_c0[0x140];
1789 };
1790
1791 struct mlx5_ifc_roce_caps_bits {
1792         u8 reserved_0[0x1e];
1793         u8 qp_ts_format[0x2];
1794         u8 reserved_at_20[0x7e0];
1795 };
1796
1797 /*
1798  * Table 1872 - Flow Table Fields Supported 2 Format
1799  */
1800 struct mlx5_ifc_ft_fields_support_2_bits {
1801         u8 reserved_at_0[0xf];
1802         u8 tunnel_header_2_3[0x1];
1803         u8 tunnel_header_0_1[0x1];
1804         u8 macsec_syndrome[0x1];
1805         u8 macsec_tag[0x1];
1806         u8 outer_lrh_sl[0x1];
1807         u8 inner_ipv4_ihl[0x1];
1808         u8 outer_ipv4_ihl[0x1];
1809         u8 psp_syndrome[0x1];
1810         u8 inner_l3_ok[0x1];
1811         u8 inner_l4_ok[0x1];
1812         u8 outer_l3_ok[0x1];
1813         u8 outer_l4_ok[0x1];
1814         u8 psp_header[0x1];
1815         u8 inner_ipv4_checksum_ok[0x1];
1816         u8 inner_l4_checksum_ok[0x1];
1817         u8 outer_ipv4_checksum_ok[0x1];
1818         u8 outer_l4_checksum_ok[0x1];
1819         u8 reserved_at_20[0x60];
1820 };
1821
1822 struct mlx5_ifc_flow_table_nic_cap_bits {
1823         u8 reserved_at_0[0x200];
1824         struct mlx5_ifc_flow_table_prop_layout_bits
1825                 flow_table_properties_nic_receive;
1826         struct mlx5_ifc_flow_table_prop_layout_bits
1827                 flow_table_properties_nic_receive_rdma;
1828         struct mlx5_ifc_flow_table_prop_layout_bits
1829                 flow_table_properties_nic_receive_sniffer;
1830         struct mlx5_ifc_flow_table_prop_layout_bits
1831                 flow_table_properties_nic_transmit;
1832         struct mlx5_ifc_flow_table_prop_layout_bits
1833                 flow_table_properties_nic_transmit_rdma;
1834         struct mlx5_ifc_flow_table_prop_layout_bits
1835                 flow_table_properties_nic_transmit_sniffer;
1836         u8 reserved_at_e00[0x600];
1837         struct mlx5_ifc_ft_fields_support_2_bits
1838                 ft_field_support_2_nic_receive;
1839 };
1840
1841 struct mlx5_ifc_cmd_hca_cap_2_bits {
1842         u8 reserved_at_0[0x80]; /* End of DW4. */
1843         u8 reserved_at_80[0xb];
1844         u8 log_max_num_reserved_qpn[0x5];
1845         u8 reserved_at_90[0x3];
1846         u8 log_reserved_qpn_granularity[0x5];
1847         u8 reserved_at_98[0x3];
1848         u8 log_reserved_qpn_max_alloc[0x5]; /* End of DW5. */
1849         u8 max_reformat_insert_size[0x8];
1850         u8 max_reformat_insert_offset[0x8];
1851         u8 max_reformat_remove_size[0x8];
1852         u8 max_reformat_remove_offset[0x8]; /* End of DW6. */
1853         u8 aso_conntrack_reg_id[0x8];
1854         u8 reserved_at_c8[0x3];
1855         u8 log_conn_track_granularity[0x5];
1856         u8 reserved_at_d0[0x3];
1857         u8 log_conn_track_max_alloc[0x5];
1858         u8 reserved_at_d8[0x3];
1859         u8 log_max_conn_track_offload[0x5];
1860         u8 reserved_at_e0[0x20]; /* End of DW7. */
1861         u8 reserved_at_100[0x700];
1862 };
1863
1864 union mlx5_ifc_hca_cap_union_bits {
1865         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1866         struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1867                per_protocol_networking_offload_caps;
1868         struct mlx5_ifc_qos_cap_bits qos_cap;
1869         struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
1870         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1871         struct mlx5_ifc_roce_caps_bits roce_caps;
1872         u8 reserved_at_0[0x8000];
1873 };
1874
1875 struct mlx5_ifc_set_action_in_bits {
1876         u8 action_type[0x4];
1877         u8 field[0xc];
1878         u8 reserved_at_10[0x3];
1879         u8 offset[0x5];
1880         u8 reserved_at_18[0x3];
1881         u8 length[0x5];
1882         u8 data[0x20];
1883 };
1884
1885 struct mlx5_ifc_query_hca_cap_out_bits {
1886         u8 status[0x8];
1887         u8 reserved_at_8[0x18];
1888         u8 syndrome[0x20];
1889         u8 reserved_at_40[0x40];
1890         union mlx5_ifc_hca_cap_union_bits capability;
1891 };
1892
1893 struct mlx5_ifc_query_hca_cap_in_bits {
1894         u8 opcode[0x10];
1895         u8 reserved_at_10[0x10];
1896         u8 reserved_at_20[0x10];
1897         u8 op_mod[0x10];
1898         u8 reserved_at_40[0x40];
1899 };
1900
1901 struct mlx5_ifc_mac_address_layout_bits {
1902         u8 reserved_at_0[0x10];
1903         u8 mac_addr_47_32[0x10];
1904         u8 mac_addr_31_0[0x20];
1905 };
1906
1907 struct mlx5_ifc_nic_vport_context_bits {
1908         u8 reserved_at_0[0x5];
1909         u8 min_wqe_inline_mode[0x3];
1910         u8 reserved_at_8[0x15];
1911         u8 disable_mc_local_lb[0x1];
1912         u8 disable_uc_local_lb[0x1];
1913         u8 roce_en[0x1];
1914         u8 arm_change_event[0x1];
1915         u8 reserved_at_21[0x1a];
1916         u8 event_on_mtu[0x1];
1917         u8 event_on_promisc_change[0x1];
1918         u8 event_on_vlan_change[0x1];
1919         u8 event_on_mc_address_change[0x1];
1920         u8 event_on_uc_address_change[0x1];
1921         u8 reserved_at_40[0xc];
1922         u8 affiliation_criteria[0x4];
1923         u8 affiliated_vhca_id[0x10];
1924         u8 reserved_at_60[0xd0];
1925         u8 mtu[0x10];
1926         u8 system_image_guid[0x40];
1927         u8 port_guid[0x40];
1928         u8 node_guid[0x40];
1929         u8 reserved_at_200[0x140];
1930         u8 qkey_violation_counter[0x10];
1931         u8 reserved_at_350[0x430];
1932         u8 promisc_uc[0x1];
1933         u8 promisc_mc[0x1];
1934         u8 promisc_all[0x1];
1935         u8 reserved_at_783[0x2];
1936         u8 allowed_list_type[0x3];
1937         u8 reserved_at_788[0xc];
1938         u8 allowed_list_size[0xc];
1939         struct mlx5_ifc_mac_address_layout_bits permanent_address;
1940         u8 reserved_at_7e0[0x20];
1941 };
1942
1943 struct mlx5_ifc_query_nic_vport_context_out_bits {
1944         u8 status[0x8];
1945         u8 reserved_at_8[0x18];
1946         u8 syndrome[0x20];
1947         u8 reserved_at_40[0x40];
1948         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
1949 };
1950
1951 struct mlx5_ifc_query_nic_vport_context_in_bits {
1952         u8 opcode[0x10];
1953         u8 reserved_at_10[0x10];
1954         u8 reserved_at_20[0x10];
1955         u8 op_mod[0x10];
1956         u8 other_vport[0x1];
1957         u8 reserved_at_41[0xf];
1958         u8 vport_number[0x10];
1959         u8 reserved_at_60[0x5];
1960         u8 allowed_list_type[0x3];
1961         u8 reserved_at_68[0x18];
1962 };
1963
1964 struct mlx5_ifc_tisc_bits {
1965         u8 strict_lag_tx_port_affinity[0x1];
1966         u8 reserved_at_1[0x3];
1967         u8 lag_tx_port_affinity[0x04];
1968         u8 reserved_at_8[0x4];
1969         u8 prio[0x4];
1970         u8 reserved_at_10[0x10];
1971         u8 reserved_at_20[0x100];
1972         u8 reserved_at_120[0x8];
1973         u8 transport_domain[0x18];
1974         u8 reserved_at_140[0x8];
1975         u8 underlay_qpn[0x18];
1976         u8 reserved_at_160[0x3a0];
1977 };
1978
1979 struct mlx5_ifc_query_tis_out_bits {
1980         u8 status[0x8];
1981         u8 reserved_at_8[0x18];
1982         u8 syndrome[0x20];
1983         u8 reserved_at_40[0x40];
1984         struct mlx5_ifc_tisc_bits tis_context;
1985 };
1986
1987 struct mlx5_ifc_query_tis_in_bits {
1988         u8 opcode[0x10];
1989         u8 reserved_at_10[0x10];
1990         u8 reserved_at_20[0x10];
1991         u8 op_mod[0x10];
1992         u8 reserved_at_40[0x8];
1993         u8 tisn[0x18];
1994         u8 reserved_at_60[0x20];
1995 };
1996
1997 struct mlx5_ifc_alloc_transport_domain_out_bits {
1998         u8 status[0x8];
1999         u8 reserved_at_8[0x18];
2000         u8 syndrome[0x20];
2001         u8 reserved_at_40[0x8];
2002         u8 transport_domain[0x18];
2003         u8 reserved_at_60[0x20];
2004 };
2005
2006 struct mlx5_ifc_alloc_transport_domain_in_bits {
2007         u8 opcode[0x10];
2008         u8 reserved_at_10[0x10];
2009         u8 reserved_at_20[0x10];
2010         u8 op_mod[0x10];
2011         u8 reserved_at_40[0x40];
2012 };
2013
2014 enum {
2015         MLX5_WQ_TYPE_LINKED_LIST                = 0x0,
2016         MLX5_WQ_TYPE_CYCLIC                     = 0x1,
2017         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ    = 0x2,
2018         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ         = 0x3,
2019 };
2020
2021 enum {
2022         MLX5_WQ_END_PAD_MODE_NONE  = 0x0,
2023         MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
2024 };
2025
2026 struct mlx5_ifc_wq_bits {
2027         u8 wq_type[0x4];
2028         u8 wq_signature[0x1];
2029         u8 end_padding_mode[0x2];
2030         u8 cd_slave[0x1];
2031         u8 reserved_at_8[0x18];
2032         u8 hds_skip_first_sge[0x1];
2033         u8 log2_hds_buf_size[0x3];
2034         u8 reserved_at_24[0x7];
2035         u8 page_offset[0x5];
2036         u8 lwm[0x10];
2037         u8 reserved_at_40[0x8];
2038         u8 pd[0x18];
2039         u8 reserved_at_60[0x8];
2040         u8 uar_page[0x18];
2041         u8 dbr_addr[0x40];
2042         u8 hw_counter[0x20];
2043         u8 sw_counter[0x20];
2044         u8 reserved_at_100[0xc];
2045         u8 log_wq_stride[0x4];
2046         u8 reserved_at_110[0x3];
2047         u8 log_wq_pg_sz[0x5];
2048         u8 reserved_at_118[0x3];
2049         u8 log_wq_sz[0x5];
2050         u8 dbr_umem_valid[0x1];
2051         u8 wq_umem_valid[0x1];
2052         u8 reserved_at_122[0x1];
2053         u8 log_hairpin_num_packets[0x5];
2054         u8 reserved_at_128[0x3];
2055         u8 log_hairpin_data_sz[0x5];
2056         u8 reserved_at_130[0x4];
2057         u8 single_wqe_log_num_of_strides[0x4];
2058         u8 two_byte_shift_en[0x1];
2059         u8 reserved_at_139[0x4];
2060         u8 single_stride_log_num_of_bytes[0x3];
2061         u8 dbr_umem_id[0x20];
2062         u8 wq_umem_id[0x20];
2063         u8 wq_umem_offset[0x40];
2064         u8 reserved_at_1c0[0x440];
2065 };
2066
2067 enum {
2068         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2069         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2070 };
2071
2072 enum {
2073         MLX5_RQC_STATE_RST  = 0x0,
2074         MLX5_RQC_STATE_RDY  = 0x1,
2075         MLX5_RQC_STATE_ERR  = 0x3,
2076 };
2077
2078 struct mlx5_ifc_rqc_bits {
2079         u8 rlky[0x1];
2080         u8 delay_drop_en[0x1];
2081         u8 scatter_fcs[0x1];
2082         u8 vsd[0x1];
2083         u8 mem_rq_type[0x4];
2084         u8 state[0x4];
2085         u8 reserved_at_c[0x1];
2086         u8 flush_in_error_en[0x1];
2087         u8 hairpin[0x1];
2088         u8 reserved_at_f[0xB];
2089         u8 ts_format[0x02];
2090         u8 reserved_at_1c[0x4];
2091         u8 reserved_at_20[0x8];
2092         u8 user_index[0x18];
2093         u8 reserved_at_40[0x8];
2094         u8 cqn[0x18];
2095         u8 counter_set_id[0x8];
2096         u8 reserved_at_68[0x18];
2097         u8 reserved_at_80[0x8];
2098         u8 rmpn[0x18];
2099         u8 reserved_at_a0[0x8];
2100         u8 hairpin_peer_sq[0x18];
2101         u8 reserved_at_c0[0x10];
2102         u8 hairpin_peer_vhca[0x10];
2103         u8 reserved_at_e0[0xa0];
2104         struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
2105 };
2106
2107 struct mlx5_ifc_create_rq_out_bits {
2108         u8 status[0x8];
2109         u8 reserved_at_8[0x18];
2110         u8 syndrome[0x20];
2111         u8 reserved_at_40[0x8];
2112         u8 rqn[0x18];
2113         u8 reserved_at_60[0x20];
2114 };
2115
2116 struct mlx5_ifc_create_rq_in_bits {
2117         u8 opcode[0x10];
2118         u8 uid[0x10];
2119         u8 reserved_at_20[0x10];
2120         u8 op_mod[0x10];
2121         u8 reserved_at_40[0xc0];
2122         struct mlx5_ifc_rqc_bits ctx;
2123 };
2124
2125 struct mlx5_ifc_modify_rq_out_bits {
2126         u8 status[0x8];
2127         u8 reserved_at_8[0x18];
2128         u8 syndrome[0x20];
2129         u8 reserved_at_40[0x40];
2130 };
2131
2132 struct mlx5_ifc_query_rq_out_bits {
2133         u8 status[0x8];
2134         u8 reserved_at_8[0x18];
2135         u8 syndrome[0x20];
2136         u8 reserved_at_40[0xc0];
2137         struct mlx5_ifc_rqc_bits rq_context;
2138 };
2139
2140 struct mlx5_ifc_query_rq_in_bits {
2141         u8 opcode[0x10];
2142         u8 reserved_at_10[0x10];
2143         u8 reserved_at_20[0x10];
2144         u8 op_mod[0x10];
2145         u8 reserved_at_40[0x8];
2146         u8 rqn[0x18];
2147         u8 reserved_at_60[0x20];
2148 };
2149
2150 struct mlx5_ifc_create_tis_out_bits {
2151         u8 status[0x8];
2152         u8 reserved_at_8[0x18];
2153         u8 syndrome[0x20];
2154         u8 reserved_at_40[0x8];
2155         u8 tisn[0x18];
2156         u8 reserved_at_60[0x20];
2157 };
2158
2159 struct mlx5_ifc_create_tis_in_bits {
2160         u8 opcode[0x10];
2161         u8 uid[0x10];
2162         u8 reserved_at_20[0x10];
2163         u8 op_mod[0x10];
2164         u8 reserved_at_40[0xc0];
2165         struct mlx5_ifc_tisc_bits ctx;
2166 };
2167
2168 enum {
2169         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
2170         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
2171         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
2172         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
2173 };
2174
2175 struct mlx5_ifc_modify_rq_in_bits {
2176         u8 opcode[0x10];
2177         u8 uid[0x10];
2178         u8 reserved_at_20[0x10];
2179         u8 op_mod[0x10];
2180         u8 rq_state[0x4];
2181         u8 reserved_at_44[0x4];
2182         u8 rqn[0x18];
2183         u8 reserved_at_60[0x20];
2184         u8 modify_bitmask[0x40];
2185         u8 reserved_at_c0[0x40];
2186         struct mlx5_ifc_rqc_bits ctx;
2187 };
2188
2189 enum {
2190         MLX5_L3_PROT_TYPE_IPV4 = 0,
2191         MLX5_L3_PROT_TYPE_IPV6 = 1,
2192 };
2193
2194 enum {
2195         MLX5_L4_PROT_TYPE_TCP = 0,
2196         MLX5_L4_PROT_TYPE_UDP = 1,
2197 };
2198
2199 enum {
2200         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
2201         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
2202         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
2203         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
2204         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
2205 };
2206
2207 struct mlx5_ifc_rx_hash_field_select_bits {
2208         u8 l3_prot_type[0x1];
2209         u8 l4_prot_type[0x1];
2210         u8 selected_fields[0x1e];
2211 };
2212
2213 enum {
2214         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2215         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2216 };
2217
2218 enum {
2219         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2220         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2221 };
2222
2223 enum {
2224         MLX5_RX_HASH_FN_NONE           = 0x0,
2225         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2226         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2227 };
2228
2229 enum {
2230         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
2231         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
2232 };
2233
2234 enum {
2235         MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4    = 0x0,
2236         MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2  = 0x1,
2237 };
2238
2239 struct mlx5_ifc_tirc_bits {
2240         u8 reserved_at_0[0x20];
2241         u8 disp_type[0x4];
2242         u8 reserved_at_24[0x1c];
2243         u8 reserved_at_40[0x40];
2244         u8 reserved_at_80[0x4];
2245         u8 lro_timeout_period_usecs[0x10];
2246         u8 lro_enable_mask[0x4];
2247         u8 lro_max_msg_sz[0x8];
2248         u8 reserved_at_a0[0x40];
2249         u8 reserved_at_e0[0x8];
2250         u8 inline_rqn[0x18];
2251         u8 rx_hash_symmetric[0x1];
2252         u8 reserved_at_101[0x1];
2253         u8 tunneled_offload_en[0x1];
2254         u8 reserved_at_103[0x5];
2255         u8 indirect_table[0x18];
2256         u8 rx_hash_fn[0x4];
2257         u8 reserved_at_124[0x2];
2258         u8 self_lb_block[0x2];
2259         u8 transport_domain[0x18];
2260         u8 rx_hash_toeplitz_key[10][0x20];
2261         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2262         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2263         u8 reserved_at_2c0[0x4c0];
2264 };
2265
2266 struct mlx5_ifc_create_tir_out_bits {
2267         u8 status[0x8];
2268         u8 reserved_at_8[0x18];
2269         u8 syndrome[0x20];
2270         u8 reserved_at_40[0x8];
2271         u8 tirn[0x18];
2272         u8 reserved_at_60[0x20];
2273 };
2274
2275 struct mlx5_ifc_create_tir_in_bits {
2276         u8 opcode[0x10];
2277         u8 uid[0x10];
2278         u8 reserved_at_20[0x10];
2279         u8 op_mod[0x10];
2280         u8 reserved_at_40[0xc0];
2281         struct mlx5_ifc_tirc_bits ctx;
2282 };
2283
2284 enum {
2285         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0,
2286         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1,
2287         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2,
2288         /* bit 3 - tunneled_offload_en modify not supported. */
2289         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4,
2290 };
2291
2292 struct mlx5_ifc_modify_tir_out_bits {
2293         u8 status[0x8];
2294         u8 reserved_at_8[0x18];
2295         u8 syndrome[0x20];
2296         u8 reserved_at_40[0x40];
2297 };
2298
2299 struct mlx5_ifc_modify_tir_in_bits {
2300         u8 opcode[0x10];
2301         u8 uid[0x10];
2302         u8 reserved_at_20[0x10];
2303         u8 op_mod[0x10];
2304         u8 reserved_at_40[0x8];
2305         u8 tirn[0x18];
2306         u8 reserved_at_60[0x20];
2307         u8 modify_bitmask[0x40];
2308         u8 reserved_at_c0[0x40];
2309         struct mlx5_ifc_tirc_bits ctx;
2310 };
2311
2312 enum {
2313         MLX5_INLINE_Q_TYPE_RQ = 0x0,
2314         MLX5_INLINE_Q_TYPE_VIRTQ = 0x1,
2315 };
2316
2317 struct mlx5_ifc_rq_num_bits {
2318         u8 reserved_at_0[0x8];
2319         u8 rq_num[0x18];
2320 };
2321
2322 struct mlx5_ifc_rqtc_bits {
2323         u8 reserved_at_0[0xa5];
2324         u8 list_q_type[0x3];
2325         u8 reserved_at_a8[0x8];
2326         u8 rqt_max_size[0x10];
2327         u8 reserved_at_c0[0x10];
2328         u8 rqt_actual_size[0x10];
2329         u8 reserved_at_e0[0x6a0];
2330         struct mlx5_ifc_rq_num_bits rq_num[];
2331 };
2332
2333 struct mlx5_ifc_create_rqt_out_bits {
2334         u8 status[0x8];
2335         u8 reserved_at_8[0x18];
2336         u8 syndrome[0x20];
2337         u8 reserved_at_40[0x8];
2338         u8 rqtn[0x18];
2339         u8 reserved_at_60[0x20];
2340 };
2341
2342 #ifdef PEDANTIC
2343 #pragma GCC diagnostic ignored "-Wpedantic"
2344 #endif
2345 struct mlx5_ifc_create_rqt_in_bits {
2346         u8 opcode[0x10];
2347         u8 uid[0x10];
2348         u8 reserved_at_20[0x10];
2349         u8 op_mod[0x10];
2350         u8 reserved_at_40[0xc0];
2351         struct mlx5_ifc_rqtc_bits rqt_context;
2352 };
2353
2354 struct mlx5_ifc_modify_rqt_in_bits {
2355         u8 opcode[0x10];
2356         u8 uid[0x10];
2357         u8 reserved_at_20[0x10];
2358         u8 op_mod[0x10];
2359         u8 reserved_at_40[0x8];
2360         u8 rqtn[0x18];
2361         u8 reserved_at_60[0x20];
2362         u8 modify_bitmask[0x40];
2363         u8 reserved_at_c0[0x40];
2364         struct mlx5_ifc_rqtc_bits rqt_context;
2365 };
2366 #ifdef PEDANTIC
2367 #pragma GCC diagnostic error "-Wpedantic"
2368 #endif
2369
2370 struct mlx5_ifc_modify_rqt_out_bits {
2371         u8 status[0x8];
2372         u8 reserved_at_8[0x18];
2373         u8 syndrome[0x20];
2374         u8 reserved_at_40[0x40];
2375 };
2376
2377 enum {
2378         MLX5_SQC_STATE_RST  = 0x0,
2379         MLX5_SQC_STATE_RDY  = 0x1,
2380         MLX5_SQC_STATE_ERR  = 0x3,
2381 };
2382
2383 struct mlx5_ifc_sqc_bits {
2384         u8 rlky[0x1];
2385         u8 cd_master[0x1];
2386         u8 fre[0x1];
2387         u8 flush_in_error_en[0x1];
2388         u8 allow_multi_pkt_send_wqe[0x1];
2389         u8 min_wqe_inline_mode[0x3];
2390         u8 state[0x4];
2391         u8 reg_umr[0x1];
2392         u8 allow_swp[0x1];
2393         u8 hairpin[0x1];
2394         u8 non_wire[0x1];
2395         u8 static_sq_wq[0x1];
2396         u8 reserved_at_11[0x9];
2397         u8 ts_format[0x02];
2398         u8 reserved_at_1c[0x4];
2399         u8 reserved_at_20[0x8];
2400         u8 user_index[0x18];
2401         u8 reserved_at_40[0x8];
2402         u8 cqn[0x18];
2403         u8 reserved_at_60[0x8];
2404         u8 hairpin_peer_rq[0x18];
2405         u8 reserved_at_80[0x10];
2406         u8 hairpin_peer_vhca[0x10];
2407         u8 reserved_at_a0[0x50];
2408         u8 packet_pacing_rate_limit_index[0x10];
2409         u8 tis_lst_sz[0x10];
2410         u8 reserved_at_110[0x10];
2411         u8 reserved_at_120[0x40];
2412         u8 reserved_at_160[0x8];
2413         u8 tis_num_0[0x18];
2414         struct mlx5_ifc_wq_bits wq;
2415 };
2416
2417 struct mlx5_ifc_query_sq_in_bits {
2418         u8 opcode[0x10];
2419         u8 reserved_at_10[0x10];
2420         u8 reserved_at_20[0x10];
2421         u8 op_mod[0x10];
2422         u8 reserved_at_40[0x8];
2423         u8 sqn[0x18];
2424         u8 reserved_at_60[0x20];
2425 };
2426
2427 struct mlx5_ifc_modify_sq_out_bits {
2428         u8 status[0x8];
2429         u8 reserved_at_8[0x18];
2430         u8 syndrome[0x20];
2431         u8 reserved_at_40[0x40];
2432 };
2433
2434 struct mlx5_ifc_modify_sq_in_bits {
2435         u8 opcode[0x10];
2436         u8 uid[0x10];
2437         u8 reserved_at_20[0x10];
2438         u8 op_mod[0x10];
2439         u8 sq_state[0x4];
2440         u8 reserved_at_44[0x4];
2441         u8 sqn[0x18];
2442         u8 reserved_at_60[0x20];
2443         u8 modify_bitmask[0x40];
2444         u8 reserved_at_c0[0x40];
2445         struct mlx5_ifc_sqc_bits ctx;
2446 };
2447
2448 struct mlx5_ifc_create_sq_out_bits {
2449         u8 status[0x8];
2450         u8 reserved_at_8[0x18];
2451         u8 syndrome[0x20];
2452         u8 reserved_at_40[0x8];
2453         u8 sqn[0x18];
2454         u8 reserved_at_60[0x20];
2455 };
2456
2457 struct mlx5_ifc_create_sq_in_bits {
2458         u8 opcode[0x10];
2459         u8 uid[0x10];
2460         u8 reserved_at_20[0x10];
2461         u8 op_mod[0x10];
2462         u8 reserved_at_40[0xc0];
2463         struct mlx5_ifc_sqc_bits ctx;
2464 };
2465
2466 enum {
2467         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
2468         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
2469         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
2470         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
2471         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
2472 };
2473
2474 struct mlx5_ifc_flow_meter_parameters_bits {
2475         u8 valid[0x1];
2476         u8 bucket_overflow[0x1];
2477         u8 start_color[0x2];
2478         u8 both_buckets_on_green[0x1];
2479         u8 meter_mode[0x2];
2480         u8 reserved_at_1[0x19];
2481         u8 reserved_at_2[0x20];
2482         u8 reserved_at_3[0x3];
2483         u8 cbs_exponent[0x5];
2484         u8 cbs_mantissa[0x8];
2485         u8 reserved_at_4[0x3];
2486         u8 cir_exponent[0x5];
2487         u8 cir_mantissa[0x8];
2488         u8 reserved_at_5[0x20];
2489         u8 reserved_at_6[0x3];
2490         u8 ebs_exponent[0x5];
2491         u8 ebs_mantissa[0x8];
2492         u8 reserved_at_7[0x3];
2493         u8 eir_exponent[0x5];
2494         u8 eir_mantissa[0x8];
2495         u8 reserved_at_8[0x60];
2496 };
2497 #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF)
2498 #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8
2499
2500 enum {
2501         MLX5_METER_MODE_IP_LEN = 0x0,
2502         MLX5_METER_MODE_L2_LEN = 0x1,
2503         MLX5_METER_MODE_L2_IPG_LEN = 0x2,
2504         MLX5_METER_MODE_PKT = 0x3,
2505 };
2506
2507 enum {
2508         MLX5_CQE_SIZE_64B = 0x0,
2509         MLX5_CQE_SIZE_128B = 0x1,
2510 };
2511
2512 struct mlx5_ifc_cqc_bits {
2513         u8 status[0x4];
2514         u8 as_notify[0x1];
2515         u8 initiator_src_dct[0x1];
2516         u8 dbr_umem_valid[0x1];
2517         u8 reserved_at_7[0x1];
2518         u8 cqe_sz[0x3];
2519         u8 cc[0x1];
2520         u8 reserved_at_c[0x1];
2521         u8 scqe_break_moderation_en[0x1];
2522         u8 oi[0x1];
2523         u8 cq_period_mode[0x2];
2524         u8 cqe_comp_en[0x1];
2525         u8 mini_cqe_res_format[0x2];
2526         u8 st[0x4];
2527         u8 reserved_at_18[0x1];
2528         u8 cqe_comp_layout[0x7];
2529         u8 dbr_umem_id[0x20];
2530         u8 reserved_at_40[0x14];
2531         u8 page_offset[0x6];
2532         u8 reserved_at_5a[0x2];
2533         u8 mini_cqe_res_format_ext[0x2];
2534         u8 cq_timestamp_format[0x2];
2535         u8 reserved_at_60[0x3];
2536         u8 log_cq_size[0x5];
2537         u8 uar_page[0x18];
2538         u8 reserved_at_80[0x4];
2539         u8 cq_period[0xc];
2540         u8 cq_max_count[0x10];
2541         u8 reserved_at_a0[0x18];
2542         u8 c_eqn[0x8];
2543         u8 reserved_at_c0[0x3];
2544         u8 log_page_size[0x5];
2545         u8 reserved_at_c8[0x18];
2546         u8 reserved_at_e0[0x20];
2547         u8 reserved_at_100[0x8];
2548         u8 last_notified_index[0x18];
2549         u8 reserved_at_120[0x8];
2550         u8 last_solicit_index[0x18];
2551         u8 reserved_at_140[0x8];
2552         u8 consumer_counter[0x18];
2553         u8 reserved_at_160[0x8];
2554         u8 producer_counter[0x18];
2555         u8 local_partition_id[0xc];
2556         u8 process_id[0x14];
2557         u8 reserved_at_1A0[0x20];
2558         u8 dbr_addr[0x40];
2559 };
2560
2561 struct mlx5_ifc_health_buffer_bits {
2562         u8 reserved_0[0x100];
2563         u8 assert_existptr[0x20];
2564         u8 assert_callra[0x20];
2565         u8 reserved_1[0x40];
2566         u8 fw_version[0x20];
2567         u8 hw_id[0x20];
2568         u8 reserved_2[0x20];
2569         u8 irisc_index[0x8];
2570         u8 synd[0x8];
2571         u8 ext_synd[0x10];
2572 };
2573
2574 struct mlx5_ifc_initial_seg_bits {
2575         u8 fw_rev_minor[0x10];
2576         u8 fw_rev_major[0x10];
2577         u8 cmd_interface_rev[0x10];
2578         u8 fw_rev_subminor[0x10];
2579         u8 reserved_0[0x40];
2580         u8 cmdq_phy_addr_63_32[0x20];
2581         u8 cmdq_phy_addr_31_12[0x14];
2582         u8 reserved_1[0x2];
2583         u8 nic_interface[0x2];
2584         u8 log_cmdq_size[0x4];
2585         u8 log_cmdq_stride[0x4];
2586         u8 command_doorbell_vector[0x20];
2587         u8 reserved_2[0xf00];
2588         u8 initializing[0x1];
2589         u8 nic_interface_supported[0x7];
2590         u8 reserved_4[0x18];
2591         struct mlx5_ifc_health_buffer_bits health_buffer;
2592         u8 no_dram_nic_offset[0x20];
2593         u8 reserved_5[0x6de0];
2594         u8 internal_timer_h[0x20];
2595         u8 internal_timer_l[0x20];
2596         u8 reserved_6[0x20];
2597         u8 reserved_7[0x1f];
2598         u8 clear_int[0x1];
2599         u8 health_syndrome[0x8];
2600         u8 health_counter[0x18];
2601         u8 reserved_8[0x17fc0];
2602 };
2603
2604 struct mlx5_ifc_create_cq_out_bits {
2605         u8 status[0x8];
2606         u8 reserved_at_8[0x18];
2607         u8 syndrome[0x20];
2608         u8 reserved_at_40[0x8];
2609         u8 cqn[0x18];
2610         u8 reserved_at_60[0x20];
2611 };
2612
2613 struct mlx5_ifc_create_cq_in_bits {
2614         u8 opcode[0x10];
2615         u8 uid[0x10];
2616         u8 reserved_at_20[0x10];
2617         u8 op_mod[0x10];
2618         u8 reserved_at_40[0x40];
2619         struct mlx5_ifc_cqc_bits cq_context;
2620         u8 cq_umem_offset[0x40];
2621         u8 cq_umem_id[0x20];
2622         u8 cq_umem_valid[0x1];
2623         u8 reserved_at_2e1[0x1f];
2624         u8 reserved_at_300[0x580];
2625         u8 pas[];
2626 };
2627
2628 enum {
2629         MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
2630         MLX5_GENERAL_OBJ_TYPE_DEK = 0x000c,
2631         MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
2632         MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
2633         MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d,
2634         MLX5_GENERAL_OBJ_TYPE_CREDENTIAL = 0x001e,
2635         MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN = 0x001f,
2636         MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,
2637         MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024,
2638         MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025,
2639         MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031,
2640 };
2641
2642 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
2643         u8 opcode[0x10];
2644         u8 reserved_at_10[0x20];
2645         u8 obj_type[0x10];
2646         u8 obj_id[0x20];
2647         u8 reserved_at_60[0x3];
2648         u8 log_obj_range[0x5];
2649         u8 reserved_at_58[0x18];
2650 };
2651
2652 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
2653         u8 status[0x8];
2654         u8 reserved_at_8[0x18];
2655         u8 syndrome[0x20];
2656         u8 obj_id[0x20];
2657         u8 reserved_at_60[0x20];
2658 };
2659
2660 struct mlx5_ifc_virtio_q_counters_bits {
2661         u8 modify_field_select[0x40];
2662         u8 reserved_at_40[0x40];
2663         u8 received_desc[0x40];
2664         u8 completed_desc[0x40];
2665         u8 error_cqes[0x20];
2666         u8 bad_desc_errors[0x20];
2667         u8 exceed_max_chain[0x20];
2668         u8 invalid_buffer[0x20];
2669         u8 reserved_at_180[0x50];
2670 };
2671
2672 struct mlx5_ifc_geneve_tlv_option_bits {
2673         u8 modify_field_select[0x40];
2674         u8 reserved_at_40[0x18];
2675         u8 geneve_option_fte_index[0x8];
2676         u8 option_class[0x10];
2677         u8 option_type[0x8];
2678         u8 reserved_at_78[0x3];
2679         u8 option_data_length[0x5];
2680         u8 reserved_at_80[0x180];
2681 };
2682
2683 struct mlx5_ifc_create_virtio_q_counters_in_bits {
2684         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2685         struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2686 };
2687
2688 struct mlx5_ifc_query_virtio_q_counters_out_bits {
2689         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2690         struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2691 };
2692
2693 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
2694         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2695         struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
2696 };
2697
2698 enum {
2699         MLX5_CRYPTO_KEY_SIZE_128b = 0x0,
2700         MLX5_CRYPTO_KEY_SIZE_256b = 0x1,
2701 };
2702
2703 enum {
2704         MLX5_CRYPTO_KEY_PURPOSE_TLS     = 0x1,
2705         MLX5_CRYPTO_KEY_PURPOSE_IPSEC   = 0x2,
2706         MLX5_CRYPTO_KEY_PURPOSE_AES_XTS = 0x3,
2707         MLX5_CRYPTO_KEY_PURPOSE_MACSEC  = 0x4,
2708         MLX5_CRYPTO_KEY_PURPOSE_GCM     = 0x5,
2709         MLX5_CRYPTO_KEY_PURPOSE_PSP     = 0x6,
2710 };
2711
2712 struct mlx5_ifc_dek_bits {
2713         u8 modify_field_select[0x40];
2714         u8 state[0x8];
2715         u8 reserved_at_48[0xc];
2716         u8 key_size[0x4];
2717         u8 has_keytag[0x1];
2718         u8 reserved_at_59[0x3];
2719         u8 key_purpose[0x4];
2720         u8 reserved_at_60[0x8];
2721         u8 pd[0x18];
2722         u8 reserved_at_80[0x100];
2723         u8 opaque[0x40];
2724         u8 reserved_at_1c0[0x40];
2725         u8 key[0x400];
2726         u8 reserved_at_600[0x200];
2727 };
2728
2729 struct mlx5_ifc_create_dek_in_bits {
2730         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2731         struct mlx5_ifc_dek_bits dek;
2732 };
2733
2734 struct mlx5_ifc_import_kek_bits {
2735         u8 modify_field_select[0x40];
2736         u8 state[0x8];
2737         u8 reserved_at_48[0xc];
2738         u8 key_size[0x4];
2739         u8 reserved_at_58[0x1a8];
2740         u8 key[0x400];
2741         u8 reserved_at_600[0x200];
2742 };
2743
2744 struct mlx5_ifc_create_import_kek_in_bits {
2745         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2746         struct mlx5_ifc_import_kek_bits import_kek;
2747 };
2748
2749 enum {
2750         MLX5_CREDENTIAL_ROLE_OFFICER = 0x0,
2751         MLX5_CREDENTIAL_ROLE_USER = 0x1,
2752 };
2753
2754 struct mlx5_ifc_credential_bits {
2755         u8 modify_field_select[0x40];
2756         u8 state[0x8];
2757         u8 reserved_at_48[0x10];
2758         u8 credential_role[0x8];
2759         u8 reserved_at_60[0x1a0];
2760         u8 credential[0x180];
2761         u8 reserved_at_380[0x480];
2762 };
2763
2764 struct mlx5_ifc_create_credential_in_bits {
2765         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2766         struct mlx5_ifc_credential_bits credential;
2767 };
2768
2769 struct mlx5_ifc_crypto_login_bits {
2770         u8 modify_field_select[0x40];
2771         u8 reserved_at_40[0x48];
2772         u8 credential_pointer[0x18];
2773         u8 reserved_at_a0[0x8];
2774         u8 session_import_kek_ptr[0x18];
2775         u8 reserved_at_c0[0x140];
2776         u8 credential[0x180];
2777         u8 reserved_at_380[0x480];
2778 };
2779
2780 struct mlx5_ifc_create_crypto_login_in_bits {
2781         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2782         struct mlx5_ifc_crypto_login_bits crypto_login;
2783 };
2784
2785 enum {
2786         MLX5_VIRTQ_STATE_INIT = 0,
2787         MLX5_VIRTQ_STATE_RDY = 1,
2788         MLX5_VIRTQ_STATE_SUSPEND = 2,
2789         MLX5_VIRTQ_STATE_ERROR = 3,
2790 };
2791
2792 enum {
2793         MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),
2794         MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),
2795         MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),
2796 };
2797
2798 struct mlx5_ifc_virtio_q_bits {
2799         u8 virtio_q_type[0x8];
2800         u8 reserved_at_8[0x5];
2801         u8 event_mode[0x3];
2802         u8 queue_index[0x10];
2803         u8 full_emulation[0x1];
2804         u8 virtio_version_1_0[0x1];
2805         u8 reserved_at_22[0x2];
2806         u8 offload_type[0x4];
2807         u8 event_qpn_or_msix[0x18];
2808         u8 doorbell_stride_idx[0x10];
2809         u8 queue_size[0x10];
2810         u8 device_emulation_id[0x20];
2811         u8 desc_addr[0x40];
2812         u8 used_addr[0x40];
2813         u8 available_addr[0x40];
2814         u8 virtio_q_mkey[0x20];
2815         u8 reserved_at_160[0x18];
2816         u8 error_type[0x8];
2817         u8 umem_1_id[0x20];
2818         u8 umem_1_size[0x20];
2819         u8 umem_1_offset[0x40];
2820         u8 umem_2_id[0x20];
2821         u8 umem_2_size[0x20];
2822         u8 umem_2_offset[0x40];
2823         u8 umem_3_id[0x20];
2824         u8 umem_3_size[0x20];
2825         u8 umem_3_offset[0x40];
2826         u8 counter_set_id[0x20];
2827         u8 reserved_at_320[0x8];
2828         u8 pd[0x18];
2829         u8 reserved_at_340[0x2];
2830         u8 queue_period_mode[0x2];
2831         u8 queue_period_us[0xc];
2832         u8 queue_max_count[0x10];
2833         u8 reserved_at_360[0xa0];
2834 };
2835
2836 struct mlx5_ifc_virtio_net_q_bits {
2837         u8 modify_field_select[0x40];
2838         u8 reserved_at_40[0x40];
2839         u8 tso_ipv4[0x1];
2840         u8 tso_ipv6[0x1];
2841         u8 tx_csum[0x1];
2842         u8 rx_csum[0x1];
2843         u8 reserved_at_84[0x6];
2844         u8 dirty_bitmap_dump_enable[0x1];
2845         u8 vhost_log_page[0x5];
2846         u8 reserved_at_90[0xc];
2847         u8 state[0x4];
2848         u8 reserved_at_a0[0x8];
2849         u8 tisn_or_qpn[0x18];
2850         u8 dirty_bitmap_mkey[0x20];
2851         u8 dirty_bitmap_size[0x20];
2852         u8 dirty_bitmap_addr[0x40];
2853         u8 hw_available_index[0x10];
2854         u8 hw_used_index[0x10];
2855         u8 reserved_at_160[0xa0];
2856         struct mlx5_ifc_virtio_q_bits virtio_q_context;
2857 };
2858
2859 struct mlx5_ifc_create_virtq_in_bits {
2860         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2861         struct mlx5_ifc_virtio_net_q_bits virtq;
2862 };
2863
2864 struct mlx5_ifc_query_virtq_out_bits {
2865         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2866         struct mlx5_ifc_virtio_net_q_bits virtq;
2867 };
2868
2869 struct mlx5_ifc_flow_hit_aso_bits {
2870         u8 modify_field_select[0x40];
2871         u8 reserved_at_40[0x48];
2872         u8 access_pd[0x18];
2873         u8 reserved_at_a0[0x160];
2874         u8 flag[0x200];
2875 };
2876
2877 struct mlx5_ifc_create_flow_hit_aso_in_bits {
2878         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2879         struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso;
2880 };
2881
2882 struct mlx5_ifc_flow_meter_aso_bits {
2883         u8 modify_field_select[0x40];
2884         u8 reserved_at_40[0x48];
2885         u8 access_pd[0x18];
2886         u8 reserved_at_a0[0x160];
2887         u8 parameters[0x200];
2888 };
2889
2890 struct mlx5_ifc_create_flow_meter_aso_in_bits {
2891         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2892         struct mlx5_ifc_flow_meter_aso_bits flow_meter_aso;
2893 };
2894
2895 struct mlx5_ifc_tcp_window_params_bits {
2896         u8 max_ack[0x20];
2897         u8 max_win[0x20];
2898         u8 reply_end[0x20];
2899         u8 sent_end[0x20];
2900 };
2901
2902 struct mlx5_ifc_conn_track_aso_bits {
2903         struct mlx5_ifc_tcp_window_params_bits reply_dir; /* End of DW3. */
2904         struct mlx5_ifc_tcp_window_params_bits original_dir; /* End of DW7. */
2905         u8 last_end[0x20]; /* End of DW8. */
2906         u8 last_ack[0x20]; /* End of DW9. */
2907         u8 last_seq[0x20]; /* End of DW10. */
2908         u8 last_win[0x10];
2909         u8 reserved_at_170[0xa];
2910         u8 last_dir[0x1];
2911         u8 last_index[0x5]; /* End of DW11. */
2912         u8 reserved_at_180[0x40]; /* End of DW13. */
2913         u8 reply_direction_tcp_scale[0x4];
2914         u8 reply_direction_tcp_close_initiated[0x1];
2915         u8 reply_direction_tcp_liberal_enabled[0x1];
2916         u8 reply_direction_tcp_data_unacked[0x1];
2917         u8 reply_direction_tcp_max_ack[0x1];
2918         u8 reserved_at_1c8[0x8];
2919         u8 original_direction_tcp_scale[0x4];
2920         u8 original_direction_tcp_close_initiated[0x1];
2921         u8 original_direction_tcp_liberal_enabled[0x1];
2922         u8 original_direction_tcp_data_unacked[0x1];
2923         u8 original_direction_tcp_max_ack[0x1];
2924         u8 reserved_at_1d8[0x8]; /* End of DW14. */
2925         u8 valid[0x1];
2926         u8 state[0x3];
2927         u8 freeze_track[0x1];
2928         u8 reserved_at_1e5[0xb];
2929         u8 reserved_at_1f0[0x1];
2930         u8 connection_assured[0x1];
2931         u8 sack_permitted[0x1];
2932         u8 challenged_acked[0x1];
2933         u8 heartbeat[0x1];
2934         u8 max_ack_window[0x3];
2935         u8 reserved_at_1f8[0x1];
2936         u8 retransmission_counter[0x3];
2937         u8 retranmission_limit_exceeded[0x1];
2938         u8 retranmission_limit[0x3]; /* End of DW15. */
2939 };
2940
2941 struct mlx5_ifc_conn_track_offload_bits {
2942         u8 modify_field_select[0x40];
2943         u8 reserved_at_40[0x40];
2944         u8 reserved_at_80[0x8];
2945         u8 conn_track_aso_access_pd[0x18];
2946         u8 reserved_at_a0[0x160];
2947         struct mlx5_ifc_conn_track_aso_bits conn_track_aso;
2948 };
2949
2950 struct mlx5_ifc_create_conn_track_aso_in_bits {
2951         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2952         struct mlx5_ifc_conn_track_offload_bits conn_track_offload;
2953 };
2954
2955 enum mlx5_access_aso_opc_mod {
2956         ASO_OPC_MOD_IPSEC = 0x0,
2957         ASO_OPC_MOD_CONNECTION_TRACKING = 0x1,
2958         ASO_OPC_MOD_POLICER = 0x2,
2959         ASO_OPC_MOD_RACE_AVOIDANCE = 0x3,
2960         ASO_OPC_MOD_FLOW_HIT = 0x4,
2961 };
2962
2963 #define ASO_CSEG_DATA_MASK_MODE_OFFSET  30
2964
2965 enum mlx5_aso_data_mask_mode {
2966         BITWISE_64BIT = 0x0,
2967         BYTEWISE_64BYTE = 0x1,
2968         CALCULATED_64BYTE = 0x2,
2969 };
2970
2971 #define ASO_CSEG_COND_0_OPER_OFFSET     20
2972 #define ASO_CSEG_COND_1_OPER_OFFSET     16
2973
2974 enum mlx5_aso_pre_cond_op {
2975         ASO_OP_ALWAYS_FALSE = 0x0,
2976         ASO_OP_ALWAYS_TRUE = 0x1,
2977         ASO_OP_EQUAL = 0x2,
2978         ASO_OP_NOT_EQUAL = 0x3,
2979         ASO_OP_GREATER_OR_EQUAL = 0x4,
2980         ASO_OP_LESSER_OR_EQUAL = 0x5,
2981         ASO_OP_LESSER = 0x6,
2982         ASO_OP_GREATER = 0x7,
2983         ASO_OP_CYCLIC_GREATER = 0x8,
2984         ASO_OP_CYCLIC_LESSER = 0x9,
2985 };
2986
2987 #define ASO_CSEG_COND_OPER_OFFSET       6
2988
2989 enum mlx5_aso_op {
2990         ASO_OPER_LOGICAL_AND = 0x0,
2991         ASO_OPER_LOGICAL_OR = 0x1,
2992 };
2993
2994 /* ASO WQE CTRL segment. */
2995 struct mlx5_aso_cseg {
2996         uint32_t va_h;
2997         uint32_t va_l_r;
2998         uint32_t lkey;
2999         uint32_t operand_masks;
3000         uint32_t condition_0_data;
3001         uint32_t condition_0_mask;
3002         uint32_t condition_1_data;
3003         uint32_t condition_1_mask;
3004         uint64_t bitwise_data;
3005         uint64_t data_mask;
3006 } __rte_packed;
3007
3008 /* A meter data segment - 2 per ASO WQE. */
3009 struct mlx5_aso_mtr_dseg {
3010         uint32_t v_bo_sc_bbog_mm;
3011         /*
3012          * bit 31: valid, 30: bucket overflow, 28-29: start color,
3013          * 27: both buckets on green, 24-25: meter mode.
3014          */
3015         uint32_t reserved;
3016         uint32_t cbs_cir;
3017         /*
3018          * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa,
3019          * bit 8-12: cir_exponent, bit 0-7 cir_mantissa.
3020          */
3021         uint32_t c_tokens;
3022         uint32_t ebs_eir;
3023         /*
3024          * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa,
3025          * bit 8-12: eir_exponent, bit 0-7 eir_mantissa.
3026          */
3027         uint32_t e_tokens;
3028         uint64_t timestamp;
3029 } __rte_packed;
3030
3031 #define ASO_DSEG_VALID_OFFSET 31
3032 #define ASO_DSEG_BO_OFFSET 30
3033 #define ASO_DSEG_SC_OFFSET 28
3034 #define ASO_DSEG_BBOG_OFFSET 27
3035 #define ASO_DSEG_MTR_MODE 24
3036 #define ASO_DSEG_CBS_EXP_OFFSET 24
3037 #define ASO_DSEG_CBS_MAN_OFFSET 16
3038 #define ASO_DSEG_XIR_EXP_MASK 0x1F
3039 #define ASO_DSEG_XIR_EXP_OFFSET 8
3040 #define ASO_DSEG_EBS_EXP_OFFSET 24
3041 #define ASO_DSEG_EBS_MAN_OFFSET 16
3042 #define ASO_DSEG_EXP_MASK 0x1F
3043 #define ASO_DSEG_MAN_MASK 0xFF
3044
3045 #define MLX5_ASO_WQE_DSEG_SIZE  0x40
3046 #define MLX5_ASO_METERS_PER_WQE 2
3047 #define MLX5_ASO_MTRS_PER_POOL 128
3048
3049 /* ASO WQE data segment. */
3050 struct mlx5_aso_dseg {
3051         union {
3052                 uint8_t data[MLX5_ASO_WQE_DSEG_SIZE];
3053                 struct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE];
3054         };
3055 } __rte_packed;
3056
3057 /* ASO WQE. */
3058 struct mlx5_aso_wqe {
3059         struct mlx5_wqe_cseg general_cseg;
3060         struct mlx5_aso_cseg aso_cseg;
3061         struct mlx5_aso_dseg aso_dseg;
3062 } __rte_packed;
3063
3064 enum {
3065         MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
3066 };
3067
3068 enum {
3069         MLX5_QP_ST_RC = 0x0,
3070 };
3071
3072 enum {
3073         MLX5_QP_PM_MIGRATED = 0x3,
3074 };
3075
3076 enum {
3077         MLX5_NON_ZERO_RQ = 0x0,
3078         MLX5_SRQ_RQ = 0x1,
3079         MLX5_CRQ_RQ = 0x2,
3080         MLX5_ZERO_LEN_RQ = 0x3,
3081 };
3082
3083 struct mlx5_ifc_ads_bits {
3084         u8 fl[0x1];
3085         u8 free_ar[0x1];
3086         u8 reserved_at_2[0xe];
3087         u8 pkey_index[0x10];
3088         u8 reserved_at_20[0x8];
3089         u8 grh[0x1];
3090         u8 mlid[0x7];
3091         u8 rlid[0x10];
3092         u8 ack_timeout[0x5];
3093         u8 reserved_at_45[0x3];
3094         u8 src_addr_index[0x8];
3095         u8 reserved_at_50[0x4];
3096         u8 stat_rate[0x4];
3097         u8 hop_limit[0x8];
3098         u8 reserved_at_60[0x4];
3099         u8 tclass[0x8];
3100         u8 flow_label[0x14];
3101         u8 rgid_rip[16][0x8];
3102         u8 reserved_at_100[0x4];
3103         u8 f_dscp[0x1];
3104         u8 f_ecn[0x1];
3105         u8 reserved_at_106[0x1];
3106         u8 f_eth_prio[0x1];
3107         u8 ecn[0x2];
3108         u8 dscp[0x6];
3109         u8 udp_sport[0x10];
3110         u8 dei_cfi[0x1];
3111         u8 eth_prio[0x3];
3112         u8 sl[0x4];
3113         u8 vhca_port_num[0x8];
3114         u8 rmac_47_32[0x10];
3115         u8 rmac_31_0[0x20];
3116 };
3117
3118 struct mlx5_ifc_qpc_bits {
3119         u8 state[0x4];
3120         u8 lag_tx_port_affinity[0x4];
3121         u8 st[0x8];
3122         u8 reserved_at_10[0x3];
3123         u8 pm_state[0x2];
3124         u8 reserved_at_15[0x1];
3125         u8 req_e2e_credit_mode[0x2];
3126         u8 offload_type[0x4];
3127         u8 end_padding_mode[0x2];
3128         u8 reserved_at_1e[0x2];
3129         u8 wq_signature[0x1];
3130         u8 block_lb_mc[0x1];
3131         u8 atomic_like_write_en[0x1];
3132         u8 latency_sensitive[0x1];
3133         u8 reserved_at_24[0x1];
3134         u8 drain_sigerr[0x1];
3135         u8 reserved_at_26[0x2];
3136         u8 pd[0x18];
3137         u8 mtu[0x3];
3138         u8 log_msg_max[0x5];
3139         u8 reserved_at_48[0x1];
3140         u8 log_rq_size[0x4];
3141         u8 log_rq_stride[0x3];
3142         u8 no_sq[0x1];
3143         u8 log_sq_size[0x4];
3144         u8 reserved_at_55[0x3];
3145         u8 ts_format[0x2];
3146         u8 reserved_at_5a[0x1];
3147         u8 rlky[0x1];
3148         u8 ulp_stateless_offload_mode[0x4];
3149         u8 counter_set_id[0x8];
3150         u8 uar_page[0x18];
3151         u8 reserved_at_80[0x8];
3152         u8 user_index[0x18];
3153         u8 reserved_at_a0[0x3];
3154         u8 log_page_size[0x5];
3155         u8 remote_qpn[0x18];
3156         struct mlx5_ifc_ads_bits primary_address_path;
3157         struct mlx5_ifc_ads_bits secondary_address_path;
3158         u8 log_ack_req_freq[0x4];
3159         u8 reserved_at_384[0x4];
3160         u8 log_sra_max[0x3];
3161         u8 reserved_at_38b[0x2];
3162         u8 retry_count[0x3];
3163         u8 rnr_retry[0x3];
3164         u8 reserved_at_393[0x1];
3165         u8 fre[0x1];
3166         u8 cur_rnr_retry[0x3];
3167         u8 cur_retry_count[0x3];
3168         u8 reserved_at_39b[0x5];
3169         u8 reserved_at_3a0[0x20];
3170         u8 reserved_at_3c0[0x8];
3171         u8 next_send_psn[0x18];
3172         u8 reserved_at_3e0[0x8];
3173         u8 cqn_snd[0x18];
3174         u8 reserved_at_400[0x8];
3175         u8 deth_sqpn[0x18];
3176         u8 reserved_at_420[0x20];
3177         u8 reserved_at_440[0x8];
3178         u8 last_acked_psn[0x18];
3179         u8 reserved_at_460[0x8];
3180         u8 ssn[0x18];
3181         u8 reserved_at_480[0x8];
3182         u8 log_rra_max[0x3];
3183         u8 reserved_at_48b[0x1];
3184         u8 atomic_mode[0x4];
3185         u8 rre[0x1];
3186         u8 rwe[0x1];
3187         u8 rae[0x1];
3188         u8 reserved_at_493[0x1];
3189         u8 page_offset[0x6];
3190         u8 reserved_at_49a[0x3];
3191         u8 cd_slave_receive[0x1];
3192         u8 cd_slave_send[0x1];
3193         u8 cd_master[0x1];
3194         u8 reserved_at_4a0[0x3];
3195         u8 min_rnr_nak[0x5];
3196         u8 next_rcv_psn[0x18];
3197         u8 reserved_at_4c0[0x8];
3198         u8 xrcd[0x18];
3199         u8 reserved_at_4e0[0x8];
3200         u8 cqn_rcv[0x18];
3201         u8 dbr_addr[0x40];
3202         u8 q_key[0x20];
3203         u8 reserved_at_560[0x5];
3204         u8 rq_type[0x3];
3205         u8 srqn_rmpn_xrqn[0x18];
3206         u8 reserved_at_580[0x8];
3207         u8 rmsn[0x18];
3208         u8 hw_sq_wqebb_counter[0x10];
3209         u8 sw_sq_wqebb_counter[0x10];
3210         u8 hw_rq_counter[0x20];
3211         u8 sw_rq_counter[0x20];
3212         u8 reserved_at_600[0x20];
3213         u8 reserved_at_620[0xf];
3214         u8 cgs[0x1];
3215         u8 cs_req[0x8];
3216         u8 cs_res[0x8];
3217         u8 dc_access_key[0x40];
3218         u8 reserved_at_680[0x3];
3219         u8 dbr_umem_valid[0x1];
3220         u8 reserved_at_684[0x9c];
3221         u8 dbr_umem_id[0x20];
3222 };
3223
3224 struct mlx5_ifc_create_qp_out_bits {
3225         u8 status[0x8];
3226         u8 reserved_at_8[0x18];
3227         u8 syndrome[0x20];
3228         u8 reserved_at_40[0x8];
3229         u8 qpn[0x18];
3230         u8 reserved_at_60[0x20];
3231 };
3232
3233 #ifdef PEDANTIC
3234 #pragma GCC diagnostic ignored "-Wpedantic"
3235 #endif
3236 struct mlx5_ifc_create_qp_in_bits {
3237         u8 opcode[0x10];
3238         u8 uid[0x10];
3239         u8 reserved_at_20[0x10];
3240         u8 op_mod[0x10];
3241         u8 reserved_at_40[0x40];
3242         u8 opt_param_mask[0x20];
3243         u8 reserved_at_a0[0x20];
3244         struct mlx5_ifc_qpc_bits qpc;
3245         u8 wq_umem_offset[0x40];
3246         u8 wq_umem_id[0x20];
3247         u8 wq_umem_valid[0x1];
3248         u8 reserved_at_861[0x1f];
3249         u8 pas[0][0x40];
3250 };
3251 #ifdef PEDANTIC
3252 #pragma GCC diagnostic error "-Wpedantic"
3253 #endif
3254
3255 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3256         u8 status[0x8];
3257         u8 reserved_at_8[0x18];
3258         u8 syndrome[0x20];
3259         u8 reserved_at_40[0x40];
3260 };
3261
3262 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3263         u8 opcode[0x10];
3264         u8 uid[0x10];
3265         u8 reserved_at_20[0x10];
3266         u8 op_mod[0x10];
3267         u8 reserved_at_40[0x8];
3268         u8 qpn[0x18];
3269         u8 reserved_at_60[0x20];
3270         u8 opt_param_mask[0x20];
3271         u8 reserved_at_a0[0x20];
3272         struct mlx5_ifc_qpc_bits qpc;
3273         u8 reserved_at_800[0x80];
3274 };
3275
3276 struct mlx5_ifc_sqd2rts_qp_out_bits {
3277         u8 status[0x8];
3278         u8 reserved_at_8[0x18];
3279         u8 syndrome[0x20];
3280         u8 reserved_at_40[0x40];
3281 };
3282
3283 struct mlx5_ifc_sqd2rts_qp_in_bits {
3284         u8 opcode[0x10];
3285         u8 uid[0x10];
3286         u8 reserved_at_20[0x10];
3287         u8 op_mod[0x10];
3288         u8 reserved_at_40[0x8];
3289         u8 qpn[0x18];
3290         u8 reserved_at_60[0x20];
3291         u8 opt_param_mask[0x20];
3292         u8 reserved_at_a0[0x20];
3293         struct mlx5_ifc_qpc_bits qpc;
3294         u8 reserved_at_800[0x80];
3295 };
3296
3297 struct mlx5_ifc_rts2rts_qp_out_bits {
3298         u8 status[0x8];
3299         u8 reserved_at_8[0x18];
3300         u8 syndrome[0x20];
3301         u8 reserved_at_40[0x40];
3302 };
3303
3304 struct mlx5_ifc_rts2rts_qp_in_bits {
3305         u8 opcode[0x10];
3306         u8 uid[0x10];
3307         u8 reserved_at_20[0x10];
3308         u8 op_mod[0x10];
3309         u8 reserved_at_40[0x8];
3310         u8 qpn[0x18];
3311         u8 reserved_at_60[0x20];
3312         u8 opt_param_mask[0x20];
3313         u8 reserved_at_a0[0x20];
3314         struct mlx5_ifc_qpc_bits qpc;
3315         u8 reserved_at_800[0x80];
3316 };
3317
3318 struct mlx5_ifc_rtr2rts_qp_out_bits {
3319         u8 status[0x8];
3320         u8 reserved_at_8[0x18];
3321         u8 syndrome[0x20];
3322         u8 reserved_at_40[0x40];
3323 };
3324
3325 struct mlx5_ifc_rtr2rts_qp_in_bits {
3326         u8 opcode[0x10];
3327         u8 uid[0x10];
3328         u8 reserved_at_20[0x10];
3329         u8 op_mod[0x10];
3330         u8 reserved_at_40[0x8];
3331         u8 qpn[0x18];
3332         u8 reserved_at_60[0x20];
3333         u8 opt_param_mask[0x20];
3334         u8 reserved_at_a0[0x20];
3335         struct mlx5_ifc_qpc_bits qpc;
3336         u8 reserved_at_800[0x80];
3337 };
3338
3339 struct mlx5_ifc_rst2init_qp_out_bits {
3340         u8 status[0x8];
3341         u8 reserved_at_8[0x18];
3342         u8 syndrome[0x20];
3343         u8 reserved_at_40[0x40];
3344 };
3345
3346 struct mlx5_ifc_rst2init_qp_in_bits {
3347         u8 opcode[0x10];
3348         u8 uid[0x10];
3349         u8 reserved_at_20[0x10];
3350         u8 op_mod[0x10];
3351         u8 reserved_at_40[0x8];
3352         u8 qpn[0x18];
3353         u8 reserved_at_60[0x20];
3354         u8 opt_param_mask[0x20];
3355         u8 reserved_at_a0[0x20];
3356         struct mlx5_ifc_qpc_bits qpc;
3357         u8 reserved_at_800[0x80];
3358 };
3359
3360 struct mlx5_ifc_init2rtr_qp_out_bits {
3361         u8 status[0x8];
3362         u8 reserved_at_8[0x18];
3363         u8 syndrome[0x20];
3364         u8 reserved_at_40[0x40];
3365 };
3366
3367 struct mlx5_ifc_init2rtr_qp_in_bits {
3368         u8 opcode[0x10];
3369         u8 uid[0x10];
3370         u8 reserved_at_20[0x10];
3371         u8 op_mod[0x10];
3372         u8 reserved_at_40[0x8];
3373         u8 qpn[0x18];
3374         u8 reserved_at_60[0x20];
3375         u8 opt_param_mask[0x20];
3376         u8 reserved_at_a0[0x20];
3377         struct mlx5_ifc_qpc_bits qpc;
3378         u8 reserved_at_800[0x80];
3379 };
3380
3381 struct mlx5_ifc_init2init_qp_out_bits {
3382         u8 status[0x8];
3383         u8 reserved_at_8[0x18];
3384         u8 syndrome[0x20];
3385         u8 reserved_at_40[0x40];
3386 };
3387
3388 struct mlx5_ifc_init2init_qp_in_bits {
3389         u8 opcode[0x10];
3390         u8 uid[0x10];
3391         u8 reserved_at_20[0x10];
3392         u8 op_mod[0x10];
3393         u8 reserved_at_40[0x8];
3394         u8 qpn[0x18];
3395         u8 reserved_at_60[0x20];
3396         u8 opt_param_mask[0x20];
3397         u8 reserved_at_a0[0x20];
3398         struct mlx5_ifc_qpc_bits qpc;
3399         u8 reserved_at_800[0x80];
3400 };
3401
3402 struct mlx5_ifc_dealloc_pd_out_bits {
3403         u8 status[0x8];
3404         u8 reserved_0[0x18];
3405         u8 syndrome[0x20];
3406         u8 reserved_1[0x40];
3407 };
3408
3409 struct mlx5_ifc_dealloc_pd_in_bits {
3410         u8 opcode[0x10];
3411         u8 reserved_0[0x10];
3412         u8 reserved_1[0x10];
3413         u8 op_mod[0x10];
3414         u8 reserved_2[0x8];
3415         u8 pd[0x18];
3416         u8 reserved_3[0x20];
3417 };
3418
3419 struct mlx5_ifc_alloc_pd_out_bits {
3420         u8 status[0x8];
3421         u8 reserved_0[0x18];
3422         u8 syndrome[0x20];
3423         u8 reserved_1[0x8];
3424         u8 pd[0x18];
3425         u8 reserved_2[0x20];
3426 };
3427
3428 struct mlx5_ifc_alloc_pd_in_bits {
3429         u8 opcode[0x10];
3430         u8 reserved_0[0x10];
3431         u8 reserved_1[0x10];
3432         u8 op_mod[0x10];
3433         u8 reserved_2[0x40];
3434 };
3435
3436 #ifdef PEDANTIC
3437 #pragma GCC diagnostic ignored "-Wpedantic"
3438 #endif
3439 struct mlx5_ifc_query_qp_out_bits {
3440         u8 status[0x8];
3441         u8 reserved_at_8[0x18];
3442         u8 syndrome[0x20];
3443         u8 reserved_at_40[0x40];
3444         u8 opt_param_mask[0x20];
3445         u8 reserved_at_a0[0x20];
3446         struct mlx5_ifc_qpc_bits qpc;
3447         u8 reserved_at_800[0x80];
3448         u8 pas[0][0x40];
3449 };
3450 #ifdef PEDANTIC
3451 #pragma GCC diagnostic error "-Wpedantic"
3452 #endif
3453
3454 struct mlx5_ifc_query_qp_in_bits {
3455         u8 opcode[0x10];
3456         u8 reserved_at_10[0x10];
3457         u8 reserved_at_20[0x10];
3458         u8 op_mod[0x10];
3459         u8 reserved_at_40[0x8];
3460         u8 qpn[0x18];
3461         u8 reserved_at_60[0x20];
3462 };
3463
3464 enum {
3465         MLX5_DATA_RATE = 0x0,
3466         MLX5_WQE_RATE = 0x1,
3467 };
3468
3469 struct mlx5_ifc_set_pp_rate_limit_context_bits {
3470         u8 rate_limit[0x20];
3471         u8 burst_upper_bound[0x20];
3472         u8 reserved_at_40[0xC];
3473         u8 rate_mode[0x4];
3474         u8 typical_packet_size[0x10];
3475         u8 reserved_at_60[0x120];
3476 };
3477
3478 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u
3479
3480 #ifdef PEDANTIC
3481 #pragma GCC diagnostic ignored "-Wpedantic"
3482 #endif
3483 struct mlx5_ifc_access_register_out_bits {
3484         u8 status[0x8];
3485         u8 reserved_at_8[0x18];
3486         u8 syndrome[0x20];
3487         u8 reserved_at_40[0x40];
3488         u8 register_data[0][0x20];
3489 };
3490
3491 struct mlx5_ifc_access_register_in_bits {
3492         u8 opcode[0x10];
3493         u8 reserved_at_10[0x10];
3494         u8 reserved_at_20[0x10];
3495         u8 op_mod[0x10];
3496         u8 reserved_at_40[0x10];
3497         u8 register_id[0x10];
3498         u8 argument[0x20];
3499         u8 register_data[0][0x20];
3500 };
3501 #ifdef PEDANTIC
3502 #pragma GCC diagnostic error "-Wpedantic"
3503 #endif
3504
3505 enum {
3506         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
3507         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
3508 };
3509
3510 enum {
3511         MLX5_REGISTER_ID_MTUTC  = 0x9055,
3512         MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002,
3513         MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003,
3514         MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004,
3515         MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005,
3516 };
3517
3518 struct mlx5_ifc_register_mtutc_bits {
3519         u8 time_stamp_mode[0x2];
3520         u8 time_stamp_state[0x2];
3521         u8 reserved_at_4[0x18];
3522         u8 operation[0x4];
3523         u8 freq_adjustment[0x20];
3524         u8 reserved_at_40[0x40];
3525         u8 utc_sec[0x20];
3526         u8 utc_nsec[0x20];
3527         u8 time_adjustment[0x20];
3528 };
3529
3530 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0
3531 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1
3532
3533 struct mlx5_ifc_crypto_operational_register_bits {
3534         u8 wrapped_crypto_operational[0x1];
3535         u8 reserved_at_1[0x1b];
3536         u8 kek_size[0x4];
3537         u8 reserved_at_20[0x20];
3538         u8 credential[0x140];
3539         u8 kek[0x100];
3540         u8 reserved_at_280[0x180];
3541 };
3542
3543 struct mlx5_ifc_crypto_commissioning_register_bits {
3544         u8 token[0x1]; /* TODO: add size after PRM update */
3545 };
3546
3547 struct mlx5_ifc_import_kek_handle_register_bits {
3548         struct mlx5_ifc_crypto_login_bits crypto_login_object;
3549         struct mlx5_ifc_import_kek_bits import_kek_object;
3550         u8 reserved_at_200[0x4];
3551         u8 write_operation[0x4];
3552         u8 import_kek_id[0x18];
3553         u8 reserved_at_220[0xe0];
3554 };
3555
3556 struct mlx5_ifc_credential_handle_register_bits {
3557         struct mlx5_ifc_crypto_login_bits crypto_login_object;
3558         struct mlx5_ifc_credential_bits credential_object;
3559         u8 reserved_at_200[0x4];
3560         u8 write_operation[0x4];
3561         u8 credential_id[0x18];
3562         u8 reserved_at_220[0xe0];
3563 };
3564
3565 enum {
3566         MLX5_REGISTER_ADD_OPERATION = 0x1,
3567         MLX5_REGISTER_DELETE_OPERATION = 0x2,
3568 };
3569
3570 struct mlx5_ifc_parse_graph_arc_bits {
3571         u8 start_inner_tunnel[0x1];
3572         u8 reserved_at_1[0x7];
3573         u8 arc_parse_graph_node[0x8];
3574         u8 compare_condition_value[0x10];
3575         u8 parse_graph_node_handle[0x20];
3576         u8 reserved_at_40[0x40];
3577 };
3578
3579 struct mlx5_ifc_parse_graph_flow_match_sample_bits {
3580         u8 flow_match_sample_en[0x1];
3581         u8 reserved_at_1[0x3];
3582         u8 flow_match_sample_offset_mode[0x4];
3583         u8 reserved_at_5[0x8];
3584         u8 flow_match_sample_field_offset[0x10];
3585         u8 reserved_at_32[0x4];
3586         u8 flow_match_sample_field_offset_shift[0x4];
3587         u8 flow_match_sample_field_base_offset[0x8];
3588         u8 reserved_at_48[0xd];
3589         u8 flow_match_sample_tunnel_mode[0x3];
3590         u8 flow_match_sample_field_offset_mask[0x20];
3591         u8 flow_match_sample_field_id[0x20];
3592 };
3593
3594 struct mlx5_ifc_parse_graph_flex_bits {
3595         u8 modify_field_select[0x40];
3596         u8 reserved_at_64[0x20];
3597         u8 header_length_base_value[0x10];
3598         u8 reserved_at_112[0x4];
3599         u8 header_length_field_shift[0x4];
3600         u8 reserved_at_120[0x4];
3601         u8 header_length_mode[0x4];
3602         u8 header_length_field_offset[0x10];
3603         u8 next_header_field_offset[0x10];
3604         u8 reserved_at_160[0x1b];
3605         u8 next_header_field_size[0x5];
3606         u8 header_length_field_mask[0x20];
3607         u8 reserved_at_224[0x20];
3608         struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8];
3609         struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8];
3610         struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8];
3611 };
3612
3613 struct mlx5_ifc_create_flex_parser_in_bits {
3614         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3615         struct mlx5_ifc_parse_graph_flex_bits flex;
3616 };
3617
3618 struct mlx5_ifc_create_flex_parser_out_bits {
3619         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3620         struct mlx5_ifc_parse_graph_flex_bits flex;
3621 };
3622
3623 struct mlx5_ifc_parse_graph_flex_out_bits {
3624         u8 status[0x8];
3625         u8 reserved_at_8[0x18];
3626         u8 syndrome[0x20];
3627         u8 reserved_at_40[0x40];
3628         struct mlx5_ifc_parse_graph_flex_bits capability;
3629 };
3630
3631 struct regexp_params_field_select_bits {
3632         u8 reserved_at_0[0x1e];
3633         u8 stop_engine[0x1];
3634         u8 db_umem_id[0x1];
3635 };
3636
3637 struct mlx5_ifc_regexp_params_bits {
3638         u8 reserved_at_0[0x1f];
3639         u8 stop_engine[0x1];
3640         u8 db_umem_id[0x20];
3641         u8 db_umem_offset[0x40];
3642         u8 reserved_at_80[0x100];
3643 };
3644
3645 struct mlx5_ifc_set_regexp_params_in_bits {
3646         u8 opcode[0x10];
3647         u8 uid[0x10];
3648         u8 reserved_at_20[0x10];
3649         u8 op_mod[0x10];
3650         u8 reserved_at_40[0x18];
3651         u8 engine_id[0x8];
3652         struct regexp_params_field_select_bits field_select;
3653         struct mlx5_ifc_regexp_params_bits regexp_params;
3654 };
3655
3656 struct mlx5_ifc_set_regexp_params_out_bits {
3657         u8 status[0x8];
3658         u8 reserved_at_8[0x18];
3659         u8 syndrome[0x20];
3660         u8 reserved_at_18[0x40];
3661 };
3662
3663 struct mlx5_ifc_query_regexp_params_in_bits {
3664         u8 opcode[0x10];
3665         u8 uid[0x10];
3666         u8 reserved_at_20[0x10];
3667         u8 op_mod[0x10];
3668         u8 reserved_at_40[0x18];
3669         u8 engine_id[0x8];
3670         u8 reserved[0x20];
3671 };
3672
3673 struct mlx5_ifc_query_regexp_params_out_bits {
3674         u8 status[0x8];
3675         u8 reserved_at_8[0x18];
3676         u8 syndrome[0x20];
3677         u8 reserved[0x40];
3678         struct mlx5_ifc_regexp_params_bits regexp_params;
3679 };
3680
3681 struct mlx5_ifc_set_regexp_register_in_bits {
3682         u8 opcode[0x10];
3683         u8 uid[0x10];
3684         u8 reserved_at_20[0x10];
3685         u8 op_mod[0x10];
3686         u8 reserved_at_40[0x18];
3687         u8 engine_id[0x8];
3688         u8 register_address[0x20];
3689         u8 register_data[0x20];
3690         u8 reserved[0x60];
3691 };
3692
3693 struct mlx5_ifc_set_regexp_register_out_bits {
3694         u8 status[0x8];
3695         u8 reserved_at_8[0x18];
3696         u8 syndrome[0x20];
3697         u8 reserved[0x40];
3698 };
3699
3700 struct mlx5_ifc_query_regexp_register_in_bits {
3701         u8 opcode[0x10];
3702         u8 uid[0x10];
3703         u8 reserved_at_20[0x10];
3704         u8 op_mod[0x10];
3705         u8 reserved_at_40[0x18];
3706         u8 engine_id[0x8];
3707         u8 register_address[0x20];
3708 };
3709
3710 struct mlx5_ifc_query_regexp_register_out_bits {
3711         u8 status[0x8];
3712         u8 reserved_at_8[0x18];
3713         u8 syndrome[0x20];
3714         u8 reserved[0x20];
3715         u8 register_data[0x20];
3716 };
3717
3718 /* Queue counters. */
3719 struct mlx5_ifc_alloc_q_counter_out_bits {
3720         u8 status[0x8];
3721         u8 reserved_at_8[0x18];
3722         u8 syndrome[0x20];
3723         u8 reserved_at_40[0x18];
3724         u8 counter_set_id[0x8];
3725         u8 reserved_at_60[0x20];
3726 };
3727
3728 struct mlx5_ifc_alloc_q_counter_in_bits {
3729         u8 opcode[0x10];
3730         u8 uid[0x10];
3731         u8 reserved_at_20[0x10];
3732         u8 op_mod[0x10];
3733         u8 reserved_at_40[0x40];
3734 };
3735
3736 struct mlx5_ifc_query_q_counter_out_bits {
3737         u8 status[0x8];
3738         u8 reserved_at_8[0x18];
3739         u8 syndrome[0x20];
3740         u8 reserved_at_40[0x40];
3741         u8 rx_write_requests[0x20];
3742         u8 reserved_at_a0[0x20];
3743         u8 rx_read_requests[0x20];
3744         u8 reserved_at_e0[0x20];
3745         u8 rx_atomic_requests[0x20];
3746         u8 reserved_at_120[0x20];
3747         u8 rx_dct_connect[0x20];
3748         u8 reserved_at_160[0x20];
3749         u8 out_of_buffer[0x20];
3750         u8 reserved_at_1a0[0x20];
3751         u8 out_of_sequence[0x20];
3752         u8 reserved_at_1e0[0x20];
3753         u8 duplicate_request[0x20];
3754         u8 reserved_at_220[0x20];
3755         u8 rnr_nak_retry_err[0x20];
3756         u8 reserved_at_260[0x20];
3757         u8 packet_seq_err[0x20];
3758         u8 reserved_at_2a0[0x20];
3759         u8 implied_nak_seq_err[0x20];
3760         u8 reserved_at_2e0[0x20];
3761         u8 local_ack_timeout_err[0x20];
3762         u8 reserved_at_320[0xa0];
3763         u8 resp_local_length_error[0x20];
3764         u8 req_local_length_error[0x20];
3765         u8 resp_local_qp_error[0x20];
3766         u8 local_operation_error[0x20];
3767         u8 resp_local_protection[0x20];
3768         u8 req_local_protection[0x20];
3769         u8 resp_cqe_error[0x20];
3770         u8 req_cqe_error[0x20];
3771         u8 req_mw_binding[0x20];
3772         u8 req_bad_response[0x20];
3773         u8 req_remote_invalid_request[0x20];
3774         u8 resp_remote_invalid_request[0x20];
3775         u8 req_remote_access_errors[0x20];
3776         u8 resp_remote_access_errors[0x20];
3777         u8 req_remote_operation_errors[0x20];
3778         u8 req_transport_retries_exceeded[0x20];
3779         u8 cq_overflow[0x20];
3780         u8 resp_cqe_flush_error[0x20];
3781         u8 req_cqe_flush_error[0x20];
3782         u8 reserved_at_620[0x1e0];
3783 };
3784
3785 struct mlx5_ifc_query_q_counter_in_bits {
3786         u8 opcode[0x10];
3787         u8 uid[0x10];
3788         u8 reserved_at_20[0x10];
3789         u8 op_mod[0x10];
3790         u8 reserved_at_40[0x80];
3791         u8 clear[0x1];
3792         u8 reserved_at_c1[0x1f];
3793         u8 reserved_at_e0[0x18];
3794         u8 counter_set_id[0x8];
3795 };
3796
3797 /* CQE format mask. */
3798 #define MLX5E_CQE_FORMAT_MASK 0xc
3799
3800 /* MPW opcode. */
3801 #define MLX5_OPC_MOD_MPW 0x01
3802
3803 /* Compressed Rx CQE structure. */
3804 struct mlx5_mini_cqe8 {
3805         union {
3806                 uint32_t rx_hash_result;
3807                 struct {
3808                         union {
3809                                 uint16_t checksum;
3810                                 uint16_t flow_tag_high;
3811                                 struct {
3812                                         uint8_t reserved;
3813                                         uint8_t hdr_type;
3814                                 };
3815                         };
3816                         uint16_t stride_idx;
3817                 };
3818                 struct {
3819                         uint16_t wqe_counter;
3820                         uint8_t  s_wqe_opcode;
3821                         uint8_t  reserved;
3822                 } s_wqe_info;
3823         };
3824         union {
3825                 uint32_t byte_cnt_flow;
3826                 uint32_t byte_cnt;
3827         };
3828 };
3829
3830 /* Mini CQE responder format. */
3831 enum {
3832         MLX5_CQE_RESP_FORMAT_HASH = 0x0,
3833         MLX5_CQE_RESP_FORMAT_CSUM = 0x1,
3834         MLX5_CQE_RESP_FORMAT_FTAG_STRIDX = 0x2,
3835         MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3,
3836         MLX5_CQE_RESP_FORMAT_L34H_STRIDX = 0x4,
3837 };
3838
3839 /* srTCM PRM flow meter parameters. */
3840 enum {
3841         MLX5_FLOW_COLOR_RED = 0,
3842         MLX5_FLOW_COLOR_YELLOW,
3843         MLX5_FLOW_COLOR_GREEN,
3844         MLX5_FLOW_COLOR_UNDEFINED,
3845 };
3846
3847 /* Maximum value of srTCM metering parameters. */
3848 #define MLX5_SRTCM_CBS_MAX (0xFF * (1ULL << 0x1F))
3849 #define MLX5_SRTCM_CIR_MAX (8 * (1ULL << 30) * 0xFF)
3850 #define MLX5_SRTCM_EBS_MAX 0
3851
3852 /* The bits meter color use. */
3853 #define MLX5_MTR_COLOR_BITS 8
3854
3855 /* The bit size of one register. */
3856 #define MLX5_REG_BITS 32
3857
3858 /* Idle bits for non-color usage in color register. */
3859 #define MLX5_MTR_IDLE_BITS_IN_COLOR_REG (MLX5_REG_BITS - MLX5_MTR_COLOR_BITS)
3860
3861 /* Length mode of dynamic flex parser graph node. */
3862 enum mlx5_parse_graph_node_len_mode {
3863         MLX5_GRAPH_NODE_LEN_FIXED = 0x0,
3864         MLX5_GRAPH_NODE_LEN_FIELD = 0x1,
3865         MLX5_GRAPH_NODE_LEN_BITMASK = 0x2,
3866 };
3867
3868 /* Offset mode of the samples of flex parser. */
3869 enum mlx5_parse_graph_flow_match_sample_offset_mode {
3870         MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0,
3871         MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1,
3872         MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2,
3873 };
3874
3875 /* Node index for an input / output arc of the flex parser graph. */
3876 enum mlx5_parse_graph_arc_node_index {
3877         MLX5_GRAPH_ARC_NODE_NULL = 0x0,
3878         MLX5_GRAPH_ARC_NODE_HEAD = 0x1,
3879         MLX5_GRAPH_ARC_NODE_MAC = 0x2,
3880         MLX5_GRAPH_ARC_NODE_IP = 0x3,
3881         MLX5_GRAPH_ARC_NODE_GRE = 0x4,
3882         MLX5_GRAPH_ARC_NODE_UDP = 0x5,
3883         MLX5_GRAPH_ARC_NODE_MPLS = 0x6,
3884         MLX5_GRAPH_ARC_NODE_TCP = 0x7,
3885         MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8,
3886         MLX5_GRAPH_ARC_NODE_GENEVE = 0x9,
3887         MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa,
3888         MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f,
3889 };
3890
3891 /**
3892  * Convert a user mark to flow mark.
3893  *
3894  * @param val
3895  *   Mark value to convert.
3896  *
3897  * @return
3898  *   Converted mark value.
3899  */
3900 static inline uint32_t
3901 mlx5_flow_mark_set(uint32_t val)
3902 {
3903         uint32_t ret;
3904
3905         /*
3906          * Add one to the user value to differentiate un-marked flows from
3907          * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
3908          * remains untouched.
3909          */
3910         if (val != MLX5_FLOW_MARK_DEFAULT)
3911                 ++val;
3912 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
3913         /*
3914          * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
3915          * word, byte-swapped by the kernel on little-endian systems. In this
3916          * case, left-shifting the resulting big-endian value ensures the
3917          * least significant 24 bits are retained when converting it back.
3918          */
3919         ret = rte_cpu_to_be_32(val) >> 8;
3920 #else
3921         ret = val;
3922 #endif
3923         return ret;
3924 }
3925
3926 /**
3927  * Convert a mark to user mark.
3928  *
3929  * @param val
3930  *   Mark value to convert.
3931  *
3932  * @return
3933  *   Converted mark value.
3934  */
3935 static inline uint32_t
3936 mlx5_flow_mark_get(uint32_t val)
3937 {
3938         /*
3939          * Subtract one from the retrieved value. It was added by
3940          * mlx5_flow_mark_set() to distinguish unmarked flows.
3941          */
3942 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
3943         return (val >> 8) - 1;
3944 #else
3945         return val - 1;
3946 #endif
3947 }
3948
3949 /**
3950  * Convert a timestamp format to configure settings in the queue context.
3951  *
3952  * @param val
3953  *   timestamp format supported by the queue.
3954  *
3955  * @return
3956  *   Converted timstamp format settings.
3957  */
3958 static inline uint32_t
3959 mlx5_ts_format_conv(uint32_t ts_format)
3960 {
3961         return ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ?
3962                         MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
3963                         MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
3964 }
3965
3966 #endif /* RTE_PMD_MLX5_PRM_H_ */