1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2016 6WIND S.A.
3 * Copyright 2016 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_PRM_H_
7 #define RTE_PMD_MLX5_PRM_H_
12 #include <rte_byteorder.h>
14 #include <mlx5_glue.h>
15 #include "mlx5_autoconf.h"
17 /* RSS hash key size. */
18 #define MLX5_RSS_HASH_KEY_LEN 40
20 /* Get CQE owner bit. */
21 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
24 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
27 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
29 /* Get CQE solicited event. */
30 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
32 /* Invalidate a CQE. */
33 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
35 /* Hardware index widths. */
36 #define MLX5_CQ_INDEX_WIDTH 24
37 #define MLX5_WQ_INDEX_WIDTH 16
39 /* WQE Segment sizes in bytes. */
40 #define MLX5_WSEG_SIZE 16u
41 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
42 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
43 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
45 /* WQE/WQEBB size in bytes. */
46 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
49 * Max size of a WQE session.
50 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
51 * the WQE size field in Control Segment is 6 bits wide.
53 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
56 * Default minimum number of Tx queues for inlining packets.
57 * If there are less queues as specified we assume we have
58 * no enough CPU resources (cycles) to perform inlining,
59 * the PCIe throughput is not supposed as bottleneck and
60 * inlining is disabled.
62 #define MLX5_INLINE_MAX_TXQS 8u
63 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
66 * Default packet length threshold to be inlined with
67 * enhanced MPW. If packet length exceeds the threshold
68 * the data are not inlined. Should be aligned in WQEBB
69 * boundary with accounting the title Control and Ethernet
72 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
73 MLX5_DSEG_MIN_INLINE_SIZE)
75 * Maximal inline data length sent with enhanced MPW.
76 * Is based on maximal WQE size.
78 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
79 MLX5_WQE_CSEG_SIZE - \
80 MLX5_WQE_ESEG_SIZE - \
81 MLX5_WQE_DSEG_SIZE + \
82 MLX5_DSEG_MIN_INLINE_SIZE)
84 * Minimal amount of packets to be sent with EMPW.
85 * This limits the minimal required size of sent EMPW.
86 * If there are no enough resources to built minimal
87 * EMPW the sending loop exits.
89 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
91 * Maximal amount of packets to be sent with EMPW.
92 * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
93 * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
94 * without CQE generation request, being multiplied by
95 * MLX5_TX_COMP_MAX_CQE it may cause significant latency
96 * in tx burst routine at the moment of freeing multiple mbufs.
98 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
99 #define MLX5_MPW_MAX_PACKETS 6
100 #define MLX5_MPW_INLINE_MAX_PACKETS 6
103 * Default packet length threshold to be inlined with
104 * ordinary SEND. Inlining saves the MR key search
105 * and extra PCIe data fetch transaction, but eats the
108 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
109 MLX5_ESEG_MIN_INLINE_SIZE - \
110 MLX5_WQE_CSEG_SIZE - \
111 MLX5_WQE_ESEG_SIZE - \
114 * Maximal inline data length sent with ordinary SEND.
115 * Is based on maximal WQE size.
117 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
118 MLX5_WQE_CSEG_SIZE - \
119 MLX5_WQE_ESEG_SIZE - \
120 MLX5_WQE_DSEG_SIZE + \
121 MLX5_ESEG_MIN_INLINE_SIZE)
123 /* Missed in mlx5dv.h, should define here. */
124 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW
125 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
128 #ifndef HAVE_MLX5_OPCODE_SEND_EN
129 #define MLX5_OPCODE_SEND_EN 0x17u
132 #ifndef HAVE_MLX5_OPCODE_WAIT
133 #define MLX5_OPCODE_WAIT 0x0fu
136 #ifndef HAVE_MLX5_OPCODE_ACCESS_ASO
137 #define MLX5_OPCODE_ACCESS_ASO 0x2du
140 /* CQE value to inform that VLAN is stripped. */
141 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
144 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
147 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
150 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
153 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
156 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
158 /* IP is fragmented. */
159 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
161 /* L2 header is valid. */
162 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
164 /* L3 header is valid. */
165 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
167 /* L4 header is valid. */
168 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
170 /* Outer packet, 0 IPv4, 1 IPv6. */
171 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
173 /* Tunnel packet bit in the CQE. */
174 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
176 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
177 #define MLX5_CQE_LRO_PUSH_MASK 0x40
179 /* Mask for L4 type in the CQE hdr_type_etc field. */
180 #define MLX5_CQE_L4_TYPE_MASK 0x70
182 /* The bit index of L4 type in CQE hdr_type_etc field. */
183 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
185 /* L4 type to indicate TCP packet without acknowledgment. */
186 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
188 /* L4 type to indicate TCP packet with acknowledgment. */
189 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
191 /* Inner L3 checksum offload (Tunneled packets only). */
192 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
194 /* Inner L4 checksum offload (Tunneled packets only). */
195 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
197 /* Outer L4 type is TCP. */
198 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5)
200 /* Outer L4 type is UDP. */
201 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5)
203 /* Outer L3 type is IPV4. */
204 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
206 /* Outer L3 type is IPV6. */
207 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
209 /* Inner L4 type is TCP. */
210 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
212 /* Inner L4 type is UDP. */
213 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
215 /* Inner L3 type is IPV4. */
216 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
218 /* Inner L3 type is IPV6. */
219 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
221 /* VLAN insertion flag. */
222 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
224 /* Data inline segment flag. */
225 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
227 /* Is flow mark valid. */
228 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
229 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
231 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
234 /* INVALID is used by packets matching no flow rules. */
235 #define MLX5_FLOW_MARK_INVALID 0
237 /* Maximum allowed value to mark a packet. */
238 #define MLX5_FLOW_MARK_MAX 0xfffff0
240 /* Default mark value used when none is provided. */
241 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
243 /* Default mark mask for metadata legacy mode. */
244 #define MLX5_FLOW_MARK_MASK 0xffffff
246 /* Byte length mask when mark is enable in miniCQE */
247 #define MLX5_LEN_WITH_MARK_MASK 0xffffff00
249 /* Maximum number of DS in WQE. Limited by 6-bit field. */
250 #define MLX5_DSEG_MAX 63
252 /* The completion mode offset in the WQE control segment line 2. */
253 #define MLX5_COMP_MODE_OFFSET 2
255 /* Amount of data bytes in minimal inline data segment. */
256 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
258 /* Amount of data bytes in minimal inline eth segment. */
259 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
261 /* Amount of data bytes after eth data segment. */
262 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
264 /* The maximum log value of segments per RQ WQE. */
265 #define MLX5_MAX_LOG_RQ_SEGS 5u
267 /* The alignment needed for WQ buffer. */
268 #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size()
270 /* The alignment needed for CQ buffer. */
271 #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size()
273 /* Completion mode. */
274 enum mlx5_completion_mode {
275 MLX5_COMP_ONLY_ERR = 0x0,
276 MLX5_COMP_ONLY_FIRST_ERR = 0x1,
277 MLX5_COMP_ALWAYS = 0x2,
278 MLX5_COMP_CQE_AND_EQE = 0x3,
285 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
288 /* WQE Control segment. */
289 struct mlx5_wqe_cseg {
294 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
297 * WQE CSEG opcode field size is 32 bits, divided:
299 * Bits 23:8 wqe_index
302 #define WQE_CSEG_OPC_MOD_OFFSET 24
303 #define WQE_CSEG_WQE_INDEX_OFFSET 8
305 /* Header of data segment. Minimal size Data Segment */
306 struct mlx5_wqe_dseg {
309 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
317 /* Subset of struct WQE Ethernet Segment. */
318 struct mlx5_wqe_eseg {
326 uint16_t inline_hdr_sz;
328 uint16_t inline_data;
335 uint32_t flow_metadata;
341 struct mlx5_wqe_qseg {
348 /* The title WQEBB, header of WQE. */
351 struct mlx5_wqe_cseg cseg;
354 struct mlx5_wqe_eseg eseg;
356 struct mlx5_wqe_dseg dseg[2];
357 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
361 /* WQE for Multi-Packet RQ. */
362 struct mlx5_wqe_mprq {
363 struct mlx5_wqe_srq_next_seg next_seg;
364 struct mlx5_wqe_data_seg dseg;
367 #define MLX5_MPRQ_LEN_MASK 0x000ffff
368 #define MLX5_MPRQ_LEN_SHIFT 0
369 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
370 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
371 #define MLX5_MPRQ_FILLER_MASK 0x80000000
372 #define MLX5_MPRQ_FILLER_SHIFT 31
374 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
376 /* CQ element structure - should be equal to the cache line size */
378 #if (RTE_CACHE_LINE_SIZE == 128)
384 uint8_t lro_tcppsh_abort_dupack;
386 uint16_t lro_tcp_win;
387 uint32_t lro_ack_seq_num;
388 uint32_t rx_hash_res;
389 uint8_t rx_hash_type;
393 uint16_t hdr_type_etc;
397 uint8_t user_index_bytes[3];
399 uint8_t user_index_hi;
400 uint16_t user_index_low;
403 uint32_t flow_table_metadata;
407 uint32_t sop_drop_qpn;
408 uint16_t wqe_counter;
415 uint32_t sop_drop_qpn;
416 uint16_t wqe_counter;
421 struct mlx5_wqe_rseg {
427 #define MLX5_UMRC_IF_OFFSET 31u
428 #define MLX5_UMRC_KO_OFFSET 16u
429 #define MLX5_UMRC_TO_BS_OFFSET 0u
431 struct mlx5_wqe_umr_cseg {
432 uint32_t if_cf_toe_cq_res;
438 struct mlx5_wqe_mkey_cseg {
439 uint32_t fr_res_af_sf;
445 uint32_t bsf_octword_size;
446 uint32_t reserved3[4];
447 uint32_t translations_octword_size;
453 MLX5_BSF_SIZE_16B = 0x0,
454 MLX5_BSF_SIZE_32B = 0x1,
455 MLX5_BSF_SIZE_64B = 0x2,
456 MLX5_BSF_SIZE_128B = 0x3,
460 MLX5_BSF_P_TYPE_SIGNATURE = 0x0,
461 MLX5_BSF_P_TYPE_CRYPTO = 0x1,
465 MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0,
466 MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1,
467 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2,
468 MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3,
472 MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0,
476 MLX5_BLOCK_SIZE_512B = 0x1,
477 MLX5_BLOCK_SIZE_520B = 0x2,
478 MLX5_BLOCK_SIZE_4096B = 0x3,
479 MLX5_BLOCK_SIZE_4160B = 0x4,
480 MLX5_BLOCK_SIZE_1MB = 0x5,
481 MLX5_BLOCK_SIZE_4048B = 0x6,
484 #define MLX5_BSF_SIZE_OFFSET 30
485 #define MLX5_BSF_P_TYPE_OFFSET 24
486 #define MLX5_ENCRYPTION_ORDER_OFFSET 16
487 #define MLX5_BLOCK_SIZE_OFFSET 24
489 struct mlx5_wqe_umr_bsf_seg {
491 * bs_bpt_eo_es contains:
492 * bs bsf_size 2 bits at MLX5_BSF_SIZE_OFFSET
493 * bpt bsf_p_type 2 bits at MLX5_BSF_P_TYPE_OFFSET
494 * eo encryption_order 4 bits at MLX5_ENCRYPTION_ORDER_OFFSET
495 * es encryption_standard 4 bits at offset 0
497 uint32_t bs_bpt_eo_es;
498 uint32_t raw_data_size;
501 * bsp crypto_block_size_pointer 8 bits at MLX5_BLOCK_SIZE_OFFSET
502 * res reserved 24 bits
506 uint8_t xts_initial_tweak[16];
509 * res reserved 8 bits
510 * dp dek_pointer 24 bits at offset 0
515 uint32_t reserved2[4];
519 #pragma GCC diagnostic ignored "-Wpedantic"
522 struct mlx5_umr_wqe {
523 struct mlx5_wqe_cseg ctr;
524 struct mlx5_wqe_umr_cseg ucseg;
525 struct mlx5_wqe_mkey_cseg mkc;
527 struct mlx5_wqe_dseg kseg[0];
528 struct mlx5_wqe_umr_bsf_seg bsf[0];
532 struct mlx5_rdma_write_wqe {
533 struct mlx5_wqe_cseg ctr;
534 struct mlx5_wqe_rseg rseg;
535 struct mlx5_wqe_dseg dseg[0];
539 #pragma GCC diagnostic error "-Wpedantic"
543 /* MMO metadata segment */
545 #define MLX5_OPCODE_MMO 0x2fu
546 #define MLX5_OPC_MOD_MMO_REGEX 0x4u
547 #define MLX5_OPC_MOD_MMO_COMP 0x2u
548 #define MLX5_OPC_MOD_MMO_DECOMP 0x3u
549 #define MLX5_OPC_MOD_MMO_DMA 0x1u
551 #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u
552 #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u
553 #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u
554 #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u
555 #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS)
556 #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u
557 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u
558 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u
560 struct mlx5_wqe_metadata_seg {
561 uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */
566 struct mlx5_gga_wqe {
570 uint32_t gga_ctrl1; /* ws 12-15, bs 16-19, dyns 20-23. */
572 uint32_t opaque_lkey;
573 uint64_t opaque_vaddr;
574 struct mlx5_wqe_dseg gather;
575 struct mlx5_wqe_dseg scatter;
578 struct mlx5_gga_compress_opaque {
581 uint32_t scattered_length;
582 uint32_t gathered_length;
583 uint64_t scatter_crc;
587 uint8_t reserved1[216];
590 struct mlx5_ifc_regexp_mmo_control_bits {
591 uint8_t reserved_at_31[0x2];
593 uint8_t reserved_at_28[0x1];
594 uint8_t subset_id_0[0xc];
595 uint8_t reserved_at_16[0x4];
596 uint8_t subset_id_1[0xc];
598 uint8_t subset_id_2[0xc];
599 uint8_t reserved_at_16_1[0x4];
600 uint8_t subset_id_3[0xc];
603 struct mlx5_ifc_regexp_metadata_bits {
604 uint8_t rof_version[0x10];
605 uint8_t latency_count[0x10];
606 uint8_t instruction_count[0x10];
607 uint8_t primary_thread_count[0x10];
608 uint8_t match_count[0x8];
609 uint8_t detected_match_count[0x8];
610 uint8_t status[0x10];
611 uint8_t job_id[0x20];
612 uint8_t reserved[0x80];
615 struct mlx5_ifc_regexp_match_tuple_bits {
616 uint8_t length[0x10];
617 uint8_t start_ptr[0x10];
618 uint8_t rule_id[0x20];
621 /* Adding direct verbs to data-path. */
623 /* CQ sequence number mask. */
624 #define MLX5_CQ_SQN_MASK 0x3
626 /* CQ sequence number index. */
627 #define MLX5_CQ_SQN_OFFSET 28
629 /* CQ doorbell index mask. */
630 #define MLX5_CI_MASK 0xffffff
632 /* CQ doorbell offset. */
633 #define MLX5_CQ_ARM_DB 1
635 /* CQ doorbell offset*/
636 #define MLX5_CQ_DOORBELL 0x20
638 /* CQE format value. */
639 #define MLX5_COMPRESSED 0x3
641 /* CQ doorbell cmd types. */
642 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24)
643 #define MLX5_CQ_DBR_CMD_ALL (0 << 24)
645 /* Action type of header modification. */
647 MLX5_MODIFICATION_TYPE_SET = 0x1,
648 MLX5_MODIFICATION_TYPE_ADD = 0x2,
649 MLX5_MODIFICATION_TYPE_COPY = 0x3,
652 /* The field of packet to be modified. */
653 enum mlx5_modification_field {
654 MLX5_MODI_OUT_NONE = -1,
655 MLX5_MODI_OUT_SMAC_47_16 = 1,
656 MLX5_MODI_OUT_SMAC_15_0,
657 MLX5_MODI_OUT_ETHERTYPE,
658 MLX5_MODI_OUT_DMAC_47_16,
659 MLX5_MODI_OUT_DMAC_15_0,
660 MLX5_MODI_OUT_IP_DSCP,
661 MLX5_MODI_OUT_TCP_FLAGS,
662 MLX5_MODI_OUT_TCP_SPORT,
663 MLX5_MODI_OUT_TCP_DPORT,
664 MLX5_MODI_OUT_IPV4_TTL,
665 MLX5_MODI_OUT_UDP_SPORT,
666 MLX5_MODI_OUT_UDP_DPORT,
667 MLX5_MODI_OUT_SIPV6_127_96,
668 MLX5_MODI_OUT_SIPV6_95_64,
669 MLX5_MODI_OUT_SIPV6_63_32,
670 MLX5_MODI_OUT_SIPV6_31_0,
671 MLX5_MODI_OUT_DIPV6_127_96,
672 MLX5_MODI_OUT_DIPV6_95_64,
673 MLX5_MODI_OUT_DIPV6_63_32,
674 MLX5_MODI_OUT_DIPV6_31_0,
677 MLX5_MODI_OUT_FIRST_VID,
678 MLX5_MODI_IN_SMAC_47_16 = 0x31,
679 MLX5_MODI_IN_SMAC_15_0,
680 MLX5_MODI_IN_ETHERTYPE,
681 MLX5_MODI_IN_DMAC_47_16,
682 MLX5_MODI_IN_DMAC_15_0,
683 MLX5_MODI_IN_IP_DSCP,
684 MLX5_MODI_IN_TCP_FLAGS,
685 MLX5_MODI_IN_TCP_SPORT,
686 MLX5_MODI_IN_TCP_DPORT,
687 MLX5_MODI_IN_IPV4_TTL,
688 MLX5_MODI_IN_UDP_SPORT,
689 MLX5_MODI_IN_UDP_DPORT,
690 MLX5_MODI_IN_SIPV6_127_96,
691 MLX5_MODI_IN_SIPV6_95_64,
692 MLX5_MODI_IN_SIPV6_63_32,
693 MLX5_MODI_IN_SIPV6_31_0,
694 MLX5_MODI_IN_DIPV6_127_96,
695 MLX5_MODI_IN_DIPV6_95_64,
696 MLX5_MODI_IN_DIPV6_63_32,
697 MLX5_MODI_IN_DIPV6_31_0,
700 MLX5_MODI_OUT_IPV6_HOPLIMIT,
701 MLX5_MODI_IN_IPV6_HOPLIMIT,
702 MLX5_MODI_META_DATA_REG_A,
703 MLX5_MODI_META_DATA_REG_B = 0x50,
704 MLX5_MODI_META_REG_C_0,
705 MLX5_MODI_META_REG_C_1,
706 MLX5_MODI_META_REG_C_2,
707 MLX5_MODI_META_REG_C_3,
708 MLX5_MODI_META_REG_C_4,
709 MLX5_MODI_META_REG_C_5,
710 MLX5_MODI_META_REG_C_6,
711 MLX5_MODI_META_REG_C_7,
712 MLX5_MODI_OUT_TCP_SEQ_NUM,
713 MLX5_MODI_IN_TCP_SEQ_NUM,
714 MLX5_MODI_OUT_TCP_ACK_NUM,
715 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
716 MLX5_MODI_GTP_TEID = 0x6E,
719 /* Total number of metadata reg_c's. */
720 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1)
736 /* Modification sub command. */
737 struct mlx5_modification_cmd {
741 unsigned int length:5;
742 unsigned int rsvd0:3;
743 unsigned int offset:5;
744 unsigned int rsvd1:3;
745 unsigned int field:12;
746 unsigned int action_type:4;
753 unsigned int rsvd2:8;
754 unsigned int dst_offset:5;
755 unsigned int rsvd3:3;
756 unsigned int dst_field:12;
757 unsigned int rsvd4:4;
762 typedef uint64_t u64;
763 typedef uint32_t u32;
764 typedef uint16_t u16;
767 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
768 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
769 #define __mlx5_bit_off(typ, fld) ((unsigned int)(uintptr_t) \
770 (&(__mlx5_nullp(typ)->fld)))
771 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
772 (__mlx5_bit_off(typ, fld) & 0x1f))
773 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
774 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
775 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
776 __mlx5_dw_bit_off(typ, fld))
777 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
778 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
779 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
780 (__mlx5_bit_off(typ, fld) & 0xf))
781 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
782 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \
783 __mlx5_16_bit_off(typ, fld))
784 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
785 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
786 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
787 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
789 /* insert a value to a struct */
790 #define MLX5_SET(typ, p, fld, v) \
793 *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \
794 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
795 __mlx5_dw_off(typ, fld))) & \
796 (~__mlx5_dw_mask(typ, fld))) | \
797 (((_v) & __mlx5_mask(typ, fld)) << \
798 __mlx5_dw_bit_off(typ, fld))); \
801 #define MLX5_SET64(typ, p, fld, v) \
803 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \
804 *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \
805 rte_cpu_to_be_64(v); \
808 #define MLX5_SET16(typ, p, fld, v) \
811 *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \
812 rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
813 __mlx5_16_off(typ, fld))) & \
814 (~__mlx5_16_mask(typ, fld))) | \
815 (((_v) & __mlx5_mask16(typ, fld)) << \
816 __mlx5_16_bit_off(typ, fld))); \
819 #define MLX5_GET_VOLATILE(typ, p, fld) \
820 ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\
821 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
822 __mlx5_mask(typ, fld))
823 #define MLX5_GET(typ, p, fld) \
824 ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\
825 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
826 __mlx5_mask(typ, fld))
827 #define MLX5_GET16(typ, p, fld) \
828 ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
829 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
830 __mlx5_mask16(typ, fld))
831 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \
832 __mlx5_64_off(typ, fld)))
833 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
834 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
836 struct mlx5_ifc_fte_match_set_misc_bits {
837 u8 gre_c_present[0x1];
838 u8 reserved_at_1[0x1];
839 u8 gre_k_present[0x1];
840 u8 gre_s_present[0x1];
841 u8 source_vhci_port[0x4];
843 u8 reserved_at_20[0x10];
844 u8 source_port[0x10];
845 u8 outer_second_prio[0x3];
846 u8 outer_second_cfi[0x1];
847 u8 outer_second_vid[0xc];
848 u8 inner_second_prio[0x3];
849 u8 inner_second_cfi[0x1];
850 u8 inner_second_vid[0xc];
851 u8 outer_second_cvlan_tag[0x1];
852 u8 inner_second_cvlan_tag[0x1];
853 u8 outer_second_svlan_tag[0x1];
854 u8 inner_second_svlan_tag[0x1];
855 u8 reserved_at_64[0xc];
856 u8 gre_protocol[0x10];
860 u8 reserved_at_b8[0x8];
862 u8 reserved_at_e4[0x6];
863 u8 geneve_tlv_option_0_exist[0x1];
865 u8 reserved_at_e0[0xc];
866 u8 outer_ipv6_flow_label[0x14];
867 u8 reserved_at_100[0xc];
868 u8 inner_ipv6_flow_label[0x14];
869 u8 reserved_at_120[0xa];
870 u8 geneve_opt_len[0x6];
871 u8 geneve_protocol_type[0x10];
872 u8 reserved_at_140[0xc0];
875 struct mlx5_ifc_ipv4_layout_bits {
876 u8 reserved_at_0[0x60];
880 struct mlx5_ifc_ipv6_layout_bits {
884 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
885 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
886 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
887 u8 reserved_at_0[0x80];
890 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
909 u8 reserved_at_c0[0x10];
913 u8 ipv4_checksum_ok[0x1];
914 u8 l4_checksum_ok[0x1];
915 u8 ip_ttl_hoplimit[0x8];
918 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
919 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
922 struct mlx5_ifc_fte_match_mpls_bits {
929 struct mlx5_ifc_fte_match_set_misc2_bits {
930 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
931 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
932 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
933 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
934 u8 metadata_reg_c_7[0x20];
935 u8 metadata_reg_c_6[0x20];
936 u8 metadata_reg_c_5[0x20];
937 u8 metadata_reg_c_4[0x20];
938 u8 metadata_reg_c_3[0x20];
939 u8 metadata_reg_c_2[0x20];
940 u8 metadata_reg_c_1[0x20];
941 u8 metadata_reg_c_0[0x20];
942 u8 metadata_reg_a[0x20];
943 u8 metadata_reg_b[0x20];
944 u8 reserved_at_1c0[0x40];
947 struct mlx5_ifc_fte_match_set_misc3_bits {
948 u8 inner_tcp_seq_num[0x20];
949 u8 outer_tcp_seq_num[0x20];
950 u8 inner_tcp_ack_num[0x20];
951 u8 outer_tcp_ack_num[0x20];
952 u8 reserved_at_auto1[0x8];
953 u8 outer_vxlan_gpe_vni[0x18];
954 u8 outer_vxlan_gpe_next_protocol[0x8];
955 u8 outer_vxlan_gpe_flags[0x8];
956 u8 reserved_at_a8[0x10];
957 u8 icmp_header_data[0x20];
958 u8 icmpv6_header_data[0x20];
963 u8 geneve_tlv_option_0_data[0x20];
965 u8 gtpu_msg_type[0x08];
966 u8 gtpu_msg_flags[0x08];
967 u8 reserved_at_170[0x10];
969 u8 gtpu_first_ext_dw_0[0x20];
971 u8 reserved_at_240[0x20];
975 struct mlx5_ifc_fte_match_set_misc4_bits {
976 u8 prog_sample_field_value_0[0x20];
977 u8 prog_sample_field_id_0[0x20];
978 u8 prog_sample_field_value_1[0x20];
979 u8 prog_sample_field_id_1[0x20];
980 u8 prog_sample_field_value_2[0x20];
981 u8 prog_sample_field_id_2[0x20];
982 u8 prog_sample_field_value_3[0x20];
983 u8 prog_sample_field_id_3[0x20];
984 u8 prog_sample_field_value_4[0x20];
985 u8 prog_sample_field_id_4[0x20];
986 u8 prog_sample_field_value_5[0x20];
987 u8 prog_sample_field_id_5[0x20];
988 u8 prog_sample_field_value_6[0x20];
989 u8 prog_sample_field_id_6[0x20];
990 u8 prog_sample_field_value_7[0x20];
991 u8 prog_sample_field_id_7[0x20];
994 struct mlx5_ifc_fte_match_set_misc5_bits {
995 u8 macsec_tag_0[0x20];
996 u8 macsec_tag_1[0x20];
997 u8 macsec_tag_2[0x20];
998 u8 macsec_tag_3[0x20];
999 u8 tunnel_header_0[0x20];
1000 u8 tunnel_header_1[0x20];
1001 u8 tunnel_header_2[0x20];
1002 u8 tunnel_header_3[0x20];
1007 struct mlx5_ifc_fte_match_param_bits {
1008 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1009 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1010 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1011 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1012 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1013 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1014 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
1016 * Add reserved bit to match the struct size with the size defined in PRM.
1017 * This extension is not required in Linux.
1019 #ifndef HAVE_INFINIBAND_VERBS_H
1020 u8 reserved_0[0x200];
1024 struct mlx5_ifc_dest_format_struct_bits {
1025 u8 destination_type[0x8];
1026 u8 destination_id[0x18];
1027 u8 reserved_0[0x20];
1031 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
1032 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
1033 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
1034 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
1035 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT,
1036 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT,
1037 MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT,
1041 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
1042 MLX5_CMD_OP_CREATE_MKEY = 0x200,
1043 MLX5_CMD_OP_CREATE_CQ = 0x400,
1044 MLX5_CMD_OP_CREATE_QP = 0x500,
1045 MLX5_CMD_OP_RST2INIT_QP = 0x502,
1046 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
1047 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
1048 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
1049 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
1050 MLX5_CMD_OP_QP_2ERR = 0x507,
1051 MLX5_CMD_OP_QP_2RST = 0x50A,
1052 MLX5_CMD_OP_QUERY_QP = 0x50B,
1053 MLX5_CMD_OP_SQD2RTS_QP = 0x50C,
1054 MLX5_CMD_OP_INIT2INIT_QP = 0x50E,
1055 MLX5_CMD_OP_SUSPEND_QP = 0x50F,
1056 MLX5_CMD_OP_RESUME_QP = 0x510,
1057 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
1058 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
1059 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
1060 MLX5_CMD_OP_ALLOC_PD = 0x800,
1061 MLX5_CMD_OP_DEALLOC_PD = 0x801,
1062 MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
1063 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
1064 MLX5_CMD_OP_QUERY_LAG = 0x842,
1065 MLX5_CMD_OP_CREATE_TIR = 0x900,
1066 MLX5_CMD_OP_MODIFY_TIR = 0x901,
1067 MLX5_CMD_OP_CREATE_SQ = 0X904,
1068 MLX5_CMD_OP_MODIFY_SQ = 0X905,
1069 MLX5_CMD_OP_CREATE_RQ = 0x908,
1070 MLX5_CMD_OP_MODIFY_RQ = 0x909,
1071 MLX5_CMD_OP_QUERY_RQ = 0x90b,
1072 MLX5_CMD_OP_CREATE_RMP = 0x90c,
1073 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
1074 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
1075 MLX5_CMD_OP_QUERY_RMP = 0x90f,
1076 MLX5_CMD_OP_CREATE_TIS = 0x912,
1077 MLX5_CMD_OP_QUERY_TIS = 0x915,
1078 MLX5_CMD_OP_CREATE_RQT = 0x916,
1079 MLX5_CMD_OP_MODIFY_RQT = 0x917,
1080 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
1081 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
1082 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
1083 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
1084 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
1085 MLX5_CMD_SET_REGEX_PARAMS = 0xb04,
1086 MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,
1087 MLX5_CMD_SET_REGEX_REGISTERS = 0xb06,
1088 MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
1089 MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c,
1093 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
1094 MLX5_MKC_ACCESS_MODE_KLM = 0x2,
1095 MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3,
1098 #define MLX5_ADAPTER_PAGE_SHIFT 12
1099 #define MLX5_LOG_RQ_STRIDE_SHIFT 4
1101 * The batch counter dcs id starts from 0x800000 and none batch counter
1102 * starts from 0. As currently, the counter is changed to be indexed by
1103 * pool index and the offset of the counter in the pool counters_raw array.
1104 * It means now the counter index is same for batch and none batch counter.
1105 * Add the 0x800000 batch counter offset to the batch counter index helps
1106 * indicate the counter index is from batch or none batch container pool.
1108 #define MLX5_CNT_BATCH_OFFSET 0x800000
1110 /* The counter batch query requires ID align with 4. */
1111 #define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4
1113 /* Flow counters. */
1114 struct mlx5_ifc_alloc_flow_counter_out_bits {
1116 u8 reserved_at_8[0x18];
1118 u8 flow_counter_id[0x20];
1119 u8 reserved_at_60[0x20];
1122 struct mlx5_ifc_alloc_flow_counter_in_bits {
1124 u8 reserved_at_10[0x10];
1125 u8 reserved_at_20[0x10];
1127 u8 flow_counter_id[0x20];
1128 u8 reserved_at_40[0x18];
1129 u8 flow_counter_bulk[0x8];
1132 struct mlx5_ifc_dealloc_flow_counter_out_bits {
1134 u8 reserved_at_8[0x18];
1136 u8 reserved_at_40[0x40];
1139 struct mlx5_ifc_dealloc_flow_counter_in_bits {
1141 u8 reserved_at_10[0x10];
1142 u8 reserved_at_20[0x10];
1144 u8 flow_counter_id[0x20];
1145 u8 reserved_at_60[0x20];
1148 struct mlx5_ifc_traffic_counter_bits {
1153 struct mlx5_ifc_query_flow_counter_out_bits {
1155 u8 reserved_at_8[0x18];
1157 u8 reserved_at_40[0x40];
1158 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
1161 struct mlx5_ifc_query_flow_counter_in_bits {
1163 u8 reserved_at_10[0x10];
1164 u8 reserved_at_20[0x10];
1166 u8 reserved_at_40[0x20];
1170 u8 dump_to_memory[0x1];
1171 u8 num_of_counters[0x1e];
1172 u8 flow_counter_id[0x20];
1175 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u
1176 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u
1178 struct mlx5_ifc_klm_bits {
1179 u8 byte_count[0x20];
1184 struct mlx5_ifc_mkc_bits {
1185 u8 reserved_at_0[0x1];
1187 u8 reserved_at_2[0x1];
1188 u8 access_mode_4_2[0x3];
1189 u8 reserved_at_6[0x7];
1190 u8 relaxed_ordering_write[0x1];
1191 u8 reserved_at_e[0x1];
1192 u8 small_fence_on_rdma_read_response[0x1];
1199 u8 access_mode_1_0[0x2];
1200 u8 reserved_at_18[0x8];
1203 u8 reserved_at_40[0x20];
1207 u8 reserved_at_63[0x2];
1208 u8 expected_sigerr_count[0x1];
1209 u8 reserved_at_66[0x1];
1212 u8 start_addr[0x40];
1214 u8 bsf_octword_size[0x20];
1215 u8 reserved_at_120[0x80];
1216 u8 translations_octword_size[0x20];
1217 u8 reserved_at_1c0[0x19];
1218 u8 relaxed_ordering_read[0x1];
1219 u8 reserved_at_1da[0x1];
1220 u8 log_page_size[0x5];
1221 u8 reserved_at_1e0[0x3];
1223 u8 reserved_at_1e5[0x1b];
1226 /* Range of values for MKEY context crypto_en field. */
1228 MLX5_MKEY_CRYPTO_DISABLED = 0x0,
1229 MLX5_MKEY_CRYPTO_ENABLED = 0x1,
1232 struct mlx5_ifc_create_mkey_out_bits {
1234 u8 reserved_at_8[0x18];
1236 u8 reserved_at_40[0x8];
1237 u8 mkey_index[0x18];
1238 u8 reserved_at_60[0x20];
1241 struct mlx5_ifc_create_mkey_in_bits {
1243 u8 reserved_at_10[0x10];
1244 u8 reserved_at_20[0x10];
1246 u8 reserved_at_40[0x20];
1248 u8 reserved_at_61[0x1f];
1249 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
1250 u8 reserved_at_280[0x80];
1251 u8 translations_octword_actual_size[0x20];
1252 u8 mkey_umem_id[0x20];
1253 u8 mkey_umem_offset[0x40];
1254 u8 reserved_at_380[0x500];
1255 u8 klm_pas_mtt[][0x20];
1259 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
1260 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
1261 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
1262 MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1,
1263 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,
1264 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
1265 MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP = 0x1C << 1,
1266 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1,
1269 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \
1270 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ)
1271 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \
1272 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS)
1273 #define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \
1274 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH)
1275 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \
1276 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO)
1277 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO \
1278 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO)
1279 #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \
1280 (1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT)
1281 #define MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD \
1282 (1ULL << MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD)
1283 #define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \
1284 (1ULL << MLX5_GENERAL_OBJ_TYPE_DEK)
1285 #define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \
1286 (1ULL << MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK)
1287 #define MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL \
1288 (1ULL << MLX5_GENERAL_OBJ_TYPE_CREDENTIAL)
1289 #define MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN \
1290 (1ULL << MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN)
1293 MLX5_HCA_CAP_OPMOD_GET_MAX = 0,
1294 MLX5_HCA_CAP_OPMOD_GET_CUR = 1,
1298 MLX5_CAP_INLINE_MODE_L2,
1299 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
1300 MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
1304 MLX5_INLINE_MODE_NONE,
1305 MLX5_INLINE_MODE_L2,
1306 MLX5_INLINE_MODE_IP,
1307 MLX5_INLINE_MODE_TCP_UDP,
1308 MLX5_INLINE_MODE_RESERVED4,
1309 MLX5_INLINE_MODE_INNER_L2,
1310 MLX5_INLINE_MODE_INNER_IP,
1311 MLX5_INLINE_MODE_INNER_TCP_UDP,
1314 /* The supported timestamp formats reported in HCA attributes. */
1316 MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR = 0x0,
1317 MLX5_HCA_CAP_TIMESTAMP_FORMAT_RT = 0x1,
1318 MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR_RT = 0x2,
1321 /* The timestamp format attributes to configure queues (RQ/SQ/QP). */
1323 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
1324 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1,
1325 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
1328 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
1329 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
1330 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
1331 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
1332 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
1333 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
1334 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
1335 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
1336 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
1337 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
1338 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
1340 /* The device steering logic format. */
1341 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 0x0
1342 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX 0x1
1344 struct mlx5_ifc_cmd_hca_cap_bits {
1345 u8 reserved_at_0[0x30];
1347 u8 reserved_at_40[0x20];
1348 u8 reserved_at_60[0x3];
1349 u8 log_regexp_scatter_gather_size[0x5];
1350 u8 reserved_at_68[0x3];
1351 u8 log_dma_mmo_size[0x5];
1352 u8 reserved_at_70[0x3];
1353 u8 log_compress_mmo_size[0x5];
1354 u8 reserved_at_78[0x3];
1355 u8 log_decompress_mmo_size[0x5];
1356 u8 log_max_srq_sz[0x8];
1357 u8 log_max_qp_sz[0x8];
1358 u8 reserved_at_90[0x9];
1359 u8 wqe_index_ignore_cap[0x1];
1360 u8 dynamic_qp_allocation[0x1];
1362 u8 reserved_at_a0[0x4];
1363 u8 regexp_num_of_engines[0x4];
1364 u8 reserved_at_a8[0x1];
1365 u8 reg_c_preserve[0x1];
1366 u8 reserved_at_aa[0x1];
1367 u8 log_max_srq[0x5];
1368 u8 reserved_at_b0[0xb];
1369 u8 scatter_fcs_w_decap_disable[0x1];
1370 u8 reserved_at_bc[0x4];
1371 u8 reserved_at_c0[0x8];
1372 u8 log_max_cq_sz[0x8];
1373 u8 reserved_at_d0[0x2];
1374 u8 access_register_user[0x1];
1375 u8 reserved_at_d3[0x8];
1377 u8 log_max_eq_sz[0x8];
1378 u8 relaxed_ordering_write[0x1];
1379 u8 relaxed_ordering_read[0x1];
1380 u8 log_max_mkey[0x6];
1381 u8 reserved_at_f0[0x8];
1382 u8 dump_fill_mkey[0x1];
1383 u8 reserved_at_f9[0x3];
1385 u8 max_indirection[0x8];
1386 u8 fixed_buffer_size[0x1];
1387 u8 log_max_mrw_sz[0x7];
1388 u8 force_teardown[0x1];
1389 u8 reserved_at_111[0x1];
1390 u8 log_max_bsf_list_size[0x6];
1391 u8 umr_extended_translation_offset[0x1];
1393 u8 log_max_klm_list_size[0x6];
1394 u8 non_wire_sq[0x1];
1395 u8 reserved_at_121[0x9];
1396 u8 log_max_ra_req_dc[0x6];
1397 u8 reserved_at_130[0x3];
1398 u8 log_max_static_sq_wq[0x5];
1399 u8 reserved_at_138[0x2];
1400 u8 log_max_ra_res_dc[0x6];
1401 u8 reserved_at_140[0xa];
1402 u8 log_max_ra_req_qp[0x6];
1403 u8 rtr2rts_qp_counters_set_id[0x1];
1404 u8 rts2rts_udp_sport[0x1];
1405 u8 rts2rts_lag_tx_port_affinity[0x1];
1407 u8 compress_min_block_size[0x4];
1408 u8 compress_mmo_sq[0x1];
1409 u8 decompress_mmo_sq[0x1];
1410 u8 log_max_ra_res_qp[0x6];
1412 u8 cc_query_allowed[0x1];
1413 u8 cc_modify_allowed[0x1];
1415 u8 cache_line_128byte[0x1];
1416 u8 reserved_at_165[0xa];
1418 u8 gid_table_size[0x10];
1419 u8 out_of_seq_cnt[0x1];
1420 u8 vport_counters[0x1];
1421 u8 retransmission_q_counters[0x1];
1423 u8 modify_rq_counter_set_id[0x1];
1424 u8 rq_delay_drop[0x1];
1426 u8 pkey_table_size[0x10];
1427 u8 vport_group_manager[0x1];
1428 u8 vhca_group_manager[0x1];
1431 u8 vnic_env_queue_counters[0x1];
1433 u8 nic_flow_table[0x1];
1434 u8 eswitch_manager[0x1];
1435 u8 device_memory[0x1];
1438 u8 local_ca_ack_delay[0x5];
1439 u8 port_module_event[0x1];
1440 u8 enhanced_error_q_counters[0x1];
1441 u8 ports_check[0x1];
1442 u8 reserved_at_1b3[0x1];
1443 u8 disable_link_up[0x1];
1447 u8 reserved_at_1c0[0x1];
1450 u8 log_max_msg[0x5];
1451 u8 reserved_at_1c8[0x4];
1453 u8 temp_warn_event[0x1];
1455 u8 general_notification_event[0x1];
1456 u8 reserved_at_1d3[0x2];
1460 u8 reserved_at_1d8[0x1];
1468 u8 stat_rate_support[0x10];
1469 u8 reserved_at_1f0[0xc];
1470 u8 cqe_version[0x4];
1471 u8 compact_address_vector[0x1];
1472 u8 striding_rq[0x1];
1473 u8 reserved_at_202[0x1];
1474 u8 ipoib_enhanced_offloads[0x1];
1475 u8 ipoib_basic_offloads[0x1];
1476 u8 reserved_at_205[0x1];
1477 u8 repeated_block_disabled[0x1];
1478 u8 umr_modify_entity_size_disabled[0x1];
1479 u8 umr_modify_atomic_disabled[0x1];
1480 u8 umr_indirect_mkey_disabled[0x1];
1482 u8 reserved_at_20c[0x3];
1483 u8 drain_sigerr[0x1];
1484 u8 cmdif_checksum[0x2];
1486 u8 reserved_at_213[0x1];
1487 u8 wq_signature[0x1];
1488 u8 sctr_data_cqe[0x1];
1489 u8 reserved_at_216[0x1];
1495 u8 eth_net_offloads[0x1];
1498 u8 reserved_at_21f[0x1];
1501 u8 cq_moderation[0x1];
1502 u8 reserved_at_223[0x3];
1503 u8 cq_eq_remap[0x1];
1505 u8 block_lb_mc[0x1];
1506 u8 reserved_at_229[0x1];
1507 u8 scqe_break_moderation[0x1];
1508 u8 cq_period_start_from_cqe[0x1];
1510 u8 reserved_at_22d[0x1];
1512 u8 vector_calc[0x1];
1513 u8 umr_ptr_rlky[0x1];
1515 u8 reserved_at_232[0x4];
1518 u8 set_deth_sqpn[0x1];
1519 u8 reserved_at_239[0x3];
1525 u8 reserved_at_241[0x8];
1526 u8 regexp_params[0x1];
1528 u8 port_selection_cap[0x1];
1529 u8 reserved_at_251[0x7];
1532 u8 driver_version[0x1];
1533 u8 pad_tx_eth_packet[0x1];
1534 u8 reserved_at_263[0x8];
1535 u8 log_bf_reg_size[0x5];
1536 u8 reserved_at_270[0xb];
1538 u8 num_lag_ports[0x4];
1539 u8 reserved_at_280[0x10];
1540 u8 max_wqe_sz_sq[0x10];
1541 u8 reserved_at_2a0[0xc];
1542 u8 regexp_mmo_sq[0x1];
1543 u8 regexp_version[0x3];
1544 u8 max_wqe_sz_rq[0x10];
1545 u8 max_flow_counter_31_16[0x10];
1546 u8 max_wqe_sz_sq_dc[0x10];
1547 u8 reserved_at_2e0[0x7];
1548 u8 max_qp_mcg[0x19];
1549 u8 reserved_at_300[0x10];
1550 u8 flow_counter_bulk_alloc[0x08];
1551 u8 log_max_mcg[0x8];
1552 u8 reserved_at_320[0x3];
1553 u8 log_max_transport_domain[0x5];
1554 u8 reserved_at_328[0x3];
1556 u8 reserved_at_330[0xb];
1557 u8 log_max_xrcd[0x5];
1558 u8 nic_receive_steering_discard[0x1];
1559 u8 receive_discard_vport_down[0x1];
1560 u8 transmit_discard_vport_down[0x1];
1561 u8 reserved_at_343[0x5];
1562 u8 log_max_flow_counter_bulk[0x8];
1563 u8 max_flow_counter_15_0[0x10];
1565 u8 flow_counters_dump[0x1];
1566 u8 reserved_at_360[0x1];
1568 u8 reserved_at_368[0x3];
1570 u8 reserved_at_370[0x3];
1571 u8 log_max_tir[0x5];
1572 u8 reserved_at_378[0x3];
1573 u8 log_max_tis[0x5];
1574 u8 basic_cyclic_rcv_wqe[0x1];
1575 u8 reserved_at_381[0x1];
1577 u8 log_max_rmp[0x5];
1578 u8 reserved_at_388[0x3];
1579 u8 log_max_rqt[0x5];
1580 u8 reserved_at_390[0x3];
1581 u8 log_max_rqt_size[0x5];
1582 u8 reserved_at_398[0x3];
1583 u8 log_max_tis_per_sq[0x5];
1584 u8 ext_stride_num_range[0x1];
1585 u8 reserved_at_3a1[0x2];
1586 u8 log_max_stride_sz_rq[0x5];
1587 u8 reserved_at_3a8[0x3];
1588 u8 log_min_stride_sz_rq[0x5];
1589 u8 reserved_at_3b0[0x3];
1590 u8 log_max_stride_sz_sq[0x5];
1591 u8 reserved_at_3b8[0x3];
1592 u8 log_min_stride_sz_sq[0x5];
1594 u8 reserved_at_3c1[0x2];
1595 u8 log_max_hairpin_queues[0x5];
1596 u8 reserved_at_3c8[0x3];
1597 u8 log_max_hairpin_wq_data_sz[0x5];
1598 u8 reserved_at_3d0[0x3];
1599 u8 log_max_hairpin_num_packets[0x5];
1600 u8 reserved_at_3d8[0x3];
1601 u8 log_max_wq_sz[0x5];
1602 u8 nic_vport_change_event[0x1];
1603 u8 disable_local_lb_uc[0x1];
1604 u8 disable_local_lb_mc[0x1];
1605 u8 log_min_hairpin_wq_data_sz[0x5];
1606 u8 reserved_at_3e8[0x3];
1607 u8 log_max_vlan_list[0x5];
1608 u8 reserved_at_3f0[0x3];
1609 u8 log_max_current_mc_list[0x5];
1610 u8 reserved_at_3f8[0x3];
1611 u8 log_max_current_uc_list[0x5];
1612 u8 general_obj_types[0x40];
1613 u8 sq_ts_format[0x2];
1614 u8 rq_ts_format[0x2];
1615 u8 steering_format_version[0x4];
1616 u8 reserved_at_448[0x18];
1617 u8 reserved_at_460[0x8];
1620 u8 reserved_at_46a[0x6];
1621 u8 max_num_eqs[0x10];
1622 u8 reserved_at_480[0x3];
1623 u8 log_max_l2_table[0x5];
1624 u8 reserved_at_488[0x8];
1625 u8 log_uar_page_sz[0x10];
1626 u8 reserved_at_4a0[0x20];
1627 u8 device_frequency_mhz[0x20];
1628 u8 device_frequency_khz[0x20];
1629 u8 reserved_at_500[0x20];
1630 u8 num_of_uars_per_page[0x20];
1631 u8 flex_parser_protocols[0x20];
1632 u8 max_geneve_tlv_options[0x8];
1633 u8 reserved_at_568[0x3];
1634 u8 max_geneve_tlv_option_data_len[0x5];
1635 u8 reserved_at_570[0x49];
1636 u8 mini_cqe_resp_l3_l4_tag[0x1];
1637 u8 mini_cqe_resp_flow_tag[0x1];
1638 u8 enhanced_cqe_compression[0x1];
1639 u8 mini_cqe_resp_stride_index[0x1];
1640 u8 cqe_128_always[0x1];
1641 u8 cqe_compression_128[0x1];
1642 u8 cqe_compression[0x1];
1643 u8 cqe_compression_timeout[0x10];
1644 u8 cqe_compression_max_num[0x10];
1645 u8 reserved_at_5e0[0x10];
1646 u8 tag_matching[0x1];
1647 u8 rndv_offload_rc[0x1];
1648 u8 rndv_offload_dc[0x1];
1649 u8 log_tag_matching_list_sz[0x5];
1650 u8 reserved_at_5f8[0x3];
1651 u8 log_max_xrq[0x5];
1652 u8 affiliate_nic_vport_criteria[0x8];
1653 u8 native_port_num[0x8];
1654 u8 num_vhca_ports[0x8];
1655 u8 reserved_at_618[0x6];
1656 u8 sw_owner_id[0x1];
1657 u8 reserved_at_61f[0x129];
1659 u8 regexp_mmo_qp[0x1];
1660 u8 compress_mmo_qp[0x1];
1661 u8 decompress_mmo_qp[0x1];
1662 u8 reserved_at_624[0xd4];
1665 struct mlx5_ifc_qos_cap_bits {
1666 u8 packet_pacing[0x1];
1667 u8 esw_scheduling[0x1];
1668 u8 esw_bw_share[0x1];
1669 u8 esw_rate_limit[0x1];
1670 u8 reserved_at_4[0x1];
1671 u8 packet_pacing_burst_bound[0x1];
1672 u8 packet_pacing_typical_size[0x1];
1673 u8 flow_meter_old[0x1];
1674 u8 reserved_at_8[0x8];
1675 u8 log_max_flow_meter[0x8];
1676 u8 flow_meter_reg_id[0x8];
1677 u8 wqe_rate_pp[0x1];
1678 u8 reserved_at_25[0x7];
1680 u8 reserved_at_2e[0x17];
1681 u8 packet_pacing_max_rate[0x20];
1682 u8 packet_pacing_min_rate[0x20];
1683 u8 reserved_at_80[0x10];
1684 u8 packet_pacing_rate_table_size[0x10];
1685 u8 esw_element_type[0x10];
1686 u8 esw_tsar_type[0x10];
1687 u8 reserved_at_c0[0x10];
1688 u8 max_qos_para_vport[0x10];
1689 u8 max_tsar_bw_share[0x20];
1690 u8 nic_element_type[0x10];
1691 u8 nic_tsar_type[0x10];
1692 u8 reserved_at_120[0x3];
1693 u8 log_meter_aso_granularity[0x5];
1694 u8 reserved_at_128[0x3];
1695 u8 log_meter_aso_max_alloc[0x5];
1696 u8 reserved_at_130[0x3];
1697 u8 log_max_num_meter_aso[0x5];
1698 u8 reserved_at_138[0x6b0];
1701 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1705 u8 lro_psh_flag[0x1];
1706 u8 lro_time_stamp[0x1];
1707 u8 lro_max_msg_sz_mode[0x2];
1708 u8 wqe_vlan_insert[0x1];
1709 u8 self_lb_en_modifiable[0x1];
1712 u8 max_lso_cap[0x5];
1713 u8 multi_pkt_send_wqe[0x2];
1714 u8 wqe_inline_mode[0x2];
1715 u8 rss_ind_tbl_cap[0x4];
1717 u8 scatter_fcs[0x1];
1718 u8 enhanced_multi_pkt_send_wqe[0x1];
1719 u8 tunnel_lso_const_out_ip_id[0x1];
1720 u8 tunnel_lro_gre[0x1];
1721 u8 tunnel_lro_vxlan[0x1];
1722 u8 tunnel_stateless_gre[0x1];
1723 u8 tunnel_stateless_vxlan[0x1];
1727 u8 reserved_at_23[0x8];
1728 u8 tunnel_stateless_gtp[0x1];
1729 u8 reserved_at_25[0x4];
1730 u8 max_vxlan_udp_ports[0x8];
1731 u8 reserved_at_38[0x6];
1732 u8 max_geneve_opt_len[0x1];
1733 u8 tunnel_stateless_geneve_rx[0x1];
1734 u8 reserved_at_40[0x10];
1735 u8 lro_min_mss_size[0x10];
1736 u8 reserved_at_60[0x120];
1737 u8 lro_timer_supported_periods[4][0x20];
1738 u8 reserved_at_200[0x600];
1742 MLX5_VIRTQ_TYPE_SPLIT = 0,
1743 MLX5_VIRTQ_TYPE_PACKED = 1,
1747 MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0,
1748 MLX5_VIRTQ_EVENT_MODE_QP = 1,
1749 MLX5_VIRTQ_EVENT_MODE_MSIX = 2,
1752 struct mlx5_ifc_virtio_emulation_cap_bits {
1753 u8 desc_tunnel_offload_type[0x1];
1754 u8 eth_frame_offload_type[0x1];
1755 u8 virtio_version_1_0[0x1];
1760 u8 reserved_at_7[0x1][0x9];
1762 u8 virtio_queue_type[0x8];
1763 u8 reserved_at_20[0x13];
1764 u8 log_doorbell_stride[0x5];
1765 u8 reserved_at_3b[0x3];
1766 u8 log_doorbell_bar_size[0x5];
1767 u8 doorbell_bar_offset[0x40];
1768 u8 reserved_at_80[0x8];
1769 u8 max_num_virtio_queues[0x18];
1770 u8 reserved_at_a0[0x60];
1771 u8 umem_1_buffer_param_a[0x20];
1772 u8 umem_1_buffer_param_b[0x20];
1773 u8 umem_2_buffer_param_a[0x20];
1774 u8 umem_2_buffer_param_b[0x20];
1775 u8 umem_3_buffer_param_a[0x20];
1776 u8 umem_3_buffer_param_b[0x20];
1777 u8 reserved_at_1c0[0x620];
1781 * PARSE_GRAPH_NODE Capabilities Field Descriptions
1783 struct mlx5_ifc_parse_graph_node_cap_bits {
1786 u8 header_length_mode[0x10];
1787 u8 sample_offset_mode[0x10];
1788 u8 max_num_arc_in[0x08];
1789 u8 max_num_arc_out[0x08];
1790 u8 max_num_sample[0x08];
1791 u8 reserved_at_78[0x07];
1792 u8 sample_id_in_out[0x1];
1793 u8 max_base_header_length[0x10];
1794 u8 reserved_at_90[0x08];
1795 u8 max_sample_base_offset[0x08];
1796 u8 max_next_header_offset[0x10];
1797 u8 reserved_at_b0[0x08];
1798 u8 header_length_mask_width[0x08];
1801 struct mlx5_ifc_flow_table_prop_layout_bits {
1804 u8 flow_counter[0x1];
1805 u8 flow_modify_en[0x1];
1806 u8 modify_root[0x1];
1807 u8 identified_miss_table[0x1];
1808 u8 flow_table_modify[0x1];
1811 u8 reset_root_to_default[0x1];
1814 u8 fpga_vendor_acceleration[0x1];
1816 u8 push_vlan_2[0x1];
1817 u8 reformat_and_vlan_action[0x1];
1818 u8 modify_and_vlan_action[0x1];
1820 u8 reformat_l3_tunnel_to_l2[0x1];
1821 u8 reformat_l2_to_l3_tunnel[0x1];
1822 u8 reformat_and_modify_action[0x1];
1823 u8 reserved_at_15[0x9];
1824 u8 sw_owner_v2[0x1];
1825 u8 reserved_at_1f[0x1];
1826 u8 reserved_at_20[0x2];
1827 u8 log_max_ft_size[0x6];
1828 u8 log_max_modify_header_context[0x8];
1829 u8 max_modify_header_actions[0x8];
1830 u8 max_ft_level[0x8];
1831 u8 reserved_at_40[0x8];
1832 u8 log_max_ft_sampler_num[8];
1833 u8 metadata_reg_b_width[0x8];
1834 u8 metadata_reg_a_width[0x8];
1835 u8 reserved_at_60[0x18];
1836 u8 log_max_ft_num[0x8];
1837 u8 reserved_at_80[0x10];
1838 u8 log_max_flow_counter[0x8];
1839 u8 log_max_destination[0x8];
1840 u8 reserved_at_a0[0x18];
1841 u8 log_max_flow[0x8];
1842 u8 reserved_at_c0[0x140];
1845 struct mlx5_ifc_roce_caps_bits {
1846 u8 reserved_0[0x1e];
1847 u8 qp_ts_format[0x2];
1848 u8 reserved_at_20[0x7e0];
1852 * Table 1872 - Flow Table Fields Supported 2 Format
1854 struct mlx5_ifc_ft_fields_support_2_bits {
1855 u8 reserved_at_0[0xf];
1856 u8 tunnel_header_2_3[0x1];
1857 u8 tunnel_header_0_1[0x1];
1858 u8 macsec_syndrome[0x1];
1860 u8 outer_lrh_sl[0x1];
1861 u8 inner_ipv4_ihl[0x1];
1862 u8 outer_ipv4_ihl[0x1];
1863 u8 psp_syndrome[0x1];
1864 u8 inner_l3_ok[0x1];
1865 u8 inner_l4_ok[0x1];
1866 u8 outer_l3_ok[0x1];
1867 u8 outer_l4_ok[0x1];
1869 u8 inner_ipv4_checksum_ok[0x1];
1870 u8 inner_l4_checksum_ok[0x1];
1871 u8 outer_ipv4_checksum_ok[0x1];
1872 u8 outer_l4_checksum_ok[0x1];
1873 u8 reserved_at_20[0x60];
1876 struct mlx5_ifc_flow_table_nic_cap_bits {
1877 u8 reserved_at_0[0x200];
1878 struct mlx5_ifc_flow_table_prop_layout_bits
1879 flow_table_properties_nic_receive;
1880 struct mlx5_ifc_flow_table_prop_layout_bits
1881 flow_table_properties_nic_receive_rdma;
1882 struct mlx5_ifc_flow_table_prop_layout_bits
1883 flow_table_properties_nic_receive_sniffer;
1884 struct mlx5_ifc_flow_table_prop_layout_bits
1885 flow_table_properties_nic_transmit;
1886 struct mlx5_ifc_flow_table_prop_layout_bits
1887 flow_table_properties_nic_transmit_rdma;
1888 struct mlx5_ifc_flow_table_prop_layout_bits
1889 flow_table_properties_nic_transmit_sniffer;
1890 u8 reserved_at_e00[0x600];
1891 struct mlx5_ifc_ft_fields_support_2_bits
1892 ft_field_support_2_nic_receive;
1896 * HCA Capabilities 2
1898 struct mlx5_ifc_cmd_hca_cap_2_bits {
1899 u8 reserved_at_0[0x80]; /* End of DW4. */
1900 u8 reserved_at_80[0x3];
1901 u8 max_num_prog_sample_field[0x5];
1902 u8 reserved_at_88[0x3];
1903 u8 log_max_num_reserved_qpn[0x5];
1904 u8 reserved_at_90[0x3];
1905 u8 log_reserved_qpn_granularity[0x5];
1906 u8 reserved_at_98[0x3];
1907 u8 log_reserved_qpn_max_alloc[0x5]; /* End of DW5. */
1908 u8 max_reformat_insert_size[0x8];
1909 u8 max_reformat_insert_offset[0x8];
1910 u8 max_reformat_remove_size[0x8];
1911 u8 max_reformat_remove_offset[0x8]; /* End of DW6. */
1912 u8 aso_conntrack_reg_id[0x8];
1913 u8 reserved_at_c8[0x3];
1914 u8 log_conn_track_granularity[0x5];
1915 u8 reserved_at_d0[0x3];
1916 u8 log_conn_track_max_alloc[0x5];
1917 u8 reserved_at_d8[0x3];
1918 u8 log_max_conn_track_offload[0x5];
1919 u8 reserved_at_e0[0x20]; /* End of DW7. */
1920 u8 reserved_at_100[0x700];
1923 union mlx5_ifc_hca_cap_union_bits {
1924 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1925 struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1926 per_protocol_networking_offload_caps;
1927 struct mlx5_ifc_qos_cap_bits qos_cap;
1928 struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
1929 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1930 struct mlx5_ifc_roce_caps_bits roce_caps;
1931 u8 reserved_at_0[0x8000];
1934 struct mlx5_ifc_set_action_in_bits {
1935 u8 action_type[0x4];
1937 u8 reserved_at_10[0x3];
1939 u8 reserved_at_18[0x3];
1944 struct mlx5_ifc_query_hca_cap_out_bits {
1946 u8 reserved_at_8[0x18];
1948 u8 reserved_at_40[0x40];
1949 union mlx5_ifc_hca_cap_union_bits capability;
1952 struct mlx5_ifc_query_hca_cap_in_bits {
1954 u8 reserved_at_10[0x10];
1955 u8 reserved_at_20[0x10];
1957 u8 reserved_at_40[0x40];
1960 struct mlx5_ifc_mac_address_layout_bits {
1961 u8 reserved_at_0[0x10];
1962 u8 mac_addr_47_32[0x10];
1963 u8 mac_addr_31_0[0x20];
1966 struct mlx5_ifc_nic_vport_context_bits {
1967 u8 reserved_at_0[0x5];
1968 u8 min_wqe_inline_mode[0x3];
1969 u8 reserved_at_8[0x15];
1970 u8 disable_mc_local_lb[0x1];
1971 u8 disable_uc_local_lb[0x1];
1973 u8 arm_change_event[0x1];
1974 u8 reserved_at_21[0x1a];
1975 u8 event_on_mtu[0x1];
1976 u8 event_on_promisc_change[0x1];
1977 u8 event_on_vlan_change[0x1];
1978 u8 event_on_mc_address_change[0x1];
1979 u8 event_on_uc_address_change[0x1];
1980 u8 reserved_at_40[0xc];
1981 u8 affiliation_criteria[0x4];
1982 u8 affiliated_vhca_id[0x10];
1983 u8 reserved_at_60[0xd0];
1985 u8 system_image_guid[0x40];
1988 u8 reserved_at_200[0x140];
1989 u8 qkey_violation_counter[0x10];
1990 u8 reserved_at_350[0x430];
1993 u8 promisc_all[0x1];
1994 u8 reserved_at_783[0x2];
1995 u8 allowed_list_type[0x3];
1996 u8 reserved_at_788[0xc];
1997 u8 allowed_list_size[0xc];
1998 struct mlx5_ifc_mac_address_layout_bits permanent_address;
1999 u8 reserved_at_7e0[0x20];
2002 struct mlx5_ifc_query_nic_vport_context_out_bits {
2004 u8 reserved_at_8[0x18];
2006 u8 reserved_at_40[0x40];
2007 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
2010 struct mlx5_ifc_query_nic_vport_context_in_bits {
2012 u8 reserved_at_10[0x10];
2013 u8 reserved_at_20[0x10];
2015 u8 other_vport[0x1];
2016 u8 reserved_at_41[0xf];
2017 u8 vport_number[0x10];
2018 u8 reserved_at_60[0x5];
2019 u8 allowed_list_type[0x3];
2020 u8 reserved_at_68[0x18];
2024 * lag_tx_port_affinity: 0 auto-selection, 1 PF1, 2 PF2 vice versa.
2025 * Each TIS binds to one PF by setting lag_tx_port_affinity (>0).
2026 * Once LAG enabled, we create multiple TISs and bind each one to
2027 * different PFs, then TIS[i] gets affinity i+1 and goes to PF i+1.
2029 #define MLX5_IFC_LAG_MAP_TIS_AFFINITY(index, num) ((num) ? \
2030 (index) % (num) + 1 : 0)
2031 struct mlx5_ifc_tisc_bits {
2032 u8 strict_lag_tx_port_affinity[0x1];
2033 u8 reserved_at_1[0x3];
2034 u8 lag_tx_port_affinity[0x04];
2035 u8 reserved_at_8[0x4];
2037 u8 reserved_at_10[0x10];
2038 u8 reserved_at_20[0x100];
2039 u8 reserved_at_120[0x8];
2040 u8 transport_domain[0x18];
2041 u8 reserved_at_140[0x8];
2042 u8 underlay_qpn[0x18];
2043 u8 reserved_at_160[0x3a0];
2046 struct mlx5_ifc_query_tis_out_bits {
2048 u8 reserved_at_8[0x18];
2050 u8 reserved_at_40[0x40];
2051 struct mlx5_ifc_tisc_bits tis_context;
2054 struct mlx5_ifc_query_tis_in_bits {
2056 u8 reserved_at_10[0x10];
2057 u8 reserved_at_20[0x10];
2059 u8 reserved_at_40[0x8];
2061 u8 reserved_at_60[0x20];
2064 /* port_select_mode definition. */
2065 enum mlx5_lag_mode_type {
2066 MLX5_LAG_MODE_TIS = 0,
2067 MLX5_LAG_MODE_HASH = 1,
2070 struct mlx5_ifc_lag_context_bits {
2071 u8 fdb_selection_mode[0x1];
2072 u8 reserved_at_1[0x14];
2073 u8 port_select_mode[0x3];
2074 u8 reserved_at_18[0x5];
2076 u8 reserved_at_20[0x14];
2077 u8 tx_remap_affinity_2[0x4];
2078 u8 reserved_at_38[0x4];
2079 u8 tx_remap_affinity_1[0x4];
2082 struct mlx5_ifc_query_lag_in_bits {
2085 u8 reserved_at_20[0x10];
2087 u8 reserved_at_40[0x40];
2090 struct mlx5_ifc_query_lag_out_bits {
2092 u8 reserved_at_8[0x18];
2094 struct mlx5_ifc_lag_context_bits context;
2097 struct mlx5_ifc_alloc_transport_domain_out_bits {
2099 u8 reserved_at_8[0x18];
2101 u8 reserved_at_40[0x8];
2102 u8 transport_domain[0x18];
2103 u8 reserved_at_60[0x20];
2106 struct mlx5_ifc_alloc_transport_domain_in_bits {
2108 u8 reserved_at_10[0x10];
2109 u8 reserved_at_20[0x10];
2111 u8 reserved_at_40[0x40];
2115 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
2116 MLX5_WQ_TYPE_CYCLIC = 0x1,
2117 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
2118 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
2122 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
2123 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
2126 struct mlx5_ifc_wq_bits {
2128 u8 wq_signature[0x1];
2129 u8 end_padding_mode[0x2];
2131 u8 reserved_at_8[0x18];
2132 u8 hds_skip_first_sge[0x1];
2133 u8 log2_hds_buf_size[0x3];
2134 u8 reserved_at_24[0x7];
2135 u8 page_offset[0x5];
2137 u8 reserved_at_40[0x8];
2139 u8 reserved_at_60[0x8];
2142 u8 hw_counter[0x20];
2143 u8 sw_counter[0x20];
2144 u8 reserved_at_100[0xc];
2145 u8 log_wq_stride[0x4];
2146 u8 reserved_at_110[0x3];
2147 u8 log_wq_pg_sz[0x5];
2148 u8 reserved_at_118[0x3];
2150 u8 dbr_umem_valid[0x1];
2151 u8 wq_umem_valid[0x1];
2152 u8 reserved_at_122[0x1];
2153 u8 log_hairpin_num_packets[0x5];
2154 u8 reserved_at_128[0x3];
2155 u8 log_hairpin_data_sz[0x5];
2156 u8 reserved_at_130[0x4];
2157 u8 single_wqe_log_num_of_strides[0x4];
2158 u8 two_byte_shift_en[0x1];
2159 u8 reserved_at_139[0x4];
2160 u8 single_stride_log_num_of_bytes[0x3];
2161 u8 dbr_umem_id[0x20];
2162 u8 wq_umem_id[0x20];
2163 u8 wq_umem_offset[0x40];
2164 u8 reserved_at_1c0[0x440];
2168 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2169 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2173 MLX5_RQC_STATE_RST = 0x0,
2174 MLX5_RQC_STATE_RDY = 0x1,
2175 MLX5_RQC_STATE_ERR = 0x3,
2178 struct mlx5_ifc_rqc_bits {
2180 u8 delay_drop_en[0x1];
2181 u8 scatter_fcs[0x1];
2183 u8 mem_rq_type[0x4];
2185 u8 reserved_at_c[0x1];
2186 u8 flush_in_error_en[0x1];
2188 u8 reserved_at_f[0xB];
2190 u8 reserved_at_1c[0x4];
2191 u8 reserved_at_20[0x8];
2192 u8 user_index[0x18];
2193 u8 reserved_at_40[0x8];
2195 u8 counter_set_id[0x8];
2196 u8 reserved_at_68[0x18];
2197 u8 reserved_at_80[0x8];
2199 u8 reserved_at_a0[0x8];
2200 u8 hairpin_peer_sq[0x18];
2201 u8 reserved_at_c0[0x10];
2202 u8 hairpin_peer_vhca[0x10];
2203 u8 reserved_at_e0[0xa0];
2204 struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
2207 struct mlx5_ifc_create_rq_out_bits {
2209 u8 reserved_at_8[0x18];
2211 u8 reserved_at_40[0x8];
2213 u8 reserved_at_60[0x20];
2216 struct mlx5_ifc_create_rq_in_bits {
2219 u8 reserved_at_20[0x10];
2221 u8 reserved_at_40[0xc0];
2222 struct mlx5_ifc_rqc_bits ctx;
2225 struct mlx5_ifc_modify_rq_out_bits {
2227 u8 reserved_at_8[0x18];
2229 u8 reserved_at_40[0x40];
2232 struct mlx5_ifc_query_rq_out_bits {
2234 u8 reserved_at_8[0x18];
2236 u8 reserved_at_40[0xc0];
2237 struct mlx5_ifc_rqc_bits rq_context;
2240 struct mlx5_ifc_query_rq_in_bits {
2242 u8 reserved_at_10[0x10];
2243 u8 reserved_at_20[0x10];
2245 u8 reserved_at_40[0x8];
2247 u8 reserved_at_60[0x20];
2251 MLX5_RMPC_STATE_RDY = 0x1,
2252 MLX5_RMPC_STATE_ERR = 0x3,
2255 struct mlx5_ifc_rmpc_bits {
2256 u8 reserved_at_0[0x8];
2258 u8 reserved_at_c[0x14];
2259 u8 basic_cyclic_rcv_wqe[0x1];
2260 u8 reserved_at_21[0x1f];
2261 u8 reserved_at_40[0x140];
2262 struct mlx5_ifc_wq_bits wq;
2265 struct mlx5_ifc_query_rmp_out_bits {
2267 u8 reserved_at_8[0x18];
2269 u8 reserved_at_40[0xc0];
2270 struct mlx5_ifc_rmpc_bits rmp_context;
2273 struct mlx5_ifc_query_rmp_in_bits {
2275 u8 reserved_at_10[0x10];
2276 u8 reserved_at_20[0x10];
2278 u8 reserved_at_40[0x8];
2280 u8 reserved_at_60[0x20];
2283 struct mlx5_ifc_modify_rmp_out_bits {
2285 u8 reserved_at_8[0x18];
2287 u8 reserved_at_40[0x40];
2290 struct mlx5_ifc_rmp_bitmask_bits {
2291 u8 reserved_at_0[0x20];
2292 u8 reserved_at_20[0x1f];
2296 struct mlx5_ifc_modify_rmp_in_bits {
2299 u8 reserved_at_20[0x10];
2302 u8 reserved_at_44[0x4];
2304 u8 reserved_at_60[0x20];
2305 struct mlx5_ifc_rmp_bitmask_bits bitmask;
2306 u8 reserved_at_c0[0x40];
2307 struct mlx5_ifc_rmpc_bits ctx;
2310 struct mlx5_ifc_create_rmp_out_bits {
2312 u8 reserved_at_8[0x18];
2314 u8 reserved_at_40[0x8];
2316 u8 reserved_at_60[0x20];
2319 struct mlx5_ifc_create_rmp_in_bits {
2322 u8 reserved_at_20[0x10];
2324 u8 reserved_at_40[0xc0];
2325 struct mlx5_ifc_rmpc_bits ctx;
2328 struct mlx5_ifc_create_tis_out_bits {
2330 u8 reserved_at_8[0x18];
2332 u8 reserved_at_40[0x8];
2334 u8 reserved_at_60[0x20];
2337 struct mlx5_ifc_create_tis_in_bits {
2340 u8 reserved_at_20[0x10];
2342 u8 reserved_at_40[0xc0];
2343 struct mlx5_ifc_tisc_bits ctx;
2347 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
2348 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
2349 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
2350 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
2353 struct mlx5_ifc_modify_rq_in_bits {
2356 u8 reserved_at_20[0x10];
2359 u8 reserved_at_44[0x4];
2361 u8 reserved_at_60[0x20];
2362 u8 modify_bitmask[0x40];
2363 u8 reserved_at_c0[0x40];
2364 struct mlx5_ifc_rqc_bits ctx;
2368 MLX5_L3_PROT_TYPE_IPV4 = 0,
2369 MLX5_L3_PROT_TYPE_IPV6 = 1,
2373 MLX5_L4_PROT_TYPE_TCP = 0,
2374 MLX5_L4_PROT_TYPE_UDP = 1,
2378 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
2379 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
2380 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
2381 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
2382 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
2385 struct mlx5_ifc_rx_hash_field_select_bits {
2386 u8 l3_prot_type[0x1];
2387 u8 l4_prot_type[0x1];
2388 u8 selected_fields[0x1e];
2392 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2393 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2397 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2398 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2402 MLX5_RX_HASH_FN_NONE = 0x0,
2403 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2404 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2408 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
2409 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
2413 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 = 0x0,
2414 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2 = 0x1,
2417 struct mlx5_ifc_tirc_bits {
2418 u8 reserved_at_0[0x20];
2420 u8 reserved_at_24[0x1c];
2421 u8 reserved_at_40[0x40];
2422 u8 reserved_at_80[0x4];
2423 u8 lro_timeout_period_usecs[0x10];
2424 u8 lro_enable_mask[0x4];
2425 u8 lro_max_msg_sz[0x8];
2426 u8 reserved_at_a0[0x40];
2427 u8 reserved_at_e0[0x8];
2428 u8 inline_rqn[0x18];
2429 u8 rx_hash_symmetric[0x1];
2430 u8 reserved_at_101[0x1];
2431 u8 tunneled_offload_en[0x1];
2432 u8 reserved_at_103[0x5];
2433 u8 indirect_table[0x18];
2435 u8 reserved_at_124[0x2];
2436 u8 self_lb_block[0x2];
2437 u8 transport_domain[0x18];
2438 u8 rx_hash_toeplitz_key[10][0x20];
2439 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2440 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2441 u8 reserved_at_2c0[0x4c0];
2444 struct mlx5_ifc_create_tir_out_bits {
2446 u8 reserved_at_8[0x18];
2448 u8 reserved_at_40[0x8];
2450 u8 reserved_at_60[0x20];
2453 struct mlx5_ifc_create_tir_in_bits {
2456 u8 reserved_at_20[0x10];
2458 u8 reserved_at_40[0xc0];
2459 struct mlx5_ifc_tirc_bits ctx;
2463 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0,
2464 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1,
2465 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2,
2466 /* bit 3 - tunneled_offload_en modify not supported. */
2467 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4,
2470 struct mlx5_ifc_modify_tir_out_bits {
2472 u8 reserved_at_8[0x18];
2474 u8 reserved_at_40[0x40];
2477 struct mlx5_ifc_modify_tir_in_bits {
2480 u8 reserved_at_20[0x10];
2482 u8 reserved_at_40[0x8];
2484 u8 reserved_at_60[0x20];
2485 u8 modify_bitmask[0x40];
2486 u8 reserved_at_c0[0x40];
2487 struct mlx5_ifc_tirc_bits ctx;
2491 MLX5_INLINE_Q_TYPE_RQ = 0x0,
2492 MLX5_INLINE_Q_TYPE_VIRTQ = 0x1,
2495 struct mlx5_ifc_rq_num_bits {
2496 u8 reserved_at_0[0x8];
2500 struct mlx5_ifc_rqtc_bits {
2501 u8 reserved_at_0[0xa5];
2502 u8 list_q_type[0x3];
2503 u8 reserved_at_a8[0x8];
2504 u8 rqt_max_size[0x10];
2505 u8 reserved_at_c0[0x10];
2506 u8 rqt_actual_size[0x10];
2507 u8 reserved_at_e0[0x6a0];
2508 struct mlx5_ifc_rq_num_bits rq_num[];
2511 struct mlx5_ifc_create_rqt_out_bits {
2513 u8 reserved_at_8[0x18];
2515 u8 reserved_at_40[0x8];
2517 u8 reserved_at_60[0x20];
2521 #pragma GCC diagnostic ignored "-Wpedantic"
2523 struct mlx5_ifc_create_rqt_in_bits {
2526 u8 reserved_at_20[0x10];
2528 u8 reserved_at_40[0xc0];
2529 struct mlx5_ifc_rqtc_bits rqt_context;
2532 struct mlx5_ifc_modify_rqt_in_bits {
2535 u8 reserved_at_20[0x10];
2537 u8 reserved_at_40[0x8];
2539 u8 reserved_at_60[0x20];
2540 u8 modify_bitmask[0x40];
2541 u8 reserved_at_c0[0x40];
2542 struct mlx5_ifc_rqtc_bits rqt_context;
2545 #pragma GCC diagnostic error "-Wpedantic"
2548 struct mlx5_ifc_modify_rqt_out_bits {
2550 u8 reserved_at_8[0x18];
2552 u8 reserved_at_40[0x40];
2556 MLX5_SQC_STATE_RST = 0x0,
2557 MLX5_SQC_STATE_RDY = 0x1,
2558 MLX5_SQC_STATE_ERR = 0x3,
2561 struct mlx5_ifc_sqc_bits {
2565 u8 flush_in_error_en[0x1];
2566 u8 allow_multi_pkt_send_wqe[0x1];
2567 u8 min_wqe_inline_mode[0x3];
2573 u8 static_sq_wq[0x1];
2574 u8 reserved_at_11[0x9];
2576 u8 reserved_at_1c[0x4];
2577 u8 reserved_at_20[0x8];
2578 u8 user_index[0x18];
2579 u8 reserved_at_40[0x8];
2581 u8 reserved_at_60[0x8];
2582 u8 hairpin_peer_rq[0x18];
2583 u8 reserved_at_80[0x10];
2584 u8 hairpin_peer_vhca[0x10];
2585 u8 reserved_at_a0[0x50];
2586 u8 packet_pacing_rate_limit_index[0x10];
2587 u8 tis_lst_sz[0x10];
2588 u8 reserved_at_110[0x10];
2589 u8 reserved_at_120[0x40];
2590 u8 reserved_at_160[0x8];
2592 struct mlx5_ifc_wq_bits wq;
2595 struct mlx5_ifc_query_sq_in_bits {
2597 u8 reserved_at_10[0x10];
2598 u8 reserved_at_20[0x10];
2600 u8 reserved_at_40[0x8];
2602 u8 reserved_at_60[0x20];
2605 struct mlx5_ifc_modify_sq_out_bits {
2607 u8 reserved_at_8[0x18];
2609 u8 reserved_at_40[0x40];
2612 struct mlx5_ifc_modify_sq_in_bits {
2615 u8 reserved_at_20[0x10];
2618 u8 reserved_at_44[0x4];
2620 u8 reserved_at_60[0x20];
2621 u8 modify_bitmask[0x40];
2622 u8 reserved_at_c0[0x40];
2623 struct mlx5_ifc_sqc_bits ctx;
2626 struct mlx5_ifc_create_sq_out_bits {
2628 u8 reserved_at_8[0x18];
2630 u8 reserved_at_40[0x8];
2632 u8 reserved_at_60[0x20];
2635 struct mlx5_ifc_create_sq_in_bits {
2638 u8 reserved_at_20[0x10];
2640 u8 reserved_at_40[0xc0];
2641 struct mlx5_ifc_sqc_bits ctx;
2645 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
2646 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
2647 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
2648 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
2649 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
2652 struct mlx5_ifc_flow_meter_parameters_bits {
2654 u8 bucket_overflow[0x1];
2655 u8 start_color[0x2];
2656 u8 both_buckets_on_green[0x1];
2658 u8 reserved_at_1[0x19];
2659 u8 reserved_at_2[0x20];
2660 u8 reserved_at_3[0x3];
2661 u8 cbs_exponent[0x5];
2662 u8 cbs_mantissa[0x8];
2663 u8 reserved_at_4[0x3];
2664 u8 cir_exponent[0x5];
2665 u8 cir_mantissa[0x8];
2666 u8 reserved_at_5[0x20];
2667 u8 reserved_at_6[0x3];
2668 u8 ebs_exponent[0x5];
2669 u8 ebs_mantissa[0x8];
2670 u8 reserved_at_7[0x3];
2671 u8 eir_exponent[0x5];
2672 u8 eir_mantissa[0x8];
2673 u8 reserved_at_8[0x60];
2675 #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF)
2676 #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8
2679 MLX5_METER_MODE_IP_LEN = 0x0,
2680 MLX5_METER_MODE_L2_LEN = 0x1,
2681 MLX5_METER_MODE_L2_IPG_LEN = 0x2,
2682 MLX5_METER_MODE_PKT = 0x3,
2686 MLX5_CQE_SIZE_64B = 0x0,
2687 MLX5_CQE_SIZE_128B = 0x1,
2690 struct mlx5_ifc_cqc_bits {
2693 u8 initiator_src_dct[0x1];
2694 u8 dbr_umem_valid[0x1];
2695 u8 reserved_at_7[0x1];
2698 u8 reserved_at_c[0x1];
2699 u8 scqe_break_moderation_en[0x1];
2701 u8 cq_period_mode[0x2];
2702 u8 cqe_comp_en[0x1];
2703 u8 mini_cqe_res_format[0x2];
2705 u8 reserved_at_18[0x1];
2706 u8 cqe_comp_layout[0x7];
2707 u8 dbr_umem_id[0x20];
2708 u8 reserved_at_40[0x14];
2709 u8 page_offset[0x6];
2710 u8 reserved_at_5a[0x2];
2711 u8 mini_cqe_res_format_ext[0x2];
2712 u8 cq_timestamp_format[0x2];
2713 u8 reserved_at_60[0x3];
2714 u8 log_cq_size[0x5];
2716 u8 reserved_at_80[0x4];
2718 u8 cq_max_count[0x10];
2719 u8 reserved_at_a0[0x18];
2721 u8 reserved_at_c0[0x3];
2722 u8 log_page_size[0x5];
2723 u8 reserved_at_c8[0x18];
2724 u8 reserved_at_e0[0x20];
2725 u8 reserved_at_100[0x8];
2726 u8 last_notified_index[0x18];
2727 u8 reserved_at_120[0x8];
2728 u8 last_solicit_index[0x18];
2729 u8 reserved_at_140[0x8];
2730 u8 consumer_counter[0x18];
2731 u8 reserved_at_160[0x8];
2732 u8 producer_counter[0x18];
2733 u8 local_partition_id[0xc];
2734 u8 process_id[0x14];
2735 u8 reserved_at_1A0[0x20];
2739 struct mlx5_ifc_health_buffer_bits {
2740 u8 reserved_0[0x100];
2741 u8 assert_existptr[0x20];
2742 u8 assert_callra[0x20];
2743 u8 reserved_1[0x40];
2744 u8 fw_version[0x20];
2746 u8 reserved_2[0x20];
2747 u8 irisc_index[0x8];
2752 struct mlx5_ifc_initial_seg_bits {
2753 u8 fw_rev_minor[0x10];
2754 u8 fw_rev_major[0x10];
2755 u8 cmd_interface_rev[0x10];
2756 u8 fw_rev_subminor[0x10];
2757 u8 reserved_0[0x40];
2758 u8 cmdq_phy_addr_63_32[0x20];
2759 u8 cmdq_phy_addr_31_12[0x14];
2761 u8 nic_interface[0x2];
2762 u8 log_cmdq_size[0x4];
2763 u8 log_cmdq_stride[0x4];
2764 u8 command_doorbell_vector[0x20];
2765 u8 reserved_2[0xf00];
2766 u8 initializing[0x1];
2767 u8 nic_interface_supported[0x7];
2768 u8 reserved_4[0x18];
2769 struct mlx5_ifc_health_buffer_bits health_buffer;
2770 u8 no_dram_nic_offset[0x20];
2771 u8 reserved_5[0x6de0];
2772 u8 internal_timer_h[0x20];
2773 u8 internal_timer_l[0x20];
2774 u8 reserved_6[0x20];
2775 u8 reserved_7[0x1f];
2777 u8 health_syndrome[0x8];
2778 u8 health_counter[0x18];
2779 u8 reserved_8[0x17fc0];
2782 struct mlx5_ifc_create_cq_out_bits {
2784 u8 reserved_at_8[0x18];
2786 u8 reserved_at_40[0x8];
2788 u8 reserved_at_60[0x20];
2791 struct mlx5_ifc_create_cq_in_bits {
2794 u8 reserved_at_20[0x10];
2796 u8 reserved_at_40[0x40];
2797 struct mlx5_ifc_cqc_bits cq_context;
2798 u8 cq_umem_offset[0x40];
2799 u8 cq_umem_id[0x20];
2800 u8 cq_umem_valid[0x1];
2801 u8 reserved_at_2e1[0x1f];
2802 u8 reserved_at_300[0x580];
2807 MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
2808 MLX5_GENERAL_OBJ_TYPE_DEK = 0x000c,
2809 MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
2810 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
2811 MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d,
2812 MLX5_GENERAL_OBJ_TYPE_CREDENTIAL = 0x001e,
2813 MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN = 0x001f,
2814 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,
2815 MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024,
2816 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025,
2817 MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031,
2820 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
2822 u8 reserved_at_10[0x20];
2825 u8 reserved_at_60[0x3];
2826 u8 log_obj_range[0x5];
2827 u8 reserved_at_58[0x18];
2830 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
2832 u8 reserved_at_8[0x18];
2835 u8 reserved_at_60[0x20];
2838 struct mlx5_ifc_virtio_q_counters_bits {
2839 u8 modify_field_select[0x40];
2840 u8 reserved_at_40[0x40];
2841 u8 received_desc[0x40];
2842 u8 completed_desc[0x40];
2843 u8 error_cqes[0x20];
2844 u8 bad_desc_errors[0x20];
2845 u8 exceed_max_chain[0x20];
2846 u8 invalid_buffer[0x20];
2847 u8 reserved_at_180[0x50];
2850 struct mlx5_ifc_geneve_tlv_option_bits {
2851 u8 modify_field_select[0x40];
2852 u8 reserved_at_40[0x18];
2853 u8 geneve_option_fte_index[0x8];
2854 u8 option_class[0x10];
2855 u8 option_type[0x8];
2856 u8 reserved_at_78[0x3];
2857 u8 option_data_length[0x5];
2858 u8 reserved_at_80[0x180];
2861 struct mlx5_ifc_create_virtio_q_counters_in_bits {
2862 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2863 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2866 struct mlx5_ifc_query_virtio_q_counters_out_bits {
2867 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2868 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2871 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
2872 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2873 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
2877 MLX5_CRYPTO_KEY_SIZE_128b = 0x0,
2878 MLX5_CRYPTO_KEY_SIZE_256b = 0x1,
2882 MLX5_CRYPTO_KEY_PURPOSE_TLS = 0x1,
2883 MLX5_CRYPTO_KEY_PURPOSE_IPSEC = 0x2,
2884 MLX5_CRYPTO_KEY_PURPOSE_AES_XTS = 0x3,
2885 MLX5_CRYPTO_KEY_PURPOSE_MACSEC = 0x4,
2886 MLX5_CRYPTO_KEY_PURPOSE_GCM = 0x5,
2887 MLX5_CRYPTO_KEY_PURPOSE_PSP = 0x6,
2890 struct mlx5_ifc_dek_bits {
2891 u8 modify_field_select[0x40];
2893 u8 reserved_at_48[0xc];
2896 u8 reserved_at_59[0x3];
2897 u8 key_purpose[0x4];
2898 u8 reserved_at_60[0x8];
2900 u8 reserved_at_80[0x100];
2902 u8 reserved_at_1c0[0x40];
2904 u8 reserved_at_600[0x200];
2907 struct mlx5_ifc_create_dek_in_bits {
2908 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2909 struct mlx5_ifc_dek_bits dek;
2912 struct mlx5_ifc_import_kek_bits {
2913 u8 modify_field_select[0x40];
2915 u8 reserved_at_48[0xc];
2917 u8 reserved_at_58[0x1a8];
2919 u8 reserved_at_600[0x200];
2922 struct mlx5_ifc_create_import_kek_in_bits {
2923 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2924 struct mlx5_ifc_import_kek_bits import_kek;
2928 MLX5_CREDENTIAL_ROLE_OFFICER = 0x0,
2929 MLX5_CREDENTIAL_ROLE_USER = 0x1,
2932 struct mlx5_ifc_credential_bits {
2933 u8 modify_field_select[0x40];
2935 u8 reserved_at_48[0x10];
2936 u8 credential_role[0x8];
2937 u8 reserved_at_60[0x1a0];
2938 u8 credential[0x180];
2939 u8 reserved_at_380[0x480];
2942 struct mlx5_ifc_create_credential_in_bits {
2943 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2944 struct mlx5_ifc_credential_bits credential;
2947 struct mlx5_ifc_crypto_login_bits {
2948 u8 modify_field_select[0x40];
2949 u8 reserved_at_40[0x48];
2950 u8 credential_pointer[0x18];
2951 u8 reserved_at_a0[0x8];
2952 u8 session_import_kek_ptr[0x18];
2953 u8 reserved_at_c0[0x140];
2954 u8 credential[0x180];
2955 u8 reserved_at_380[0x480];
2958 struct mlx5_ifc_create_crypto_login_in_bits {
2959 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2960 struct mlx5_ifc_crypto_login_bits crypto_login;
2964 MLX5_VIRTQ_STATE_INIT = 0,
2965 MLX5_VIRTQ_STATE_RDY = 1,
2966 MLX5_VIRTQ_STATE_SUSPEND = 2,
2967 MLX5_VIRTQ_STATE_ERROR = 3,
2971 MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),
2972 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),
2973 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),
2976 struct mlx5_ifc_virtio_q_bits {
2977 u8 virtio_q_type[0x8];
2978 u8 reserved_at_8[0x5];
2980 u8 queue_index[0x10];
2981 u8 full_emulation[0x1];
2982 u8 virtio_version_1_0[0x1];
2983 u8 reserved_at_22[0x2];
2984 u8 offload_type[0x4];
2985 u8 event_qpn_or_msix[0x18];
2986 u8 doorbell_stride_idx[0x10];
2987 u8 queue_size[0x10];
2988 u8 device_emulation_id[0x20];
2991 u8 available_addr[0x40];
2992 u8 virtio_q_mkey[0x20];
2993 u8 reserved_at_160[0x18];
2996 u8 umem_1_size[0x20];
2997 u8 umem_1_offset[0x40];
2999 u8 umem_2_size[0x20];
3000 u8 umem_2_offset[0x40];
3002 u8 umem_3_size[0x20];
3003 u8 umem_3_offset[0x40];
3004 u8 counter_set_id[0x20];
3005 u8 reserved_at_320[0x8];
3007 u8 reserved_at_340[0x2];
3008 u8 queue_period_mode[0x2];
3009 u8 queue_period_us[0xc];
3010 u8 queue_max_count[0x10];
3011 u8 reserved_at_360[0xa0];
3014 struct mlx5_ifc_virtio_net_q_bits {
3015 u8 modify_field_select[0x40];
3016 u8 reserved_at_40[0x40];
3021 u8 reserved_at_84[0x6];
3022 u8 dirty_bitmap_dump_enable[0x1];
3023 u8 vhost_log_page[0x5];
3024 u8 reserved_at_90[0xc];
3026 u8 reserved_at_a0[0x8];
3027 u8 tisn_or_qpn[0x18];
3028 u8 dirty_bitmap_mkey[0x20];
3029 u8 dirty_bitmap_size[0x20];
3030 u8 dirty_bitmap_addr[0x40];
3031 u8 hw_available_index[0x10];
3032 u8 hw_used_index[0x10];
3033 u8 reserved_at_160[0xa0];
3034 struct mlx5_ifc_virtio_q_bits virtio_q_context;
3037 struct mlx5_ifc_create_virtq_in_bits {
3038 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3039 struct mlx5_ifc_virtio_net_q_bits virtq;
3042 struct mlx5_ifc_query_virtq_out_bits {
3043 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3044 struct mlx5_ifc_virtio_net_q_bits virtq;
3047 struct mlx5_ifc_flow_hit_aso_bits {
3048 u8 modify_field_select[0x40];
3049 u8 reserved_at_40[0x48];
3051 u8 reserved_at_a0[0x160];
3055 struct mlx5_ifc_create_flow_hit_aso_in_bits {
3056 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3057 struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso;
3060 struct mlx5_ifc_flow_meter_aso_bits {
3061 u8 modify_field_select[0x40];
3062 u8 reserved_at_40[0x48];
3064 u8 reserved_at_a0[0x160];
3065 u8 parameters[0x200];
3068 struct mlx5_ifc_create_flow_meter_aso_in_bits {
3069 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3070 struct mlx5_ifc_flow_meter_aso_bits flow_meter_aso;
3073 struct mlx5_ifc_tcp_window_params_bits {
3080 struct mlx5_ifc_conn_track_aso_bits {
3081 struct mlx5_ifc_tcp_window_params_bits reply_dir; /* End of DW3. */
3082 struct mlx5_ifc_tcp_window_params_bits original_dir; /* End of DW7. */
3083 u8 last_end[0x20]; /* End of DW8. */
3084 u8 last_ack[0x20]; /* End of DW9. */
3085 u8 last_seq[0x20]; /* End of DW10. */
3087 u8 reserved_at_170[0xa];
3089 u8 last_index[0x5]; /* End of DW11. */
3090 u8 reserved_at_180[0x40]; /* End of DW13. */
3091 u8 reply_direction_tcp_scale[0x4];
3092 u8 reply_direction_tcp_close_initiated[0x1];
3093 u8 reply_direction_tcp_liberal_enabled[0x1];
3094 u8 reply_direction_tcp_data_unacked[0x1];
3095 u8 reply_direction_tcp_max_ack[0x1];
3096 u8 reserved_at_1c8[0x8];
3097 u8 original_direction_tcp_scale[0x4];
3098 u8 original_direction_tcp_close_initiated[0x1];
3099 u8 original_direction_tcp_liberal_enabled[0x1];
3100 u8 original_direction_tcp_data_unacked[0x1];
3101 u8 original_direction_tcp_max_ack[0x1];
3102 u8 reserved_at_1d8[0x8]; /* End of DW14. */
3105 u8 freeze_track[0x1];
3106 u8 reserved_at_1e5[0xb];
3107 u8 reserved_at_1f0[0x1];
3108 u8 connection_assured[0x1];
3109 u8 sack_permitted[0x1];
3110 u8 challenged_acked[0x1];
3112 u8 max_ack_window[0x3];
3113 u8 reserved_at_1f8[0x1];
3114 u8 retransmission_counter[0x3];
3115 u8 retranmission_limit_exceeded[0x1];
3116 u8 retranmission_limit[0x3]; /* End of DW15. */
3119 struct mlx5_ifc_conn_track_offload_bits {
3120 u8 modify_field_select[0x40];
3121 u8 reserved_at_40[0x40];
3122 u8 reserved_at_80[0x8];
3123 u8 conn_track_aso_access_pd[0x18];
3124 u8 reserved_at_a0[0x160];
3125 struct mlx5_ifc_conn_track_aso_bits conn_track_aso;
3128 struct mlx5_ifc_create_conn_track_aso_in_bits {
3129 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3130 struct mlx5_ifc_conn_track_offload_bits conn_track_offload;
3133 enum mlx5_access_aso_opc_mod {
3134 ASO_OPC_MOD_IPSEC = 0x0,
3135 ASO_OPC_MOD_CONNECTION_TRACKING = 0x1,
3136 ASO_OPC_MOD_POLICER = 0x2,
3137 ASO_OPC_MOD_RACE_AVOIDANCE = 0x3,
3138 ASO_OPC_MOD_FLOW_HIT = 0x4,
3141 #define ASO_CSEG_DATA_MASK_MODE_OFFSET 30
3143 enum mlx5_aso_data_mask_mode {
3144 BITWISE_64BIT = 0x0,
3145 BYTEWISE_64BYTE = 0x1,
3146 CALCULATED_64BYTE = 0x2,
3149 #define ASO_CSEG_COND_0_OPER_OFFSET 20
3150 #define ASO_CSEG_COND_1_OPER_OFFSET 16
3152 enum mlx5_aso_pre_cond_op {
3153 ASO_OP_ALWAYS_FALSE = 0x0,
3154 ASO_OP_ALWAYS_TRUE = 0x1,
3156 ASO_OP_NOT_EQUAL = 0x3,
3157 ASO_OP_GREATER_OR_EQUAL = 0x4,
3158 ASO_OP_LESSER_OR_EQUAL = 0x5,
3159 ASO_OP_LESSER = 0x6,
3160 ASO_OP_GREATER = 0x7,
3161 ASO_OP_CYCLIC_GREATER = 0x8,
3162 ASO_OP_CYCLIC_LESSER = 0x9,
3165 #define ASO_CSEG_COND_OPER_OFFSET 6
3168 ASO_OPER_LOGICAL_AND = 0x0,
3169 ASO_OPER_LOGICAL_OR = 0x1,
3172 /* ASO WQE CTRL segment. */
3173 struct mlx5_aso_cseg {
3177 uint32_t operand_masks;
3178 uint32_t condition_0_data;
3179 uint32_t condition_0_mask;
3180 uint32_t condition_1_data;
3181 uint32_t condition_1_mask;
3182 uint64_t bitwise_data;
3186 /* A meter data segment - 2 per ASO WQE. */
3187 struct mlx5_aso_mtr_dseg {
3188 uint32_t v_bo_sc_bbog_mm;
3190 * bit 31: valid, 30: bucket overflow, 28-29: start color,
3191 * 27: both buckets on green, 24-25: meter mode.
3196 * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa,
3197 * bit 8-12: cir_exponent, bit 0-7 cir_mantissa.
3202 * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa,
3203 * bit 8-12: eir_exponent, bit 0-7 eir_mantissa.
3209 #define ASO_DSEG_VALID_OFFSET 31
3210 #define ASO_DSEG_BO_OFFSET 30
3211 #define ASO_DSEG_SC_OFFSET 28
3212 #define ASO_DSEG_BBOG_OFFSET 27
3213 #define ASO_DSEG_MTR_MODE 24
3214 #define ASO_DSEG_CBS_EXP_OFFSET 24
3215 #define ASO_DSEG_CBS_MAN_OFFSET 16
3216 #define ASO_DSEG_XIR_EXP_MASK 0x1F
3217 #define ASO_DSEG_XIR_EXP_OFFSET 8
3218 #define ASO_DSEG_EBS_EXP_OFFSET 24
3219 #define ASO_DSEG_EBS_MAN_OFFSET 16
3220 #define ASO_DSEG_EXP_MASK 0x1F
3221 #define ASO_DSEG_MAN_MASK 0xFF
3223 #define MLX5_ASO_WQE_DSEG_SIZE 0x40
3224 #define MLX5_ASO_METERS_PER_WQE 2
3225 #define MLX5_ASO_MTRS_PER_POOL 128
3227 /* ASO WQE data segment. */
3228 struct mlx5_aso_dseg {
3230 uint8_t data[MLX5_ASO_WQE_DSEG_SIZE];
3231 struct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE];
3236 struct mlx5_aso_wqe {
3237 struct mlx5_wqe_cseg general_cseg;
3238 struct mlx5_aso_cseg aso_cseg;
3239 struct mlx5_aso_dseg aso_dseg;
3243 MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
3247 MLX5_QP_ST_RC = 0x0,
3251 MLX5_QP_PM_MIGRATED = 0x3,
3255 MLX5_NON_ZERO_RQ = 0x0,
3258 MLX5_ZERO_LEN_RQ = 0x3,
3261 struct mlx5_ifc_ads_bits {
3264 u8 reserved_at_2[0xe];
3265 u8 pkey_index[0x10];
3266 u8 reserved_at_20[0x8];
3270 u8 ack_timeout[0x5];
3271 u8 reserved_at_45[0x3];
3272 u8 src_addr_index[0x8];
3273 u8 reserved_at_50[0x4];
3276 u8 reserved_at_60[0x4];
3278 u8 flow_label[0x14];
3279 u8 rgid_rip[16][0x8];
3280 u8 reserved_at_100[0x4];
3283 u8 reserved_at_106[0x1];
3291 u8 vhca_port_num[0x8];
3292 u8 rmac_47_32[0x10];
3296 struct mlx5_ifc_qpc_bits {
3298 u8 lag_tx_port_affinity[0x4];
3300 u8 reserved_at_10[0x3];
3302 u8 reserved_at_15[0x1];
3303 u8 req_e2e_credit_mode[0x2];
3304 u8 offload_type[0x4];
3305 u8 end_padding_mode[0x2];
3306 u8 reserved_at_1e[0x2];
3307 u8 wq_signature[0x1];
3308 u8 block_lb_mc[0x1];
3309 u8 atomic_like_write_en[0x1];
3310 u8 latency_sensitive[0x1];
3311 u8 reserved_at_24[0x1];
3312 u8 drain_sigerr[0x1];
3313 u8 reserved_at_26[0x2];
3316 u8 log_msg_max[0x5];
3317 u8 reserved_at_48[0x1];
3318 u8 log_rq_size[0x4];
3319 u8 log_rq_stride[0x3];
3321 u8 log_sq_size[0x4];
3322 u8 reserved_at_55[0x3];
3324 u8 reserved_at_5a[0x1];
3326 u8 ulp_stateless_offload_mode[0x4];
3327 u8 counter_set_id[0x8];
3329 u8 reserved_at_80[0x8];
3330 u8 user_index[0x18];
3331 u8 reserved_at_a0[0x3];
3332 u8 log_page_size[0x5];
3333 u8 remote_qpn[0x18];
3334 struct mlx5_ifc_ads_bits primary_address_path;
3335 struct mlx5_ifc_ads_bits secondary_address_path;
3336 u8 log_ack_req_freq[0x4];
3337 u8 reserved_at_384[0x4];
3338 u8 log_sra_max[0x3];
3339 u8 reserved_at_38b[0x2];
3340 u8 retry_count[0x3];
3342 u8 reserved_at_393[0x1];
3344 u8 cur_rnr_retry[0x3];
3345 u8 cur_retry_count[0x3];
3346 u8 reserved_at_39b[0x5];
3347 u8 reserved_at_3a0[0x20];
3348 u8 reserved_at_3c0[0x8];
3349 u8 next_send_psn[0x18];
3350 u8 reserved_at_3e0[0x8];
3352 u8 reserved_at_400[0x8];
3354 u8 reserved_at_420[0x20];
3355 u8 reserved_at_440[0x8];
3356 u8 last_acked_psn[0x18];
3357 u8 reserved_at_460[0x8];
3359 u8 reserved_at_480[0x8];
3360 u8 log_rra_max[0x3];
3361 u8 reserved_at_48b[0x1];
3362 u8 atomic_mode[0x4];
3366 u8 reserved_at_493[0x1];
3367 u8 page_offset[0x6];
3368 u8 reserved_at_49a[0x3];
3369 u8 cd_slave_receive[0x1];
3370 u8 cd_slave_send[0x1];
3372 u8 reserved_at_4a0[0x3];
3373 u8 min_rnr_nak[0x5];
3374 u8 next_rcv_psn[0x18];
3375 u8 reserved_at_4c0[0x8];
3377 u8 reserved_at_4e0[0x8];
3381 u8 reserved_at_560[0x5];
3383 u8 srqn_rmpn_xrqn[0x18];
3384 u8 reserved_at_580[0x8];
3386 u8 hw_sq_wqebb_counter[0x10];
3387 u8 sw_sq_wqebb_counter[0x10];
3388 u8 hw_rq_counter[0x20];
3389 u8 sw_rq_counter[0x20];
3390 u8 reserved_at_600[0x20];
3391 u8 reserved_at_620[0xf];
3395 u8 dc_access_key[0x40];
3396 u8 reserved_at_680[0x3];
3397 u8 dbr_umem_valid[0x1];
3398 u8 reserved_at_684[0x9c];
3399 u8 dbr_umem_id[0x20];
3402 struct mlx5_ifc_create_qp_out_bits {
3404 u8 reserved_at_8[0x18];
3406 u8 reserved_at_40[0x8];
3408 u8 reserved_at_60[0x20];
3411 struct mlx5_ifc_qpc_extension_bits {
3412 u8 reserved_at_0[0x2];
3414 u8 reserved_at_3[0x5fd];
3418 #pragma GCC diagnostic ignored "-Wpedantic"
3420 struct mlx5_ifc_qpc_pas_list_bits {
3425 #pragma GCC diagnostic ignored "-Wpedantic"
3427 struct mlx5_ifc_qpc_extension_and_pas_list_bits {
3428 struct mlx5_ifc_qpc_extension_bits qpc_data_extension;
3434 #pragma GCC diagnostic ignored "-Wpedantic"
3436 struct mlx5_ifc_create_qp_in_bits {
3439 u8 reserved_at_20[0x10];
3442 u8 reserved_at_41[0x3f];
3443 u8 opt_param_mask[0x20];
3444 u8 reserved_at_a0[0x20];
3445 struct mlx5_ifc_qpc_bits qpc;
3446 u8 wq_umem_offset[0x40];
3447 u8 wq_umem_id[0x20];
3448 u8 wq_umem_valid[0x1];
3449 u8 reserved_at_861[0x1f];
3451 struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list;
3452 struct mlx5_ifc_qpc_extension_and_pas_list_bits
3453 qpc_extension_and_pas_list;
3457 #pragma GCC diagnostic error "-Wpedantic"
3460 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3462 u8 reserved_at_8[0x18];
3464 u8 reserved_at_40[0x40];
3467 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3470 u8 reserved_at_20[0x10];
3472 u8 reserved_at_40[0x8];
3474 u8 reserved_at_60[0x20];
3475 u8 opt_param_mask[0x20];
3476 u8 reserved_at_a0[0x20];
3477 struct mlx5_ifc_qpc_bits qpc;
3478 u8 reserved_at_800[0x80];
3481 struct mlx5_ifc_sqd2rts_qp_out_bits {
3483 u8 reserved_at_8[0x18];
3485 u8 reserved_at_40[0x40];
3488 struct mlx5_ifc_sqd2rts_qp_in_bits {
3491 u8 reserved_at_20[0x10];
3493 u8 reserved_at_40[0x8];
3495 u8 reserved_at_60[0x20];
3496 u8 opt_param_mask[0x20];
3497 u8 reserved_at_a0[0x20];
3498 struct mlx5_ifc_qpc_bits qpc;
3499 u8 reserved_at_800[0x80];
3502 struct mlx5_ifc_rts2rts_qp_out_bits {
3504 u8 reserved_at_8[0x18];
3506 u8 reserved_at_40[0x40];
3509 struct mlx5_ifc_rts2rts_qp_in_bits {
3512 u8 reserved_at_20[0x10];
3514 u8 reserved_at_40[0x8];
3516 u8 reserved_at_60[0x20];
3517 u8 opt_param_mask[0x20];
3518 u8 reserved_at_a0[0x20];
3519 struct mlx5_ifc_qpc_bits qpc;
3520 u8 reserved_at_800[0x80];
3523 struct mlx5_ifc_rtr2rts_qp_out_bits {
3525 u8 reserved_at_8[0x18];
3527 u8 reserved_at_40[0x40];
3530 struct mlx5_ifc_rtr2rts_qp_in_bits {
3533 u8 reserved_at_20[0x10];
3535 u8 reserved_at_40[0x8];
3537 u8 reserved_at_60[0x20];
3538 u8 opt_param_mask[0x20];
3539 u8 reserved_at_a0[0x20];
3540 struct mlx5_ifc_qpc_bits qpc;
3541 u8 reserved_at_800[0x80];
3544 struct mlx5_ifc_rst2init_qp_out_bits {
3546 u8 reserved_at_8[0x18];
3548 u8 reserved_at_40[0x40];
3551 struct mlx5_ifc_rst2init_qp_in_bits {
3554 u8 reserved_at_20[0x10];
3556 u8 reserved_at_40[0x8];
3558 u8 reserved_at_60[0x20];
3559 u8 opt_param_mask[0x20];
3560 u8 reserved_at_a0[0x20];
3561 struct mlx5_ifc_qpc_bits qpc;
3562 u8 reserved_at_800[0x80];
3565 struct mlx5_ifc_init2rtr_qp_out_bits {
3567 u8 reserved_at_8[0x18];
3569 u8 reserved_at_40[0x40];
3572 struct mlx5_ifc_init2rtr_qp_in_bits {
3575 u8 reserved_at_20[0x10];
3577 u8 reserved_at_40[0x8];
3579 u8 reserved_at_60[0x20];
3580 u8 opt_param_mask[0x20];
3581 u8 reserved_at_a0[0x20];
3582 struct mlx5_ifc_qpc_bits qpc;
3583 u8 reserved_at_800[0x80];
3586 struct mlx5_ifc_init2init_qp_out_bits {
3588 u8 reserved_at_8[0x18];
3590 u8 reserved_at_40[0x40];
3593 struct mlx5_ifc_init2init_qp_in_bits {
3596 u8 reserved_at_20[0x10];
3598 u8 reserved_at_40[0x8];
3600 u8 reserved_at_60[0x20];
3601 u8 opt_param_mask[0x20];
3602 u8 reserved_at_a0[0x20];
3603 struct mlx5_ifc_qpc_bits qpc;
3604 u8 reserved_at_800[0x80];
3607 struct mlx5_ifc_dealloc_pd_out_bits {
3609 u8 reserved_0[0x18];
3611 u8 reserved_1[0x40];
3614 struct mlx5_ifc_dealloc_pd_in_bits {
3616 u8 reserved_0[0x10];
3617 u8 reserved_1[0x10];
3621 u8 reserved_3[0x20];
3624 struct mlx5_ifc_alloc_pd_out_bits {
3626 u8 reserved_0[0x18];
3630 u8 reserved_2[0x20];
3633 struct mlx5_ifc_alloc_pd_in_bits {
3635 u8 reserved_0[0x10];
3636 u8 reserved_1[0x10];
3638 u8 reserved_2[0x40];
3642 #pragma GCC diagnostic ignored "-Wpedantic"
3644 struct mlx5_ifc_query_qp_out_bits {
3646 u8 reserved_at_8[0x18];
3648 u8 reserved_at_40[0x40];
3649 u8 opt_param_mask[0x20];
3650 u8 reserved_at_a0[0x20];
3651 struct mlx5_ifc_qpc_bits qpc;
3652 u8 reserved_at_800[0x80];
3656 #pragma GCC diagnostic error "-Wpedantic"
3659 struct mlx5_ifc_query_qp_in_bits {
3661 u8 reserved_at_10[0x10];
3662 u8 reserved_at_20[0x10];
3664 u8 reserved_at_40[0x8];
3666 u8 reserved_at_60[0x20];
3670 MLX5_DATA_RATE = 0x0,
3671 MLX5_WQE_RATE = 0x1,
3674 struct mlx5_ifc_set_pp_rate_limit_context_bits {
3675 u8 rate_limit[0x20];
3676 u8 burst_upper_bound[0x20];
3677 u8 reserved_at_40[0xC];
3679 u8 typical_packet_size[0x10];
3680 u8 reserved_at_60[0x120];
3683 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u
3686 #pragma GCC diagnostic ignored "-Wpedantic"
3688 struct mlx5_ifc_access_register_out_bits {
3690 u8 reserved_at_8[0x18];
3692 u8 reserved_at_40[0x40];
3693 u8 register_data[0][0x20];
3696 struct mlx5_ifc_access_register_in_bits {
3698 u8 reserved_at_10[0x10];
3699 u8 reserved_at_20[0x10];
3701 u8 reserved_at_40[0x10];
3702 u8 register_id[0x10];
3704 u8 register_data[0][0x20];
3707 #pragma GCC diagnostic error "-Wpedantic"
3711 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
3712 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
3716 MLX5_REGISTER_ID_MTUTC = 0x9055,
3717 MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002,
3718 MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003,
3719 MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004,
3720 MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005,
3723 struct mlx5_ifc_register_mtutc_bits {
3724 u8 time_stamp_mode[0x2];
3725 u8 time_stamp_state[0x2];
3726 u8 reserved_at_4[0x18];
3728 u8 freq_adjustment[0x20];
3729 u8 reserved_at_40[0x40];
3732 u8 time_adjustment[0x20];
3735 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0
3736 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1
3738 struct mlx5_ifc_crypto_operational_register_bits {
3739 u8 wrapped_crypto_operational[0x1];
3740 u8 reserved_at_1[0x1b];
3742 u8 reserved_at_20[0x20];
3743 u8 credential[0x140];
3745 u8 reserved_at_280[0x180];
3748 struct mlx5_ifc_crypto_commissioning_register_bits {
3749 u8 token[0x1]; /* TODO: add size after PRM update */
3752 struct mlx5_ifc_import_kek_handle_register_bits {
3753 struct mlx5_ifc_crypto_login_bits crypto_login_object;
3754 struct mlx5_ifc_import_kek_bits import_kek_object;
3755 u8 reserved_at_200[0x4];
3756 u8 write_operation[0x4];
3757 u8 import_kek_id[0x18];
3758 u8 reserved_at_220[0xe0];
3761 struct mlx5_ifc_credential_handle_register_bits {
3762 struct mlx5_ifc_crypto_login_bits crypto_login_object;
3763 struct mlx5_ifc_credential_bits credential_object;
3764 u8 reserved_at_200[0x4];
3765 u8 write_operation[0x4];
3766 u8 credential_id[0x18];
3767 u8 reserved_at_220[0xe0];
3771 MLX5_REGISTER_ADD_OPERATION = 0x1,
3772 MLX5_REGISTER_DELETE_OPERATION = 0x2,
3775 struct mlx5_ifc_parse_graph_arc_bits {
3776 u8 start_inner_tunnel[0x1];
3777 u8 reserved_at_1[0x7];
3778 u8 arc_parse_graph_node[0x8];
3779 u8 compare_condition_value[0x10];
3780 u8 parse_graph_node_handle[0x20];
3781 u8 reserved_at_40[0x40];
3784 struct mlx5_ifc_parse_graph_flow_match_sample_bits {
3785 u8 flow_match_sample_en[0x1];
3786 u8 reserved_at_1[0x3];
3787 u8 flow_match_sample_offset_mode[0x4];
3788 u8 reserved_at_5[0x8];
3789 u8 flow_match_sample_field_offset[0x10];
3790 u8 reserved_at_32[0x4];
3791 u8 flow_match_sample_field_offset_shift[0x4];
3792 u8 flow_match_sample_field_base_offset[0x8];
3793 u8 reserved_at_48[0xd];
3794 u8 flow_match_sample_tunnel_mode[0x3];
3795 u8 flow_match_sample_field_offset_mask[0x20];
3796 u8 flow_match_sample_field_id[0x20];
3799 struct mlx5_ifc_parse_graph_flex_bits {
3800 u8 modify_field_select[0x40];
3801 u8 reserved_at_64[0x20];
3802 u8 header_length_base_value[0x10];
3803 u8 reserved_at_112[0x4];
3804 u8 header_length_field_shift[0x4];
3805 u8 reserved_at_120[0x4];
3806 u8 header_length_mode[0x4];
3807 u8 header_length_field_offset[0x10];
3808 u8 next_header_field_offset[0x10];
3809 u8 reserved_at_160[0x1b];
3810 u8 next_header_field_size[0x5];
3811 u8 header_length_field_mask[0x20];
3812 u8 reserved_at_224[0x20];
3813 struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8];
3814 struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8];
3815 struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8];
3818 struct mlx5_ifc_create_flex_parser_in_bits {
3819 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3820 struct mlx5_ifc_parse_graph_flex_bits flex;
3823 struct mlx5_ifc_create_flex_parser_out_bits {
3824 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3825 struct mlx5_ifc_parse_graph_flex_bits flex;
3828 struct mlx5_ifc_parse_graph_flex_out_bits {
3830 u8 reserved_at_8[0x18];
3832 u8 reserved_at_40[0x40];
3833 struct mlx5_ifc_parse_graph_flex_bits capability;
3836 struct regexp_params_field_select_bits {
3837 u8 reserved_at_0[0x1d];
3839 u8 stop_engine[0x1];
3840 u8 reserved_at_1f[0x1];
3843 struct mlx5_ifc_regexp_params_bits {
3844 u8 reserved_at_0[0x1f];
3845 u8 stop_engine[0x1];
3846 u8 reserved_at_20[0x60];
3849 u8 rof_mkey_va[0x40];
3850 u8 reserved_at_100[0x80];
3853 struct mlx5_ifc_set_regexp_params_in_bits {
3856 u8 reserved_at_20[0x10];
3858 u8 reserved_at_40[0x18];
3860 struct regexp_params_field_select_bits field_select;
3861 struct mlx5_ifc_regexp_params_bits regexp_params;
3864 struct mlx5_ifc_set_regexp_params_out_bits {
3866 u8 reserved_at_8[0x18];
3868 u8 reserved_at_18[0x40];
3871 struct mlx5_ifc_query_regexp_params_in_bits {
3874 u8 reserved_at_20[0x10];
3876 u8 reserved_at_40[0x18];
3881 struct mlx5_ifc_query_regexp_params_out_bits {
3883 u8 reserved_at_8[0x18];
3886 struct mlx5_ifc_regexp_params_bits regexp_params;
3889 struct mlx5_ifc_set_regexp_register_in_bits {
3892 u8 reserved_at_20[0x10];
3894 u8 reserved_at_40[0x18];
3896 u8 register_address[0x20];
3897 u8 register_data[0x20];
3901 struct mlx5_ifc_set_regexp_register_out_bits {
3903 u8 reserved_at_8[0x18];
3908 struct mlx5_ifc_query_regexp_register_in_bits {
3911 u8 reserved_at_20[0x10];
3913 u8 reserved_at_40[0x18];
3915 u8 register_address[0x20];
3918 struct mlx5_ifc_query_regexp_register_out_bits {
3920 u8 reserved_at_8[0x18];
3923 u8 register_data[0x20];
3926 /* Queue counters. */
3927 struct mlx5_ifc_alloc_q_counter_out_bits {
3929 u8 reserved_at_8[0x18];
3931 u8 reserved_at_40[0x18];
3932 u8 counter_set_id[0x8];
3933 u8 reserved_at_60[0x20];
3936 struct mlx5_ifc_alloc_q_counter_in_bits {
3939 u8 reserved_at_20[0x10];
3941 u8 reserved_at_40[0x40];
3944 struct mlx5_ifc_query_q_counter_out_bits {
3946 u8 reserved_at_8[0x18];
3948 u8 reserved_at_40[0x40];
3949 u8 rx_write_requests[0x20];
3950 u8 reserved_at_a0[0x20];
3951 u8 rx_read_requests[0x20];
3952 u8 reserved_at_e0[0x20];
3953 u8 rx_atomic_requests[0x20];
3954 u8 reserved_at_120[0x20];
3955 u8 rx_dct_connect[0x20];
3956 u8 reserved_at_160[0x20];
3957 u8 out_of_buffer[0x20];
3958 u8 reserved_at_1a0[0x20];
3959 u8 out_of_sequence[0x20];
3960 u8 reserved_at_1e0[0x20];
3961 u8 duplicate_request[0x20];
3962 u8 reserved_at_220[0x20];
3963 u8 rnr_nak_retry_err[0x20];
3964 u8 reserved_at_260[0x20];
3965 u8 packet_seq_err[0x20];
3966 u8 reserved_at_2a0[0x20];
3967 u8 implied_nak_seq_err[0x20];
3968 u8 reserved_at_2e0[0x20];
3969 u8 local_ack_timeout_err[0x20];
3970 u8 reserved_at_320[0xa0];
3971 u8 resp_local_length_error[0x20];
3972 u8 req_local_length_error[0x20];
3973 u8 resp_local_qp_error[0x20];
3974 u8 local_operation_error[0x20];
3975 u8 resp_local_protection[0x20];
3976 u8 req_local_protection[0x20];
3977 u8 resp_cqe_error[0x20];
3978 u8 req_cqe_error[0x20];
3979 u8 req_mw_binding[0x20];
3980 u8 req_bad_response[0x20];
3981 u8 req_remote_invalid_request[0x20];
3982 u8 resp_remote_invalid_request[0x20];
3983 u8 req_remote_access_errors[0x20];
3984 u8 resp_remote_access_errors[0x20];
3985 u8 req_remote_operation_errors[0x20];
3986 u8 req_transport_retries_exceeded[0x20];
3987 u8 cq_overflow[0x20];
3988 u8 resp_cqe_flush_error[0x20];
3989 u8 req_cqe_flush_error[0x20];
3990 u8 reserved_at_620[0x1e0];
3993 struct mlx5_ifc_query_q_counter_in_bits {
3996 u8 reserved_at_20[0x10];
3998 u8 reserved_at_40[0x80];
4000 u8 reserved_at_c1[0x1f];
4001 u8 reserved_at_e0[0x18];
4002 u8 counter_set_id[0x8];
4005 /* CQE format mask. */
4006 #define MLX5E_CQE_FORMAT_MASK 0xc
4009 #define MLX5_OPC_MOD_MPW 0x01
4011 /* Compressed Rx CQE structure. */
4012 struct mlx5_mini_cqe8 {
4014 uint32_t rx_hash_result;
4018 uint16_t flow_tag_high;
4024 uint16_t stride_idx;
4027 uint16_t wqe_counter;
4028 uint8_t s_wqe_opcode;
4033 uint32_t byte_cnt_flow;
4038 /* Mini CQE responder format. */
4040 MLX5_CQE_RESP_FORMAT_HASH = 0x0,
4041 MLX5_CQE_RESP_FORMAT_CSUM = 0x1,
4042 MLX5_CQE_RESP_FORMAT_FTAG_STRIDX = 0x2,
4043 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3,
4044 MLX5_CQE_RESP_FORMAT_L34H_STRIDX = 0x4,
4047 /* srTCM PRM flow meter parameters. */
4049 MLX5_FLOW_COLOR_RED = 0,
4050 MLX5_FLOW_COLOR_YELLOW,
4051 MLX5_FLOW_COLOR_GREEN,
4052 MLX5_FLOW_COLOR_UNDEFINED,
4055 /* Maximum value of srTCM & trTCM metering parameters. */
4056 #define MLX5_SRTCM_XBS_MAX (0xFF * (1ULL << 0x1F))
4057 #define MLX5_SRTCM_XIR_MAX (8 * (1ULL << 30) * 0xFF)
4059 /* The bits meter color use. */
4060 #define MLX5_MTR_COLOR_BITS 8
4062 /* The bit size of one register. */
4063 #define MLX5_REG_BITS 32
4065 /* Idle bits for non-color usage in color register. */
4066 #define MLX5_MTR_IDLE_BITS_IN_COLOR_REG (MLX5_REG_BITS - MLX5_MTR_COLOR_BITS)
4068 /* Length mode of dynamic flex parser graph node. */
4069 enum mlx5_parse_graph_node_len_mode {
4070 MLX5_GRAPH_NODE_LEN_FIXED = 0x0,
4071 MLX5_GRAPH_NODE_LEN_FIELD = 0x1,
4072 MLX5_GRAPH_NODE_LEN_BITMASK = 0x2,
4075 /* Offset mode of the samples of flex parser. */
4076 enum mlx5_parse_graph_flow_match_sample_offset_mode {
4077 MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0,
4078 MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1,
4079 MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2,
4082 enum mlx5_parse_graph_flow_match_sample_tunnel_mode {
4083 MLX5_GRAPH_SAMPLE_TUNNEL_OUTER = 0x0,
4084 MLX5_GRAPH_SAMPLE_TUNNEL_INNER = 0x1,
4085 MLX5_GRAPH_SAMPLE_TUNNEL_FIRST = 0x2
4088 /* Node index for an input / output arc of the flex parser graph. */
4089 enum mlx5_parse_graph_arc_node_index {
4090 MLX5_GRAPH_ARC_NODE_NULL = 0x0,
4091 MLX5_GRAPH_ARC_NODE_HEAD = 0x1,
4092 MLX5_GRAPH_ARC_NODE_MAC = 0x2,
4093 MLX5_GRAPH_ARC_NODE_IP = 0x3,
4094 MLX5_GRAPH_ARC_NODE_GRE = 0x4,
4095 MLX5_GRAPH_ARC_NODE_UDP = 0x5,
4096 MLX5_GRAPH_ARC_NODE_MPLS = 0x6,
4097 MLX5_GRAPH_ARC_NODE_TCP = 0x7,
4098 MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8,
4099 MLX5_GRAPH_ARC_NODE_GENEVE = 0x9,
4100 MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa,
4101 MLX5_GRAPH_ARC_NODE_IPV4 = 0xb,
4102 MLX5_GRAPH_ARC_NODE_IPV6 = 0xc,
4103 MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f,
4106 #define MLX5_PARSE_GRAPH_FLOW_SAMPLE_MAX 8
4107 #define MLX5_PARSE_GRAPH_IN_ARC_MAX 8
4108 #define MLX5_PARSE_GRAPH_OUT_ARC_MAX 8
4111 * Convert a user mark to flow mark.
4114 * Mark value to convert.
4117 * Converted mark value.
4119 static inline uint32_t
4120 mlx5_flow_mark_set(uint32_t val)
4125 * Add one to the user value to differentiate un-marked flows from
4126 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
4127 * remains untouched.
4129 if (val != MLX5_FLOW_MARK_DEFAULT)
4131 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
4133 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
4134 * word, byte-swapped by the kernel on little-endian systems. In this
4135 * case, left-shifting the resulting big-endian value ensures the
4136 * least significant 24 bits are retained when converting it back.
4138 ret = rte_cpu_to_be_32(val) >> 8;
4146 * Convert a mark to user mark.
4149 * Mark value to convert.
4152 * Converted mark value.
4154 static inline uint32_t
4155 mlx5_flow_mark_get(uint32_t val)
4158 * Subtract one from the retrieved value. It was added by
4159 * mlx5_flow_mark_set() to distinguish unmarked flows.
4161 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
4162 return (val >> 8) - 1;
4169 * Convert a timestamp format to configure settings in the queue context.
4172 * timestamp format supported by the queue.
4175 * Converted timestamp format settings.
4177 static inline uint32_t
4178 mlx5_ts_format_conv(uint32_t ts_format)
4180 return ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ?
4181 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
4182 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
4185 #endif /* RTE_PMD_MLX5_PRM_H_ */