1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2016 6WIND S.A.
3 * Copyright 2016 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_PRM_H_
7 #define RTE_PMD_MLX5_PRM_H_
12 #include <rte_byteorder.h>
14 #include <mlx5_glue.h>
15 #include "mlx5_autoconf.h"
17 /* RSS hash key size. */
18 #define MLX5_RSS_HASH_KEY_LEN 40
20 /* Get CQE owner bit. */
21 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
24 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
27 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
29 /* Get CQE solicited event. */
30 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
32 /* Invalidate a CQE. */
33 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
35 /* Hardware index widths. */
36 #define MLX5_CQ_INDEX_WIDTH 24
37 #define MLX5_WQ_INDEX_WIDTH 16
39 /* WQE Segment sizes in bytes. */
40 #define MLX5_WSEG_SIZE 16u
41 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
42 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
43 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
45 /* WQE/WQEBB size in bytes. */
46 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
49 * Max size of a WQE session.
50 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
51 * the WQE size field in Control Segment is 6 bits wide.
53 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
56 * Default minimum number of Tx queues for inlining packets.
57 * If there are less queues as specified we assume we have
58 * no enough CPU resources (cycles) to perform inlining,
59 * the PCIe throughput is not supposed as bottleneck and
60 * inlining is disabled.
62 #define MLX5_INLINE_MAX_TXQS 8u
63 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
66 * Default packet length threshold to be inlined with
67 * enhanced MPW. If packet length exceeds the threshold
68 * the data are not inlined. Should be aligned in WQEBB
69 * boundary with accounting the title Control and Ethernet
72 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
73 MLX5_DSEG_MIN_INLINE_SIZE)
75 * Maximal inline data length sent with enhanced MPW.
76 * Is based on maximal WQE size.
78 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
79 MLX5_WQE_CSEG_SIZE - \
80 MLX5_WQE_ESEG_SIZE - \
81 MLX5_WQE_DSEG_SIZE + \
82 MLX5_DSEG_MIN_INLINE_SIZE)
84 * Minimal amount of packets to be sent with EMPW.
85 * This limits the minimal required size of sent EMPW.
86 * If there are no enough resources to built minimal
87 * EMPW the sending loop exits.
89 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
91 * Maximal amount of packets to be sent with EMPW.
92 * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
93 * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
94 * without CQE generation request, being multiplied by
95 * MLX5_TX_COMP_MAX_CQE it may cause significant latency
96 * in tx burst routine at the moment of freeing multiple mbufs.
98 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
99 #define MLX5_MPW_MAX_PACKETS 6
100 #define MLX5_MPW_INLINE_MAX_PACKETS 6
103 * Default packet length threshold to be inlined with
104 * ordinary SEND. Inlining saves the MR key search
105 * and extra PCIe data fetch transaction, but eats the
108 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
109 MLX5_ESEG_MIN_INLINE_SIZE - \
110 MLX5_WQE_CSEG_SIZE - \
111 MLX5_WQE_ESEG_SIZE - \
114 * Maximal inline data length sent with ordinary SEND.
115 * Is based on maximal WQE size.
117 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
118 MLX5_WQE_CSEG_SIZE - \
119 MLX5_WQE_ESEG_SIZE - \
120 MLX5_WQE_DSEG_SIZE + \
121 MLX5_ESEG_MIN_INLINE_SIZE)
123 /* Missed in mlv5dv.h, should define here. */
124 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW
125 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
128 #ifndef HAVE_MLX5_OPCODE_SEND_EN
129 #define MLX5_OPCODE_SEND_EN 0x17u
132 #ifndef HAVE_MLX5_OPCODE_WAIT
133 #define MLX5_OPCODE_WAIT 0x0fu
136 /* CQE value to inform that VLAN is stripped. */
137 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
140 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
143 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
146 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
149 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
152 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
154 /* IP is fragmented. */
155 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
157 /* L2 header is valid. */
158 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
160 /* L3 header is valid. */
161 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
163 /* L4 header is valid. */
164 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
166 /* Outer packet, 0 IPv4, 1 IPv6. */
167 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
169 /* Tunnel packet bit in the CQE. */
170 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
172 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
173 #define MLX5_CQE_LRO_PUSH_MASK 0x40
175 /* Mask for L4 type in the CQE hdr_type_etc field. */
176 #define MLX5_CQE_L4_TYPE_MASK 0x70
178 /* The bit index of L4 type in CQE hdr_type_etc field. */
179 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
181 /* L4 type to indicate TCP packet without acknowledgment. */
182 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
184 /* L4 type to indicate TCP packet with acknowledgment. */
185 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
187 /* Inner L3 checksum offload (Tunneled packets only). */
188 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
190 /* Inner L4 checksum offload (Tunneled packets only). */
191 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
193 /* Outer L4 type is TCP. */
194 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5)
196 /* Outer L4 type is UDP. */
197 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5)
199 /* Outer L3 type is IPV4. */
200 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
202 /* Outer L3 type is IPV6. */
203 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
205 /* Inner L4 type is TCP. */
206 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
208 /* Inner L4 type is UDP. */
209 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
211 /* Inner L3 type is IPV4. */
212 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
214 /* Inner L3 type is IPV6. */
215 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
217 /* VLAN insertion flag. */
218 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
220 /* Data inline segment flag. */
221 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
223 /* Is flow mark valid. */
224 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
225 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
227 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
230 /* INVALID is used by packets matching no flow rules. */
231 #define MLX5_FLOW_MARK_INVALID 0
233 /* Maximum allowed value to mark a packet. */
234 #define MLX5_FLOW_MARK_MAX 0xfffff0
236 /* Default mark value used when none is provided. */
237 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
239 /* Default mark mask for metadata legacy mode. */
240 #define MLX5_FLOW_MARK_MASK 0xffffff
242 /* Maximum number of DS in WQE. Limited by 6-bit field. */
243 #define MLX5_DSEG_MAX 63
245 /* The completion mode offset in the WQE control segment line 2. */
246 #define MLX5_COMP_MODE_OFFSET 2
248 /* Amount of data bytes in minimal inline data segment. */
249 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
251 /* Amount of data bytes in minimal inline eth segment. */
252 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
254 /* Amount of data bytes after eth data segment. */
255 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
257 /* The maximum log value of segments per RQ WQE. */
258 #define MLX5_MAX_LOG_RQ_SEGS 5u
260 /* The alignment needed for WQ buffer. */
261 #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size()
263 /* The alignment needed for CQ buffer. */
264 #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size()
266 /* Completion mode. */
267 enum mlx5_completion_mode {
268 MLX5_COMP_ONLY_ERR = 0x0,
269 MLX5_COMP_ONLY_FIRST_ERR = 0x1,
270 MLX5_COMP_ALWAYS = 0x2,
271 MLX5_COMP_CQE_AND_EQE = 0x3,
278 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
281 /* WQE Control segment. */
282 struct mlx5_wqe_cseg {
287 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
289 /* Header of data segment. Minimal size Data Segment */
290 struct mlx5_wqe_dseg {
293 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
301 /* Subset of struct WQE Ethernet Segment. */
302 struct mlx5_wqe_eseg {
310 uint16_t inline_hdr_sz;
312 uint16_t inline_data;
319 uint32_t flow_metadata;
325 struct mlx5_wqe_qseg {
332 /* The title WQEBB, header of WQE. */
335 struct mlx5_wqe_cseg cseg;
338 struct mlx5_wqe_eseg eseg;
340 struct mlx5_wqe_dseg dseg[2];
341 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
345 /* WQE for Multi-Packet RQ. */
346 struct mlx5_wqe_mprq {
347 struct mlx5_wqe_srq_next_seg next_seg;
348 struct mlx5_wqe_data_seg dseg;
351 #define MLX5_MPRQ_LEN_MASK 0x000ffff
352 #define MLX5_MPRQ_LEN_SHIFT 0
353 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
354 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
355 #define MLX5_MPRQ_FILLER_MASK 0x80000000
356 #define MLX5_MPRQ_FILLER_SHIFT 31
358 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
360 /* CQ element structure - should be equal to the cache line size */
362 #if (RTE_CACHE_LINE_SIZE == 128)
368 uint8_t lro_tcppsh_abort_dupack;
370 uint16_t lro_tcp_win;
371 uint32_t lro_ack_seq_num;
372 uint32_t rx_hash_res;
373 uint8_t rx_hash_type;
377 uint16_t hdr_type_etc;
381 uint32_t flow_table_metadata;
385 uint32_t sop_drop_qpn;
386 uint16_t wqe_counter;
393 uint32_t sop_drop_qpn;
394 uint16_t wqe_counter;
399 /* MMO metadata segment */
401 #define MLX5_OPCODE_MMO 0x2f
402 #define MLX5_OPC_MOD_MMO_REGEX 0x4
404 struct mlx5_wqe_metadata_seg {
405 uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */
410 struct mlx5_ifc_regexp_mmo_control_bits {
411 uint8_t reserved_at_31[0x2];
413 uint8_t reserved_at_28[0x1];
414 uint8_t subset_id_0[0xc];
415 uint8_t reserved_at_16[0x4];
416 uint8_t subset_id_1[0xc];
418 uint8_t subset_id_2[0xc];
419 uint8_t reserved_at_16_1[0x4];
420 uint8_t subset_id_3[0xc];
423 struct mlx5_ifc_regexp_metadata_bits {
424 uint8_t rof_version[0x10];
425 uint8_t latency_count[0x10];
426 uint8_t instruction_count[0x10];
427 uint8_t primary_thread_count[0x10];
428 uint8_t match_count[0x8];
429 uint8_t detected_match_count[0x8];
430 uint8_t status[0x10];
431 uint8_t job_id[0x20];
432 uint8_t reserved[0x80];
435 struct mlx5_ifc_regexp_match_tuple_bits {
436 uint8_t length[0x10];
437 uint8_t start_ptr[0x10];
438 uint8_t rule_id[0x20];
441 /* Adding direct verbs to data-path. */
443 /* CQ sequence number mask. */
444 #define MLX5_CQ_SQN_MASK 0x3
446 /* CQ sequence number index. */
447 #define MLX5_CQ_SQN_OFFSET 28
449 /* CQ doorbell index mask. */
450 #define MLX5_CI_MASK 0xffffff
452 /* CQ doorbell offset. */
453 #define MLX5_CQ_ARM_DB 1
455 /* CQ doorbell offset*/
456 #define MLX5_CQ_DOORBELL 0x20
458 /* CQE format value. */
459 #define MLX5_COMPRESSED 0x3
461 /* CQ doorbell cmd types. */
462 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24)
463 #define MLX5_CQ_DBR_CMD_ALL (0 << 24)
465 /* Action type of header modification. */
467 MLX5_MODIFICATION_TYPE_SET = 0x1,
468 MLX5_MODIFICATION_TYPE_ADD = 0x2,
469 MLX5_MODIFICATION_TYPE_COPY = 0x3,
472 /* The field of packet to be modified. */
473 enum mlx5_modification_field {
474 MLX5_MODI_OUT_NONE = -1,
475 MLX5_MODI_OUT_SMAC_47_16 = 1,
476 MLX5_MODI_OUT_SMAC_15_0,
477 MLX5_MODI_OUT_ETHERTYPE,
478 MLX5_MODI_OUT_DMAC_47_16,
479 MLX5_MODI_OUT_DMAC_15_0,
480 MLX5_MODI_OUT_IP_DSCP,
481 MLX5_MODI_OUT_TCP_FLAGS,
482 MLX5_MODI_OUT_TCP_SPORT,
483 MLX5_MODI_OUT_TCP_DPORT,
484 MLX5_MODI_OUT_IPV4_TTL,
485 MLX5_MODI_OUT_UDP_SPORT,
486 MLX5_MODI_OUT_UDP_DPORT,
487 MLX5_MODI_OUT_SIPV6_127_96,
488 MLX5_MODI_OUT_SIPV6_95_64,
489 MLX5_MODI_OUT_SIPV6_63_32,
490 MLX5_MODI_OUT_SIPV6_31_0,
491 MLX5_MODI_OUT_DIPV6_127_96,
492 MLX5_MODI_OUT_DIPV6_95_64,
493 MLX5_MODI_OUT_DIPV6_63_32,
494 MLX5_MODI_OUT_DIPV6_31_0,
497 MLX5_MODI_OUT_FIRST_VID,
498 MLX5_MODI_IN_SMAC_47_16 = 0x31,
499 MLX5_MODI_IN_SMAC_15_0,
500 MLX5_MODI_IN_ETHERTYPE,
501 MLX5_MODI_IN_DMAC_47_16,
502 MLX5_MODI_IN_DMAC_15_0,
503 MLX5_MODI_IN_IP_DSCP,
504 MLX5_MODI_IN_TCP_FLAGS,
505 MLX5_MODI_IN_TCP_SPORT,
506 MLX5_MODI_IN_TCP_DPORT,
507 MLX5_MODI_IN_IPV4_TTL,
508 MLX5_MODI_IN_UDP_SPORT,
509 MLX5_MODI_IN_UDP_DPORT,
510 MLX5_MODI_IN_SIPV6_127_96,
511 MLX5_MODI_IN_SIPV6_95_64,
512 MLX5_MODI_IN_SIPV6_63_32,
513 MLX5_MODI_IN_SIPV6_31_0,
514 MLX5_MODI_IN_DIPV6_127_96,
515 MLX5_MODI_IN_DIPV6_95_64,
516 MLX5_MODI_IN_DIPV6_63_32,
517 MLX5_MODI_IN_DIPV6_31_0,
520 MLX5_MODI_OUT_IPV6_HOPLIMIT,
521 MLX5_MODI_IN_IPV6_HOPLIMIT,
522 MLX5_MODI_META_DATA_REG_A,
523 MLX5_MODI_META_DATA_REG_B = 0x50,
524 MLX5_MODI_META_REG_C_0,
525 MLX5_MODI_META_REG_C_1,
526 MLX5_MODI_META_REG_C_2,
527 MLX5_MODI_META_REG_C_3,
528 MLX5_MODI_META_REG_C_4,
529 MLX5_MODI_META_REG_C_5,
530 MLX5_MODI_META_REG_C_6,
531 MLX5_MODI_META_REG_C_7,
532 MLX5_MODI_OUT_TCP_SEQ_NUM,
533 MLX5_MODI_IN_TCP_SEQ_NUM,
534 MLX5_MODI_OUT_TCP_ACK_NUM,
535 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
538 /* Total number of metadata reg_c's. */
539 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1)
555 /* Modification sub command. */
556 struct mlx5_modification_cmd {
560 unsigned int length:5;
561 unsigned int rsvd0:3;
562 unsigned int offset:5;
563 unsigned int rsvd1:3;
564 unsigned int field:12;
565 unsigned int action_type:4;
572 unsigned int rsvd2:8;
573 unsigned int dst_offset:5;
574 unsigned int rsvd3:3;
575 unsigned int dst_field:12;
576 unsigned int rsvd4:4;
581 typedef uint32_t u32;
582 typedef uint16_t u16;
585 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
586 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
587 #define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \
588 (&(__mlx5_nullp(typ)->fld)))
589 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
590 (__mlx5_bit_off(typ, fld) & 0x1f))
591 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
592 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
593 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
594 __mlx5_dw_bit_off(typ, fld))
595 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
596 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
597 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
598 (__mlx5_bit_off(typ, fld) & 0xf))
599 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
600 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \
601 __mlx5_16_bit_off(typ, fld))
602 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
603 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
604 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
605 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
607 /* insert a value to a struct */
608 #define MLX5_SET(typ, p, fld, v) \
611 *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \
612 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
613 __mlx5_dw_off(typ, fld))) & \
614 (~__mlx5_dw_mask(typ, fld))) | \
615 (((_v) & __mlx5_mask(typ, fld)) << \
616 __mlx5_dw_bit_off(typ, fld))); \
619 #define MLX5_SET64(typ, p, fld, v) \
621 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \
622 *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \
623 rte_cpu_to_be_64(v); \
626 #define MLX5_SET16(typ, p, fld, v) \
629 *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \
630 rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
631 __mlx5_16_off(typ, fld))) & \
632 (~__mlx5_16_mask(typ, fld))) | \
633 (((_v) & __mlx5_mask16(typ, fld)) << \
634 __mlx5_16_bit_off(typ, fld))); \
637 #define MLX5_GET_VOLATILE(typ, p, fld) \
638 ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\
639 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
640 __mlx5_mask(typ, fld))
641 #define MLX5_GET(typ, p, fld) \
642 ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\
643 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
644 __mlx5_mask(typ, fld))
645 #define MLX5_GET16(typ, p, fld) \
646 ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
647 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
648 __mlx5_mask16(typ, fld))
649 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \
650 __mlx5_64_off(typ, fld)))
651 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
653 struct mlx5_ifc_fte_match_set_misc_bits {
654 u8 gre_c_present[0x1];
655 u8 reserved_at_1[0x1];
656 u8 gre_k_present[0x1];
657 u8 gre_s_present[0x1];
658 u8 source_vhci_port[0x4];
660 u8 reserved_at_20[0x10];
661 u8 source_port[0x10];
662 u8 outer_second_prio[0x3];
663 u8 outer_second_cfi[0x1];
664 u8 outer_second_vid[0xc];
665 u8 inner_second_prio[0x3];
666 u8 inner_second_cfi[0x1];
667 u8 inner_second_vid[0xc];
668 u8 outer_second_cvlan_tag[0x1];
669 u8 inner_second_cvlan_tag[0x1];
670 u8 outer_second_svlan_tag[0x1];
671 u8 inner_second_svlan_tag[0x1];
672 u8 reserved_at_64[0xc];
673 u8 gre_protocol[0x10];
677 u8 reserved_at_b8[0x8];
679 u8 reserved_at_e4[0x7];
681 u8 reserved_at_e0[0xc];
682 u8 outer_ipv6_flow_label[0x14];
683 u8 reserved_at_100[0xc];
684 u8 inner_ipv6_flow_label[0x14];
685 u8 reserved_at_120[0xa];
686 u8 geneve_opt_len[0x6];
687 u8 geneve_protocol_type[0x10];
688 u8 reserved_at_140[0xc0];
691 struct mlx5_ifc_ipv4_layout_bits {
692 u8 reserved_at_0[0x60];
696 struct mlx5_ifc_ipv6_layout_bits {
700 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
701 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
702 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
703 u8 reserved_at_0[0x80];
706 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
725 u8 reserved_at_c0[0x18];
726 u8 ip_ttl_hoplimit[0x8];
729 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
730 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
733 struct mlx5_ifc_fte_match_mpls_bits {
740 struct mlx5_ifc_fte_match_set_misc2_bits {
741 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
742 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
743 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
744 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
745 u8 metadata_reg_c_7[0x20];
746 u8 metadata_reg_c_6[0x20];
747 u8 metadata_reg_c_5[0x20];
748 u8 metadata_reg_c_4[0x20];
749 u8 metadata_reg_c_3[0x20];
750 u8 metadata_reg_c_2[0x20];
751 u8 metadata_reg_c_1[0x20];
752 u8 metadata_reg_c_0[0x20];
753 u8 metadata_reg_a[0x20];
754 u8 metadata_reg_b[0x20];
755 u8 reserved_at_1c0[0x40];
758 struct mlx5_ifc_fte_match_set_misc3_bits {
759 u8 inner_tcp_seq_num[0x20];
760 u8 outer_tcp_seq_num[0x20];
761 u8 inner_tcp_ack_num[0x20];
762 u8 outer_tcp_ack_num[0x20];
763 u8 reserved_at_auto1[0x8];
764 u8 outer_vxlan_gpe_vni[0x18];
765 u8 outer_vxlan_gpe_next_protocol[0x8];
766 u8 outer_vxlan_gpe_flags[0x8];
767 u8 reserved_at_a8[0x10];
768 u8 icmp_header_data[0x20];
769 u8 icmpv6_header_data[0x20];
774 u8 reserved_at_120[0x20];
776 u8 gtpu_msg_type[0x08];
777 u8 gtpu_msg_flags[0x08];
778 u8 reserved_at_170[0x90];
781 struct mlx5_ifc_fte_match_set_misc4_bits {
782 u8 prog_sample_field_value_0[0x20];
783 u8 prog_sample_field_id_0[0x20];
784 u8 prog_sample_field_value_1[0x20];
785 u8 prog_sample_field_id_1[0x20];
786 u8 prog_sample_field_value_2[0x20];
787 u8 prog_sample_field_id_2[0x20];
788 u8 prog_sample_field_value_3[0x20];
789 u8 prog_sample_field_id_3[0x20];
790 u8 reserved_at_100[0x100];
794 struct mlx5_ifc_fte_match_param_bits {
795 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
796 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
797 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
798 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
799 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
800 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
804 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
805 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
806 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
807 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
808 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT,
809 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT,
813 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
814 MLX5_CMD_OP_CREATE_MKEY = 0x200,
815 MLX5_CMD_OP_CREATE_CQ = 0x400,
816 MLX5_CMD_OP_CREATE_QP = 0x500,
817 MLX5_CMD_OP_RST2INIT_QP = 0x502,
818 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
819 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
820 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
821 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
822 MLX5_CMD_OP_QP_2ERR = 0x507,
823 MLX5_CMD_OP_QP_2RST = 0x50A,
824 MLX5_CMD_OP_QUERY_QP = 0x50B,
825 MLX5_CMD_OP_SQD2RTS_QP = 0x50C,
826 MLX5_CMD_OP_INIT2INIT_QP = 0x50E,
827 MLX5_CMD_OP_SUSPEND_QP = 0x50F,
828 MLX5_CMD_OP_RESUME_QP = 0x510,
829 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
830 MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
831 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
832 MLX5_CMD_OP_CREATE_TIR = 0x900,
833 MLX5_CMD_OP_CREATE_SQ = 0X904,
834 MLX5_CMD_OP_MODIFY_SQ = 0X905,
835 MLX5_CMD_OP_CREATE_RQ = 0x908,
836 MLX5_CMD_OP_MODIFY_RQ = 0x909,
837 MLX5_CMD_OP_CREATE_TIS = 0x912,
838 MLX5_CMD_OP_QUERY_TIS = 0x915,
839 MLX5_CMD_OP_CREATE_RQT = 0x916,
840 MLX5_CMD_OP_MODIFY_RQT = 0x917,
841 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
842 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
843 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
844 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
845 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
846 MLX5_CMD_SET_REGEX_PARAMS = 0xb04,
847 MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,
848 MLX5_CMD_SET_REGEX_REGISTERS = 0xb06,
849 MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
850 MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c,
854 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
855 MLX5_MKC_ACCESS_MODE_KLM = 0x2,
856 MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3,
859 #define MLX5_ADAPTER_PAGE_SHIFT 12
860 #define MLX5_LOG_RQ_STRIDE_SHIFT 4
862 * The batch counter dcs id starts from 0x800000 and none batch counter
863 * starts from 0. As currently, the counter is changed to be indexed by
864 * pool index and the offset of the counter in the pool counters_raw array.
865 * It means now the counter index is same for batch and none batch counter.
866 * Add the 0x800000 batch counter offset to the batch counter index helps
867 * indicate the counter index is from batch or none batch container pool.
869 #define MLX5_CNT_BATCH_OFFSET 0x800000
871 /* The counter batch query requires ID align with 4. */
872 #define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4
875 struct mlx5_ifc_alloc_flow_counter_out_bits {
877 u8 reserved_at_8[0x18];
879 u8 flow_counter_id[0x20];
880 u8 reserved_at_60[0x20];
883 struct mlx5_ifc_alloc_flow_counter_in_bits {
885 u8 reserved_at_10[0x10];
886 u8 reserved_at_20[0x10];
888 u8 flow_counter_id[0x20];
889 u8 reserved_at_40[0x18];
890 u8 flow_counter_bulk[0x8];
893 struct mlx5_ifc_dealloc_flow_counter_out_bits {
895 u8 reserved_at_8[0x18];
897 u8 reserved_at_40[0x40];
900 struct mlx5_ifc_dealloc_flow_counter_in_bits {
902 u8 reserved_at_10[0x10];
903 u8 reserved_at_20[0x10];
905 u8 flow_counter_id[0x20];
906 u8 reserved_at_60[0x20];
909 struct mlx5_ifc_traffic_counter_bits {
914 struct mlx5_ifc_query_flow_counter_out_bits {
916 u8 reserved_at_8[0x18];
918 u8 reserved_at_40[0x40];
919 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
922 struct mlx5_ifc_query_flow_counter_in_bits {
924 u8 reserved_at_10[0x10];
925 u8 reserved_at_20[0x10];
927 u8 reserved_at_40[0x20];
931 u8 dump_to_memory[0x1];
932 u8 num_of_counters[0x1e];
933 u8 flow_counter_id[0x20];
936 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u
937 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u
940 struct mlx5_ifc_klm_bits {
946 struct mlx5_ifc_mkc_bits {
947 u8 reserved_at_0[0x1];
949 u8 reserved_at_2[0x1];
950 u8 access_mode_4_2[0x3];
951 u8 reserved_at_6[0x7];
952 u8 relaxed_ordering_write[0x1];
953 u8 reserved_at_e[0x1];
954 u8 small_fence_on_rdma_read_response[0x1];
961 u8 access_mode_1_0[0x2];
962 u8 reserved_at_18[0x8];
967 u8 reserved_at_40[0x20];
972 u8 reserved_at_63[0x2];
973 u8 expected_sigerr_count[0x1];
974 u8 reserved_at_66[0x1];
982 u8 bsf_octword_size[0x20];
984 u8 reserved_at_120[0x80];
986 u8 translations_octword_size[0x20];
988 u8 reserved_at_1c0[0x19];
989 u8 relaxed_ordering_read[0x1];
990 u8 reserved_at_1da[0x1];
991 u8 log_page_size[0x5];
993 u8 reserved_at_1e0[0x20];
996 struct mlx5_ifc_create_mkey_out_bits {
998 u8 reserved_at_8[0x18];
1002 u8 reserved_at_40[0x8];
1003 u8 mkey_index[0x18];
1005 u8 reserved_at_60[0x20];
1008 struct mlx5_ifc_create_mkey_in_bits {
1010 u8 reserved_at_10[0x10];
1012 u8 reserved_at_20[0x10];
1015 u8 reserved_at_40[0x20];
1018 u8 reserved_at_61[0x1f];
1020 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
1022 u8 reserved_at_280[0x80];
1024 u8 translations_octword_actual_size[0x20];
1026 u8 mkey_umem_id[0x20];
1028 u8 mkey_umem_offset[0x40];
1030 u8 reserved_at_380[0x500];
1032 u8 klm_pas_mtt[][0x20];
1036 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
1037 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
1038 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
1039 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,
1040 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
1043 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q (1ULL << 0xd)
1044 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS (1ULL << 0x1c)
1045 #define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE (1ULL << 0x22)
1048 MLX5_HCA_CAP_OPMOD_GET_MAX = 0,
1049 MLX5_HCA_CAP_OPMOD_GET_CUR = 1,
1053 MLX5_CAP_INLINE_MODE_L2,
1054 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
1055 MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
1059 MLX5_INLINE_MODE_NONE,
1060 MLX5_INLINE_MODE_L2,
1061 MLX5_INLINE_MODE_IP,
1062 MLX5_INLINE_MODE_TCP_UDP,
1063 MLX5_INLINE_MODE_RESERVED4,
1064 MLX5_INLINE_MODE_INNER_L2,
1065 MLX5_INLINE_MODE_INNER_IP,
1066 MLX5_INLINE_MODE_INNER_TCP_UDP,
1069 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
1070 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
1071 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
1072 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
1073 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
1074 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
1075 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
1076 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
1077 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
1078 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
1079 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
1081 struct mlx5_ifc_cmd_hca_cap_bits {
1082 u8 reserved_at_0[0x30];
1084 u8 reserved_at_40[0x40];
1085 u8 log_max_srq_sz[0x8];
1086 u8 log_max_qp_sz[0x8];
1087 u8 reserved_at_90[0x9];
1088 u8 wqe_index_ignore_cap[0x1];
1089 u8 dynamic_qp_allocation[0x1];
1092 u8 reserved_at_a1[0x3];
1093 u8 regexp_num_of_engines[0x4];
1094 u8 reserved_at_a8[0x3];
1095 u8 log_max_srq[0x5];
1096 u8 reserved_at_b0[0x3];
1097 u8 regexp_log_crspace_size[0x5];
1098 u8 reserved_at_b8[0x3];
1099 u8 scatter_fcs_w_decap_disable[0x1];
1100 u8 reserved_at_bc[0x4];
1101 u8 reserved_at_c0[0x8];
1102 u8 log_max_cq_sz[0x8];
1103 u8 reserved_at_d0[0xb];
1105 u8 log_max_eq_sz[0x8];
1106 u8 relaxed_ordering_write[0x1];
1107 u8 relaxed_ordering_read[0x1];
1108 u8 access_register_user[0x1];
1109 u8 log_max_mkey[0x5];
1110 u8 reserved_at_f0[0x8];
1111 u8 dump_fill_mkey[0x1];
1112 u8 reserved_at_f9[0x3];
1114 u8 max_indirection[0x8];
1115 u8 fixed_buffer_size[0x1];
1116 u8 log_max_mrw_sz[0x7];
1117 u8 force_teardown[0x1];
1118 u8 reserved_at_111[0x1];
1119 u8 log_max_bsf_list_size[0x6];
1120 u8 umr_extended_translation_offset[0x1];
1122 u8 log_max_klm_list_size[0x6];
1123 u8 non_wire_sq[0x1];
1124 u8 reserved_at_121[0x9];
1125 u8 log_max_ra_req_dc[0x6];
1126 u8 reserved_at_130[0x3];
1127 u8 log_max_static_sq_wq[0x5];
1128 u8 reserved_at_138[0x2];
1129 u8 log_max_ra_res_dc[0x6];
1130 u8 reserved_at_140[0xa];
1131 u8 log_max_ra_req_qp[0x6];
1132 u8 reserved_at_150[0xa];
1133 u8 log_max_ra_res_qp[0x6];
1135 u8 cc_query_allowed[0x1];
1136 u8 cc_modify_allowed[0x1];
1138 u8 cache_line_128byte[0x1];
1139 u8 reserved_at_165[0xa];
1141 u8 gid_table_size[0x10];
1142 u8 out_of_seq_cnt[0x1];
1143 u8 vport_counters[0x1];
1144 u8 retransmission_q_counters[0x1];
1146 u8 modify_rq_counter_set_id[0x1];
1147 u8 rq_delay_drop[0x1];
1149 u8 pkey_table_size[0x10];
1150 u8 vport_group_manager[0x1];
1151 u8 vhca_group_manager[0x1];
1154 u8 vnic_env_queue_counters[0x1];
1156 u8 nic_flow_table[0x1];
1157 u8 eswitch_manager[0x1];
1158 u8 device_memory[0x1];
1161 u8 local_ca_ack_delay[0x5];
1162 u8 port_module_event[0x1];
1163 u8 enhanced_error_q_counters[0x1];
1164 u8 ports_check[0x1];
1165 u8 reserved_at_1b3[0x1];
1166 u8 disable_link_up[0x1];
1170 u8 reserved_at_1c0[0x1];
1173 u8 log_max_msg[0x5];
1174 u8 reserved_at_1c8[0x4];
1176 u8 temp_warn_event[0x1];
1178 u8 general_notification_event[0x1];
1179 u8 reserved_at_1d3[0x2];
1183 u8 reserved_at_1d8[0x1];
1191 u8 stat_rate_support[0x10];
1192 u8 reserved_at_1f0[0xc];
1193 u8 cqe_version[0x4];
1194 u8 compact_address_vector[0x1];
1195 u8 striding_rq[0x1];
1196 u8 reserved_at_202[0x1];
1197 u8 ipoib_enhanced_offloads[0x1];
1198 u8 ipoib_basic_offloads[0x1];
1199 u8 reserved_at_205[0x1];
1200 u8 repeated_block_disabled[0x1];
1201 u8 umr_modify_entity_size_disabled[0x1];
1202 u8 umr_modify_atomic_disabled[0x1];
1203 u8 umr_indirect_mkey_disabled[0x1];
1205 u8 reserved_at_20c[0x3];
1206 u8 drain_sigerr[0x1];
1207 u8 cmdif_checksum[0x2];
1209 u8 reserved_at_213[0x1];
1210 u8 wq_signature[0x1];
1211 u8 sctr_data_cqe[0x1];
1212 u8 reserved_at_216[0x1];
1218 u8 eth_net_offloads[0x1];
1221 u8 reserved_at_21f[0x1];
1224 u8 cq_moderation[0x1];
1225 u8 reserved_at_223[0x3];
1226 u8 cq_eq_remap[0x1];
1228 u8 block_lb_mc[0x1];
1229 u8 reserved_at_229[0x1];
1230 u8 scqe_break_moderation[0x1];
1231 u8 cq_period_start_from_cqe[0x1];
1233 u8 reserved_at_22d[0x1];
1235 u8 vector_calc[0x1];
1236 u8 umr_ptr_rlky[0x1];
1238 u8 reserved_at_232[0x4];
1241 u8 set_deth_sqpn[0x1];
1242 u8 reserved_at_239[0x3];
1248 u8 reserved_at_241[0x9];
1250 u8 reserved_at_250[0x8];
1253 u8 driver_version[0x1];
1254 u8 pad_tx_eth_packet[0x1];
1255 u8 reserved_at_263[0x8];
1256 u8 log_bf_reg_size[0x5];
1257 u8 reserved_at_270[0xb];
1259 u8 num_lag_ports[0x4];
1260 u8 reserved_at_280[0x10];
1261 u8 max_wqe_sz_sq[0x10];
1262 u8 reserved_at_2a0[0x10];
1263 u8 max_wqe_sz_rq[0x10];
1264 u8 max_flow_counter_31_16[0x10];
1265 u8 max_wqe_sz_sq_dc[0x10];
1266 u8 reserved_at_2e0[0x7];
1267 u8 max_qp_mcg[0x19];
1268 u8 reserved_at_300[0x10];
1269 u8 flow_counter_bulk_alloc[0x08];
1270 u8 log_max_mcg[0x8];
1271 u8 reserved_at_320[0x3];
1272 u8 log_max_transport_domain[0x5];
1273 u8 reserved_at_328[0x3];
1275 u8 reserved_at_330[0xb];
1276 u8 log_max_xrcd[0x5];
1277 u8 nic_receive_steering_discard[0x1];
1278 u8 receive_discard_vport_down[0x1];
1279 u8 transmit_discard_vport_down[0x1];
1280 u8 reserved_at_343[0x5];
1281 u8 log_max_flow_counter_bulk[0x8];
1282 u8 max_flow_counter_15_0[0x10];
1284 u8 flow_counters_dump[0x1];
1285 u8 reserved_at_360[0x1];
1287 u8 reserved_at_368[0x3];
1289 u8 reserved_at_370[0x3];
1290 u8 log_max_tir[0x5];
1291 u8 reserved_at_378[0x3];
1292 u8 log_max_tis[0x5];
1293 u8 basic_cyclic_rcv_wqe[0x1];
1294 u8 reserved_at_381[0x2];
1295 u8 log_max_rmp[0x5];
1296 u8 reserved_at_388[0x3];
1297 u8 log_max_rqt[0x5];
1298 u8 reserved_at_390[0x3];
1299 u8 log_max_rqt_size[0x5];
1300 u8 reserved_at_398[0x3];
1301 u8 log_max_tis_per_sq[0x5];
1302 u8 ext_stride_num_range[0x1];
1303 u8 reserved_at_3a1[0x2];
1304 u8 log_max_stride_sz_rq[0x5];
1305 u8 reserved_at_3a8[0x3];
1306 u8 log_min_stride_sz_rq[0x5];
1307 u8 reserved_at_3b0[0x3];
1308 u8 log_max_stride_sz_sq[0x5];
1309 u8 reserved_at_3b8[0x3];
1310 u8 log_min_stride_sz_sq[0x5];
1312 u8 reserved_at_3c1[0x2];
1313 u8 log_max_hairpin_queues[0x5];
1314 u8 reserved_at_3c8[0x3];
1315 u8 log_max_hairpin_wq_data_sz[0x5];
1316 u8 reserved_at_3d0[0x3];
1317 u8 log_max_hairpin_num_packets[0x5];
1318 u8 reserved_at_3d8[0x3];
1319 u8 log_max_wq_sz[0x5];
1320 u8 nic_vport_change_event[0x1];
1321 u8 disable_local_lb_uc[0x1];
1322 u8 disable_local_lb_mc[0x1];
1323 u8 log_min_hairpin_wq_data_sz[0x5];
1324 u8 reserved_at_3e8[0x3];
1325 u8 log_max_vlan_list[0x5];
1326 u8 reserved_at_3f0[0x3];
1327 u8 log_max_current_mc_list[0x5];
1328 u8 reserved_at_3f8[0x3];
1329 u8 log_max_current_uc_list[0x5];
1330 u8 general_obj_types[0x40];
1331 u8 reserved_at_440[0x20];
1332 u8 reserved_at_460[0x10];
1333 u8 max_num_eqs[0x10];
1334 u8 reserved_at_480[0x3];
1335 u8 log_max_l2_table[0x5];
1336 u8 reserved_at_488[0x8];
1337 u8 log_uar_page_sz[0x10];
1338 u8 reserved_at_4a0[0x20];
1339 u8 device_frequency_mhz[0x20];
1340 u8 device_frequency_khz[0x20];
1341 u8 reserved_at_500[0x20];
1342 u8 num_of_uars_per_page[0x20];
1343 u8 flex_parser_protocols[0x20];
1344 u8 reserved_at_560[0x20];
1345 u8 reserved_at_580[0x3c];
1346 u8 mini_cqe_resp_stride_index[0x1];
1347 u8 cqe_128_always[0x1];
1348 u8 cqe_compression_128[0x1];
1349 u8 cqe_compression[0x1];
1350 u8 cqe_compression_timeout[0x10];
1351 u8 cqe_compression_max_num[0x10];
1352 u8 reserved_at_5e0[0x10];
1353 u8 tag_matching[0x1];
1354 u8 rndv_offload_rc[0x1];
1355 u8 rndv_offload_dc[0x1];
1356 u8 log_tag_matching_list_sz[0x5];
1357 u8 reserved_at_5f8[0x3];
1358 u8 log_max_xrq[0x5];
1359 u8 affiliate_nic_vport_criteria[0x8];
1360 u8 native_port_num[0x8];
1361 u8 num_vhca_ports[0x8];
1362 u8 reserved_at_618[0x6];
1363 u8 sw_owner_id[0x1];
1364 u8 reserved_at_61f[0x1e1];
1367 struct mlx5_ifc_qos_cap_bits {
1368 u8 packet_pacing[0x1];
1369 u8 esw_scheduling[0x1];
1370 u8 esw_bw_share[0x1];
1371 u8 esw_rate_limit[0x1];
1372 u8 reserved_at_4[0x1];
1373 u8 packet_pacing_burst_bound[0x1];
1374 u8 packet_pacing_typical_size[0x1];
1375 u8 flow_meter_srtcm[0x1];
1376 u8 reserved_at_8[0x8];
1377 u8 log_max_flow_meter[0x8];
1378 u8 flow_meter_reg_id[0x8];
1379 u8 wqe_rate_pp[0x1];
1380 u8 reserved_at_25[0x7];
1381 u8 flow_meter_reg_share[0x1];
1382 u8 reserved_at_2e[0x17];
1383 u8 packet_pacing_max_rate[0x20];
1384 u8 packet_pacing_min_rate[0x20];
1385 u8 reserved_at_80[0x10];
1386 u8 packet_pacing_rate_table_size[0x10];
1387 u8 esw_element_type[0x10];
1388 u8 esw_tsar_type[0x10];
1389 u8 reserved_at_c0[0x10];
1390 u8 max_qos_para_vport[0x10];
1391 u8 max_tsar_bw_share[0x20];
1392 u8 reserved_at_100[0x6e8];
1395 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1399 u8 lro_psh_flag[0x1];
1400 u8 lro_time_stamp[0x1];
1401 u8 lro_max_msg_sz_mode[0x2];
1402 u8 wqe_vlan_insert[0x1];
1403 u8 self_lb_en_modifiable[0x1];
1406 u8 max_lso_cap[0x5];
1407 u8 multi_pkt_send_wqe[0x2];
1408 u8 wqe_inline_mode[0x2];
1409 u8 rss_ind_tbl_cap[0x4];
1411 u8 scatter_fcs[0x1];
1412 u8 enhanced_multi_pkt_send_wqe[0x1];
1413 u8 tunnel_lso_const_out_ip_id[0x1];
1414 u8 tunnel_lro_gre[0x1];
1415 u8 tunnel_lro_vxlan[0x1];
1416 u8 tunnel_stateless_gre[0x1];
1417 u8 tunnel_stateless_vxlan[0x1];
1421 u8 reserved_at_23[0x8];
1422 u8 tunnel_stateless_gtp[0x1];
1423 u8 reserved_at_25[0x4];
1424 u8 max_vxlan_udp_ports[0x8];
1425 u8 reserved_at_38[0x6];
1426 u8 max_geneve_opt_len[0x1];
1427 u8 tunnel_stateless_geneve_rx[0x1];
1428 u8 reserved_at_40[0x10];
1429 u8 lro_min_mss_size[0x10];
1430 u8 reserved_at_60[0x120];
1431 u8 lro_timer_supported_periods[4][0x20];
1432 u8 reserved_at_200[0x600];
1436 MLX5_VIRTQ_TYPE_SPLIT = 0,
1437 MLX5_VIRTQ_TYPE_PACKED = 1,
1441 MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0,
1442 MLX5_VIRTQ_EVENT_MODE_QP = 1,
1443 MLX5_VIRTQ_EVENT_MODE_MSIX = 2,
1446 struct mlx5_ifc_virtio_emulation_cap_bits {
1447 u8 desc_tunnel_offload_type[0x1];
1448 u8 eth_frame_offload_type[0x1];
1449 u8 virtio_version_1_0[0x1];
1454 u8 reserved_at_7[0x1][0x9];
1456 u8 virtio_queue_type[0x8];
1457 u8 reserved_at_20[0x13];
1458 u8 log_doorbell_stride[0x5];
1459 u8 reserved_at_3b[0x3];
1460 u8 log_doorbell_bar_size[0x5];
1461 u8 doorbell_bar_offset[0x40];
1462 u8 reserved_at_80[0x8];
1463 u8 max_num_virtio_queues[0x18];
1464 u8 reserved_at_a0[0x60];
1465 u8 umem_1_buffer_param_a[0x20];
1466 u8 umem_1_buffer_param_b[0x20];
1467 u8 umem_2_buffer_param_a[0x20];
1468 u8 umem_2_buffer_param_b[0x20];
1469 u8 umem_3_buffer_param_a[0x20];
1470 u8 umem_3_buffer_param_b[0x20];
1471 u8 reserved_at_1c0[0x620];
1474 struct mlx5_ifc_flow_table_prop_layout_bits {
1477 u8 flow_counter[0x1];
1478 u8 flow_modify_en[0x1];
1479 u8 modify_root[0x1];
1480 u8 identified_miss_table[0x1];
1481 u8 flow_table_modify[0x1];
1484 u8 reset_root_to_default[0x1];
1487 u8 fpga_vendor_acceleration[0x1];
1489 u8 push_vlan_2[0x1];
1490 u8 reformat_and_vlan_action[0x1];
1491 u8 modify_and_vlan_action[0x1];
1493 u8 reformat_l3_tunnel_to_l2[0x1];
1494 u8 reformat_l2_to_l3_tunnel[0x1];
1495 u8 reformat_and_modify_action[0x1];
1496 u8 reserved_at_15[0x9];
1497 u8 sw_owner_v2[0x1];
1498 u8 reserved_at_1f[0x1];
1499 u8 reserved_at_20[0x2];
1500 u8 log_max_ft_size[0x6];
1501 u8 log_max_modify_header_context[0x8];
1502 u8 max_modify_header_actions[0x8];
1503 u8 max_ft_level[0x8];
1504 u8 reserved_at_40[0x8];
1505 u8 log_max_ft_sampler_num[8];
1506 u8 metadata_reg_b_width[0x8];
1507 u8 metadata_reg_a_width[0x8];
1508 u8 reserved_at_60[0x18];
1509 u8 log_max_ft_num[0x8];
1510 u8 reserved_at_80[0x10];
1511 u8 log_max_flow_counter[0x8];
1512 u8 log_max_destination[0x8];
1513 u8 reserved_at_a0[0x18];
1514 u8 log_max_flow[0x8];
1515 u8 reserved_at_c0[0x140];
1518 struct mlx5_ifc_flow_table_nic_cap_bits {
1519 u8 reserved_at_0[0x200];
1520 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties;
1523 union mlx5_ifc_hca_cap_union_bits {
1524 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1525 struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1526 per_protocol_networking_offload_caps;
1527 struct mlx5_ifc_qos_cap_bits qos_cap;
1528 struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
1529 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1530 u8 reserved_at_0[0x8000];
1533 struct mlx5_ifc_set_action_in_bits {
1534 u8 action_type[0x4];
1536 u8 reserved_at_10[0x3];
1538 u8 reserved_at_18[0x3];
1543 struct mlx5_ifc_query_hca_cap_out_bits {
1545 u8 reserved_at_8[0x18];
1547 u8 reserved_at_40[0x40];
1548 union mlx5_ifc_hca_cap_union_bits capability;
1551 struct mlx5_ifc_query_hca_cap_in_bits {
1553 u8 reserved_at_10[0x10];
1554 u8 reserved_at_20[0x10];
1556 u8 reserved_at_40[0x40];
1559 struct mlx5_ifc_mac_address_layout_bits {
1560 u8 reserved_at_0[0x10];
1561 u8 mac_addr_47_32[0x10];
1562 u8 mac_addr_31_0[0x20];
1565 struct mlx5_ifc_nic_vport_context_bits {
1566 u8 reserved_at_0[0x5];
1567 u8 min_wqe_inline_mode[0x3];
1568 u8 reserved_at_8[0x15];
1569 u8 disable_mc_local_lb[0x1];
1570 u8 disable_uc_local_lb[0x1];
1572 u8 arm_change_event[0x1];
1573 u8 reserved_at_21[0x1a];
1574 u8 event_on_mtu[0x1];
1575 u8 event_on_promisc_change[0x1];
1576 u8 event_on_vlan_change[0x1];
1577 u8 event_on_mc_address_change[0x1];
1578 u8 event_on_uc_address_change[0x1];
1579 u8 reserved_at_40[0xc];
1580 u8 affiliation_criteria[0x4];
1581 u8 affiliated_vhca_id[0x10];
1582 u8 reserved_at_60[0xd0];
1584 u8 system_image_guid[0x40];
1587 u8 reserved_at_200[0x140];
1588 u8 qkey_violation_counter[0x10];
1589 u8 reserved_at_350[0x430];
1592 u8 promisc_all[0x1];
1593 u8 reserved_at_783[0x2];
1594 u8 allowed_list_type[0x3];
1595 u8 reserved_at_788[0xc];
1596 u8 allowed_list_size[0xc];
1597 struct mlx5_ifc_mac_address_layout_bits permanent_address;
1598 u8 reserved_at_7e0[0x20];
1601 struct mlx5_ifc_query_nic_vport_context_out_bits {
1603 u8 reserved_at_8[0x18];
1605 u8 reserved_at_40[0x40];
1606 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
1609 struct mlx5_ifc_query_nic_vport_context_in_bits {
1611 u8 reserved_at_10[0x10];
1612 u8 reserved_at_20[0x10];
1614 u8 other_vport[0x1];
1615 u8 reserved_at_41[0xf];
1616 u8 vport_number[0x10];
1617 u8 reserved_at_60[0x5];
1618 u8 allowed_list_type[0x3];
1619 u8 reserved_at_68[0x18];
1622 struct mlx5_ifc_tisc_bits {
1623 u8 strict_lag_tx_port_affinity[0x1];
1624 u8 reserved_at_1[0x3];
1625 u8 lag_tx_port_affinity[0x04];
1626 u8 reserved_at_8[0x4];
1628 u8 reserved_at_10[0x10];
1629 u8 reserved_at_20[0x100];
1630 u8 reserved_at_120[0x8];
1631 u8 transport_domain[0x18];
1632 u8 reserved_at_140[0x8];
1633 u8 underlay_qpn[0x18];
1634 u8 reserved_at_160[0x3a0];
1637 struct mlx5_ifc_query_tis_out_bits {
1639 u8 reserved_at_8[0x18];
1641 u8 reserved_at_40[0x40];
1642 struct mlx5_ifc_tisc_bits tis_context;
1645 struct mlx5_ifc_query_tis_in_bits {
1647 u8 reserved_at_10[0x10];
1648 u8 reserved_at_20[0x10];
1650 u8 reserved_at_40[0x8];
1652 u8 reserved_at_60[0x20];
1655 struct mlx5_ifc_alloc_transport_domain_out_bits {
1657 u8 reserved_at_8[0x18];
1659 u8 reserved_at_40[0x8];
1660 u8 transport_domain[0x18];
1661 u8 reserved_at_60[0x20];
1664 struct mlx5_ifc_alloc_transport_domain_in_bits {
1666 u8 reserved_at_10[0x10];
1667 u8 reserved_at_20[0x10];
1669 u8 reserved_at_40[0x40];
1673 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1674 MLX5_WQ_TYPE_CYCLIC = 0x1,
1675 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1676 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1680 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1681 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1684 struct mlx5_ifc_wq_bits {
1686 u8 wq_signature[0x1];
1687 u8 end_padding_mode[0x2];
1689 u8 reserved_at_8[0x18];
1690 u8 hds_skip_first_sge[0x1];
1691 u8 log2_hds_buf_size[0x3];
1692 u8 reserved_at_24[0x7];
1693 u8 page_offset[0x5];
1695 u8 reserved_at_40[0x8];
1697 u8 reserved_at_60[0x8];
1700 u8 hw_counter[0x20];
1701 u8 sw_counter[0x20];
1702 u8 reserved_at_100[0xc];
1703 u8 log_wq_stride[0x4];
1704 u8 reserved_at_110[0x3];
1705 u8 log_wq_pg_sz[0x5];
1706 u8 reserved_at_118[0x3];
1708 u8 dbr_umem_valid[0x1];
1709 u8 wq_umem_valid[0x1];
1710 u8 reserved_at_122[0x1];
1711 u8 log_hairpin_num_packets[0x5];
1712 u8 reserved_at_128[0x3];
1713 u8 log_hairpin_data_sz[0x5];
1714 u8 reserved_at_130[0x4];
1715 u8 single_wqe_log_num_of_strides[0x4];
1716 u8 two_byte_shift_en[0x1];
1717 u8 reserved_at_139[0x4];
1718 u8 single_stride_log_num_of_bytes[0x3];
1719 u8 dbr_umem_id[0x20];
1720 u8 wq_umem_id[0x20];
1721 u8 wq_umem_offset[0x40];
1722 u8 reserved_at_1c0[0x440];
1726 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1727 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
1731 MLX5_RQC_STATE_RST = 0x0,
1732 MLX5_RQC_STATE_RDY = 0x1,
1733 MLX5_RQC_STATE_ERR = 0x3,
1736 struct mlx5_ifc_rqc_bits {
1738 u8 delay_drop_en[0x1];
1739 u8 scatter_fcs[0x1];
1741 u8 mem_rq_type[0x4];
1743 u8 reserved_at_c[0x1];
1744 u8 flush_in_error_en[0x1];
1746 u8 reserved_at_f[0x11];
1747 u8 reserved_at_20[0x8];
1748 u8 user_index[0x18];
1749 u8 reserved_at_40[0x8];
1751 u8 counter_set_id[0x8];
1752 u8 reserved_at_68[0x18];
1753 u8 reserved_at_80[0x8];
1755 u8 reserved_at_a0[0x8];
1756 u8 hairpin_peer_sq[0x18];
1757 u8 reserved_at_c0[0x10];
1758 u8 hairpin_peer_vhca[0x10];
1759 u8 reserved_at_e0[0xa0];
1760 struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
1763 struct mlx5_ifc_create_rq_out_bits {
1765 u8 reserved_at_8[0x18];
1767 u8 reserved_at_40[0x8];
1769 u8 reserved_at_60[0x20];
1772 struct mlx5_ifc_create_rq_in_bits {
1775 u8 reserved_at_20[0x10];
1777 u8 reserved_at_40[0xc0];
1778 struct mlx5_ifc_rqc_bits ctx;
1781 struct mlx5_ifc_modify_rq_out_bits {
1783 u8 reserved_at_8[0x18];
1785 u8 reserved_at_40[0x40];
1788 struct mlx5_ifc_create_tis_out_bits {
1790 u8 reserved_at_8[0x18];
1792 u8 reserved_at_40[0x8];
1794 u8 reserved_at_60[0x20];
1797 struct mlx5_ifc_create_tis_in_bits {
1800 u8 reserved_at_20[0x10];
1802 u8 reserved_at_40[0xc0];
1803 struct mlx5_ifc_tisc_bits ctx;
1807 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
1808 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
1809 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
1810 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
1813 struct mlx5_ifc_modify_rq_in_bits {
1816 u8 reserved_at_20[0x10];
1819 u8 reserved_at_44[0x4];
1821 u8 reserved_at_60[0x20];
1822 u8 modify_bitmask[0x40];
1823 u8 reserved_at_c0[0x40];
1824 struct mlx5_ifc_rqc_bits ctx;
1828 MLX5_L3_PROT_TYPE_IPV4 = 0,
1829 MLX5_L3_PROT_TYPE_IPV6 = 1,
1833 MLX5_L4_PROT_TYPE_TCP = 0,
1834 MLX5_L4_PROT_TYPE_UDP = 1,
1838 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1839 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1840 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1841 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1842 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1845 struct mlx5_ifc_rx_hash_field_select_bits {
1846 u8 l3_prot_type[0x1];
1847 u8 l4_prot_type[0x1];
1848 u8 selected_fields[0x1e];
1852 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
1853 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
1857 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
1858 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
1862 MLX5_RX_HASH_FN_NONE = 0x0,
1863 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
1864 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
1868 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
1869 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
1873 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 = 0x0,
1874 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2 = 0x1,
1877 struct mlx5_ifc_tirc_bits {
1878 u8 reserved_at_0[0x20];
1880 u8 reserved_at_24[0x1c];
1881 u8 reserved_at_40[0x40];
1882 u8 reserved_at_80[0x4];
1883 u8 lro_timeout_period_usecs[0x10];
1884 u8 lro_enable_mask[0x4];
1885 u8 lro_max_msg_sz[0x8];
1886 u8 reserved_at_a0[0x40];
1887 u8 reserved_at_e0[0x8];
1888 u8 inline_rqn[0x18];
1889 u8 rx_hash_symmetric[0x1];
1890 u8 reserved_at_101[0x1];
1891 u8 tunneled_offload_en[0x1];
1892 u8 reserved_at_103[0x5];
1893 u8 indirect_table[0x18];
1895 u8 reserved_at_124[0x2];
1896 u8 self_lb_block[0x2];
1897 u8 transport_domain[0x18];
1898 u8 rx_hash_toeplitz_key[10][0x20];
1899 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1900 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1901 u8 reserved_at_2c0[0x4c0];
1904 struct mlx5_ifc_create_tir_out_bits {
1906 u8 reserved_at_8[0x18];
1908 u8 reserved_at_40[0x8];
1910 u8 reserved_at_60[0x20];
1913 struct mlx5_ifc_create_tir_in_bits {
1916 u8 reserved_at_20[0x10];
1918 u8 reserved_at_40[0xc0];
1919 struct mlx5_ifc_tirc_bits ctx;
1923 MLX5_INLINE_Q_TYPE_RQ = 0x0,
1924 MLX5_INLINE_Q_TYPE_VIRTQ = 0x1,
1927 struct mlx5_ifc_rq_num_bits {
1928 u8 reserved_at_0[0x8];
1932 struct mlx5_ifc_rqtc_bits {
1933 u8 reserved_at_0[0xa5];
1934 u8 list_q_type[0x3];
1935 u8 reserved_at_a8[0x8];
1936 u8 rqt_max_size[0x10];
1937 u8 reserved_at_c0[0x10];
1938 u8 rqt_actual_size[0x10];
1939 u8 reserved_at_e0[0x6a0];
1940 struct mlx5_ifc_rq_num_bits rq_num[];
1943 struct mlx5_ifc_create_rqt_out_bits {
1945 u8 reserved_at_8[0x18];
1947 u8 reserved_at_40[0x8];
1949 u8 reserved_at_60[0x20];
1953 #pragma GCC diagnostic ignored "-Wpedantic"
1955 struct mlx5_ifc_create_rqt_in_bits {
1958 u8 reserved_at_20[0x10];
1960 u8 reserved_at_40[0xc0];
1961 struct mlx5_ifc_rqtc_bits rqt_context;
1964 struct mlx5_ifc_modify_rqt_in_bits {
1967 u8 reserved_at_20[0x10];
1969 u8 reserved_at_40[0x8];
1971 u8 reserved_at_60[0x20];
1972 u8 modify_bitmask[0x40];
1973 u8 reserved_at_c0[0x40];
1974 struct mlx5_ifc_rqtc_bits rqt_context;
1977 #pragma GCC diagnostic error "-Wpedantic"
1980 struct mlx5_ifc_modify_rqt_out_bits {
1982 u8 reserved_at_8[0x18];
1984 u8 reserved_at_40[0x40];
1988 MLX5_SQC_STATE_RST = 0x0,
1989 MLX5_SQC_STATE_RDY = 0x1,
1990 MLX5_SQC_STATE_ERR = 0x3,
1993 struct mlx5_ifc_sqc_bits {
1997 u8 flush_in_error_en[0x1];
1998 u8 allow_multi_pkt_send_wqe[0x1];
1999 u8 min_wqe_inline_mode[0x3];
2005 u8 static_sq_wq[0x1];
2006 u8 reserved_at_11[0xf];
2007 u8 reserved_at_20[0x8];
2008 u8 user_index[0x18];
2009 u8 reserved_at_40[0x8];
2011 u8 reserved_at_60[0x8];
2012 u8 hairpin_peer_rq[0x18];
2013 u8 reserved_at_80[0x10];
2014 u8 hairpin_peer_vhca[0x10];
2015 u8 reserved_at_a0[0x50];
2016 u8 packet_pacing_rate_limit_index[0x10];
2017 u8 tis_lst_sz[0x10];
2018 u8 reserved_at_110[0x10];
2019 u8 reserved_at_120[0x40];
2020 u8 reserved_at_160[0x8];
2022 struct mlx5_ifc_wq_bits wq;
2025 struct mlx5_ifc_query_sq_in_bits {
2027 u8 reserved_at_10[0x10];
2028 u8 reserved_at_20[0x10];
2030 u8 reserved_at_40[0x8];
2032 u8 reserved_at_60[0x20];
2035 struct mlx5_ifc_modify_sq_out_bits {
2037 u8 reserved_at_8[0x18];
2039 u8 reserved_at_40[0x40];
2042 struct mlx5_ifc_modify_sq_in_bits {
2045 u8 reserved_at_20[0x10];
2048 u8 reserved_at_44[0x4];
2050 u8 reserved_at_60[0x20];
2051 u8 modify_bitmask[0x40];
2052 u8 reserved_at_c0[0x40];
2053 struct mlx5_ifc_sqc_bits ctx;
2056 struct mlx5_ifc_create_sq_out_bits {
2058 u8 reserved_at_8[0x18];
2060 u8 reserved_at_40[0x8];
2062 u8 reserved_at_60[0x20];
2065 struct mlx5_ifc_create_sq_in_bits {
2068 u8 reserved_at_20[0x10];
2070 u8 reserved_at_40[0xc0];
2071 struct mlx5_ifc_sqc_bits ctx;
2075 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
2076 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
2077 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
2078 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
2079 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
2082 struct mlx5_ifc_flow_meter_parameters_bits {
2083 u8 valid[0x1]; // 00h
2084 u8 bucket_overflow[0x1];
2085 u8 start_color[0x2];
2086 u8 both_buckets_on_green[0x1];
2088 u8 reserved_at_1[0x19];
2089 u8 reserved_at_2[0x20]; //04h
2090 u8 reserved_at_3[0x3];
2091 u8 cbs_exponent[0x5]; // 08h
2092 u8 cbs_mantissa[0x8];
2093 u8 reserved_at_4[0x3];
2094 u8 cir_exponent[0x5];
2095 u8 cir_mantissa[0x8];
2096 u8 reserved_at_5[0x20]; // 0Ch
2097 u8 reserved_at_6[0x3];
2098 u8 ebs_exponent[0x5]; // 10h
2099 u8 ebs_mantissa[0x8];
2100 u8 reserved_at_7[0x3];
2101 u8 eir_exponent[0x5];
2102 u8 eir_mantissa[0x8];
2103 u8 reserved_at_8[0x60]; // 14h-1Ch
2107 MLX5_CQE_SIZE_64B = 0x0,
2108 MLX5_CQE_SIZE_128B = 0x1,
2111 struct mlx5_ifc_cqc_bits {
2114 u8 initiator_src_dct[0x1];
2115 u8 dbr_umem_valid[0x1];
2116 u8 reserved_at_7[0x1];
2119 u8 reserved_at_c[0x1];
2120 u8 scqe_break_moderation_en[0x1];
2122 u8 cq_period_mode[0x2];
2123 u8 cqe_comp_en[0x1];
2124 u8 mini_cqe_res_format[0x2];
2126 u8 reserved_at_18[0x8];
2127 u8 dbr_umem_id[0x20];
2128 u8 reserved_at_40[0x14];
2129 u8 page_offset[0x6];
2130 u8 reserved_at_5a[0x6];
2131 u8 reserved_at_60[0x3];
2132 u8 log_cq_size[0x5];
2134 u8 reserved_at_80[0x4];
2136 u8 cq_max_count[0x10];
2137 u8 reserved_at_a0[0x18];
2139 u8 reserved_at_c0[0x3];
2140 u8 log_page_size[0x5];
2141 u8 reserved_at_c8[0x18];
2142 u8 reserved_at_e0[0x20];
2143 u8 reserved_at_100[0x8];
2144 u8 last_notified_index[0x18];
2145 u8 reserved_at_120[0x8];
2146 u8 last_solicit_index[0x18];
2147 u8 reserved_at_140[0x8];
2148 u8 consumer_counter[0x18];
2149 u8 reserved_at_160[0x8];
2150 u8 producer_counter[0x18];
2151 u8 local_partition_id[0xc];
2152 u8 process_id[0x14];
2153 u8 reserved_at_1A0[0x20];
2157 struct mlx5_ifc_create_cq_out_bits {
2159 u8 reserved_at_8[0x18];
2161 u8 reserved_at_40[0x8];
2163 u8 reserved_at_60[0x20];
2166 struct mlx5_ifc_create_cq_in_bits {
2169 u8 reserved_at_20[0x10];
2171 u8 reserved_at_40[0x40];
2172 struct mlx5_ifc_cqc_bits cq_context;
2173 u8 cq_umem_offset[0x40];
2174 u8 cq_umem_id[0x20];
2175 u8 cq_umem_valid[0x1];
2176 u8 reserved_at_2e1[0x1f];
2177 u8 reserved_at_300[0x580];
2182 MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
2183 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
2184 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,
2187 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
2189 u8 reserved_at_10[0x20];
2192 u8 reserved_at_60[0x20];
2195 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
2197 u8 reserved_at_8[0x18];
2200 u8 reserved_at_60[0x20];
2203 struct mlx5_ifc_virtio_q_counters_bits {
2204 u8 modify_field_select[0x40];
2205 u8 reserved_at_40[0x40];
2206 u8 received_desc[0x40];
2207 u8 completed_desc[0x40];
2208 u8 error_cqes[0x20];
2209 u8 bad_desc_errors[0x20];
2210 u8 exceed_max_chain[0x20];
2211 u8 invalid_buffer[0x20];
2212 u8 reserved_at_180[0x50];
2215 struct mlx5_ifc_create_virtio_q_counters_in_bits {
2216 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2217 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2220 struct mlx5_ifc_query_virtio_q_counters_out_bits {
2221 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2222 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2225 MLX5_VIRTQ_STATE_INIT = 0,
2226 MLX5_VIRTQ_STATE_RDY = 1,
2227 MLX5_VIRTQ_STATE_SUSPEND = 2,
2228 MLX5_VIRTQ_STATE_ERROR = 3,
2232 MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),
2233 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),
2234 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),
2237 struct mlx5_ifc_virtio_q_bits {
2238 u8 virtio_q_type[0x8];
2239 u8 reserved_at_8[0x5];
2241 u8 queue_index[0x10];
2242 u8 full_emulation[0x1];
2243 u8 virtio_version_1_0[0x1];
2244 u8 reserved_at_22[0x2];
2245 u8 offload_type[0x4];
2246 u8 event_qpn_or_msix[0x18];
2247 u8 doorbell_stride_idx[0x10];
2248 u8 queue_size[0x10];
2249 u8 device_emulation_id[0x20];
2252 u8 available_addr[0x40];
2253 u8 virtio_q_mkey[0x20];
2254 u8 reserved_at_160[0x20];
2256 u8 umem_1_size[0x20];
2257 u8 umem_1_offset[0x40];
2259 u8 umem_2_size[0x20];
2260 u8 umem_2_offset[0x40];
2262 u8 umem_3_size[0x20];
2263 u8 umem_3_offset[0x40];
2264 u8 counter_set_id[0x20];
2265 u8 reserved_at_320[0x8];
2267 u8 reserved_at_340[0xc0];
2270 struct mlx5_ifc_virtio_net_q_bits {
2271 u8 modify_field_select[0x40];
2272 u8 reserved_at_40[0x40];
2277 u8 reserved_at_84[0x6];
2278 u8 dirty_bitmap_dump_enable[0x1];
2279 u8 vhost_log_page[0x5];
2280 u8 reserved_at_90[0xc];
2283 u8 tisn_or_qpn[0x18];
2284 u8 dirty_bitmap_mkey[0x20];
2285 u8 dirty_bitmap_size[0x20];
2286 u8 dirty_bitmap_addr[0x40];
2287 u8 hw_available_index[0x10];
2288 u8 hw_used_index[0x10];
2289 u8 reserved_at_160[0xa0];
2290 struct mlx5_ifc_virtio_q_bits virtio_q_context;
2293 struct mlx5_ifc_create_virtq_in_bits {
2294 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2295 struct mlx5_ifc_virtio_net_q_bits virtq;
2298 struct mlx5_ifc_query_virtq_out_bits {
2299 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2300 struct mlx5_ifc_virtio_net_q_bits virtq;
2304 MLX5_QP_ST_RC = 0x0,
2308 MLX5_QP_PM_MIGRATED = 0x3,
2312 MLX5_NON_ZERO_RQ = 0x0,
2315 MLX5_ZERO_LEN_RQ = 0x3,
2318 struct mlx5_ifc_ads_bits {
2321 u8 reserved_at_2[0xe];
2322 u8 pkey_index[0x10];
2323 u8 reserved_at_20[0x8];
2327 u8 ack_timeout[0x5];
2328 u8 reserved_at_45[0x3];
2329 u8 src_addr_index[0x8];
2330 u8 reserved_at_50[0x4];
2333 u8 reserved_at_60[0x4];
2335 u8 flow_label[0x14];
2336 u8 rgid_rip[16][0x8];
2337 u8 reserved_at_100[0x4];
2340 u8 reserved_at_106[0x1];
2348 u8 vhca_port_num[0x8];
2349 u8 rmac_47_32[0x10];
2353 struct mlx5_ifc_qpc_bits {
2355 u8 lag_tx_port_affinity[0x4];
2357 u8 reserved_at_10[0x3];
2359 u8 reserved_at_15[0x1];
2360 u8 req_e2e_credit_mode[0x2];
2361 u8 offload_type[0x4];
2362 u8 end_padding_mode[0x2];
2363 u8 reserved_at_1e[0x2];
2364 u8 wq_signature[0x1];
2365 u8 block_lb_mc[0x1];
2366 u8 atomic_like_write_en[0x1];
2367 u8 latency_sensitive[0x1];
2368 u8 reserved_at_24[0x1];
2369 u8 drain_sigerr[0x1];
2370 u8 reserved_at_26[0x2];
2373 u8 log_msg_max[0x5];
2374 u8 reserved_at_48[0x1];
2375 u8 log_rq_size[0x4];
2376 u8 log_rq_stride[0x3];
2378 u8 log_sq_size[0x4];
2379 u8 reserved_at_55[0x6];
2381 u8 ulp_stateless_offload_mode[0x4];
2382 u8 counter_set_id[0x8];
2384 u8 reserved_at_80[0x8];
2385 u8 user_index[0x18];
2386 u8 reserved_at_a0[0x3];
2387 u8 log_page_size[0x5];
2388 u8 remote_qpn[0x18];
2389 struct mlx5_ifc_ads_bits primary_address_path;
2390 struct mlx5_ifc_ads_bits secondary_address_path;
2391 u8 log_ack_req_freq[0x4];
2392 u8 reserved_at_384[0x4];
2393 u8 log_sra_max[0x3];
2394 u8 reserved_at_38b[0x2];
2395 u8 retry_count[0x3];
2397 u8 reserved_at_393[0x1];
2399 u8 cur_rnr_retry[0x3];
2400 u8 cur_retry_count[0x3];
2401 u8 reserved_at_39b[0x5];
2402 u8 reserved_at_3a0[0x20];
2403 u8 reserved_at_3c0[0x8];
2404 u8 next_send_psn[0x18];
2405 u8 reserved_at_3e0[0x8];
2407 u8 reserved_at_400[0x8];
2409 u8 reserved_at_420[0x20];
2410 u8 reserved_at_440[0x8];
2411 u8 last_acked_psn[0x18];
2412 u8 reserved_at_460[0x8];
2414 u8 reserved_at_480[0x8];
2415 u8 log_rra_max[0x3];
2416 u8 reserved_at_48b[0x1];
2417 u8 atomic_mode[0x4];
2421 u8 reserved_at_493[0x1];
2422 u8 page_offset[0x6];
2423 u8 reserved_at_49a[0x3];
2424 u8 cd_slave_receive[0x1];
2425 u8 cd_slave_send[0x1];
2427 u8 reserved_at_4a0[0x3];
2428 u8 min_rnr_nak[0x5];
2429 u8 next_rcv_psn[0x18];
2430 u8 reserved_at_4c0[0x8];
2432 u8 reserved_at_4e0[0x8];
2436 u8 reserved_at_560[0x5];
2438 u8 srqn_rmpn_xrqn[0x18];
2439 u8 reserved_at_580[0x8];
2441 u8 hw_sq_wqebb_counter[0x10];
2442 u8 sw_sq_wqebb_counter[0x10];
2443 u8 hw_rq_counter[0x20];
2444 u8 sw_rq_counter[0x20];
2445 u8 reserved_at_600[0x20];
2446 u8 reserved_at_620[0xf];
2450 u8 dc_access_key[0x40];
2451 u8 reserved_at_680[0x3];
2452 u8 dbr_umem_valid[0x1];
2453 u8 reserved_at_684[0x9c];
2454 u8 dbr_umem_id[0x20];
2457 struct mlx5_ifc_create_qp_out_bits {
2459 u8 reserved_at_8[0x18];
2461 u8 reserved_at_40[0x8];
2463 u8 reserved_at_60[0x20];
2467 #pragma GCC diagnostic ignored "-Wpedantic"
2469 struct mlx5_ifc_create_qp_in_bits {
2472 u8 reserved_at_20[0x10];
2474 u8 reserved_at_40[0x40];
2475 u8 opt_param_mask[0x20];
2476 u8 reserved_at_a0[0x20];
2477 struct mlx5_ifc_qpc_bits qpc;
2478 u8 wq_umem_offset[0x40];
2479 u8 wq_umem_id[0x20];
2480 u8 wq_umem_valid[0x1];
2481 u8 reserved_at_861[0x1f];
2485 #pragma GCC diagnostic error "-Wpedantic"
2488 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2490 u8 reserved_at_8[0x18];
2492 u8 reserved_at_40[0x40];
2495 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2498 u8 reserved_at_20[0x10];
2500 u8 reserved_at_40[0x8];
2502 u8 reserved_at_60[0x20];
2503 u8 opt_param_mask[0x20];
2504 u8 reserved_at_a0[0x20];
2505 struct mlx5_ifc_qpc_bits qpc;
2506 u8 reserved_at_800[0x80];
2509 struct mlx5_ifc_sqd2rts_qp_out_bits {
2511 u8 reserved_at_8[0x18];
2513 u8 reserved_at_40[0x40];
2516 struct mlx5_ifc_sqd2rts_qp_in_bits {
2519 u8 reserved_at_20[0x10];
2521 u8 reserved_at_40[0x8];
2523 u8 reserved_at_60[0x20];
2524 u8 opt_param_mask[0x20];
2525 u8 reserved_at_a0[0x20];
2526 struct mlx5_ifc_qpc_bits qpc;
2527 u8 reserved_at_800[0x80];
2530 struct mlx5_ifc_rts2rts_qp_out_bits {
2532 u8 reserved_at_8[0x18];
2534 u8 reserved_at_40[0x40];
2537 struct mlx5_ifc_rts2rts_qp_in_bits {
2540 u8 reserved_at_20[0x10];
2542 u8 reserved_at_40[0x8];
2544 u8 reserved_at_60[0x20];
2545 u8 opt_param_mask[0x20];
2546 u8 reserved_at_a0[0x20];
2547 struct mlx5_ifc_qpc_bits qpc;
2548 u8 reserved_at_800[0x80];
2551 struct mlx5_ifc_rtr2rts_qp_out_bits {
2553 u8 reserved_at_8[0x18];
2555 u8 reserved_at_40[0x40];
2558 struct mlx5_ifc_rtr2rts_qp_in_bits {
2561 u8 reserved_at_20[0x10];
2563 u8 reserved_at_40[0x8];
2565 u8 reserved_at_60[0x20];
2566 u8 opt_param_mask[0x20];
2567 u8 reserved_at_a0[0x20];
2568 struct mlx5_ifc_qpc_bits qpc;
2569 u8 reserved_at_800[0x80];
2572 struct mlx5_ifc_rst2init_qp_out_bits {
2574 u8 reserved_at_8[0x18];
2576 u8 reserved_at_40[0x40];
2579 struct mlx5_ifc_rst2init_qp_in_bits {
2582 u8 reserved_at_20[0x10];
2584 u8 reserved_at_40[0x8];
2586 u8 reserved_at_60[0x20];
2587 u8 opt_param_mask[0x20];
2588 u8 reserved_at_a0[0x20];
2589 struct mlx5_ifc_qpc_bits qpc;
2590 u8 reserved_at_800[0x80];
2593 struct mlx5_ifc_init2rtr_qp_out_bits {
2595 u8 reserved_at_8[0x18];
2597 u8 reserved_at_40[0x40];
2600 struct mlx5_ifc_init2rtr_qp_in_bits {
2603 u8 reserved_at_20[0x10];
2605 u8 reserved_at_40[0x8];
2607 u8 reserved_at_60[0x20];
2608 u8 opt_param_mask[0x20];
2609 u8 reserved_at_a0[0x20];
2610 struct mlx5_ifc_qpc_bits qpc;
2611 u8 reserved_at_800[0x80];
2614 struct mlx5_ifc_init2init_qp_out_bits {
2616 u8 reserved_at_8[0x18];
2618 u8 reserved_at_40[0x40];
2621 struct mlx5_ifc_init2init_qp_in_bits {
2624 u8 reserved_at_20[0x10];
2626 u8 reserved_at_40[0x8];
2628 u8 reserved_at_60[0x20];
2629 u8 opt_param_mask[0x20];
2630 u8 reserved_at_a0[0x20];
2631 struct mlx5_ifc_qpc_bits qpc;
2632 u8 reserved_at_800[0x80];
2636 #pragma GCC diagnostic ignored "-Wpedantic"
2638 struct mlx5_ifc_query_qp_out_bits {
2640 u8 reserved_at_8[0x18];
2642 u8 reserved_at_40[0x40];
2643 u8 opt_param_mask[0x20];
2644 u8 reserved_at_a0[0x20];
2645 struct mlx5_ifc_qpc_bits qpc;
2646 u8 reserved_at_800[0x80];
2650 #pragma GCC diagnostic error "-Wpedantic"
2653 struct mlx5_ifc_query_qp_in_bits {
2655 u8 reserved_at_10[0x10];
2656 u8 reserved_at_20[0x10];
2658 u8 reserved_at_40[0x8];
2660 u8 reserved_at_60[0x20];
2664 MLX5_DATA_RATE = 0x0,
2665 MLX5_WQE_RATE = 0x1,
2668 struct mlx5_ifc_set_pp_rate_limit_context_bits {
2669 u8 rate_limit[0x20];
2670 u8 burst_upper_bound[0x20];
2671 u8 reserved_at_40[0xC];
2673 u8 typical_packet_size[0x10];
2674 u8 reserved_at_60[0x120];
2677 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u
2680 #pragma GCC diagnostic ignored "-Wpedantic"
2682 struct mlx5_ifc_access_register_out_bits {
2684 u8 reserved_at_8[0x18];
2686 u8 reserved_at_40[0x40];
2687 u8 register_data[0][0x20];
2690 struct mlx5_ifc_access_register_in_bits {
2692 u8 reserved_at_10[0x10];
2693 u8 reserved_at_20[0x10];
2695 u8 reserved_at_40[0x10];
2696 u8 register_id[0x10];
2698 u8 register_data[0][0x20];
2701 #pragma GCC diagnostic error "-Wpedantic"
2705 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
2706 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
2710 MLX5_REGISTER_ID_MTUTC = 0x9055,
2713 struct mlx5_ifc_register_mtutc_bits {
2714 u8 time_stamp_mode[0x2];
2715 u8 time_stamp_state[0x2];
2716 u8 reserved_at_4[0x18];
2718 u8 freq_adjustment[0x20];
2719 u8 reserved_at_40[0x40];
2722 u8 time_adjustment[0x20];
2725 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0
2726 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1
2728 struct mlx5_ifc_parse_graph_arc_bits {
2729 u8 start_inner_tunnel[0x1];
2730 u8 reserved_at_1[0x7];
2731 u8 arc_parse_graph_node[0x8];
2732 u8 compare_condition_value[0x10];
2733 u8 parse_graph_node_handle[0x20];
2734 u8 reserved_at_40[0x40];
2737 struct mlx5_ifc_parse_graph_flow_match_sample_bits {
2738 u8 flow_match_sample_en[0x1];
2739 u8 reserved_at_1[0x3];
2740 u8 flow_match_sample_offset_mode[0x4];
2741 u8 reserved_at_5[0x8];
2742 u8 flow_match_sample_field_offset[0x10];
2743 u8 reserved_at_32[0x4];
2744 u8 flow_match_sample_field_offset_shift[0x4];
2745 u8 flow_match_sample_field_base_offset[0x8];
2746 u8 reserved_at_48[0xd];
2747 u8 flow_match_sample_tunnel_mode[0x3];
2748 u8 flow_match_sample_field_offset_mask[0x20];
2749 u8 flow_match_sample_field_id[0x20];
2752 struct mlx5_ifc_parse_graph_flex_bits {
2753 u8 modify_field_select[0x40];
2754 u8 reserved_at_64[0x20];
2755 u8 header_length_base_value[0x10];
2756 u8 reserved_at_112[0x4];
2757 u8 header_length_field_shift[0x4];
2758 u8 reserved_at_120[0x4];
2759 u8 header_length_mode[0x4];
2760 u8 header_length_field_offset[0x10];
2761 u8 next_header_field_offset[0x10];
2762 u8 reserved_at_160[0x1b];
2763 u8 next_header_field_size[0x5];
2764 u8 header_length_field_mask[0x20];
2765 u8 reserved_at_224[0x20];
2766 struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8];
2767 struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8];
2768 struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8];
2771 struct mlx5_ifc_create_flex_parser_in_bits {
2772 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2773 struct mlx5_ifc_parse_graph_flex_bits flex;
2776 struct mlx5_ifc_create_flex_parser_out_bits {
2777 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2778 struct mlx5_ifc_parse_graph_flex_bits flex;
2781 struct mlx5_ifc_parse_graph_flex_out_bits {
2783 u8 reserved_at_8[0x18];
2785 u8 reserved_at_40[0x40];
2786 struct mlx5_ifc_parse_graph_flex_bits capability;
2789 struct regexp_params_field_select_bits {
2790 u8 reserved_at_0[0x1e];
2791 u8 stop_engine[0x1];
2795 struct mlx5_ifc_regexp_params_bits {
2796 u8 reserved_at_0[0x1f];
2797 u8 stop_engine[0x1];
2798 u8 db_umem_id[0x20];
2799 u8 db_umem_offset[0x40];
2800 u8 reserved_at_80[0x100];
2803 struct mlx5_ifc_set_regexp_params_in_bits {
2806 u8 reserved_at_20[0x10];
2808 u8 reserved_at_40[0x18];
2810 struct regexp_params_field_select_bits field_select;
2811 struct mlx5_ifc_regexp_params_bits regexp_params;
2814 struct mlx5_ifc_set_regexp_params_out_bits {
2816 u8 reserved_at_8[0x18];
2818 u8 reserved_at_18[0x40];
2821 struct mlx5_ifc_query_regexp_params_in_bits {
2824 u8 reserved_at_20[0x10];
2826 u8 reserved_at_40[0x18];
2831 struct mlx5_ifc_query_regexp_params_out_bits {
2833 u8 reserved_at_8[0x18];
2836 struct mlx5_ifc_regexp_params_bits regexp_params;
2839 struct mlx5_ifc_set_regexp_register_in_bits {
2842 u8 reserved_at_20[0x10];
2844 u8 reserved_at_40[0x18];
2846 u8 register_address[0x20];
2847 u8 register_data[0x20];
2851 struct mlx5_ifc_set_regexp_register_out_bits {
2853 u8 reserved_at_8[0x18];
2858 struct mlx5_ifc_query_regexp_register_in_bits {
2861 u8 reserved_at_20[0x10];
2863 u8 reserved_at_40[0x18];
2865 u8 register_address[0x20];
2868 struct mlx5_ifc_query_regexp_register_out_bits {
2870 u8 reserved_at_8[0x18];
2873 u8 register_data[0x20];
2876 /* CQE format mask. */
2877 #define MLX5E_CQE_FORMAT_MASK 0xc
2880 #define MLX5_OPC_MOD_MPW 0x01
2882 /* Compressed Rx CQE structure. */
2883 struct mlx5_mini_cqe8 {
2885 uint32_t rx_hash_result;
2888 uint16_t stride_idx;
2891 uint16_t wqe_counter;
2892 uint8_t s_wqe_opcode;
2899 /* Mini CQE responder format. */
2901 MLX5_CQE_RESP_FORMAT_HASH = 0x0,
2902 MLX5_CQE_RESP_FORMAT_CSUM = 0x1,
2903 MLX5_CQE_RESP_FORMAT_CSUM_FLOW_TAG = 0x2,
2904 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3,
2907 /* srTCM PRM flow meter parameters. */
2909 MLX5_FLOW_COLOR_RED = 0,
2910 MLX5_FLOW_COLOR_YELLOW,
2911 MLX5_FLOW_COLOR_GREEN,
2912 MLX5_FLOW_COLOR_UNDEFINED,
2915 /* Maximum value of srTCM metering parameters. */
2916 #define MLX5_SRTCM_CBS_MAX (0xFF * (1ULL << 0x1F))
2917 #define MLX5_SRTCM_CIR_MAX (8 * (1ULL << 30) * 0xFF)
2918 #define MLX5_SRTCM_EBS_MAX 0
2920 /* The bits meter color use. */
2921 #define MLX5_MTR_COLOR_BITS 8
2923 /* Length mode of dynamic flex parser graph node. */
2924 enum mlx5_parse_graph_node_len_mode {
2925 MLX5_GRAPH_NODE_LEN_FIXED = 0x0,
2926 MLX5_GRAPH_NODE_LEN_FIELD = 0x1,
2927 MLX5_GRAPH_NODE_LEN_BITMASK = 0x2,
2930 /* Offset mode of the samples of flex parser. */
2931 enum mlx5_parse_graph_flow_match_sample_offset_mode {
2932 MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0,
2933 MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1,
2934 MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2,
2937 /* Node index for an input / output arc of the flex parser graph. */
2938 enum mlx5_parse_graph_arc_node_index {
2939 MLX5_GRAPH_ARC_NODE_NULL = 0x0,
2940 MLX5_GRAPH_ARC_NODE_HEAD = 0x1,
2941 MLX5_GRAPH_ARC_NODE_MAC = 0x2,
2942 MLX5_GRAPH_ARC_NODE_IP = 0x3,
2943 MLX5_GRAPH_ARC_NODE_GRE = 0x4,
2944 MLX5_GRAPH_ARC_NODE_UDP = 0x5,
2945 MLX5_GRAPH_ARC_NODE_MPLS = 0x6,
2946 MLX5_GRAPH_ARC_NODE_TCP = 0x7,
2947 MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8,
2948 MLX5_GRAPH_ARC_NODE_GENEVE = 0x9,
2949 MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa,
2950 MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f,
2954 * Convert a user mark to flow mark.
2957 * Mark value to convert.
2960 * Converted mark value.
2962 static inline uint32_t
2963 mlx5_flow_mark_set(uint32_t val)
2968 * Add one to the user value to differentiate un-marked flows from
2969 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
2970 * remains untouched.
2972 if (val != MLX5_FLOW_MARK_DEFAULT)
2974 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
2976 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
2977 * word, byte-swapped by the kernel on little-endian systems. In this
2978 * case, left-shifting the resulting big-endian value ensures the
2979 * least significant 24 bits are retained when converting it back.
2981 ret = rte_cpu_to_be_32(val) >> 8;
2989 * Convert a mark to user mark.
2992 * Mark value to convert.
2995 * Converted mark value.
2997 static inline uint32_t
2998 mlx5_flow_mark_get(uint32_t val)
3001 * Subtract one from the retrieved value. It was added by
3002 * mlx5_flow_mark_set() to distinguish unmarked flows.
3004 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
3005 return (val >> 8) - 1;
3011 #endif /* RTE_PMD_MLX5_PRM_H_ */