1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2016 6WIND S.A.
3 * Copyright 2016 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_PRM_H_
7 #define RTE_PMD_MLX5_PRM_H_
10 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
12 #pragma GCC diagnostic ignored "-Wpedantic"
14 #include <infiniband/mlx5dv.h>
16 #pragma GCC diagnostic error "-Wpedantic"
22 #include <rte_byteorder.h>
24 #include "mlx5_autoconf.h"
26 /* RSS hash key size. */
27 #define MLX5_RSS_HASH_KEY_LEN 40
29 /* Get CQE owner bit. */
30 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
33 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
36 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
38 /* Get CQE solicited event. */
39 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
41 /* Invalidate a CQE. */
42 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
44 /* WQE Segment sizes in bytes. */
45 #define MLX5_WSEG_SIZE 16u
46 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
47 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
48 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
50 /* WQE/WQEBB size in bytes. */
51 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
54 * Max size of a WQE session.
55 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
56 * the WQE size field in Control Segment is 6 bits wide.
58 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
61 * Default minimum number of Tx queues for inlining packets.
62 * If there are less queues as specified we assume we have
63 * no enough CPU resources (cycles) to perform inlining,
64 * the PCIe throughput is not supposed as bottleneck and
65 * inlining is disabled.
67 #define MLX5_INLINE_MAX_TXQS 8u
68 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
71 * Default packet length threshold to be inlined with
72 * enhanced MPW. If packet length exceeds the threshold
73 * the data are not inlined. Should be aligned in WQEBB
74 * boundary with accounting the title Control and Ethernet
77 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
78 MLX5_DSEG_MIN_INLINE_SIZE)
80 * Maximal inline data length sent with enhanced MPW.
81 * Is based on maximal WQE size.
83 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
84 MLX5_WQE_CSEG_SIZE - \
85 MLX5_WQE_ESEG_SIZE - \
86 MLX5_WQE_DSEG_SIZE + \
87 MLX5_DSEG_MIN_INLINE_SIZE)
89 * Minimal amount of packets to be sent with EMPW.
90 * This limits the minimal required size of sent EMPW.
91 * If there are no enough resources to built minimal
92 * EMPW the sending loop exits.
94 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
96 * Maximal amount of packets to be sent with EMPW.
97 * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
98 * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
99 * without CQE generation request, being multiplied by
100 * MLX5_TX_COMP_MAX_CQE it may cause significant latency
101 * in tx burst routine at the moment of freeing multiple mbufs.
103 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
104 #define MLX5_MPW_MAX_PACKETS 6
105 #define MLX5_MPW_INLINE_MAX_PACKETS 6
108 * Default packet length threshold to be inlined with
109 * ordinary SEND. Inlining saves the MR key search
110 * and extra PCIe data fetch transaction, but eats the
113 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
114 MLX5_ESEG_MIN_INLINE_SIZE - \
115 MLX5_WQE_CSEG_SIZE - \
116 MLX5_WQE_ESEG_SIZE - \
119 * Maximal inline data length sent with ordinary SEND.
120 * Is based on maximal WQE size.
122 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
123 MLX5_WQE_CSEG_SIZE - \
124 MLX5_WQE_ESEG_SIZE - \
125 MLX5_WQE_DSEG_SIZE + \
126 MLX5_ESEG_MIN_INLINE_SIZE)
128 /* Missed in mlv5dv.h, should define here. */
129 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
131 /* CQE value to inform that VLAN is stripped. */
132 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
135 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
138 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
141 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
144 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
147 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
149 /* IP is fragmented. */
150 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
152 /* L2 header is valid. */
153 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
155 /* L3 header is valid. */
156 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
158 /* L4 header is valid. */
159 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
161 /* Outer packet, 0 IPv4, 1 IPv6. */
162 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
164 /* Tunnel packet bit in the CQE. */
165 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
167 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
168 #define MLX5_CQE_LRO_PUSH_MASK 0x40
170 /* Mask for L4 type in the CQE hdr_type_etc field. */
171 #define MLX5_CQE_L4_TYPE_MASK 0x70
173 /* The bit index of L4 type in CQE hdr_type_etc field. */
174 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
176 /* L4 type to indicate TCP packet without acknowledgment. */
177 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
179 /* L4 type to indicate TCP packet with acknowledgment. */
180 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
182 /* Inner L3 checksum offload (Tunneled packets only). */
183 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
185 /* Inner L4 checksum offload (Tunneled packets only). */
186 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
188 /* Outer L4 type is TCP. */
189 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5)
191 /* Outer L4 type is UDP. */
192 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5)
194 /* Outer L3 type is IPV4. */
195 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
197 /* Outer L3 type is IPV6. */
198 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
200 /* Inner L4 type is TCP. */
201 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
203 /* Inner L4 type is UDP. */
204 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
206 /* Inner L3 type is IPV4. */
207 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
209 /* Inner L3 type is IPV6. */
210 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
212 /* VLAN insertion flag. */
213 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
215 /* Data inline segment flag. */
216 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
218 /* Is flow mark valid. */
219 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
220 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
222 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
225 /* INVALID is used by packets matching no flow rules. */
226 #define MLX5_FLOW_MARK_INVALID 0
228 /* Maximum allowed value to mark a packet. */
229 #define MLX5_FLOW_MARK_MAX 0xfffff0
231 /* Default mark value used when none is provided. */
232 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
234 /* Default mark mask for metadata legacy mode. */
235 #define MLX5_FLOW_MARK_MASK 0xffffff
237 /* Maximum number of DS in WQE. Limited by 6-bit field. */
238 #define MLX5_DSEG_MAX 63
240 /* The completion mode offset in the WQE control segment line 2. */
241 #define MLX5_COMP_MODE_OFFSET 2
243 /* Amount of data bytes in minimal inline data segment. */
244 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
246 /* Amount of data bytes in minimal inline eth segment. */
247 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
249 /* Amount of data bytes after eth data segment. */
250 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
252 /* The maximum log value of segments per RQ WQE. */
253 #define MLX5_MAX_LOG_RQ_SEGS 5u
255 /* The alignment needed for WQ buffer. */
256 #define MLX5_WQE_BUF_ALIGNMENT sysconf(_SC_PAGESIZE)
258 /* Completion mode. */
259 enum mlx5_completion_mode {
260 MLX5_COMP_ONLY_ERR = 0x0,
261 MLX5_COMP_ONLY_FIRST_ERR = 0x1,
262 MLX5_COMP_ALWAYS = 0x2,
263 MLX5_COMP_CQE_AND_EQE = 0x3,
270 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
273 /* WQE Control segment. */
274 struct mlx5_wqe_cseg {
279 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
281 /* Header of data segment. Minimal size Data Segment */
282 struct mlx5_wqe_dseg {
285 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
293 /* Subset of struct WQE Ethernet Segment. */
294 struct mlx5_wqe_eseg {
302 uint16_t inline_hdr_sz;
304 uint16_t inline_data;
311 uint32_t flow_metadata;
317 /* The title WQEBB, header of WQE. */
320 struct mlx5_wqe_cseg cseg;
323 struct mlx5_wqe_eseg eseg;
325 struct mlx5_wqe_dseg dseg[2];
326 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
330 /* WQE for Multi-Packet RQ. */
331 struct mlx5_wqe_mprq {
332 struct mlx5_wqe_srq_next_seg next_seg;
333 struct mlx5_wqe_data_seg dseg;
336 #define MLX5_MPRQ_LEN_MASK 0x000ffff
337 #define MLX5_MPRQ_LEN_SHIFT 0
338 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
339 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
340 #define MLX5_MPRQ_FILLER_MASK 0x80000000
341 #define MLX5_MPRQ_FILLER_SHIFT 31
343 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
345 /* CQ element structure - should be equal to the cache line size */
347 #if (RTE_CACHE_LINE_SIZE == 128)
353 uint8_t lro_tcppsh_abort_dupack;
355 uint16_t lro_tcp_win;
356 uint32_t lro_ack_seq_num;
357 uint32_t rx_hash_res;
358 uint8_t rx_hash_type;
362 uint16_t hdr_type_etc;
366 uint32_t flow_table_metadata;
370 uint32_t sop_drop_qpn;
371 uint16_t wqe_counter;
376 /* MMO metadata segment */
378 #define MLX5_OPCODE_MMO 0x2f
379 #define MLX5_OPC_MOD_MMO_REGEX 0x4
381 struct mlx5_wqe_metadata_seg {
382 uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */
387 struct mlx5_ifc_regexp_mmo_control_bits {
388 uint8_t reserved_at_31[0x2];
390 uint8_t reserved_at_28[0x1];
391 uint8_t subset_id_0[0xc];
392 uint8_t reserved_at_16[0x4];
393 uint8_t subset_id_1[0xc];
395 uint8_t subset_id_2[0xc];
396 uint8_t reserved_at_16_1[0x4];
397 uint8_t subset_id_3[0xc];
400 struct mlx5_ifc_regexp_metadata_bits {
401 uint8_t rof_version[0x10];
402 uint8_t latency_count[0x10];
403 uint8_t instruction_count[0x10];
404 uint8_t primary_thread_count[0x10];
405 uint8_t match_count[0x8];
406 uint8_t detected_match_count[0x8];
407 uint8_t status[0x10];
408 uint8_t job_id[0x20];
409 uint8_t reserved[0x80];
412 struct mlx5_ifc_regexp_match_tuple_bits {
413 uint8_t length[0x10];
414 uint8_t start_ptr[0x10];
415 uint8_t rule_id[0x20];
418 /* Adding direct verbs to data-path. */
420 /* CQ sequence number mask. */
421 #define MLX5_CQ_SQN_MASK 0x3
423 /* CQ sequence number index. */
424 #define MLX5_CQ_SQN_OFFSET 28
426 /* CQ doorbell index mask. */
427 #define MLX5_CI_MASK 0xffffff
429 /* CQ doorbell offset. */
430 #define MLX5_CQ_ARM_DB 1
432 /* CQ doorbell offset*/
433 #define MLX5_CQ_DOORBELL 0x20
435 /* CQE format value. */
436 #define MLX5_COMPRESSED 0x3
438 /* CQ doorbell cmd types. */
439 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24)
440 #define MLX5_CQ_DBR_CMD_ALL (0 << 24)
442 /* Action type of header modification. */
444 MLX5_MODIFICATION_TYPE_SET = 0x1,
445 MLX5_MODIFICATION_TYPE_ADD = 0x2,
446 MLX5_MODIFICATION_TYPE_COPY = 0x3,
449 /* The field of packet to be modified. */
450 enum mlx5_modification_field {
451 MLX5_MODI_OUT_NONE = -1,
452 MLX5_MODI_OUT_SMAC_47_16 = 1,
453 MLX5_MODI_OUT_SMAC_15_0,
454 MLX5_MODI_OUT_ETHERTYPE,
455 MLX5_MODI_OUT_DMAC_47_16,
456 MLX5_MODI_OUT_DMAC_15_0,
457 MLX5_MODI_OUT_IP_DSCP,
458 MLX5_MODI_OUT_TCP_FLAGS,
459 MLX5_MODI_OUT_TCP_SPORT,
460 MLX5_MODI_OUT_TCP_DPORT,
461 MLX5_MODI_OUT_IPV4_TTL,
462 MLX5_MODI_OUT_UDP_SPORT,
463 MLX5_MODI_OUT_UDP_DPORT,
464 MLX5_MODI_OUT_SIPV6_127_96,
465 MLX5_MODI_OUT_SIPV6_95_64,
466 MLX5_MODI_OUT_SIPV6_63_32,
467 MLX5_MODI_OUT_SIPV6_31_0,
468 MLX5_MODI_OUT_DIPV6_127_96,
469 MLX5_MODI_OUT_DIPV6_95_64,
470 MLX5_MODI_OUT_DIPV6_63_32,
471 MLX5_MODI_OUT_DIPV6_31_0,
474 MLX5_MODI_OUT_FIRST_VID,
475 MLX5_MODI_IN_SMAC_47_16 = 0x31,
476 MLX5_MODI_IN_SMAC_15_0,
477 MLX5_MODI_IN_ETHERTYPE,
478 MLX5_MODI_IN_DMAC_47_16,
479 MLX5_MODI_IN_DMAC_15_0,
480 MLX5_MODI_IN_IP_DSCP,
481 MLX5_MODI_IN_TCP_FLAGS,
482 MLX5_MODI_IN_TCP_SPORT,
483 MLX5_MODI_IN_TCP_DPORT,
484 MLX5_MODI_IN_IPV4_TTL,
485 MLX5_MODI_IN_UDP_SPORT,
486 MLX5_MODI_IN_UDP_DPORT,
487 MLX5_MODI_IN_SIPV6_127_96,
488 MLX5_MODI_IN_SIPV6_95_64,
489 MLX5_MODI_IN_SIPV6_63_32,
490 MLX5_MODI_IN_SIPV6_31_0,
491 MLX5_MODI_IN_DIPV6_127_96,
492 MLX5_MODI_IN_DIPV6_95_64,
493 MLX5_MODI_IN_DIPV6_63_32,
494 MLX5_MODI_IN_DIPV6_31_0,
497 MLX5_MODI_OUT_IPV6_HOPLIMIT,
498 MLX5_MODI_IN_IPV6_HOPLIMIT,
499 MLX5_MODI_META_DATA_REG_A,
500 MLX5_MODI_META_DATA_REG_B = 0x50,
501 MLX5_MODI_META_REG_C_0,
502 MLX5_MODI_META_REG_C_1,
503 MLX5_MODI_META_REG_C_2,
504 MLX5_MODI_META_REG_C_3,
505 MLX5_MODI_META_REG_C_4,
506 MLX5_MODI_META_REG_C_5,
507 MLX5_MODI_META_REG_C_6,
508 MLX5_MODI_META_REG_C_7,
509 MLX5_MODI_OUT_TCP_SEQ_NUM,
510 MLX5_MODI_IN_TCP_SEQ_NUM,
511 MLX5_MODI_OUT_TCP_ACK_NUM,
512 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
515 /* Total number of metadata reg_c's. */
516 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1)
532 /* Modification sub command. */
533 struct mlx5_modification_cmd {
537 unsigned int length:5;
538 unsigned int rsvd0:3;
539 unsigned int offset:5;
540 unsigned int rsvd1:3;
541 unsigned int field:12;
542 unsigned int action_type:4;
549 unsigned int rsvd2:8;
550 unsigned int dst_offset:5;
551 unsigned int rsvd3:3;
552 unsigned int dst_field:12;
553 unsigned int rsvd4:4;
558 typedef uint32_t u32;
559 typedef uint16_t u16;
562 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
563 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
564 #define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \
565 (&(__mlx5_nullp(typ)->fld)))
566 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
567 (__mlx5_bit_off(typ, fld) & 0x1f))
568 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
569 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
570 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
571 __mlx5_dw_bit_off(typ, fld))
572 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
573 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
574 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
575 (__mlx5_bit_off(typ, fld) & 0xf))
576 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
577 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \
578 __mlx5_16_bit_off(typ, fld))
579 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
580 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
581 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
582 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
584 /* insert a value to a struct */
585 #define MLX5_SET(typ, p, fld, v) \
588 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
589 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
590 __mlx5_dw_off(typ, fld))) & \
591 (~__mlx5_dw_mask(typ, fld))) | \
592 (((_v) & __mlx5_mask(typ, fld)) << \
593 __mlx5_dw_bit_off(typ, fld))); \
596 #define MLX5_SET64(typ, p, fld, v) \
598 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \
599 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = \
600 rte_cpu_to_be_64(v); \
603 #define MLX5_SET16(typ, p, fld, v) \
606 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
607 rte_cpu_to_be_16((rte_be_to_cpu_16(*((__be16 *)(p) + \
608 __mlx5_16_off(typ, fld))) & \
609 (~__mlx5_16_mask(typ, fld))) | \
610 (((_v) & __mlx5_mask16(typ, fld)) << \
611 __mlx5_16_bit_off(typ, fld))); \
614 #define MLX5_GET_VOLATILE(typ, p, fld) \
615 ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\
616 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
617 __mlx5_mask(typ, fld))
618 #define MLX5_GET(typ, p, fld) \
619 ((rte_be_to_cpu_32(*((__be32 *)(p) +\
620 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
621 __mlx5_mask(typ, fld))
622 #define MLX5_GET16(typ, p, fld) \
623 ((rte_be_to_cpu_16(*((__be16 *)(p) + \
624 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
625 __mlx5_mask16(typ, fld))
626 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((__be64 *)(p) + \
627 __mlx5_64_off(typ, fld)))
628 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
630 struct mlx5_ifc_fte_match_set_misc_bits {
631 u8 gre_c_present[0x1];
632 u8 reserved_at_1[0x1];
633 u8 gre_k_present[0x1];
634 u8 gre_s_present[0x1];
635 u8 source_vhci_port[0x4];
637 u8 reserved_at_20[0x10];
638 u8 source_port[0x10];
639 u8 outer_second_prio[0x3];
640 u8 outer_second_cfi[0x1];
641 u8 outer_second_vid[0xc];
642 u8 inner_second_prio[0x3];
643 u8 inner_second_cfi[0x1];
644 u8 inner_second_vid[0xc];
645 u8 outer_second_cvlan_tag[0x1];
646 u8 inner_second_cvlan_tag[0x1];
647 u8 outer_second_svlan_tag[0x1];
648 u8 inner_second_svlan_tag[0x1];
649 u8 reserved_at_64[0xc];
650 u8 gre_protocol[0x10];
654 u8 reserved_at_b8[0x8];
656 u8 reserved_at_e4[0x7];
658 u8 reserved_at_e0[0xc];
659 u8 outer_ipv6_flow_label[0x14];
660 u8 reserved_at_100[0xc];
661 u8 inner_ipv6_flow_label[0x14];
662 u8 reserved_at_120[0xa];
663 u8 geneve_opt_len[0x6];
664 u8 geneve_protocol_type[0x10];
665 u8 reserved_at_140[0xc0];
668 struct mlx5_ifc_ipv4_layout_bits {
669 u8 reserved_at_0[0x60];
673 struct mlx5_ifc_ipv6_layout_bits {
677 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
678 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
679 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
680 u8 reserved_at_0[0x80];
683 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
702 u8 reserved_at_c0[0x18];
703 u8 ip_ttl_hoplimit[0x8];
706 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
707 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
710 struct mlx5_ifc_fte_match_mpls_bits {
717 struct mlx5_ifc_fte_match_set_misc2_bits {
718 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
719 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
720 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
721 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
722 u8 metadata_reg_c_7[0x20];
723 u8 metadata_reg_c_6[0x20];
724 u8 metadata_reg_c_5[0x20];
725 u8 metadata_reg_c_4[0x20];
726 u8 metadata_reg_c_3[0x20];
727 u8 metadata_reg_c_2[0x20];
728 u8 metadata_reg_c_1[0x20];
729 u8 metadata_reg_c_0[0x20];
730 u8 metadata_reg_a[0x20];
731 u8 metadata_reg_b[0x20];
732 u8 reserved_at_1c0[0x40];
735 struct mlx5_ifc_fte_match_set_misc3_bits {
736 u8 inner_tcp_seq_num[0x20];
737 u8 outer_tcp_seq_num[0x20];
738 u8 inner_tcp_ack_num[0x20];
739 u8 outer_tcp_ack_num[0x20];
740 u8 reserved_at_auto1[0x8];
741 u8 outer_vxlan_gpe_vni[0x18];
742 u8 outer_vxlan_gpe_next_protocol[0x8];
743 u8 outer_vxlan_gpe_flags[0x8];
744 u8 reserved_at_a8[0x10];
745 u8 icmp_header_data[0x20];
746 u8 icmpv6_header_data[0x20];
751 u8 reserved_at_120[0x20];
753 u8 gtpu_msg_type[0x08];
754 u8 gtpu_msg_flags[0x08];
755 u8 reserved_at_170[0x90];
759 struct mlx5_ifc_fte_match_param_bits {
760 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
761 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
762 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
763 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
764 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
768 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
769 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
770 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
771 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
772 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT
776 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
777 MLX5_CMD_OP_CREATE_MKEY = 0x200,
778 MLX5_CMD_OP_CREATE_CQ = 0x400,
779 MLX5_CMD_OP_CREATE_QP = 0x500,
780 MLX5_CMD_OP_RST2INIT_QP = 0x502,
781 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
782 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
783 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
784 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
785 MLX5_CMD_OP_QP_2ERR = 0x507,
786 MLX5_CMD_OP_QP_2RST = 0x50A,
787 MLX5_CMD_OP_QUERY_QP = 0x50B,
788 MLX5_CMD_OP_SQD2RTS_QP = 0x50C,
789 MLX5_CMD_OP_INIT2INIT_QP = 0x50E,
790 MLX5_CMD_OP_SUSPEND_QP = 0x50F,
791 MLX5_CMD_OP_RESUME_QP = 0x510,
792 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
793 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
794 MLX5_CMD_OP_CREATE_TIR = 0x900,
795 MLX5_CMD_OP_CREATE_SQ = 0X904,
796 MLX5_CMD_OP_MODIFY_SQ = 0X905,
797 MLX5_CMD_OP_CREATE_RQ = 0x908,
798 MLX5_CMD_OP_MODIFY_RQ = 0x909,
799 MLX5_CMD_OP_CREATE_TIS = 0x912,
800 MLX5_CMD_OP_QUERY_TIS = 0x915,
801 MLX5_CMD_OP_CREATE_RQT = 0x916,
802 MLX5_CMD_OP_MODIFY_RQT = 0x917,
803 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
804 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
805 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
806 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
807 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
808 MLX5_CMD_SET_REGEX_PARAMS = 0xb04,
809 MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,
810 MLX5_CMD_SET_REGEX_REGISTERS = 0xb06,
811 MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
815 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
816 MLX5_MKC_ACCESS_MODE_KLM = 0x2,
817 MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3,
820 #define MLX5_ADAPTER_PAGE_SHIFT 12
821 #define MLX5_LOG_RQ_STRIDE_SHIFT 4
823 * The batch counter dcs id starts from 0x800000 and none batch counter
824 * starts from 0. As currently, the counter is changed to be indexed by
825 * pool index and the offset of the counter in the pool counters_raw array.
826 * It means now the counter index is same for batch and none batch counter.
827 * Add the 0x800000 batch counter offset to the batch counter index helps
828 * indicate the counter index is from batch or none batch container pool.
830 #define MLX5_CNT_BATCH_OFFSET 0x800000
833 struct mlx5_ifc_alloc_flow_counter_out_bits {
835 u8 reserved_at_8[0x18];
837 u8 flow_counter_id[0x20];
838 u8 reserved_at_60[0x20];
841 struct mlx5_ifc_alloc_flow_counter_in_bits {
843 u8 reserved_at_10[0x10];
844 u8 reserved_at_20[0x10];
846 u8 flow_counter_id[0x20];
847 u8 reserved_at_40[0x18];
848 u8 flow_counter_bulk[0x8];
851 struct mlx5_ifc_dealloc_flow_counter_out_bits {
853 u8 reserved_at_8[0x18];
855 u8 reserved_at_40[0x40];
858 struct mlx5_ifc_dealloc_flow_counter_in_bits {
860 u8 reserved_at_10[0x10];
861 u8 reserved_at_20[0x10];
863 u8 flow_counter_id[0x20];
864 u8 reserved_at_60[0x20];
867 struct mlx5_ifc_traffic_counter_bits {
872 struct mlx5_ifc_query_flow_counter_out_bits {
874 u8 reserved_at_8[0x18];
876 u8 reserved_at_40[0x40];
877 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
880 struct mlx5_ifc_query_flow_counter_in_bits {
882 u8 reserved_at_10[0x10];
883 u8 reserved_at_20[0x10];
885 u8 reserved_at_40[0x20];
889 u8 dump_to_memory[0x1];
890 u8 num_of_counters[0x1e];
891 u8 flow_counter_id[0x20];
894 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u
895 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u
898 struct mlx5_ifc_klm_bits {
904 struct mlx5_ifc_mkc_bits {
905 u8 reserved_at_0[0x1];
907 u8 reserved_at_2[0x1];
908 u8 access_mode_4_2[0x3];
909 u8 reserved_at_6[0x7];
910 u8 relaxed_ordering_write[0x1];
911 u8 reserved_at_e[0x1];
912 u8 small_fence_on_rdma_read_response[0x1];
919 u8 access_mode_1_0[0x2];
920 u8 reserved_at_18[0x8];
925 u8 reserved_at_40[0x20];
930 u8 reserved_at_63[0x2];
931 u8 expected_sigerr_count[0x1];
932 u8 reserved_at_66[0x1];
940 u8 bsf_octword_size[0x20];
942 u8 reserved_at_120[0x80];
944 u8 translations_octword_size[0x20];
946 u8 reserved_at_1c0[0x19];
947 u8 relaxed_ordering_read[0x1];
948 u8 reserved_at_1da[0x1];
949 u8 log_page_size[0x5];
951 u8 reserved_at_1e0[0x20];
954 struct mlx5_ifc_create_mkey_out_bits {
956 u8 reserved_at_8[0x18];
960 u8 reserved_at_40[0x8];
963 u8 reserved_at_60[0x20];
966 struct mlx5_ifc_create_mkey_in_bits {
968 u8 reserved_at_10[0x10];
970 u8 reserved_at_20[0x10];
973 u8 reserved_at_40[0x20];
976 u8 reserved_at_61[0x1f];
978 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
980 u8 reserved_at_280[0x80];
982 u8 translations_octword_actual_size[0x20];
984 u8 mkey_umem_id[0x20];
986 u8 mkey_umem_offset[0x40];
988 u8 reserved_at_380[0x500];
990 u8 klm_pas_mtt[][0x20];
994 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
995 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
996 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
997 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
1001 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q = (1ULL << 0xd),
1002 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS = (1ULL << 0x1c),
1006 MLX5_HCA_CAP_OPMOD_GET_MAX = 0,
1007 MLX5_HCA_CAP_OPMOD_GET_CUR = 1,
1011 MLX5_CAP_INLINE_MODE_L2,
1012 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
1013 MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
1017 MLX5_INLINE_MODE_NONE,
1018 MLX5_INLINE_MODE_L2,
1019 MLX5_INLINE_MODE_IP,
1020 MLX5_INLINE_MODE_TCP_UDP,
1021 MLX5_INLINE_MODE_RESERVED4,
1022 MLX5_INLINE_MODE_INNER_L2,
1023 MLX5_INLINE_MODE_INNER_IP,
1024 MLX5_INLINE_MODE_INNER_TCP_UDP,
1027 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
1028 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
1029 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
1030 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
1031 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
1032 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
1033 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
1034 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
1035 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
1036 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
1037 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
1039 struct mlx5_ifc_cmd_hca_cap_bits {
1040 u8 reserved_at_0[0x30];
1042 u8 reserved_at_40[0x40];
1043 u8 log_max_srq_sz[0x8];
1044 u8 log_max_qp_sz[0x8];
1045 u8 reserved_at_90[0xb];
1048 u8 reserved_at_a1[0x3];
1049 u8 regexp_num_of_engines[0x4];
1050 u8 reserved_at_a8[0x3];
1051 u8 log_max_srq[0x5];
1052 u8 reserved_at_b0[0x3];
1053 u8 regexp_log_crspace_size[0x5];
1054 u8 reserved_at_b8[0x8];
1055 u8 reserved_at_c0[0x8];
1056 u8 log_max_cq_sz[0x8];
1057 u8 reserved_at_d0[0xb];
1059 u8 log_max_eq_sz[0x8];
1060 u8 relaxed_ordering_write[0x1];
1061 u8 relaxed_ordering_read[0x1];
1062 u8 log_max_mkey[0x6];
1063 u8 reserved_at_f0[0x8];
1064 u8 dump_fill_mkey[0x1];
1065 u8 reserved_at_f9[0x3];
1067 u8 max_indirection[0x8];
1068 u8 fixed_buffer_size[0x1];
1069 u8 log_max_mrw_sz[0x7];
1070 u8 force_teardown[0x1];
1071 u8 reserved_at_111[0x1];
1072 u8 log_max_bsf_list_size[0x6];
1073 u8 umr_extended_translation_offset[0x1];
1075 u8 log_max_klm_list_size[0x6];
1076 u8 reserved_at_120[0xa];
1077 u8 log_max_ra_req_dc[0x6];
1078 u8 reserved_at_130[0xa];
1079 u8 log_max_ra_res_dc[0x6];
1080 u8 reserved_at_140[0xa];
1081 u8 log_max_ra_req_qp[0x6];
1082 u8 reserved_at_150[0xa];
1083 u8 log_max_ra_res_qp[0x6];
1085 u8 cc_query_allowed[0x1];
1086 u8 cc_modify_allowed[0x1];
1088 u8 cache_line_128byte[0x1];
1089 u8 reserved_at_165[0xa];
1091 u8 gid_table_size[0x10];
1092 u8 out_of_seq_cnt[0x1];
1093 u8 vport_counters[0x1];
1094 u8 retransmission_q_counters[0x1];
1096 u8 modify_rq_counter_set_id[0x1];
1097 u8 rq_delay_drop[0x1];
1099 u8 pkey_table_size[0x10];
1100 u8 vport_group_manager[0x1];
1101 u8 vhca_group_manager[0x1];
1104 u8 vnic_env_queue_counters[0x1];
1106 u8 nic_flow_table[0x1];
1107 u8 eswitch_manager[0x1];
1108 u8 device_memory[0x1];
1111 u8 local_ca_ack_delay[0x5];
1112 u8 port_module_event[0x1];
1113 u8 enhanced_error_q_counters[0x1];
1114 u8 ports_check[0x1];
1115 u8 reserved_at_1b3[0x1];
1116 u8 disable_link_up[0x1];
1120 u8 reserved_at_1c0[0x1];
1123 u8 log_max_msg[0x5];
1124 u8 reserved_at_1c8[0x4];
1126 u8 temp_warn_event[0x1];
1128 u8 general_notification_event[0x1];
1129 u8 reserved_at_1d3[0x2];
1133 u8 reserved_at_1d8[0x1];
1141 u8 stat_rate_support[0x10];
1142 u8 reserved_at_1f0[0xc];
1143 u8 cqe_version[0x4];
1144 u8 compact_address_vector[0x1];
1145 u8 striding_rq[0x1];
1146 u8 reserved_at_202[0x1];
1147 u8 ipoib_enhanced_offloads[0x1];
1148 u8 ipoib_basic_offloads[0x1];
1149 u8 reserved_at_205[0x1];
1150 u8 repeated_block_disabled[0x1];
1151 u8 umr_modify_entity_size_disabled[0x1];
1152 u8 umr_modify_atomic_disabled[0x1];
1153 u8 umr_indirect_mkey_disabled[0x1];
1155 u8 reserved_at_20c[0x3];
1156 u8 drain_sigerr[0x1];
1157 u8 cmdif_checksum[0x2];
1159 u8 reserved_at_213[0x1];
1160 u8 wq_signature[0x1];
1161 u8 sctr_data_cqe[0x1];
1162 u8 reserved_at_216[0x1];
1168 u8 eth_net_offloads[0x1];
1171 u8 reserved_at_21f[0x1];
1174 u8 cq_moderation[0x1];
1175 u8 reserved_at_223[0x3];
1176 u8 cq_eq_remap[0x1];
1178 u8 block_lb_mc[0x1];
1179 u8 reserved_at_229[0x1];
1180 u8 scqe_break_moderation[0x1];
1181 u8 cq_period_start_from_cqe[0x1];
1183 u8 reserved_at_22d[0x1];
1185 u8 vector_calc[0x1];
1186 u8 umr_ptr_rlky[0x1];
1188 u8 reserved_at_232[0x4];
1191 u8 set_deth_sqpn[0x1];
1192 u8 reserved_at_239[0x3];
1198 u8 reserved_at_241[0x9];
1200 u8 reserved_at_250[0x8];
1203 u8 driver_version[0x1];
1204 u8 pad_tx_eth_packet[0x1];
1205 u8 reserved_at_263[0x8];
1206 u8 log_bf_reg_size[0x5];
1207 u8 reserved_at_270[0xb];
1209 u8 num_lag_ports[0x4];
1210 u8 reserved_at_280[0x10];
1211 u8 max_wqe_sz_sq[0x10];
1212 u8 reserved_at_2a0[0x10];
1213 u8 max_wqe_sz_rq[0x10];
1214 u8 max_flow_counter_31_16[0x10];
1215 u8 max_wqe_sz_sq_dc[0x10];
1216 u8 reserved_at_2e0[0x7];
1217 u8 max_qp_mcg[0x19];
1218 u8 reserved_at_300[0x10];
1219 u8 flow_counter_bulk_alloc[0x08];
1220 u8 log_max_mcg[0x8];
1221 u8 reserved_at_320[0x3];
1222 u8 log_max_transport_domain[0x5];
1223 u8 reserved_at_328[0x3];
1225 u8 reserved_at_330[0xb];
1226 u8 log_max_xrcd[0x5];
1227 u8 nic_receive_steering_discard[0x1];
1228 u8 receive_discard_vport_down[0x1];
1229 u8 transmit_discard_vport_down[0x1];
1230 u8 reserved_at_343[0x5];
1231 u8 log_max_flow_counter_bulk[0x8];
1232 u8 max_flow_counter_15_0[0x10];
1234 u8 flow_counters_dump[0x1];
1235 u8 reserved_at_360[0x1];
1237 u8 reserved_at_368[0x3];
1239 u8 reserved_at_370[0x3];
1240 u8 log_max_tir[0x5];
1241 u8 reserved_at_378[0x3];
1242 u8 log_max_tis[0x5];
1243 u8 basic_cyclic_rcv_wqe[0x1];
1244 u8 reserved_at_381[0x2];
1245 u8 log_max_rmp[0x5];
1246 u8 reserved_at_388[0x3];
1247 u8 log_max_rqt[0x5];
1248 u8 reserved_at_390[0x3];
1249 u8 log_max_rqt_size[0x5];
1250 u8 reserved_at_398[0x3];
1251 u8 log_max_tis_per_sq[0x5];
1252 u8 ext_stride_num_range[0x1];
1253 u8 reserved_at_3a1[0x2];
1254 u8 log_max_stride_sz_rq[0x5];
1255 u8 reserved_at_3a8[0x3];
1256 u8 log_min_stride_sz_rq[0x5];
1257 u8 reserved_at_3b0[0x3];
1258 u8 log_max_stride_sz_sq[0x5];
1259 u8 reserved_at_3b8[0x3];
1260 u8 log_min_stride_sz_sq[0x5];
1262 u8 reserved_at_3c1[0x2];
1263 u8 log_max_hairpin_queues[0x5];
1264 u8 reserved_at_3c8[0x3];
1265 u8 log_max_hairpin_wq_data_sz[0x5];
1266 u8 reserved_at_3d0[0x3];
1267 u8 log_max_hairpin_num_packets[0x5];
1268 u8 reserved_at_3d8[0x3];
1269 u8 log_max_wq_sz[0x5];
1270 u8 nic_vport_change_event[0x1];
1271 u8 disable_local_lb_uc[0x1];
1272 u8 disable_local_lb_mc[0x1];
1273 u8 log_min_hairpin_wq_data_sz[0x5];
1274 u8 reserved_at_3e8[0x3];
1275 u8 log_max_vlan_list[0x5];
1276 u8 reserved_at_3f0[0x3];
1277 u8 log_max_current_mc_list[0x5];
1278 u8 reserved_at_3f8[0x3];
1279 u8 log_max_current_uc_list[0x5];
1280 u8 general_obj_types[0x40];
1281 u8 reserved_at_440[0x20];
1282 u8 reserved_at_460[0x10];
1283 u8 max_num_eqs[0x10];
1284 u8 reserved_at_480[0x3];
1285 u8 log_max_l2_table[0x5];
1286 u8 reserved_at_488[0x8];
1287 u8 log_uar_page_sz[0x10];
1288 u8 reserved_at_4a0[0x20];
1289 u8 device_frequency_mhz[0x20];
1290 u8 device_frequency_khz[0x20];
1291 u8 reserved_at_500[0x20];
1292 u8 num_of_uars_per_page[0x20];
1293 u8 flex_parser_protocols[0x20];
1294 u8 reserved_at_560[0x20];
1295 u8 reserved_at_580[0x3c];
1296 u8 mini_cqe_resp_stride_index[0x1];
1297 u8 cqe_128_always[0x1];
1298 u8 cqe_compression_128[0x1];
1299 u8 cqe_compression[0x1];
1300 u8 cqe_compression_timeout[0x10];
1301 u8 cqe_compression_max_num[0x10];
1302 u8 reserved_at_5e0[0x10];
1303 u8 tag_matching[0x1];
1304 u8 rndv_offload_rc[0x1];
1305 u8 rndv_offload_dc[0x1];
1306 u8 log_tag_matching_list_sz[0x5];
1307 u8 reserved_at_5f8[0x3];
1308 u8 log_max_xrq[0x5];
1309 u8 affiliate_nic_vport_criteria[0x8];
1310 u8 native_port_num[0x8];
1311 u8 num_vhca_ports[0x8];
1312 u8 reserved_at_618[0x6];
1313 u8 sw_owner_id[0x1];
1314 u8 reserved_at_61f[0x1e1];
1317 struct mlx5_ifc_qos_cap_bits {
1318 u8 packet_pacing[0x1];
1319 u8 esw_scheduling[0x1];
1320 u8 esw_bw_share[0x1];
1321 u8 esw_rate_limit[0x1];
1322 u8 reserved_at_4[0x1];
1323 u8 packet_pacing_burst_bound[0x1];
1324 u8 packet_pacing_typical_size[0x1];
1325 u8 flow_meter_srtcm[0x1];
1326 u8 reserved_at_8[0x8];
1327 u8 log_max_flow_meter[0x8];
1328 u8 flow_meter_reg_id[0x8];
1329 u8 reserved_at_25[0x8];
1330 u8 flow_meter_reg_share[0x1];
1331 u8 reserved_at_2e[0x17];
1332 u8 packet_pacing_max_rate[0x20];
1333 u8 packet_pacing_min_rate[0x20];
1334 u8 reserved_at_80[0x10];
1335 u8 packet_pacing_rate_table_size[0x10];
1336 u8 esw_element_type[0x10];
1337 u8 esw_tsar_type[0x10];
1338 u8 reserved_at_c0[0x10];
1339 u8 max_qos_para_vport[0x10];
1340 u8 max_tsar_bw_share[0x20];
1341 u8 reserved_at_100[0x6e8];
1344 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1348 u8 lro_psh_flag[0x1];
1349 u8 lro_time_stamp[0x1];
1350 u8 lro_max_msg_sz_mode[0x2];
1351 u8 wqe_vlan_insert[0x1];
1352 u8 self_lb_en_modifiable[0x1];
1355 u8 max_lso_cap[0x5];
1356 u8 multi_pkt_send_wqe[0x2];
1357 u8 wqe_inline_mode[0x2];
1358 u8 rss_ind_tbl_cap[0x4];
1360 u8 scatter_fcs[0x1];
1361 u8 enhanced_multi_pkt_send_wqe[0x1];
1362 u8 tunnel_lso_const_out_ip_id[0x1];
1363 u8 tunnel_lro_gre[0x1];
1364 u8 tunnel_lro_vxlan[0x1];
1365 u8 tunnel_stateless_gre[0x1];
1366 u8 tunnel_stateless_vxlan[0x1];
1370 u8 reserved_at_23[0x8];
1371 u8 tunnel_stateless_gtp[0x1];
1372 u8 reserved_at_25[0x4];
1373 u8 max_vxlan_udp_ports[0x8];
1374 u8 reserved_at_38[0x6];
1375 u8 max_geneve_opt_len[0x1];
1376 u8 tunnel_stateless_geneve_rx[0x1];
1377 u8 reserved_at_40[0x10];
1378 u8 lro_min_mss_size[0x10];
1379 u8 reserved_at_60[0x120];
1380 u8 lro_timer_supported_periods[4][0x20];
1381 u8 reserved_at_200[0x600];
1385 MLX5_VIRTQ_TYPE_SPLIT = 0,
1386 MLX5_VIRTQ_TYPE_PACKED = 1,
1390 MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0,
1391 MLX5_VIRTQ_EVENT_MODE_QP = 1,
1392 MLX5_VIRTQ_EVENT_MODE_MSIX = 2,
1395 struct mlx5_ifc_virtio_emulation_cap_bits {
1396 u8 desc_tunnel_offload_type[0x1];
1397 u8 eth_frame_offload_type[0x1];
1398 u8 virtio_version_1_0[0x1];
1403 u8 reserved_at_7[0x1][0x9];
1405 u8 virtio_queue_type[0x8];
1406 u8 reserved_at_20[0x13];
1407 u8 log_doorbell_stride[0x5];
1408 u8 reserved_at_3b[0x3];
1409 u8 log_doorbell_bar_size[0x5];
1410 u8 doorbell_bar_offset[0x40];
1411 u8 reserved_at_80[0x8];
1412 u8 max_num_virtio_queues[0x18];
1413 u8 reserved_at_a0[0x60];
1414 u8 umem_1_buffer_param_a[0x20];
1415 u8 umem_1_buffer_param_b[0x20];
1416 u8 umem_2_buffer_param_a[0x20];
1417 u8 umem_2_buffer_param_b[0x20];
1418 u8 umem_3_buffer_param_a[0x20];
1419 u8 umem_3_buffer_param_b[0x20];
1420 u8 reserved_at_1c0[0x620];
1423 union mlx5_ifc_hca_cap_union_bits {
1424 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1425 struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1426 per_protocol_networking_offload_caps;
1427 struct mlx5_ifc_qos_cap_bits qos_cap;
1428 struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
1429 u8 reserved_at_0[0x8000];
1432 struct mlx5_ifc_query_hca_cap_out_bits {
1434 u8 reserved_at_8[0x18];
1436 u8 reserved_at_40[0x40];
1437 union mlx5_ifc_hca_cap_union_bits capability;
1440 struct mlx5_ifc_query_hca_cap_in_bits {
1442 u8 reserved_at_10[0x10];
1443 u8 reserved_at_20[0x10];
1445 u8 reserved_at_40[0x40];
1448 struct mlx5_ifc_mac_address_layout_bits {
1449 u8 reserved_at_0[0x10];
1450 u8 mac_addr_47_32[0x10];
1451 u8 mac_addr_31_0[0x20];
1454 struct mlx5_ifc_nic_vport_context_bits {
1455 u8 reserved_at_0[0x5];
1456 u8 min_wqe_inline_mode[0x3];
1457 u8 reserved_at_8[0x15];
1458 u8 disable_mc_local_lb[0x1];
1459 u8 disable_uc_local_lb[0x1];
1461 u8 arm_change_event[0x1];
1462 u8 reserved_at_21[0x1a];
1463 u8 event_on_mtu[0x1];
1464 u8 event_on_promisc_change[0x1];
1465 u8 event_on_vlan_change[0x1];
1466 u8 event_on_mc_address_change[0x1];
1467 u8 event_on_uc_address_change[0x1];
1468 u8 reserved_at_40[0xc];
1469 u8 affiliation_criteria[0x4];
1470 u8 affiliated_vhca_id[0x10];
1471 u8 reserved_at_60[0xd0];
1473 u8 system_image_guid[0x40];
1476 u8 reserved_at_200[0x140];
1477 u8 qkey_violation_counter[0x10];
1478 u8 reserved_at_350[0x430];
1481 u8 promisc_all[0x1];
1482 u8 reserved_at_783[0x2];
1483 u8 allowed_list_type[0x3];
1484 u8 reserved_at_788[0xc];
1485 u8 allowed_list_size[0xc];
1486 struct mlx5_ifc_mac_address_layout_bits permanent_address;
1487 u8 reserved_at_7e0[0x20];
1490 struct mlx5_ifc_query_nic_vport_context_out_bits {
1492 u8 reserved_at_8[0x18];
1494 u8 reserved_at_40[0x40];
1495 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
1498 struct mlx5_ifc_query_nic_vport_context_in_bits {
1500 u8 reserved_at_10[0x10];
1501 u8 reserved_at_20[0x10];
1503 u8 other_vport[0x1];
1504 u8 reserved_at_41[0xf];
1505 u8 vport_number[0x10];
1506 u8 reserved_at_60[0x5];
1507 u8 allowed_list_type[0x3];
1508 u8 reserved_at_68[0x18];
1511 struct mlx5_ifc_tisc_bits {
1512 u8 strict_lag_tx_port_affinity[0x1];
1513 u8 reserved_at_1[0x3];
1514 u8 lag_tx_port_affinity[0x04];
1515 u8 reserved_at_8[0x4];
1517 u8 reserved_at_10[0x10];
1518 u8 reserved_at_20[0x100];
1519 u8 reserved_at_120[0x8];
1520 u8 transport_domain[0x18];
1521 u8 reserved_at_140[0x8];
1522 u8 underlay_qpn[0x18];
1523 u8 reserved_at_160[0x3a0];
1526 struct mlx5_ifc_query_tis_out_bits {
1528 u8 reserved_at_8[0x18];
1530 u8 reserved_at_40[0x40];
1531 struct mlx5_ifc_tisc_bits tis_context;
1534 struct mlx5_ifc_query_tis_in_bits {
1536 u8 reserved_at_10[0x10];
1537 u8 reserved_at_20[0x10];
1539 u8 reserved_at_40[0x8];
1541 u8 reserved_at_60[0x20];
1544 struct mlx5_ifc_alloc_transport_domain_out_bits {
1546 u8 reserved_at_8[0x18];
1548 u8 reserved_at_40[0x8];
1549 u8 transport_domain[0x18];
1550 u8 reserved_at_60[0x20];
1553 struct mlx5_ifc_alloc_transport_domain_in_bits {
1555 u8 reserved_at_10[0x10];
1556 u8 reserved_at_20[0x10];
1558 u8 reserved_at_40[0x40];
1562 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1563 MLX5_WQ_TYPE_CYCLIC = 0x1,
1564 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1565 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1569 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1570 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1573 struct mlx5_ifc_wq_bits {
1575 u8 wq_signature[0x1];
1576 u8 end_padding_mode[0x2];
1578 u8 reserved_at_8[0x18];
1579 u8 hds_skip_first_sge[0x1];
1580 u8 log2_hds_buf_size[0x3];
1581 u8 reserved_at_24[0x7];
1582 u8 page_offset[0x5];
1584 u8 reserved_at_40[0x8];
1586 u8 reserved_at_60[0x8];
1589 u8 hw_counter[0x20];
1590 u8 sw_counter[0x20];
1591 u8 reserved_at_100[0xc];
1592 u8 log_wq_stride[0x4];
1593 u8 reserved_at_110[0x3];
1594 u8 log_wq_pg_sz[0x5];
1595 u8 reserved_at_118[0x3];
1597 u8 dbr_umem_valid[0x1];
1598 u8 wq_umem_valid[0x1];
1599 u8 reserved_at_122[0x1];
1600 u8 log_hairpin_num_packets[0x5];
1601 u8 reserved_at_128[0x3];
1602 u8 log_hairpin_data_sz[0x5];
1603 u8 reserved_at_130[0x4];
1604 u8 single_wqe_log_num_of_strides[0x4];
1605 u8 two_byte_shift_en[0x1];
1606 u8 reserved_at_139[0x4];
1607 u8 single_stride_log_num_of_bytes[0x3];
1608 u8 dbr_umem_id[0x20];
1609 u8 wq_umem_id[0x20];
1610 u8 wq_umem_offset[0x40];
1611 u8 reserved_at_1c0[0x440];
1615 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1616 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
1620 MLX5_RQC_STATE_RST = 0x0,
1621 MLX5_RQC_STATE_RDY = 0x1,
1622 MLX5_RQC_STATE_ERR = 0x3,
1625 struct mlx5_ifc_rqc_bits {
1627 u8 delay_drop_en[0x1];
1628 u8 scatter_fcs[0x1];
1630 u8 mem_rq_type[0x4];
1632 u8 reserved_at_c[0x1];
1633 u8 flush_in_error_en[0x1];
1635 u8 reserved_at_f[0x11];
1636 u8 reserved_at_20[0x8];
1637 u8 user_index[0x18];
1638 u8 reserved_at_40[0x8];
1640 u8 counter_set_id[0x8];
1641 u8 reserved_at_68[0x18];
1642 u8 reserved_at_80[0x8];
1644 u8 reserved_at_a0[0x8];
1645 u8 hairpin_peer_sq[0x18];
1646 u8 reserved_at_c0[0x10];
1647 u8 hairpin_peer_vhca[0x10];
1648 u8 reserved_at_e0[0xa0];
1649 struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
1652 struct mlx5_ifc_create_rq_out_bits {
1654 u8 reserved_at_8[0x18];
1656 u8 reserved_at_40[0x8];
1658 u8 reserved_at_60[0x20];
1661 struct mlx5_ifc_create_rq_in_bits {
1664 u8 reserved_at_20[0x10];
1666 u8 reserved_at_40[0xc0];
1667 struct mlx5_ifc_rqc_bits ctx;
1670 struct mlx5_ifc_modify_rq_out_bits {
1672 u8 reserved_at_8[0x18];
1674 u8 reserved_at_40[0x40];
1677 struct mlx5_ifc_create_tis_out_bits {
1679 u8 reserved_at_8[0x18];
1681 u8 reserved_at_40[0x8];
1683 u8 reserved_at_60[0x20];
1686 struct mlx5_ifc_create_tis_in_bits {
1689 u8 reserved_at_20[0x10];
1691 u8 reserved_at_40[0xc0];
1692 struct mlx5_ifc_tisc_bits ctx;
1696 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
1697 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
1698 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
1699 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
1702 struct mlx5_ifc_modify_rq_in_bits {
1705 u8 reserved_at_20[0x10];
1708 u8 reserved_at_44[0x4];
1710 u8 reserved_at_60[0x20];
1711 u8 modify_bitmask[0x40];
1712 u8 reserved_at_c0[0x40];
1713 struct mlx5_ifc_rqc_bits ctx;
1717 MLX5_L3_PROT_TYPE_IPV4 = 0,
1718 MLX5_L3_PROT_TYPE_IPV6 = 1,
1722 MLX5_L4_PROT_TYPE_TCP = 0,
1723 MLX5_L4_PROT_TYPE_UDP = 1,
1727 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1728 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1729 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1730 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1731 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1734 struct mlx5_ifc_rx_hash_field_select_bits {
1735 u8 l3_prot_type[0x1];
1736 u8 l4_prot_type[0x1];
1737 u8 selected_fields[0x1e];
1741 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
1742 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
1746 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
1747 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
1751 MLX5_RX_HASH_FN_NONE = 0x0,
1752 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
1753 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
1757 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
1758 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
1762 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 = 0x0,
1763 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2 = 0x1,
1766 struct mlx5_ifc_tirc_bits {
1767 u8 reserved_at_0[0x20];
1769 u8 reserved_at_24[0x1c];
1770 u8 reserved_at_40[0x40];
1771 u8 reserved_at_80[0x4];
1772 u8 lro_timeout_period_usecs[0x10];
1773 u8 lro_enable_mask[0x4];
1774 u8 lro_max_msg_sz[0x8];
1775 u8 reserved_at_a0[0x40];
1776 u8 reserved_at_e0[0x8];
1777 u8 inline_rqn[0x18];
1778 u8 rx_hash_symmetric[0x1];
1779 u8 reserved_at_101[0x1];
1780 u8 tunneled_offload_en[0x1];
1781 u8 reserved_at_103[0x5];
1782 u8 indirect_table[0x18];
1784 u8 reserved_at_124[0x2];
1785 u8 self_lb_block[0x2];
1786 u8 transport_domain[0x18];
1787 u8 rx_hash_toeplitz_key[10][0x20];
1788 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1789 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1790 u8 reserved_at_2c0[0x4c0];
1793 struct mlx5_ifc_create_tir_out_bits {
1795 u8 reserved_at_8[0x18];
1797 u8 reserved_at_40[0x8];
1799 u8 reserved_at_60[0x20];
1802 struct mlx5_ifc_create_tir_in_bits {
1805 u8 reserved_at_20[0x10];
1807 u8 reserved_at_40[0xc0];
1808 struct mlx5_ifc_tirc_bits ctx;
1812 MLX5_INLINE_Q_TYPE_RQ = 0x0,
1813 MLX5_INLINE_Q_TYPE_VIRTQ = 0x1,
1816 struct mlx5_ifc_rq_num_bits {
1817 u8 reserved_at_0[0x8];
1821 struct mlx5_ifc_rqtc_bits {
1822 u8 reserved_at_0[0xa5];
1823 u8 list_q_type[0x3];
1824 u8 reserved_at_a8[0x8];
1825 u8 rqt_max_size[0x10];
1826 u8 reserved_at_c0[0x10];
1827 u8 rqt_actual_size[0x10];
1828 u8 reserved_at_e0[0x6a0];
1829 struct mlx5_ifc_rq_num_bits rq_num[];
1832 struct mlx5_ifc_create_rqt_out_bits {
1834 u8 reserved_at_8[0x18];
1836 u8 reserved_at_40[0x8];
1838 u8 reserved_at_60[0x20];
1842 #pragma GCC diagnostic ignored "-Wpedantic"
1844 struct mlx5_ifc_create_rqt_in_bits {
1847 u8 reserved_at_20[0x10];
1849 u8 reserved_at_40[0xc0];
1850 struct mlx5_ifc_rqtc_bits rqt_context;
1853 struct mlx5_ifc_modify_rqt_in_bits {
1856 u8 reserved_at_20[0x10];
1858 u8 reserved_at_40[0x8];
1860 u8 reserved_at_60[0x20];
1861 u8 modify_bitmask[0x40];
1862 u8 reserved_at_c0[0x40];
1863 struct mlx5_ifc_rqtc_bits rqt_context;
1866 #pragma GCC diagnostic error "-Wpedantic"
1869 struct mlx5_ifc_modify_rqt_out_bits {
1871 u8 reserved_at_8[0x18];
1873 u8 reserved_at_40[0x40];
1877 MLX5_SQC_STATE_RST = 0x0,
1878 MLX5_SQC_STATE_RDY = 0x1,
1879 MLX5_SQC_STATE_ERR = 0x3,
1882 struct mlx5_ifc_sqc_bits {
1886 u8 flush_in_error_en[0x1];
1887 u8 allow_multi_pkt_send_wqe[0x1];
1888 u8 min_wqe_inline_mode[0x3];
1893 u8 reserved_at_f[0x11];
1894 u8 reserved_at_20[0x8];
1895 u8 user_index[0x18];
1896 u8 reserved_at_40[0x8];
1898 u8 reserved_at_60[0x8];
1899 u8 hairpin_peer_rq[0x18];
1900 u8 reserved_at_80[0x10];
1901 u8 hairpin_peer_vhca[0x10];
1902 u8 reserved_at_a0[0x50];
1903 u8 packet_pacing_rate_limit_index[0x10];
1904 u8 tis_lst_sz[0x10];
1905 u8 reserved_at_110[0x10];
1906 u8 reserved_at_120[0x40];
1907 u8 reserved_at_160[0x8];
1909 struct mlx5_ifc_wq_bits wq;
1912 struct mlx5_ifc_query_sq_in_bits {
1914 u8 reserved_at_10[0x10];
1915 u8 reserved_at_20[0x10];
1917 u8 reserved_at_40[0x8];
1919 u8 reserved_at_60[0x20];
1922 struct mlx5_ifc_modify_sq_out_bits {
1924 u8 reserved_at_8[0x18];
1926 u8 reserved_at_40[0x40];
1929 struct mlx5_ifc_modify_sq_in_bits {
1932 u8 reserved_at_20[0x10];
1935 u8 reserved_at_44[0x4];
1937 u8 reserved_at_60[0x20];
1938 u8 modify_bitmask[0x40];
1939 u8 reserved_at_c0[0x40];
1940 struct mlx5_ifc_sqc_bits ctx;
1943 struct mlx5_ifc_create_sq_out_bits {
1945 u8 reserved_at_8[0x18];
1947 u8 reserved_at_40[0x8];
1949 u8 reserved_at_60[0x20];
1952 struct mlx5_ifc_create_sq_in_bits {
1955 u8 reserved_at_20[0x10];
1957 u8 reserved_at_40[0xc0];
1958 struct mlx5_ifc_sqc_bits ctx;
1962 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
1963 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
1964 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
1965 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
1966 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
1969 struct mlx5_ifc_flow_meter_parameters_bits {
1970 u8 valid[0x1]; // 00h
1971 u8 bucket_overflow[0x1];
1972 u8 start_color[0x2];
1973 u8 both_buckets_on_green[0x1];
1975 u8 reserved_at_1[0x19];
1976 u8 reserved_at_2[0x20]; //04h
1977 u8 reserved_at_3[0x3];
1978 u8 cbs_exponent[0x5]; // 08h
1979 u8 cbs_mantissa[0x8];
1980 u8 reserved_at_4[0x3];
1981 u8 cir_exponent[0x5];
1982 u8 cir_mantissa[0x8];
1983 u8 reserved_at_5[0x20]; // 0Ch
1984 u8 reserved_at_6[0x3];
1985 u8 ebs_exponent[0x5]; // 10h
1986 u8 ebs_mantissa[0x8];
1987 u8 reserved_at_7[0x3];
1988 u8 eir_exponent[0x5];
1989 u8 eir_mantissa[0x8];
1990 u8 reserved_at_8[0x60]; // 14h-1Ch
1993 struct mlx5_ifc_cqc_bits {
1996 u8 initiator_src_dct[0x1];
1997 u8 dbr_umem_valid[0x1];
1998 u8 reserved_at_7[0x1];
2001 u8 reserved_at_c[0x1];
2002 u8 scqe_break_moderation_en[0x1];
2004 u8 cq_period_mode[0x2];
2005 u8 cqe_comp_en[0x1];
2006 u8 mini_cqe_res_format[0x2];
2008 u8 reserved_at_18[0x8];
2009 u8 dbr_umem_id[0x20];
2010 u8 reserved_at_40[0x14];
2011 u8 page_offset[0x6];
2012 u8 reserved_at_5a[0x6];
2013 u8 reserved_at_60[0x3];
2014 u8 log_cq_size[0x5];
2016 u8 reserved_at_80[0x4];
2018 u8 cq_max_count[0x10];
2019 u8 reserved_at_a0[0x18];
2021 u8 reserved_at_c0[0x3];
2022 u8 log_page_size[0x5];
2023 u8 reserved_at_c8[0x18];
2024 u8 reserved_at_e0[0x20];
2025 u8 reserved_at_100[0x8];
2026 u8 last_notified_index[0x18];
2027 u8 reserved_at_120[0x8];
2028 u8 last_solicit_index[0x18];
2029 u8 reserved_at_140[0x8];
2030 u8 consumer_counter[0x18];
2031 u8 reserved_at_160[0x8];
2032 u8 producer_counter[0x18];
2033 u8 local_partition_id[0xc];
2034 u8 process_id[0x14];
2035 u8 reserved_at_1A0[0x20];
2039 struct mlx5_ifc_create_cq_out_bits {
2041 u8 reserved_at_8[0x18];
2043 u8 reserved_at_40[0x8];
2045 u8 reserved_at_60[0x20];
2048 struct mlx5_ifc_create_cq_in_bits {
2051 u8 reserved_at_20[0x10];
2053 u8 reserved_at_40[0x40];
2054 struct mlx5_ifc_cqc_bits cq_context;
2055 u8 cq_umem_offset[0x40];
2056 u8 cq_umem_id[0x20];
2057 u8 cq_umem_valid[0x1];
2058 u8 reserved_at_2e1[0x1f];
2059 u8 reserved_at_300[0x580];
2064 MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
2065 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
2068 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
2070 u8 reserved_at_10[0x20];
2073 u8 reserved_at_60[0x20];
2076 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
2078 u8 reserved_at_8[0x18];
2081 u8 reserved_at_60[0x20];
2084 struct mlx5_ifc_virtio_q_counters_bits {
2085 u8 modify_field_select[0x40];
2086 u8 reserved_at_40[0x40];
2087 u8 received_desc[0x40];
2088 u8 completed_desc[0x40];
2089 u8 error_cqes[0x20];
2090 u8 bad_desc_errors[0x20];
2091 u8 exceed_max_chain[0x20];
2092 u8 invalid_buffer[0x20];
2093 u8 reserved_at_180[0x50];
2096 struct mlx5_ifc_create_virtio_q_counters_in_bits {
2097 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2098 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2101 struct mlx5_ifc_query_virtio_q_counters_out_bits {
2102 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2103 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2106 MLX5_VIRTQ_STATE_INIT = 0,
2107 MLX5_VIRTQ_STATE_RDY = 1,
2108 MLX5_VIRTQ_STATE_SUSPEND = 2,
2109 MLX5_VIRTQ_STATE_ERROR = 3,
2113 MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),
2114 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),
2115 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),
2118 struct mlx5_ifc_virtio_q_bits {
2119 u8 virtio_q_type[0x8];
2120 u8 reserved_at_8[0x5];
2122 u8 queue_index[0x10];
2123 u8 full_emulation[0x1];
2124 u8 virtio_version_1_0[0x1];
2125 u8 reserved_at_22[0x2];
2126 u8 offload_type[0x4];
2127 u8 event_qpn_or_msix[0x18];
2128 u8 doorbell_stride_idx[0x10];
2129 u8 queue_size[0x10];
2130 u8 device_emulation_id[0x20];
2133 u8 available_addr[0x40];
2134 u8 virtio_q_mkey[0x20];
2135 u8 reserved_at_160[0x20];
2137 u8 umem_1_size[0x20];
2138 u8 umem_1_offset[0x40];
2140 u8 umem_2_size[0x20];
2141 u8 umem_2_offset[0x40];
2143 u8 umem_3_size[0x20];
2144 u8 umem_3_offset[0x40];
2145 u8 counter_set_id[0x20];
2146 u8 reserved_at_320[0x8];
2148 u8 reserved_at_340[0xc0];
2151 struct mlx5_ifc_virtio_net_q_bits {
2152 u8 modify_field_select[0x40];
2153 u8 reserved_at_40[0x40];
2158 u8 reserved_at_84[0x6];
2159 u8 dirty_bitmap_dump_enable[0x1];
2160 u8 vhost_log_page[0x5];
2161 u8 reserved_at_90[0xc];
2164 u8 tisn_or_qpn[0x18];
2165 u8 dirty_bitmap_mkey[0x20];
2166 u8 dirty_bitmap_size[0x20];
2167 u8 dirty_bitmap_addr[0x40];
2168 u8 hw_available_index[0x10];
2169 u8 hw_used_index[0x10];
2170 u8 reserved_at_160[0xa0];
2171 struct mlx5_ifc_virtio_q_bits virtio_q_context;
2174 struct mlx5_ifc_create_virtq_in_bits {
2175 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2176 struct mlx5_ifc_virtio_net_q_bits virtq;
2179 struct mlx5_ifc_query_virtq_out_bits {
2180 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2181 struct mlx5_ifc_virtio_net_q_bits virtq;
2185 MLX5_QP_ST_RC = 0x0,
2189 MLX5_QP_PM_MIGRATED = 0x3,
2193 MLX5_NON_ZERO_RQ = 0x0,
2196 MLX5_ZERO_LEN_RQ = 0x3,
2199 struct mlx5_ifc_ads_bits {
2202 u8 reserved_at_2[0xe];
2203 u8 pkey_index[0x10];
2204 u8 reserved_at_20[0x8];
2208 u8 ack_timeout[0x5];
2209 u8 reserved_at_45[0x3];
2210 u8 src_addr_index[0x8];
2211 u8 reserved_at_50[0x4];
2214 u8 reserved_at_60[0x4];
2216 u8 flow_label[0x14];
2217 u8 rgid_rip[16][0x8];
2218 u8 reserved_at_100[0x4];
2221 u8 reserved_at_106[0x1];
2229 u8 vhca_port_num[0x8];
2230 u8 rmac_47_32[0x10];
2234 struct mlx5_ifc_qpc_bits {
2236 u8 lag_tx_port_affinity[0x4];
2238 u8 reserved_at_10[0x3];
2240 u8 reserved_at_15[0x1];
2241 u8 req_e2e_credit_mode[0x2];
2242 u8 offload_type[0x4];
2243 u8 end_padding_mode[0x2];
2244 u8 reserved_at_1e[0x2];
2245 u8 wq_signature[0x1];
2246 u8 block_lb_mc[0x1];
2247 u8 atomic_like_write_en[0x1];
2248 u8 latency_sensitive[0x1];
2249 u8 reserved_at_24[0x1];
2250 u8 drain_sigerr[0x1];
2251 u8 reserved_at_26[0x2];
2254 u8 log_msg_max[0x5];
2255 u8 reserved_at_48[0x1];
2256 u8 log_rq_size[0x4];
2257 u8 log_rq_stride[0x3];
2259 u8 log_sq_size[0x4];
2260 u8 reserved_at_55[0x6];
2262 u8 ulp_stateless_offload_mode[0x4];
2263 u8 counter_set_id[0x8];
2265 u8 reserved_at_80[0x8];
2266 u8 user_index[0x18];
2267 u8 reserved_at_a0[0x3];
2268 u8 log_page_size[0x5];
2269 u8 remote_qpn[0x18];
2270 struct mlx5_ifc_ads_bits primary_address_path;
2271 struct mlx5_ifc_ads_bits secondary_address_path;
2272 u8 log_ack_req_freq[0x4];
2273 u8 reserved_at_384[0x4];
2274 u8 log_sra_max[0x3];
2275 u8 reserved_at_38b[0x2];
2276 u8 retry_count[0x3];
2278 u8 reserved_at_393[0x1];
2280 u8 cur_rnr_retry[0x3];
2281 u8 cur_retry_count[0x3];
2282 u8 reserved_at_39b[0x5];
2283 u8 reserved_at_3a0[0x20];
2284 u8 reserved_at_3c0[0x8];
2285 u8 next_send_psn[0x18];
2286 u8 reserved_at_3e0[0x8];
2288 u8 reserved_at_400[0x8];
2290 u8 reserved_at_420[0x20];
2291 u8 reserved_at_440[0x8];
2292 u8 last_acked_psn[0x18];
2293 u8 reserved_at_460[0x8];
2295 u8 reserved_at_480[0x8];
2296 u8 log_rra_max[0x3];
2297 u8 reserved_at_48b[0x1];
2298 u8 atomic_mode[0x4];
2302 u8 reserved_at_493[0x1];
2303 u8 page_offset[0x6];
2304 u8 reserved_at_49a[0x3];
2305 u8 cd_slave_receive[0x1];
2306 u8 cd_slave_send[0x1];
2308 u8 reserved_at_4a0[0x3];
2309 u8 min_rnr_nak[0x5];
2310 u8 next_rcv_psn[0x18];
2311 u8 reserved_at_4c0[0x8];
2313 u8 reserved_at_4e0[0x8];
2317 u8 reserved_at_560[0x5];
2319 u8 srqn_rmpn_xrqn[0x18];
2320 u8 reserved_at_580[0x8];
2322 u8 hw_sq_wqebb_counter[0x10];
2323 u8 sw_sq_wqebb_counter[0x10];
2324 u8 hw_rq_counter[0x20];
2325 u8 sw_rq_counter[0x20];
2326 u8 reserved_at_600[0x20];
2327 u8 reserved_at_620[0xf];
2331 u8 dc_access_key[0x40];
2332 u8 reserved_at_680[0x3];
2333 u8 dbr_umem_valid[0x1];
2334 u8 reserved_at_684[0x9c];
2335 u8 dbr_umem_id[0x20];
2338 struct mlx5_ifc_create_qp_out_bits {
2340 u8 reserved_at_8[0x18];
2342 u8 reserved_at_40[0x8];
2344 u8 reserved_at_60[0x20];
2348 #pragma GCC diagnostic ignored "-Wpedantic"
2350 struct mlx5_ifc_create_qp_in_bits {
2353 u8 reserved_at_20[0x10];
2355 u8 reserved_at_40[0x40];
2356 u8 opt_param_mask[0x20];
2357 u8 reserved_at_a0[0x20];
2358 struct mlx5_ifc_qpc_bits qpc;
2359 u8 wq_umem_offset[0x40];
2360 u8 wq_umem_id[0x20];
2361 u8 wq_umem_valid[0x1];
2362 u8 reserved_at_861[0x1f];
2366 #pragma GCC diagnostic error "-Wpedantic"
2369 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2371 u8 reserved_at_8[0x18];
2373 u8 reserved_at_40[0x40];
2376 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2379 u8 reserved_at_20[0x10];
2381 u8 reserved_at_40[0x8];
2383 u8 reserved_at_60[0x20];
2384 u8 opt_param_mask[0x20];
2385 u8 reserved_at_a0[0x20];
2386 struct mlx5_ifc_qpc_bits qpc;
2387 u8 reserved_at_800[0x80];
2390 struct mlx5_ifc_sqd2rts_qp_out_bits {
2392 u8 reserved_at_8[0x18];
2394 u8 reserved_at_40[0x40];
2397 struct mlx5_ifc_sqd2rts_qp_in_bits {
2400 u8 reserved_at_20[0x10];
2402 u8 reserved_at_40[0x8];
2404 u8 reserved_at_60[0x20];
2405 u8 opt_param_mask[0x20];
2406 u8 reserved_at_a0[0x20];
2407 struct mlx5_ifc_qpc_bits qpc;
2408 u8 reserved_at_800[0x80];
2411 struct mlx5_ifc_rts2rts_qp_out_bits {
2413 u8 reserved_at_8[0x18];
2415 u8 reserved_at_40[0x40];
2418 struct mlx5_ifc_rts2rts_qp_in_bits {
2421 u8 reserved_at_20[0x10];
2423 u8 reserved_at_40[0x8];
2425 u8 reserved_at_60[0x20];
2426 u8 opt_param_mask[0x20];
2427 u8 reserved_at_a0[0x20];
2428 struct mlx5_ifc_qpc_bits qpc;
2429 u8 reserved_at_800[0x80];
2432 struct mlx5_ifc_rtr2rts_qp_out_bits {
2434 u8 reserved_at_8[0x18];
2436 u8 reserved_at_40[0x40];
2439 struct mlx5_ifc_rtr2rts_qp_in_bits {
2442 u8 reserved_at_20[0x10];
2444 u8 reserved_at_40[0x8];
2446 u8 reserved_at_60[0x20];
2447 u8 opt_param_mask[0x20];
2448 u8 reserved_at_a0[0x20];
2449 struct mlx5_ifc_qpc_bits qpc;
2450 u8 reserved_at_800[0x80];
2453 struct mlx5_ifc_rst2init_qp_out_bits {
2455 u8 reserved_at_8[0x18];
2457 u8 reserved_at_40[0x40];
2460 struct mlx5_ifc_rst2init_qp_in_bits {
2463 u8 reserved_at_20[0x10];
2465 u8 reserved_at_40[0x8];
2467 u8 reserved_at_60[0x20];
2468 u8 opt_param_mask[0x20];
2469 u8 reserved_at_a0[0x20];
2470 struct mlx5_ifc_qpc_bits qpc;
2471 u8 reserved_at_800[0x80];
2474 struct mlx5_ifc_init2rtr_qp_out_bits {
2476 u8 reserved_at_8[0x18];
2478 u8 reserved_at_40[0x40];
2481 struct mlx5_ifc_init2rtr_qp_in_bits {
2484 u8 reserved_at_20[0x10];
2486 u8 reserved_at_40[0x8];
2488 u8 reserved_at_60[0x20];
2489 u8 opt_param_mask[0x20];
2490 u8 reserved_at_a0[0x20];
2491 struct mlx5_ifc_qpc_bits qpc;
2492 u8 reserved_at_800[0x80];
2495 struct mlx5_ifc_init2init_qp_out_bits {
2497 u8 reserved_at_8[0x18];
2499 u8 reserved_at_40[0x40];
2502 struct mlx5_ifc_init2init_qp_in_bits {
2505 u8 reserved_at_20[0x10];
2507 u8 reserved_at_40[0x8];
2509 u8 reserved_at_60[0x20];
2510 u8 opt_param_mask[0x20];
2511 u8 reserved_at_a0[0x20];
2512 struct mlx5_ifc_qpc_bits qpc;
2513 u8 reserved_at_800[0x80];
2517 #pragma GCC diagnostic ignored "-Wpedantic"
2519 struct mlx5_ifc_query_qp_out_bits {
2521 u8 reserved_at_8[0x18];
2523 u8 reserved_at_40[0x40];
2524 u8 opt_param_mask[0x20];
2525 u8 reserved_at_a0[0x20];
2526 struct mlx5_ifc_qpc_bits qpc;
2527 u8 reserved_at_800[0x80];
2531 #pragma GCC diagnostic error "-Wpedantic"
2534 struct mlx5_ifc_query_qp_in_bits {
2536 u8 reserved_at_10[0x10];
2537 u8 reserved_at_20[0x10];
2539 u8 reserved_at_40[0x8];
2541 u8 reserved_at_60[0x20];
2544 struct regexp_params_field_select_bits {
2545 u8 reserved_at_0[0x1e];
2546 u8 stop_engine[0x1];
2550 struct mlx5_ifc_regexp_params_bits {
2551 u8 reserved_at_0[0x1f];
2552 u8 stop_engine[0x1];
2553 u8 db_umem_id[0x20];
2554 u8 db_umem_offset[0x40];
2555 u8 reserved_at_80[0x100];
2558 struct mlx5_ifc_set_regexp_params_in_bits {
2561 u8 reserved_at_20[0x10];
2563 u8 reserved_at_40[0x18];
2565 struct regexp_params_field_select_bits field_select;
2566 struct mlx5_ifc_regexp_params_bits regexp_params;
2569 struct mlx5_ifc_set_regexp_params_out_bits {
2571 u8 reserved_at_8[0x18];
2573 u8 reserved_at_18[0x40];
2576 struct mlx5_ifc_query_regexp_params_in_bits {
2579 u8 reserved_at_20[0x10];
2581 u8 reserved_at_40[0x18];
2586 struct mlx5_ifc_query_regexp_params_out_bits {
2588 u8 reserved_at_8[0x18];
2591 struct mlx5_ifc_regexp_params_bits regexp_params;
2594 struct mlx5_ifc_set_regexp_register_in_bits {
2597 u8 reserved_at_20[0x10];
2599 u8 reserved_at_40[0x18];
2601 u8 register_address[0x20];
2602 u8 register_data[0x20];
2606 struct mlx5_ifc_set_regexp_register_out_bits {
2608 u8 reserved_at_8[0x18];
2613 struct mlx5_ifc_query_regexp_register_in_bits {
2616 u8 reserved_at_20[0x10];
2618 u8 reserved_at_40[0x18];
2620 u8 register_address[0x20];
2623 struct mlx5_ifc_query_regexp_register_out_bits {
2625 u8 reserved_at_8[0x18];
2628 u8 register_data[0x20];
2631 /* CQE format mask. */
2632 #define MLX5E_CQE_FORMAT_MASK 0xc
2635 #define MLX5_OPC_MOD_MPW 0x01
2637 /* Compressed Rx CQE structure. */
2638 struct mlx5_mini_cqe8 {
2640 uint32_t rx_hash_result;
2643 uint16_t stride_idx;
2646 uint16_t wqe_counter;
2647 uint8_t s_wqe_opcode;
2654 /* srTCM PRM flow meter parameters. */
2656 MLX5_FLOW_COLOR_RED = 0,
2657 MLX5_FLOW_COLOR_YELLOW,
2658 MLX5_FLOW_COLOR_GREEN,
2659 MLX5_FLOW_COLOR_UNDEFINED,
2662 /* Maximum value of srTCM metering parameters. */
2663 #define MLX5_SRTCM_CBS_MAX (0xFF * (1ULL << 0x1F))
2664 #define MLX5_SRTCM_CIR_MAX (8 * (1ULL << 30) * 0xFF)
2665 #define MLX5_SRTCM_EBS_MAX 0
2667 /* The bits meter color use. */
2668 #define MLX5_MTR_COLOR_BITS 8
2671 * Convert a user mark to flow mark.
2674 * Mark value to convert.
2677 * Converted mark value.
2679 static inline uint32_t
2680 mlx5_flow_mark_set(uint32_t val)
2685 * Add one to the user value to differentiate un-marked flows from
2686 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
2687 * remains untouched.
2689 if (val != MLX5_FLOW_MARK_DEFAULT)
2691 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
2693 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
2694 * word, byte-swapped by the kernel on little-endian systems. In this
2695 * case, left-shifting the resulting big-endian value ensures the
2696 * least significant 24 bits are retained when converting it back.
2698 ret = rte_cpu_to_be_32(val) >> 8;
2706 * Convert a mark to user mark.
2709 * Mark value to convert.
2712 * Converted mark value.
2714 static inline uint32_t
2715 mlx5_flow_mark_get(uint32_t val)
2718 * Subtract one from the retrieved value. It was added by
2719 * mlx5_flow_mark_set() to distinguish unmarked flows.
2721 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
2722 return (val >> 8) - 1;
2728 #endif /* RTE_PMD_MLX5_PRM_H_ */