drivers/common/mlx5/mlx5_prm.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2016 6WIND S.A.
   3  * Copyright 2016 Mellanox Technologies, Ltd
   4  */
   5
   6 #ifndef RTE_PMD_MLX5_PRM_H_
   7 #define RTE_PMD_MLX5_PRM_H_
   8
   9 #include <unistd.h>
  10
  11 #include <rte_vect.h>
  12 #include <rte_byteorder.h>
  13
  14 #include <mlx5_glue.h>
  15 #include "mlx5_autoconf.h"
  16
  17 /* RSS hash key size. */
  18 #define MLX5_RSS_HASH_KEY_LEN 40
  19
  20 /* Get CQE owner bit. */
  21 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
  22
  23 /* Get CQE format. */
  24 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
  25
  26 /* Get CQE opcode. */
  27 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
  28
  29 /* Get CQE solicited event. */
  30 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
  31
  32 /* Invalidate a CQE. */
  33 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
  34
  35 /* Hardware index widths. */
  36 #define MLX5_CQ_INDEX_WIDTH 24
  37 #define MLX5_WQ_INDEX_WIDTH 16
  38
  39 /* WQE Segment sizes in bytes. */
  40 #define MLX5_WSEG_SIZE 16u
  41 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
  42 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
  43 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
  44
  45 /* WQE/WQEBB size in bytes. */
  46 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
  47
  48 /*
  49  * Max size of a WQE session.
  50  * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
  51  * the WQE size field in Control Segment is 6 bits wide.
  52  */
  53 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
  54
  55 /*
  56  * Default minimum number of Tx queues for inlining packets.
  57  * If there are less queues as specified we assume we have
  58  * no enough CPU resources (cycles) to perform inlining,
  59  * the PCIe throughput is not supposed as bottleneck and
  60  * inlining is disabled.
  61  */
  62 #define MLX5_INLINE_MAX_TXQS 8u
  63 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
  64
  65 /*
  66  * Default packet length threshold to be inlined with
  67  * enhanced MPW. If packet length exceeds the threshold
  68  * the data are not inlined. Should be aligned in WQEBB
  69  * boundary with accounting the title Control and Ethernet
  70  * segments.
  71  */
  72 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
  73                                   MLX5_DSEG_MIN_INLINE_SIZE)
  74 /*
  75  * Maximal inline data length sent with enhanced MPW.
  76  * Is based on maximal WQE size.
  77  */
  78 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
  79                                   MLX5_WQE_CSEG_SIZE - \
  80                                   MLX5_WQE_ESEG_SIZE - \
  81                                   MLX5_WQE_DSEG_SIZE + \
  82                                   MLX5_DSEG_MIN_INLINE_SIZE)
  83 /*
  84  * Minimal amount of packets to be sent with EMPW.
  85  * This limits the minimal required size of sent EMPW.
  86  * If there are no enough resources to built minimal
  87  * EMPW the sending loop exits.
  88  */
  89 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
  90 /*
  91  * Maximal amount of packets to be sent with EMPW.
  92  * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
  93  * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
  94  * without CQE generation request, being multiplied by
  95  * MLX5_TX_COMP_MAX_CQE it may cause significant latency
  96  * in tx burst routine at the moment of freeing multiple mbufs.
  97  */
  98 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
  99 #define MLX5_MPW_MAX_PACKETS 6
 100 #define MLX5_MPW_INLINE_MAX_PACKETS 6
 101
 102 /*
 103  * Default packet length threshold to be inlined with
 104  * ordinary SEND. Inlining saves the MR key search
 105  * and extra PCIe data fetch transaction, but eats the
 106  * CPU cycles.
 107  */
 108 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
 109                                   MLX5_ESEG_MIN_INLINE_SIZE - \
 110                                   MLX5_WQE_CSEG_SIZE - \
 111                                   MLX5_WQE_ESEG_SIZE - \
 112                                   MLX5_WQE_DSEG_SIZE)
 113 /*
 114  * Maximal inline data length sent with ordinary SEND.
 115  * Is based on maximal WQE size.
 116  */
 117 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
 118                                   MLX5_WQE_CSEG_SIZE - \
 119                                   MLX5_WQE_ESEG_SIZE - \
 120                                   MLX5_WQE_DSEG_SIZE + \
 121                                   MLX5_ESEG_MIN_INLINE_SIZE)
 122
 123 /* Missed in mlx5dv.h, should define here. */
 124 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW
 125 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
 126 #endif
 127
 128 #ifndef HAVE_MLX5_OPCODE_SEND_EN
 129 #define MLX5_OPCODE_SEND_EN 0x17u
 130 #endif
 131
 132 #ifndef HAVE_MLX5_OPCODE_WAIT
 133 #define MLX5_OPCODE_WAIT 0x0fu
 134 #endif
 135
 136 #define MLX5_OPC_MOD_WAIT_CQ_PI 0u
 137 #define MLX5_OPC_MOD_WAIT_DATA 1u
 138 #define MLX5_OPC_MOD_WAIT_TIME 2u
 139
 140
 141 #define MLX5_WAIT_COND_INVERT 0x10u
 142 #define MLX5_WAIT_COND_ALWAYS_TRUE 0u
 143 #define MLX5_WAIT_COND_EQUAL 1u
 144 #define MLX5_WAIT_COND_BIGGER 2u
 145 #define MLX5_WAIT_COND_SMALLER 3u
 146 #define MLX5_WAIT_COND_CYCLIC_BIGGER 4u
 147 #define MLX5_WAIT_COND_CYCLIC_SMALLER 5u
 148
 149 #ifndef HAVE_MLX5_OPCODE_ACCESS_ASO
 150 #define MLX5_OPCODE_ACCESS_ASO 0x2du
 151 #endif
 152
 153 /* CQE value to inform that VLAN is stripped. */
 154 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
 155
 156 /* IPv4 options. */
 157 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
 158
 159 /* IPv6 packet. */
 160 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
 161
 162 /* IPv4 packet. */
 163 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
 164
 165 /* TCP packet. */
 166 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
 167
 168 /* UDP packet. */
 169 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
 170
 171 /* IP is fragmented. */
 172 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
 173
 174 /* L2 header is valid. */
 175 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
 176
 177 /* L3 header is valid. */
 178 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
 179
 180 /* L4 header is valid. */
 181 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
 182
 183 /* Outer packet, 0 IPv4, 1 IPv6. */
 184 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
 185
 186 /* Tunnel packet bit in the CQE. */
 187 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
 188
 189 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
 190 #define MLX5_CQE_LRO_PUSH_MASK 0x40
 191
 192 /* Mask for L4 type in the CQE hdr_type_etc field. */
 193 #define MLX5_CQE_L4_TYPE_MASK 0x70
 194
 195 /* The bit index of L4 type in CQE hdr_type_etc field. */
 196 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
 197
 198 /* L4 type to indicate TCP packet without acknowledgment. */
 199 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
 200
 201 /* L4 type to indicate TCP packet with acknowledgment. */
 202 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
 203
 204 /* Inner L3 checksum offload (Tunneled packets only). */
 205 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
 206
 207 /* Inner L4 checksum offload (Tunneled packets only). */
 208 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
 209
 210 /* Outer L4 type is TCP. */
 211 #define MLX5_ETH_WQE_L4_OUTER_TCP  (0u << 5)
 212
 213 /* Outer L4 type is UDP. */
 214 #define MLX5_ETH_WQE_L4_OUTER_UDP  (1u << 5)
 215
 216 /* Outer L3 type is IPV4. */
 217 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
 218
 219 /* Outer L3 type is IPV6. */
 220 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
 221
 222 /* Inner L4 type is TCP. */
 223 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
 224
 225 /* Inner L4 type is UDP. */
 226 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
 227
 228 /* Inner L3 type is IPV4. */
 229 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
 230
 231 /* Inner L3 type is IPV6. */
 232 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
 233
 234 /* VLAN insertion flag. */
 235 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
 236
 237 /* Data inline segment flag. */
 238 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
 239
 240 /* Is flow mark valid. */
 241 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
 242 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
 243 #else
 244 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
 245 #endif
 246
 247 /* INVALID is used by packets matching no flow rules. */
 248 #define MLX5_FLOW_MARK_INVALID 0
 249
 250 /* Maximum allowed value to mark a packet. */
 251 #define MLX5_FLOW_MARK_MAX 0xfffff0
 252
 253 /* Default mark value used when none is provided. */
 254 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
 255
 256 /* Default mark mask for metadata legacy mode. */
 257 #define MLX5_FLOW_MARK_MASK 0xffffff
 258
 259 /* Byte length mask when mark is enable in miniCQE */
 260 #define MLX5_LEN_WITH_MARK_MASK 0xffffff00
 261
 262 /* Maximum number of DS in WQE. Limited by 6-bit field. */
 263 #define MLX5_DSEG_MAX 63
 264
 265 /* The completion mode offset in the WQE control segment line 2. */
 266 #define MLX5_COMP_MODE_OFFSET 2
 267
 268 /* Amount of data bytes in minimal inline data segment. */
 269 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
 270
 271 /* Amount of data bytes in minimal inline eth segment. */
 272 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
 273
 274 /* Amount of data bytes after eth data segment. */
 275 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
 276
 277 /* The maximum log value of segments per RQ WQE. */
 278 #define MLX5_MAX_LOG_RQ_SEGS 5u
 279
 280 /* Log 2 of the default size of a WQE for Multi-Packet RQ. */
 281 #define MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE 14U
 282
 283 /* The alignment needed for WQ buffer. */
 284 #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size()
 285
 286 /* The alignment needed for CQ buffer. */
 287 #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size()
 288
 289 /* Completion mode. */
 290 enum mlx5_completion_mode {
 291         MLX5_COMP_ONLY_ERR = 0x0,
 292         MLX5_COMP_ONLY_FIRST_ERR = 0x1,
 293         MLX5_COMP_ALWAYS = 0x2,
 294         MLX5_COMP_CQE_AND_EQE = 0x3,
 295 };
 296
 297 /* MPW mode. */
 298 enum mlx5_mpw_mode {
 299         MLX5_MPW_DISABLED,
 300         MLX5_MPW,
 301         MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
 302 };
 303
 304 /* WQE Control segment. */
 305 struct mlx5_wqe_cseg {
 306         uint32_t opcode;
 307         uint32_t sq_ds;
 308         uint32_t flags;
 309         uint32_t misc;
 310 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
 311
 312 /*
 313  * WQE CSEG opcode field size is 32 bits, divided:
 314  * Bits 31:24 OPC_MOD
 315  * Bits 23:8 wqe_index
 316  * Bits 7:0 OPCODE
 317  */
 318 #define WQE_CSEG_OPC_MOD_OFFSET         24
 319 #define WQE_CSEG_WQE_INDEX_OFFSET        8
 320
 321 /* Header of data segment. Minimal size Data Segment */
 322 struct mlx5_wqe_dseg {
 323         uint32_t bcount;
 324         union {
 325                 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
 326                 struct {
 327                         uint32_t lkey;
 328                         uint64_t pbuf;
 329                 } __rte_packed;
 330         };
 331 } __rte_packed;
 332
 333 /* Subset of struct WQE Ethernet Segment. */
 334 struct mlx5_wqe_eseg {
 335         union {
 336                 struct {
 337                         uint32_t swp_offs;
 338                         uint8_t cs_flags;
 339                         uint8_t swp_flags;
 340                         uint16_t mss;
 341                         uint32_t metadata;
 342                         uint16_t inline_hdr_sz;
 343                         union {
 344                                 uint16_t inline_data;
 345                                 uint16_t vlan_tag;
 346                         };
 347                 } __rte_packed;
 348                 struct {
 349                         uint32_t offsets;
 350                         uint32_t flags;
 351                         uint32_t flow_metadata;
 352                         uint32_t inline_hdr;
 353                 } __rte_packed;
 354         };
 355 } __rte_packed;
 356
 357 struct mlx5_wqe_qseg {
 358         uint32_t reserved0;
 359         uint32_t reserved1;
 360         uint32_t max_index;
 361         uint32_t qpn_cqn;
 362 } __rte_packed;
 363
 364 struct mlx5_wqe_wseg {
 365         uint32_t operation;
 366         uint32_t lkey;
 367         uint32_t va_high;
 368         uint32_t va_low;
 369         uint64_t value;
 370         uint64_t mask;
 371 } __rte_packed;
 372
 373 /* The title WQEBB, header of WQE. */
 374 struct mlx5_wqe {
 375         union {
 376                 struct mlx5_wqe_cseg cseg;
 377                 uint32_t ctrl[4];
 378         };
 379         struct mlx5_wqe_eseg eseg;
 380         union {
 381                 struct mlx5_wqe_dseg dseg[2];
 382                 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
 383         };
 384 } __rte_packed;
 385
 386 /* WQE for Multi-Packet RQ. */
 387 struct mlx5_wqe_mprq {
 388         struct mlx5_wqe_srq_next_seg next_seg;
 389         struct mlx5_wqe_data_seg dseg;
 390 };
 391
 392 #define MLX5_MPRQ_LEN_MASK 0x000ffff
 393 #define MLX5_MPRQ_LEN_SHIFT 0
 394 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
 395 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
 396 #define MLX5_MPRQ_FILLER_MASK 0x80000000
 397 #define MLX5_MPRQ_FILLER_SHIFT 31
 398
 399 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
 400
 401 /* CQ element structure - should be equal to the cache line size */
 402 struct mlx5_cqe {
 403 #if (RTE_CACHE_LINE_SIZE == 128)
 404         uint8_t padding[64];
 405 #endif
 406         uint8_t pkt_info;
 407         uint8_t rsvd0;
 408         uint16_t wqe_id;
 409         uint8_t lro_tcppsh_abort_dupack;
 410         uint8_t lro_min_ttl;
 411         uint16_t lro_tcp_win;
 412         uint32_t lro_ack_seq_num;
 413         uint32_t rx_hash_res;
 414         uint8_t rx_hash_type;
 415         uint8_t rsvd1[3];
 416         uint16_t csum;
 417         uint8_t rsvd2[6];
 418         uint16_t hdr_type_etc;
 419         uint16_t vlan_info;
 420         uint8_t lro_num_seg;
 421         union {
 422                 uint8_t user_index_bytes[3];
 423                 struct {
 424                         uint8_t user_index_hi;
 425                         uint16_t user_index_low;
 426                 } __rte_packed;
 427         };
 428         uint32_t flow_table_metadata;
 429         uint8_t rsvd4[4];
 430         uint32_t byte_cnt;
 431         uint64_t timestamp;
 432         uint32_t sop_drop_qpn;
 433         uint16_t wqe_counter;
 434         uint8_t rsvd5;
 435         uint8_t op_own;
 436 };
 437
 438 struct mlx5_cqe_ts {
 439         uint64_t timestamp;
 440         uint32_t sop_drop_qpn;
 441         uint16_t wqe_counter;
 442         uint8_t rsvd5;
 443         uint8_t op_own;
 444 };
 445
 446 struct mlx5_wqe_rseg {
 447         uint64_t raddr;
 448         uint32_t rkey;
 449         uint32_t reserved;
 450 } __rte_packed;
 451
 452 #define MLX5_UMRC_IF_OFFSET 31u
 453 #define MLX5_UMRC_KO_OFFSET 16u
 454 #define MLX5_UMRC_TO_BS_OFFSET 0u
 455
 456 struct mlx5_wqe_umr_cseg {
 457         uint32_t if_cf_toe_cq_res;
 458         uint32_t ko_to_bs;
 459         uint64_t mkey_mask;
 460         uint32_t rsvd1[8];
 461 } __rte_packed;
 462
 463 struct mlx5_wqe_mkey_cseg {
 464         uint32_t fr_res_af_sf;
 465         uint32_t qpn_mkey;
 466         uint32_t reserved2;
 467         uint32_t flags_pd;
 468         uint64_t start_addr;
 469         uint64_t len;
 470         uint32_t bsf_octword_size;
 471         uint32_t reserved3[4];
 472         uint32_t translations_octword_size;
 473         uint32_t res4_lps;
 474         uint32_t reserved;
 475 } __rte_packed;
 476
 477 enum {
 478         MLX5_BSF_SIZE_16B = 0x0,
 479         MLX5_BSF_SIZE_32B = 0x1,
 480         MLX5_BSF_SIZE_64B = 0x2,
 481         MLX5_BSF_SIZE_128B = 0x3,
 482 };
 483
 484 enum {
 485         MLX5_BSF_P_TYPE_SIGNATURE = 0x0,
 486         MLX5_BSF_P_TYPE_CRYPTO = 0x1,
 487 };
 488
 489 enum {
 490         MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0,
 491         MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1,
 492         MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2,
 493         MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3,
 494 };
 495
 496 enum {
 497         MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0,
 498 };
 499
 500 enum {
 501         MLX5_BLOCK_SIZE_512B    = 0x1,
 502         MLX5_BLOCK_SIZE_520B    = 0x2,
 503         MLX5_BLOCK_SIZE_4096B   = 0x3,
 504         MLX5_BLOCK_SIZE_4160B   = 0x4,
 505         MLX5_BLOCK_SIZE_1MB     = 0x5,
 506         MLX5_BLOCK_SIZE_4048B   = 0x6,
 507 };
 508
 509 #define MLX5_BSF_SIZE_OFFSET            30
 510 #define MLX5_BSF_P_TYPE_OFFSET          24
 511 #define MLX5_ENCRYPTION_ORDER_OFFSET    16
 512 #define MLX5_BLOCK_SIZE_OFFSET          24
 513
 514 struct mlx5_wqe_umr_bsf_seg {
 515         /*
 516          * bs_bpt_eo_es contains:
 517          * bs   bsf_size                2 bits at MLX5_BSF_SIZE_OFFSET
 518          * bpt  bsf_p_type              2 bits at MLX5_BSF_P_TYPE_OFFSET
 519          * eo   encryption_order        4 bits at MLX5_ENCRYPTION_ORDER_OFFSET
 520          * es   encryption_standard     4 bits at offset 0
 521          */
 522         uint32_t bs_bpt_eo_es;
 523         uint32_t raw_data_size;
 524         /*
 525          * bsp_res contains:
 526          * bsp  crypto_block_size_pointer       8 bits at MLX5_BLOCK_SIZE_OFFSET
 527          * res  reserved 24 bits
 528          */
 529         uint32_t bsp_res;
 530         uint32_t reserved0;
 531         uint8_t xts_initial_tweak[16];
 532         /*
 533          * res_dp contains:
 534          * res  reserved 8 bits
 535          * dp   dek_pointer             24 bits at offset 0
 536          */
 537         uint32_t res_dp;
 538         uint32_t reserved1;
 539         uint64_t keytag;
 540         uint32_t reserved2[4];
 541 } __rte_packed;
 542
 543 #ifdef PEDANTIC
 544 #pragma GCC diagnostic ignored "-Wpedantic"
 545 #endif
 546
 547 struct mlx5_umr_wqe {
 548         struct mlx5_wqe_cseg ctr;
 549         struct mlx5_wqe_umr_cseg ucseg;
 550         struct mlx5_wqe_mkey_cseg mkc;
 551         union {
 552                 struct mlx5_wqe_dseg kseg[0];
 553                 struct mlx5_wqe_umr_bsf_seg bsf[0];
 554         };
 555 } __rte_packed;
 556
 557 struct mlx5_rdma_write_wqe {
 558         struct mlx5_wqe_cseg ctr;
 559         struct mlx5_wqe_rseg rseg;
 560         struct mlx5_wqe_dseg dseg[0];
 561 } __rte_packed;
 562
 563 #ifdef PEDANTIC
 564 #pragma GCC diagnostic error "-Wpedantic"
 565 #endif
 566
 567 /* GGA */
 568 /* MMO metadata segment */
 569
 570 #define MLX5_OPCODE_MMO 0x2fu
 571 #define MLX5_OPC_MOD_MMO_REGEX 0x4u
 572 #define MLX5_OPC_MOD_MMO_COMP 0x2u
 573 #define MLX5_OPC_MOD_MMO_DECOMP 0x3u
 574 #define MLX5_OPC_MOD_MMO_DMA 0x1u
 575
 576 #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u
 577 #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u
 578 #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u
 579 #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u
 580 #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS)
 581 #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u
 582 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u
 583 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u
 584
 585 struct mlx5_wqe_metadata_seg {
 586         uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */
 587         uint32_t lkey;
 588         uint64_t addr;
 589 };
 590
 591 struct mlx5_gga_wqe {
 592         uint32_t opcode;
 593         uint32_t sq_ds;
 594         uint32_t flags;
 595         uint32_t gga_ctrl1;  /* ws 12-15, bs 16-19, dyns 20-23. */
 596         uint32_t gga_ctrl2;
 597         uint32_t opaque_lkey;
 598         uint64_t opaque_vaddr;
 599         struct mlx5_wqe_dseg gather;
 600         struct mlx5_wqe_dseg scatter;
 601 } __rte_packed;
 602
 603 struct mlx5_gga_compress_opaque {
 604         uint32_t syndrom;
 605         uint32_t reserved0;
 606         uint32_t scattered_length;
 607         uint32_t gathered_length;
 608         uint64_t scatter_crc;
 609         uint64_t gather_crc;
 610         uint32_t crc32;
 611         uint32_t adler32;
 612         uint8_t reserved1[216];
 613 } __rte_packed;
 614
 615 struct mlx5_ifc_regexp_mmo_control_bits {
 616         uint8_t reserved_at_31[0x2];
 617         uint8_t le[0x1];
 618         uint8_t reserved_at_28[0x1];
 619         uint8_t subset_id_0[0xc];
 620         uint8_t reserved_at_16[0x4];
 621         uint8_t subset_id_1[0xc];
 622         uint8_t ctrl[0x4];
 623         uint8_t subset_id_2[0xc];
 624         uint8_t reserved_at_16_1[0x4];
 625         uint8_t subset_id_3[0xc];
 626 };
 627
 628 struct mlx5_ifc_regexp_metadata_bits {
 629         uint8_t rof_version[0x10];
 630         uint8_t latency_count[0x10];
 631         uint8_t instruction_count[0x10];
 632         uint8_t primary_thread_count[0x10];
 633         uint8_t match_count[0x8];
 634         uint8_t detected_match_count[0x8];
 635         uint8_t status[0x10];
 636         uint8_t job_id[0x20];
 637         uint8_t reserved[0x80];
 638 };
 639
 640 struct mlx5_ifc_regexp_match_tuple_bits {
 641         uint8_t length[0x10];
 642         uint8_t start_ptr[0x10];
 643         uint8_t rule_id[0x20];
 644 };
 645
 646 /* Adding direct verbs to data-path. */
 647
 648 /* CQ sequence number mask. */
 649 #define MLX5_CQ_SQN_MASK 0x3
 650
 651 /* CQ sequence number index. */
 652 #define MLX5_CQ_SQN_OFFSET 28
 653
 654 /* CQ doorbell index mask. */
 655 #define MLX5_CI_MASK 0xffffff
 656
 657 /* CQ doorbell offset. */
 658 #define MLX5_CQ_ARM_DB 1
 659
 660 /* CQ doorbell offset*/
 661 #define MLX5_CQ_DOORBELL 0x20
 662
 663 /* CQE format value. */
 664 #define MLX5_COMPRESSED 0x3
 665
 666 /* CQ doorbell cmd types. */
 667 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24)
 668 #define MLX5_CQ_DBR_CMD_ALL (0 << 24)
 669
 670 /* Action type of header modification. */
 671 enum {
 672         MLX5_MODIFICATION_TYPE_SET = 0x1,
 673         MLX5_MODIFICATION_TYPE_ADD = 0x2,
 674         MLX5_MODIFICATION_TYPE_COPY = 0x3,
 675 };
 676
 677 /* The field of packet to be modified. */
 678 enum mlx5_modification_field {
 679         MLX5_MODI_OUT_NONE = -1,
 680         MLX5_MODI_OUT_SMAC_47_16 = 1,
 681         MLX5_MODI_OUT_SMAC_15_0,
 682         MLX5_MODI_OUT_ETHERTYPE,
 683         MLX5_MODI_OUT_DMAC_47_16,
 684         MLX5_MODI_OUT_DMAC_15_0,
 685         MLX5_MODI_OUT_IP_DSCP,
 686         MLX5_MODI_OUT_TCP_FLAGS,
 687         MLX5_MODI_OUT_TCP_SPORT,
 688         MLX5_MODI_OUT_TCP_DPORT,
 689         MLX5_MODI_OUT_IPV4_TTL,
 690         MLX5_MODI_OUT_UDP_SPORT,
 691         MLX5_MODI_OUT_UDP_DPORT,
 692         MLX5_MODI_OUT_SIPV6_127_96,
 693         MLX5_MODI_OUT_SIPV6_95_64,
 694         MLX5_MODI_OUT_SIPV6_63_32,
 695         MLX5_MODI_OUT_SIPV6_31_0,
 696         MLX5_MODI_OUT_DIPV6_127_96,
 697         MLX5_MODI_OUT_DIPV6_95_64,
 698         MLX5_MODI_OUT_DIPV6_63_32,
 699         MLX5_MODI_OUT_DIPV6_31_0,
 700         MLX5_MODI_OUT_SIPV4,
 701         MLX5_MODI_OUT_DIPV4,
 702         MLX5_MODI_OUT_FIRST_VID,
 703         MLX5_MODI_IN_SMAC_47_16 = 0x31,
 704         MLX5_MODI_IN_SMAC_15_0,
 705         MLX5_MODI_IN_ETHERTYPE,
 706         MLX5_MODI_IN_DMAC_47_16,
 707         MLX5_MODI_IN_DMAC_15_0,
 708         MLX5_MODI_IN_IP_DSCP,
 709         MLX5_MODI_IN_TCP_FLAGS,
 710         MLX5_MODI_IN_TCP_SPORT,
 711         MLX5_MODI_IN_TCP_DPORT,
 712         MLX5_MODI_IN_IPV4_TTL,
 713         MLX5_MODI_IN_UDP_SPORT,
 714         MLX5_MODI_IN_UDP_DPORT,
 715         MLX5_MODI_IN_SIPV6_127_96,
 716         MLX5_MODI_IN_SIPV6_95_64,
 717         MLX5_MODI_IN_SIPV6_63_32,
 718         MLX5_MODI_IN_SIPV6_31_0,
 719         MLX5_MODI_IN_DIPV6_127_96,
 720         MLX5_MODI_IN_DIPV6_95_64,
 721         MLX5_MODI_IN_DIPV6_63_32,
 722         MLX5_MODI_IN_DIPV6_31_0,
 723         MLX5_MODI_IN_SIPV4,
 724         MLX5_MODI_IN_DIPV4,
 725         MLX5_MODI_OUT_IPV6_HOPLIMIT,
 726         MLX5_MODI_IN_IPV6_HOPLIMIT,
 727         MLX5_MODI_META_DATA_REG_A,
 728         MLX5_MODI_META_DATA_REG_B = 0x50,
 729         MLX5_MODI_META_REG_C_0,
 730         MLX5_MODI_META_REG_C_1,
 731         MLX5_MODI_META_REG_C_2,
 732         MLX5_MODI_META_REG_C_3,
 733         MLX5_MODI_META_REG_C_4,
 734         MLX5_MODI_META_REG_C_5,
 735         MLX5_MODI_META_REG_C_6,
 736         MLX5_MODI_META_REG_C_7,
 737         MLX5_MODI_OUT_TCP_SEQ_NUM,
 738         MLX5_MODI_IN_TCP_SEQ_NUM,
 739         MLX5_MODI_OUT_TCP_ACK_NUM,
 740         MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
 741         MLX5_MODI_GTP_TEID = 0x6E,
 742 };
 743
 744 /* Total number of metadata reg_c's. */
 745 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1)
 746
 747 enum modify_reg {
 748         REG_NON = 0,
 749         REG_A,
 750         REG_B,
 751         REG_C_0,
 752         REG_C_1,
 753         REG_C_2,
 754         REG_C_3,
 755         REG_C_4,
 756         REG_C_5,
 757         REG_C_6,
 758         REG_C_7,
 759 };
 760
 761 /* Modification sub command. */
 762 struct mlx5_modification_cmd {
 763         union {
 764                 uint32_t data0;
 765                 struct {
 766                         unsigned int length:5;
 767                         unsigned int rsvd0:3;
 768                         unsigned int offset:5;
 769                         unsigned int rsvd1:3;
 770                         unsigned int field:12;
 771                         unsigned int action_type:4;
 772                 };
 773         };
 774         union {
 775                 uint32_t data1;
 776                 uint8_t data[4];
 777                 struct {
 778                         unsigned int rsvd2:8;
 779                         unsigned int dst_offset:5;
 780                         unsigned int rsvd3:3;
 781                         unsigned int dst_field:12;
 782                         unsigned int rsvd4:4;
 783                 };
 784         };
 785 };
 786
 787 typedef uint64_t u64;
 788 typedef uint32_t u32;
 789 typedef uint16_t u16;
 790 typedef uint8_t u8;
 791
 792 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
 793 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
 794 #define __mlx5_bit_off(typ, fld) ((unsigned int)(uintptr_t) \
 795                                   (&(__mlx5_nullp(typ)->fld)))
 796 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
 797                                     (__mlx5_bit_off(typ, fld) & 0x1f))
 798 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
 799 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
 800 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
 801                                   __mlx5_dw_bit_off(typ, fld))
 802 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
 803 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
 804 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
 805                                     (__mlx5_bit_off(typ, fld) & 0xf))
 806 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
 807 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \
 808                                   __mlx5_16_bit_off(typ, fld))
 809 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
 810 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
 811 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
 812 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
 813
 814 /* insert a value to a struct */
 815 #define MLX5_SET(typ, p, fld, v) \
 816         do { \
 817                 u32 _v = v; \
 818                 *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \
 819                 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
 820                                   __mlx5_dw_off(typ, fld))) & \
 821                                   (~__mlx5_dw_mask(typ, fld))) | \
 822                                  (((_v) & __mlx5_mask(typ, fld)) << \
 823                                    __mlx5_dw_bit_off(typ, fld))); \
 824         } while (0)
 825
 826 #define MLX5_SET64(typ, p, fld, v) \
 827         do { \
 828                 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \
 829                 *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \
 830                         rte_cpu_to_be_64(v); \
 831         } while (0)
 832
 833 #define MLX5_SET16(typ, p, fld, v) \
 834         do { \
 835                 u16 _v = v; \
 836                 *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \
 837                 rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
 838                                   __mlx5_16_off(typ, fld))) & \
 839                                   (~__mlx5_16_mask(typ, fld))) | \
 840                                  (((_v) & __mlx5_mask16(typ, fld)) << \
 841                                   __mlx5_16_bit_off(typ, fld))); \
 842         } while (0)
 843
 844 #define MLX5_GET_VOLATILE(typ, p, fld) \
 845         ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\
 846         __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
 847         __mlx5_mask(typ, fld))
 848 #define MLX5_GET(typ, p, fld) \
 849         ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\
 850         __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
 851         __mlx5_mask(typ, fld))
 852 #define MLX5_GET16(typ, p, fld) \
 853         ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
 854           __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
 855          __mlx5_mask16(typ, fld))
 856 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \
 857                                                    __mlx5_64_off(typ, fld)))
 858 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
 859 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
 860
 861 struct mlx5_ifc_fte_match_set_misc_bits {
 862         u8 gre_c_present[0x1];
 863         u8 reserved_at_1[0x1];
 864         u8 gre_k_present[0x1];
 865         u8 gre_s_present[0x1];
 866         u8 source_vhci_port[0x4];
 867         u8 source_sqn[0x18];
 868         u8 reserved_at_20[0x10];
 869         u8 source_port[0x10];
 870         u8 outer_second_prio[0x3];
 871         u8 outer_second_cfi[0x1];
 872         u8 outer_second_vid[0xc];
 873         u8 inner_second_prio[0x3];
 874         u8 inner_second_cfi[0x1];
 875         u8 inner_second_vid[0xc];
 876         u8 outer_second_cvlan_tag[0x1];
 877         u8 inner_second_cvlan_tag[0x1];
 878         u8 outer_second_svlan_tag[0x1];
 879         u8 inner_second_svlan_tag[0x1];
 880         u8 reserved_at_64[0xc];
 881         u8 gre_protocol[0x10];
 882         u8 gre_key_h[0x18];
 883         u8 gre_key_l[0x8];
 884         u8 vxlan_vni[0x18];
 885         u8 reserved_at_b8[0x8];
 886         u8 geneve_vni[0x18];
 887         u8 reserved_at_e4[0x6];
 888         u8 geneve_tlv_option_0_exist[0x1];
 889         u8 geneve_oam[0x1];
 890         u8 reserved_at_e0[0xc];
 891         u8 outer_ipv6_flow_label[0x14];
 892         u8 reserved_at_100[0xc];
 893         u8 inner_ipv6_flow_label[0x14];
 894         u8 reserved_at_120[0xa];
 895         u8 geneve_opt_len[0x6];
 896         u8 geneve_protocol_type[0x10];
 897         u8 reserved_at_140[0xc0];
 898 };
 899
 900 struct mlx5_ifc_ipv4_layout_bits {
 901         u8 reserved_at_0[0x60];
 902         u8 ipv4[0x20];
 903 };
 904
 905 struct mlx5_ifc_ipv6_layout_bits {
 906         u8 ipv6[16][0x8];
 907 };
 908
 909 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 910         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 911         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 912         u8 reserved_at_0[0x80];
 913 };
 914
 915 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 916         u8 smac_47_16[0x20];
 917         u8 smac_15_0[0x10];
 918         u8 ethertype[0x10];
 919         u8 dmac_47_16[0x20];
 920         u8 dmac_15_0[0x10];
 921         u8 first_prio[0x3];
 922         u8 first_cfi[0x1];
 923         u8 first_vid[0xc];
 924         u8 ip_protocol[0x8];
 925         u8 ip_dscp[0x6];
 926         u8 ip_ecn[0x2];
 927         u8 cvlan_tag[0x1];
 928         u8 svlan_tag[0x1];
 929         u8 frag[0x1];
 930         u8 ip_version[0x4];
 931         u8 tcp_flags[0x9];
 932         u8 tcp_sport[0x10];
 933         u8 tcp_dport[0x10];
 934         u8 reserved_at_c0[0x10];
 935         u8 ipv4_ihl[0x4];
 936         u8 l3_ok[0x1];
 937         u8 l4_ok[0x1];
 938         u8 ipv4_checksum_ok[0x1];
 939         u8 l4_checksum_ok[0x1];
 940         u8 ip_ttl_hoplimit[0x8];
 941         u8 udp_sport[0x10];
 942         u8 udp_dport[0x10];
 943         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 944         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 945 };
 946
 947 struct mlx5_ifc_fte_match_mpls_bits {
 948         u8 mpls_label[0x14];
 949         u8 mpls_exp[0x3];
 950         u8 mpls_s_bos[0x1];
 951         u8 mpls_ttl[0x8];
 952 };
 953
 954 struct mlx5_ifc_fte_match_set_misc2_bits {
 955         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 956         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 957         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 958         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 959         u8 metadata_reg_c_7[0x20];
 960         u8 metadata_reg_c_6[0x20];
 961         u8 metadata_reg_c_5[0x20];
 962         u8 metadata_reg_c_4[0x20];
 963         u8 metadata_reg_c_3[0x20];
 964         u8 metadata_reg_c_2[0x20];
 965         u8 metadata_reg_c_1[0x20];
 966         u8 metadata_reg_c_0[0x20];
 967         u8 metadata_reg_a[0x20];
 968         u8 metadata_reg_b[0x20];
 969         u8 reserved_at_1c0[0x40];
 970 };
 971
 972 struct mlx5_ifc_fte_match_set_misc3_bits {
 973         u8 inner_tcp_seq_num[0x20];
 974         u8 outer_tcp_seq_num[0x20];
 975         u8 inner_tcp_ack_num[0x20];
 976         u8 outer_tcp_ack_num[0x20];
 977         u8 reserved_at_auto1[0x8];
 978         u8 outer_vxlan_gpe_vni[0x18];
 979         u8 outer_vxlan_gpe_next_protocol[0x8];
 980         u8 outer_vxlan_gpe_flags[0x8];
 981         u8 reserved_at_a8[0x10];
 982         u8 icmp_header_data[0x20];
 983         u8 icmpv6_header_data[0x20];
 984         u8 icmp_type[0x8];
 985         u8 icmp_code[0x8];
 986         u8 icmpv6_type[0x8];
 987         u8 icmpv6_code[0x8];
 988         u8 geneve_tlv_option_0_data[0x20];
 989         u8 gtpu_teid[0x20];
 990         u8 gtpu_msg_type[0x08];
 991         u8 gtpu_msg_flags[0x08];
 992         u8 reserved_at_170[0x10];
 993         u8 gtpu_dw_2[0x20];
 994         u8 gtpu_first_ext_dw_0[0x20];
 995         u8 gtpu_dw_0[0x20];
 996         u8 reserved_at_240[0x20];
 997
 998 };
 999
1000 struct mlx5_ifc_fte_match_set_misc4_bits {
1001         u8 prog_sample_field_value_0[0x20];
1002         u8 prog_sample_field_id_0[0x20];
1003         u8 prog_sample_field_value_1[0x20];
1004         u8 prog_sample_field_id_1[0x20];
1005         u8 prog_sample_field_value_2[0x20];
1006         u8 prog_sample_field_id_2[0x20];
1007         u8 prog_sample_field_value_3[0x20];
1008         u8 prog_sample_field_id_3[0x20];
1009         u8 prog_sample_field_value_4[0x20];
1010         u8 prog_sample_field_id_4[0x20];
1011         u8 prog_sample_field_value_5[0x20];
1012         u8 prog_sample_field_id_5[0x20];
1013         u8 prog_sample_field_value_6[0x20];
1014         u8 prog_sample_field_id_6[0x20];
1015         u8 prog_sample_field_value_7[0x20];
1016         u8 prog_sample_field_id_7[0x20];
1017 };
1018
1019 struct mlx5_ifc_fte_match_set_misc5_bits {
1020         u8 macsec_tag_0[0x20];
1021         u8 macsec_tag_1[0x20];
1022         u8 macsec_tag_2[0x20];
1023         u8 macsec_tag_3[0x20];
1024         u8 tunnel_header_0[0x20];
1025         u8 tunnel_header_1[0x20];
1026         u8 tunnel_header_2[0x20];
1027         u8 tunnel_header_3[0x20];
1028         u8 reserved[0x100];
1029 };
1030
1031 /* Flow matcher. */
1032 struct mlx5_ifc_fte_match_param_bits {
1033         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1034         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1035         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1036         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1037         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1038         struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1039         struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
1040 /*
1041  * Add reserved bit to match the struct size with the size defined in PRM.
1042  * This extension is not required in Linux.
1043  */
1044 #ifndef HAVE_INFINIBAND_VERBS_H
1045         u8 reserved_0[0x200];
1046 #endif
1047 };
1048
1049 struct mlx5_ifc_dest_format_struct_bits {
1050         u8 destination_type[0x8];
1051         u8 destination_id[0x18];
1052         u8 reserved_0[0x20];
1053 };
1054
1055 enum {
1056         MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
1057         MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
1058         MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
1059         MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
1060         MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT,
1061         MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT,
1062         MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT,
1063 };
1064
1065 enum {
1066         MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
1067         MLX5_CMD_OP_CREATE_MKEY = 0x200,
1068         MLX5_CMD_OP_CREATE_CQ = 0x400,
1069         MLX5_CMD_OP_CREATE_QP = 0x500,
1070         MLX5_CMD_OP_RST2INIT_QP = 0x502,
1071         MLX5_CMD_OP_INIT2RTR_QP = 0x503,
1072         MLX5_CMD_OP_RTR2RTS_QP = 0x504,
1073         MLX5_CMD_OP_RTS2RTS_QP = 0x505,
1074         MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
1075         MLX5_CMD_OP_QP_2ERR = 0x507,
1076         MLX5_CMD_OP_QP_2RST = 0x50A,
1077         MLX5_CMD_OP_QUERY_QP = 0x50B,
1078         MLX5_CMD_OP_SQD2RTS_QP = 0x50C,
1079         MLX5_CMD_OP_INIT2INIT_QP = 0x50E,
1080         MLX5_CMD_OP_SUSPEND_QP = 0x50F,
1081         MLX5_CMD_OP_RESUME_QP = 0x510,
1082         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
1083         MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
1084         MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
1085         MLX5_CMD_OP_ALLOC_PD = 0x800,
1086         MLX5_CMD_OP_DEALLOC_PD = 0x801,
1087         MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
1088         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
1089         MLX5_CMD_OP_QUERY_LAG = 0x842,
1090         MLX5_CMD_OP_CREATE_TIR = 0x900,
1091         MLX5_CMD_OP_MODIFY_TIR = 0x901,
1092         MLX5_CMD_OP_CREATE_SQ = 0X904,
1093         MLX5_CMD_OP_MODIFY_SQ = 0X905,
1094         MLX5_CMD_OP_CREATE_RQ = 0x908,
1095         MLX5_CMD_OP_MODIFY_RQ = 0x909,
1096         MLX5_CMD_OP_QUERY_RQ = 0x90b,
1097         MLX5_CMD_OP_CREATE_RMP = 0x90c,
1098         MLX5_CMD_OP_MODIFY_RMP = 0x90d,
1099         MLX5_CMD_OP_DESTROY_RMP = 0x90e,
1100         MLX5_CMD_OP_QUERY_RMP = 0x90f,
1101         MLX5_CMD_OP_CREATE_TIS = 0x912,
1102         MLX5_CMD_OP_QUERY_TIS = 0x915,
1103         MLX5_CMD_OP_CREATE_RQT = 0x916,
1104         MLX5_CMD_OP_MODIFY_RQT = 0x917,
1105         MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
1106         MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
1107         MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
1108         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
1109         MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
1110         MLX5_CMD_SET_REGEX_PARAMS = 0xb04,
1111         MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,
1112         MLX5_CMD_SET_REGEX_REGISTERS = 0xb06,
1113         MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
1114         MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c,
1115 };
1116
1117 enum {
1118         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
1119         MLX5_MKC_ACCESS_MODE_KLM   = 0x2,
1120         MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3,
1121 };
1122
1123 #define MLX5_ADAPTER_PAGE_SHIFT 12
1124 #define MLX5_LOG_RQ_STRIDE_SHIFT 4
1125 /**
1126  * The batch counter dcs id starts from 0x800000 and none batch counter
1127  * starts from 0. As currently, the counter is changed to be indexed by
1128  * pool index and the offset of the counter in the pool counters_raw array.
1129  * It means now the counter index is same for batch and none batch counter.
1130  * Add the 0x800000 batch counter offset to the batch counter index helps
1131  * indicate the counter index is from batch or none batch container pool.
1132  */
1133 #define MLX5_CNT_BATCH_OFFSET 0x800000
1134
1135 /* The counter batch query requires ID align with 4. */
1136 #define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4
1137
1138 /* Flow counters. */
1139 struct mlx5_ifc_alloc_flow_counter_out_bits {
1140         u8 status[0x8];
1141         u8 reserved_at_8[0x18];
1142         u8 syndrome[0x20];
1143         u8 flow_counter_id[0x20];
1144         u8 reserved_at_60[0x20];
1145 };
1146
1147 struct mlx5_ifc_alloc_flow_counter_in_bits {
1148         u8 opcode[0x10];
1149         u8 reserved_at_10[0x10];
1150         u8 reserved_at_20[0x10];
1151         u8 op_mod[0x10];
1152         u8 flow_counter_id[0x20];
1153         u8 reserved_at_40[0x18];
1154         u8 flow_counter_bulk[0x8];
1155 };
1156
1157 struct mlx5_ifc_dealloc_flow_counter_out_bits {
1158         u8 status[0x8];
1159         u8 reserved_at_8[0x18];
1160         u8 syndrome[0x20];
1161         u8 reserved_at_40[0x40];
1162 };
1163
1164 struct mlx5_ifc_dealloc_flow_counter_in_bits {
1165         u8 opcode[0x10];
1166         u8 reserved_at_10[0x10];
1167         u8 reserved_at_20[0x10];
1168         u8 op_mod[0x10];
1169         u8 flow_counter_id[0x20];
1170         u8 reserved_at_60[0x20];
1171 };
1172
1173 struct mlx5_ifc_traffic_counter_bits {
1174         u8 packets[0x40];
1175         u8 octets[0x40];
1176 };
1177
1178 struct mlx5_ifc_query_flow_counter_out_bits {
1179         u8 status[0x8];
1180         u8 reserved_at_8[0x18];
1181         u8 syndrome[0x20];
1182         u8 reserved_at_40[0x40];
1183         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
1184 };
1185
1186 struct mlx5_ifc_query_flow_counter_in_bits {
1187         u8 opcode[0x10];
1188         u8 reserved_at_10[0x10];
1189         u8 reserved_at_20[0x10];
1190         u8 op_mod[0x10];
1191         u8 reserved_at_40[0x20];
1192         u8 mkey[0x20];
1193         u8 address[0x40];
1194         u8 clear[0x1];
1195         u8 dump_to_memory[0x1];
1196         u8 num_of_counters[0x1e];
1197         u8 flow_counter_id[0x20];
1198 };
1199
1200 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u
1201 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u
1202
1203 struct mlx5_ifc_klm_bits {
1204         u8 byte_count[0x20];
1205         u8 mkey[0x20];
1206         u8 address[0x40];
1207 };
1208
1209 struct mlx5_ifc_mkc_bits {
1210         u8 reserved_at_0[0x1];
1211         u8 free[0x1];
1212         u8 reserved_at_2[0x1];
1213         u8 access_mode_4_2[0x3];
1214         u8 reserved_at_6[0x7];
1215         u8 relaxed_ordering_write[0x1];
1216         u8 reserved_at_e[0x1];
1217         u8 small_fence_on_rdma_read_response[0x1];
1218         u8 umr_en[0x1];
1219         u8 a[0x1];
1220         u8 rw[0x1];
1221         u8 rr[0x1];
1222         u8 lw[0x1];
1223         u8 lr[0x1];
1224         u8 access_mode_1_0[0x2];
1225         u8 reserved_at_18[0x8];
1226         u8 qpn[0x18];
1227         u8 mkey_7_0[0x8];
1228         u8 reserved_at_40[0x20];
1229         u8 length64[0x1];
1230         u8 bsf_en[0x1];
1231         u8 sync_umr[0x1];
1232         u8 reserved_at_63[0x2];
1233         u8 expected_sigerr_count[0x1];
1234         u8 reserved_at_66[0x1];
1235         u8 en_rinval[0x1];
1236         u8 pd[0x18];
1237         u8 start_addr[0x40];
1238         u8 len[0x40];
1239         u8 bsf_octword_size[0x20];
1240         u8 reserved_at_120[0x80];
1241         u8 translations_octword_size[0x20];
1242         u8 reserved_at_1c0[0x19];
1243         u8 relaxed_ordering_read[0x1];
1244         u8 reserved_at_1da[0x1];
1245         u8 log_page_size[0x5];
1246         u8 reserved_at_1e0[0x3];
1247         u8 crypto_en[0x2];
1248         u8 reserved_at_1e5[0x1b];
1249 };
1250
1251 /* Range of values for MKEY context crypto_en field. */
1252 enum {
1253         MLX5_MKEY_CRYPTO_DISABLED = 0x0,
1254         MLX5_MKEY_CRYPTO_ENABLED = 0x1,
1255 };
1256
1257 struct mlx5_ifc_create_mkey_out_bits {
1258         u8 status[0x8];
1259         u8 reserved_at_8[0x18];
1260         u8 syndrome[0x20];
1261         u8 reserved_at_40[0x8];
1262         u8 mkey_index[0x18];
1263         u8 reserved_at_60[0x20];
1264 };
1265
1266 struct mlx5_ifc_create_mkey_in_bits {
1267         u8 opcode[0x10];
1268         u8 reserved_at_10[0x10];
1269         u8 reserved_at_20[0x10];
1270         u8 op_mod[0x10];
1271         u8 reserved_at_40[0x20];
1272         u8 pg_access[0x1];
1273         u8 reserved_at_61[0x1f];
1274         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
1275         u8 reserved_at_280[0x80];
1276         u8 translations_octword_actual_size[0x20];
1277         u8 mkey_umem_id[0x20];
1278         u8 mkey_umem_offset[0x40];
1279         u8 reserved_at_380[0x500];
1280         u8 klm_pas_mtt[][0x20];
1281 };
1282
1283 enum {
1284         MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
1285         MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
1286         MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
1287         MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1,
1288         MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,
1289         MLX5_SET_HCA_CAP_OP_MOD_ESW = 0x9 << 1,
1290         MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
1291         MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP = 0x1C << 1,
1292         MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1,
1293 };
1294
1295 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \
1296                         (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ)
1297 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \
1298                         (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS)
1299 #define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \
1300                         (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH)
1301 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \
1302                         (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO)
1303 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO \
1304                         (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO)
1305 #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \
1306                         (1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT)
1307 #define MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD \
1308                         (1ULL << MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD)
1309 #define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \
1310                         (1ULL << MLX5_GENERAL_OBJ_TYPE_DEK)
1311 #define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \
1312                         (1ULL << MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK)
1313 #define MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL \
1314                         (1ULL << MLX5_GENERAL_OBJ_TYPE_CREDENTIAL)
1315 #define MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN \
1316                         (1ULL << MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN)
1317
1318 enum {
1319         MLX5_HCA_CAP_OPMOD_GET_MAX   = 0,
1320         MLX5_HCA_CAP_OPMOD_GET_CUR   = 1,
1321 };
1322
1323 enum {
1324         MLX5_CAP_INLINE_MODE_L2,
1325         MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
1326         MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
1327 };
1328
1329 enum {
1330         MLX5_INLINE_MODE_NONE,
1331         MLX5_INLINE_MODE_L2,
1332         MLX5_INLINE_MODE_IP,
1333         MLX5_INLINE_MODE_TCP_UDP,
1334         MLX5_INLINE_MODE_RESERVED4,
1335         MLX5_INLINE_MODE_INNER_L2,
1336         MLX5_INLINE_MODE_INNER_IP,
1337         MLX5_INLINE_MODE_INNER_TCP_UDP,
1338 };
1339
1340 /* The supported timestamp formats reported in HCA attributes. */
1341 enum {
1342         MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR = 0x0,
1343         MLX5_HCA_CAP_TIMESTAMP_FORMAT_RT = 0x1,
1344         MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR_RT = 0x2,
1345 };
1346
1347 /* The timestamp format attributes to configure queues (RQ/SQ/QP). */
1348 enum {
1349         MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
1350         MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
1351         MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
1352 };
1353
1354 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
1355 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
1356 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
1357 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
1358 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
1359 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
1360 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
1361 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
1362 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
1363 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
1364 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
1365
1366 /* The device steering logic format. */
1367 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 0x0
1368 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX 0x1
1369
1370 struct mlx5_ifc_cmd_hca_cap_bits {
1371         u8 reserved_at_0[0x20];
1372         u8 hca_cap_2[0x1];
1373         u8 reserved_at_21[0xf];
1374         u8 vhca_id[0x10];
1375         u8 reserved_at_40[0x20];
1376         u8 reserved_at_60[0x3];
1377         u8 log_regexp_scatter_gather_size[0x5];
1378         u8 reserved_at_68[0x3];
1379         u8 log_dma_mmo_size[0x5];
1380         u8 reserved_at_70[0x3];
1381         u8 log_compress_mmo_size[0x5];
1382         u8 reserved_at_78[0x3];
1383         u8 log_decompress_mmo_size[0x5];
1384         u8 log_max_srq_sz[0x8];
1385         u8 log_max_qp_sz[0x8];
1386         u8 reserved_at_90[0x9];
1387         u8 wqe_index_ignore_cap[0x1];
1388         u8 dynamic_qp_allocation[0x1];
1389         u8 log_max_qp[0x5];
1390         u8 reserved_at_a0[0x4];
1391         u8 regexp_num_of_engines[0x4];
1392         u8 reserved_at_a8[0x1];
1393         u8 reg_c_preserve[0x1];
1394         u8 reserved_at_aa[0x1];
1395         u8 log_max_srq[0x5];
1396         u8 reserved_at_b0[0xb];
1397         u8 scatter_fcs_w_decap_disable[0x1];
1398         u8 reserved_at_bc[0x4];
1399         u8 reserved_at_c0[0x8];
1400         u8 log_max_cq_sz[0x8];
1401         u8 reserved_at_d0[0x2];
1402         u8 access_register_user[0x1];
1403         u8 reserved_at_d3[0x8];
1404         u8 log_max_cq[0x5];
1405         u8 log_max_eq_sz[0x8];
1406         u8 relaxed_ordering_write[0x1];
1407         u8 relaxed_ordering_read[0x1];
1408         u8 log_max_mkey[0x6];
1409         u8 reserved_at_f0[0x8];
1410         u8 dump_fill_mkey[0x1];
1411         u8 reserved_at_f9[0x3];
1412         u8 log_max_eq[0x4];
1413         u8 max_indirection[0x8];
1414         u8 fixed_buffer_size[0x1];
1415         u8 log_max_mrw_sz[0x7];
1416         u8 force_teardown[0x1];
1417         u8 reserved_at_111[0x1];
1418         u8 log_max_bsf_list_size[0x6];
1419         u8 umr_extended_translation_offset[0x1];
1420         u8 null_mkey[0x1];
1421         u8 log_max_klm_list_size[0x6];
1422         u8 non_wire_sq[0x1];
1423         u8 reserved_at_121[0x9];
1424         u8 log_max_ra_req_dc[0x6];
1425         u8 reserved_at_130[0x3];
1426         u8 log_max_static_sq_wq[0x5];
1427         u8 reserved_at_138[0x2];
1428         u8 log_max_ra_res_dc[0x6];
1429         u8 reserved_at_140[0xa];
1430         u8 log_max_ra_req_qp[0x6];
1431         u8 rtr2rts_qp_counters_set_id[0x1];
1432         u8 rts2rts_udp_sport[0x1];
1433         u8 rts2rts_lag_tx_port_affinity[0x1];
1434         u8 dma_mmo_sq[0x1];
1435         u8 compress_min_block_size[0x4];
1436         u8 compress_mmo_sq[0x1];
1437         u8 decompress_mmo_sq[0x1];
1438         u8 log_max_ra_res_qp[0x6];
1439         u8 end_pad[0x1];
1440         u8 cc_query_allowed[0x1];
1441         u8 cc_modify_allowed[0x1];
1442         u8 start_pad[0x1];
1443         u8 cache_line_128byte[0x1];
1444         u8 reserved_at_165[0xa];
1445         u8 qcam_reg[0x1];
1446         u8 gid_table_size[0x10];
1447         u8 out_of_seq_cnt[0x1];
1448         u8 vport_counters[0x1];
1449         u8 retransmission_q_counters[0x1];
1450         u8 debug[0x1];
1451         u8 modify_rq_counter_set_id[0x1];
1452         u8 rq_delay_drop[0x1];
1453         u8 max_qp_cnt[0xa];
1454         u8 pkey_table_size[0x10];
1455         u8 vport_group_manager[0x1];
1456         u8 vhca_group_manager[0x1];
1457         u8 ib_virt[0x1];
1458         u8 eth_virt[0x1];
1459         u8 vnic_env_queue_counters[0x1];
1460         u8 ets[0x1];
1461         u8 nic_flow_table[0x1];
1462         u8 eswitch_manager[0x1];
1463         u8 device_memory[0x1];
1464         u8 mcam_reg[0x1];
1465         u8 pcam_reg[0x1];
1466         u8 local_ca_ack_delay[0x5];
1467         u8 port_module_event[0x1];
1468         u8 enhanced_error_q_counters[0x1];
1469         u8 ports_check[0x1];
1470         u8 reserved_at_1b3[0x1];
1471         u8 disable_link_up[0x1];
1472         u8 beacon_led[0x1];
1473         u8 port_type[0x2];
1474         u8 num_ports[0x8];
1475         u8 reserved_at_1c0[0x1];
1476         u8 pps[0x1];
1477         u8 pps_modify[0x1];
1478         u8 log_max_msg[0x5];
1479         u8 reserved_at_1c8[0x4];
1480         u8 max_tc[0x4];
1481         u8 temp_warn_event[0x1];
1482         u8 dcbx[0x1];
1483         u8 general_notification_event[0x1];
1484         u8 reserved_at_1d3[0x2];
1485         u8 fpga[0x1];
1486         u8 rol_s[0x1];
1487         u8 rol_g[0x1];
1488         u8 reserved_at_1d8[0x1];
1489         u8 wol_s[0x1];
1490         u8 wol_g[0x1];
1491         u8 wol_a[0x1];
1492         u8 wol_b[0x1];
1493         u8 wol_m[0x1];
1494         u8 wol_u[0x1];
1495         u8 wol_p[0x1];
1496         u8 stat_rate_support[0x10];
1497         u8 reserved_at_1f0[0xc];
1498         u8 cqe_version[0x4];
1499         u8 compact_address_vector[0x1];
1500         u8 striding_rq[0x1];
1501         u8 reserved_at_202[0x1];
1502         u8 ipoib_enhanced_offloads[0x1];
1503         u8 ipoib_basic_offloads[0x1];
1504         u8 reserved_at_205[0x1];
1505         u8 repeated_block_disabled[0x1];
1506         u8 umr_modify_entity_size_disabled[0x1];
1507         u8 umr_modify_atomic_disabled[0x1];
1508         u8 umr_indirect_mkey_disabled[0x1];
1509         u8 umr_fence[0x2];
1510         u8 reserved_at_20c[0x3];
1511         u8 drain_sigerr[0x1];
1512         u8 cmdif_checksum[0x2];
1513         u8 sigerr_cqe[0x1];
1514         u8 reserved_at_213[0x1];
1515         u8 wq_signature[0x1];
1516         u8 sctr_data_cqe[0x1];
1517         u8 reserved_at_216[0x1];
1518         u8 sho[0x1];
1519         u8 tph[0x1];
1520         u8 rf[0x1];
1521         u8 dct[0x1];
1522         u8 qos[0x1];
1523         u8 eth_net_offloads[0x1];
1524         u8 roce[0x1];
1525         u8 atomic[0x1];
1526         u8 reserved_at_21f[0x1];
1527         u8 cq_oi[0x1];
1528         u8 cq_resize[0x1];
1529         u8 cq_moderation[0x1];
1530         u8 reserved_at_223[0x3];
1531         u8 cq_eq_remap[0x1];
1532         u8 pg[0x1];
1533         u8 block_lb_mc[0x1];
1534         u8 reserved_at_229[0x1];
1535         u8 scqe_break_moderation[0x1];
1536         u8 cq_period_start_from_cqe[0x1];
1537         u8 cd[0x1];
1538         u8 reserved_at_22d[0x1];
1539         u8 apm[0x1];
1540         u8 vector_calc[0x1];
1541         u8 umr_ptr_rlky[0x1];
1542         u8 imaicl[0x1];
1543         u8 reserved_at_232[0x4];
1544         u8 qkv[0x1];
1545         u8 pkv[0x1];
1546         u8 set_deth_sqpn[0x1];
1547         u8 reserved_at_239[0x3];
1548         u8 xrc[0x1];
1549         u8 ud[0x1];
1550         u8 uc[0x1];
1551         u8 rc[0x1];
1552         u8 uar_4k[0x1];
1553         u8 reserved_at_241[0x8];
1554         u8 regexp_params[0x1];
1555         u8 uar_sz[0x6];
1556         u8 port_selection_cap[0x1];
1557         u8 reserved_at_251[0x7];
1558         u8 log_pg_sz[0x8];
1559         u8 bf[0x1];
1560         u8 driver_version[0x1];
1561         u8 pad_tx_eth_packet[0x1];
1562         u8 reserved_at_263[0x8];
1563         u8 log_bf_reg_size[0x5];
1564         u8 reserved_at_270[0xb];
1565         u8 lag_master[0x1];
1566         u8 num_lag_ports[0x4];
1567         u8 reserved_at_280[0x10];
1568         u8 max_wqe_sz_sq[0x10];
1569         u8 reserved_at_2a0[0xc];
1570         u8 regexp_mmo_sq[0x1];
1571         u8 regexp_version[0x3];
1572         u8 max_wqe_sz_rq[0x10];
1573         u8 max_flow_counter_31_16[0x10];
1574         u8 max_wqe_sz_sq_dc[0x10];
1575         u8 reserved_at_2e0[0x7];
1576         u8 max_qp_mcg[0x19];
1577         u8 reserved_at_300[0x10];
1578         u8 flow_counter_bulk_alloc[0x08];
1579         u8 log_max_mcg[0x8];
1580         u8 reserved_at_320[0x3];
1581         u8 log_max_transport_domain[0x5];
1582         u8 reserved_at_328[0x3];
1583         u8 log_max_pd[0x5];
1584         u8 reserved_at_330[0xb];
1585         u8 log_max_xrcd[0x5];
1586         u8 nic_receive_steering_discard[0x1];
1587         u8 receive_discard_vport_down[0x1];
1588         u8 transmit_discard_vport_down[0x1];
1589         u8 reserved_at_343[0x5];
1590         u8 log_max_flow_counter_bulk[0x8];
1591         u8 max_flow_counter_15_0[0x10];
1592         u8 modify_tis[0x1];
1593         u8 flow_counters_dump[0x1];
1594         u8 reserved_at_360[0x1];
1595         u8 log_max_rq[0x5];
1596         u8 reserved_at_368[0x3];
1597         u8 log_max_sq[0x5];
1598         u8 reserved_at_370[0x3];
1599         u8 log_max_tir[0x5];
1600         u8 reserved_at_378[0x3];
1601         u8 log_max_tis[0x5];
1602         u8 basic_cyclic_rcv_wqe[0x1];
1603         u8 reserved_at_381[0x1];
1604         u8 mem_rq_rmp[0x1];
1605         u8 log_max_rmp[0x5];
1606         u8 reserved_at_388[0x3];
1607         u8 log_max_rqt[0x5];
1608         u8 reserved_at_390[0x3];
1609         u8 log_max_rqt_size[0x5];
1610         u8 reserved_at_398[0x3];
1611         u8 log_max_tis_per_sq[0x5];
1612         u8 ext_stride_num_range[0x1];
1613         u8 reserved_at_3a1[0x2];
1614         u8 log_max_stride_sz_rq[0x5];
1615         u8 reserved_at_3a8[0x3];
1616         u8 log_min_stride_sz_rq[0x5];
1617         u8 reserved_at_3b0[0x3];
1618         u8 log_max_stride_sz_sq[0x5];
1619         u8 reserved_at_3b8[0x3];
1620         u8 log_min_stride_sz_sq[0x5];
1621         u8 hairpin[0x1];
1622         u8 reserved_at_3c1[0x2];
1623         u8 log_max_hairpin_queues[0x5];
1624         u8 reserved_at_3c8[0x3];
1625         u8 log_max_hairpin_wq_data_sz[0x5];
1626         u8 reserved_at_3d0[0x3];
1627         u8 log_max_hairpin_num_packets[0x5];
1628         u8 reserved_at_3d8[0x3];
1629         u8 log_max_wq_sz[0x5];
1630         u8 nic_vport_change_event[0x1];
1631         u8 disable_local_lb_uc[0x1];
1632         u8 disable_local_lb_mc[0x1];
1633         u8 log_min_hairpin_wq_data_sz[0x5];
1634         u8 reserved_at_3e8[0x3];
1635         u8 log_max_vlan_list[0x5];
1636         u8 reserved_at_3f0[0x3];
1637         u8 log_max_current_mc_list[0x5];
1638         u8 reserved_at_3f8[0x3];
1639         u8 log_max_current_uc_list[0x5];
1640         u8 general_obj_types[0x40];
1641         u8 sq_ts_format[0x2];
1642         u8 rq_ts_format[0x2];
1643         u8 steering_format_version[0x4];
1644         u8 reserved_at_448[0x18];
1645         u8 reserved_at_460[0x8];
1646         u8 aes_xts[0x1];
1647         u8 crypto[0x1];
1648         u8 reserved_at_46a[0x6];
1649         u8 max_num_eqs[0x10];
1650         u8 reserved_at_480[0x3];
1651         u8 log_max_l2_table[0x5];
1652         u8 reserved_at_488[0x8];
1653         u8 log_uar_page_sz[0x10];
1654         u8 reserved_at_4a0[0x20];
1655         u8 device_frequency_mhz[0x20];
1656         u8 device_frequency_khz[0x20];
1657         u8 reserved_at_500[0x20];
1658         u8 num_of_uars_per_page[0x20];
1659         u8 flex_parser_protocols[0x20];
1660         u8 max_geneve_tlv_options[0x8];
1661         u8 reserved_at_568[0x3];
1662         u8 max_geneve_tlv_option_data_len[0x5];
1663         u8 reserved_at_570[0x49];
1664         u8 mini_cqe_resp_l3_l4_tag[0x1];
1665         u8 mini_cqe_resp_flow_tag[0x1];
1666         u8 enhanced_cqe_compression[0x1];
1667         u8 mini_cqe_resp_stride_index[0x1];
1668         u8 cqe_128_always[0x1];
1669         u8 cqe_compression_128[0x1];
1670         u8 cqe_compression[0x1];
1671         u8 cqe_compression_timeout[0x10];
1672         u8 cqe_compression_max_num[0x10];
1673         u8 reserved_at_5e0[0x10];
1674         u8 tag_matching[0x1];
1675         u8 rndv_offload_rc[0x1];
1676         u8 rndv_offload_dc[0x1];
1677         u8 log_tag_matching_list_sz[0x5];
1678         u8 reserved_at_5f8[0x3];
1679         u8 log_max_xrq[0x5];
1680         u8 affiliate_nic_vport_criteria[0x8];
1681         u8 native_port_num[0x8];
1682         u8 num_vhca_ports[0x8];
1683         u8 reserved_at_618[0x6];
1684         u8 sw_owner_id[0x1];
1685         u8 reserved_at_61f[0x6C];
1686         u8 wait_on_data[0x1];
1687         u8 wait_on_time[0x1];
1688         u8 reserved_at_68d[0xBB];
1689         u8 dma_mmo_qp[0x1];
1690         u8 regexp_mmo_qp[0x1];
1691         u8 compress_mmo_qp[0x1];
1692         u8 decompress_mmo_qp[0x1];
1693         u8 reserved_at_624[0xd4];
1694 };
1695
1696 struct mlx5_ifc_qos_cap_bits {
1697         u8 packet_pacing[0x1];
1698         u8 esw_scheduling[0x1];
1699         u8 esw_bw_share[0x1];
1700         u8 esw_rate_limit[0x1];
1701         u8 reserved_at_4[0x1];
1702         u8 packet_pacing_burst_bound[0x1];
1703         u8 packet_pacing_typical_size[0x1];
1704         u8 flow_meter_old[0x1];
1705         u8 reserved_at_8[0x8];
1706         u8 log_max_flow_meter[0x8];
1707         u8 flow_meter_reg_id[0x8];
1708         u8 wqe_rate_pp[0x1];
1709         u8 reserved_at_25[0x7];
1710         u8 flow_meter[0x1];
1711         u8 reserved_at_2e[0x17];
1712         u8 packet_pacing_max_rate[0x20];
1713         u8 packet_pacing_min_rate[0x20];
1714         u8 reserved_at_80[0x10];
1715         u8 packet_pacing_rate_table_size[0x10];
1716         u8 esw_element_type[0x10];
1717         u8 esw_tsar_type[0x10];
1718         u8 reserved_at_c0[0x10];
1719         u8 max_qos_para_vport[0x10];
1720         u8 max_tsar_bw_share[0x20];
1721         u8 nic_element_type[0x10];
1722         u8 nic_tsar_type[0x10];
1723         u8 reserved_at_120[0x3];
1724         u8 log_meter_aso_granularity[0x5];
1725         u8 reserved_at_128[0x3];
1726         u8 log_meter_aso_max_alloc[0x5];
1727         u8 reserved_at_130[0x3];
1728         u8 log_max_num_meter_aso[0x5];
1729         u8 reserved_at_138[0x6b0];
1730 };
1731
1732 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1733         u8 csum_cap[0x1];
1734         u8 vlan_cap[0x1];
1735         u8 lro_cap[0x1];
1736         u8 lro_psh_flag[0x1];
1737         u8 lro_time_stamp[0x1];
1738         u8 lro_max_msg_sz_mode[0x2];
1739         u8 wqe_vlan_insert[0x1];
1740         u8 self_lb_en_modifiable[0x1];
1741         u8 self_lb_mc[0x1];
1742         u8 self_lb_uc[0x1];
1743         u8 max_lso_cap[0x5];
1744         u8 multi_pkt_send_wqe[0x2];
1745         u8 wqe_inline_mode[0x2];
1746         u8 rss_ind_tbl_cap[0x4];
1747         u8 reg_umr_sq[0x1];
1748         u8 scatter_fcs[0x1];
1749         u8 enhanced_multi_pkt_send_wqe[0x1];
1750         u8 tunnel_lso_const_out_ip_id[0x1];
1751         u8 tunnel_lro_gre[0x1];
1752         u8 tunnel_lro_vxlan[0x1];
1753         u8 tunnel_stateless_gre[0x1];
1754         u8 tunnel_stateless_vxlan[0x1];
1755         u8 swp[0x1];
1756         u8 swp_csum[0x1];
1757         u8 swp_lso[0x1];
1758         u8 reserved_at_23[0x8];
1759         u8 tunnel_stateless_gtp[0x1];
1760         u8 reserved_at_25[0x4];
1761         u8 max_vxlan_udp_ports[0x8];
1762         u8 reserved_at_38[0x6];
1763         u8 max_geneve_opt_len[0x1];
1764         u8 tunnel_stateless_geneve_rx[0x1];
1765         u8 reserved_at_40[0x10];
1766         u8 lro_min_mss_size[0x10];
1767         u8 reserved_at_60[0x120];
1768         u8 lro_timer_supported_periods[4][0x20];
1769         u8 reserved_at_200[0x600];
1770 };
1771
1772 enum {
1773         MLX5_VIRTQ_TYPE_SPLIT = 0,
1774         MLX5_VIRTQ_TYPE_PACKED = 1,
1775 };
1776
1777 enum {
1778         MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0,
1779         MLX5_VIRTQ_EVENT_MODE_QP = 1,
1780         MLX5_VIRTQ_EVENT_MODE_MSIX = 2,
1781 };
1782
1783 struct mlx5_ifc_virtio_emulation_cap_bits {
1784         u8 desc_tunnel_offload_type[0x1];
1785         u8 eth_frame_offload_type[0x1];
1786         u8 virtio_version_1_0[0x1];
1787         u8 tso_ipv4[0x1];
1788         u8 tso_ipv6[0x1];
1789         u8 tx_csum[0x1];
1790         u8 rx_csum[0x1];
1791         u8 reserved_at_7[0x1][0x9];
1792         u8 event_mode[0x8];
1793         u8 virtio_queue_type[0x8];
1794         u8 reserved_at_20[0x13];
1795         u8 log_doorbell_stride[0x5];
1796         u8 reserved_at_3b[0x3];
1797         u8 log_doorbell_bar_size[0x5];
1798         u8 doorbell_bar_offset[0x40];
1799         u8 reserved_at_80[0x8];
1800         u8 max_num_virtio_queues[0x18];
1801         u8 reserved_at_a0[0x60];
1802         u8 umem_1_buffer_param_a[0x20];
1803         u8 umem_1_buffer_param_b[0x20];
1804         u8 umem_2_buffer_param_a[0x20];
1805         u8 umem_2_buffer_param_b[0x20];
1806         u8 umem_3_buffer_param_a[0x20];
1807         u8 umem_3_buffer_param_b[0x20];
1808         u8 reserved_at_1c0[0x620];
1809 };
1810
1811 /**
1812  * PARSE_GRAPH_NODE Capabilities Field Descriptions
1813  */
1814 struct mlx5_ifc_parse_graph_node_cap_bits {
1815         u8 node_in[0x20];
1816         u8 node_out[0x20];
1817         u8 header_length_mode[0x10];
1818         u8 sample_offset_mode[0x10];
1819         u8 max_num_arc_in[0x08];
1820         u8 max_num_arc_out[0x08];
1821         u8 max_num_sample[0x08];
1822         u8 reserved_at_78[0x07];
1823         u8 sample_id_in_out[0x1];
1824         u8 max_base_header_length[0x10];
1825         u8 reserved_at_90[0x08];
1826         u8 max_sample_base_offset[0x08];
1827         u8 max_next_header_offset[0x10];
1828         u8 reserved_at_b0[0x08];
1829         u8 header_length_mask_width[0x08];
1830 };
1831
1832 struct mlx5_ifc_flow_table_prop_layout_bits {
1833         u8 ft_support[0x1];
1834         u8 flow_tag[0x1];
1835         u8 flow_counter[0x1];
1836         u8 flow_modify_en[0x1];
1837         u8 modify_root[0x1];
1838         u8 identified_miss_table[0x1];
1839         u8 flow_table_modify[0x1];
1840         u8 reformat[0x1];
1841         u8 decap[0x1];
1842         u8 reset_root_to_default[0x1];
1843         u8 pop_vlan[0x1];
1844         u8 push_vlan[0x1];
1845         u8 fpga_vendor_acceleration[0x1];
1846         u8 pop_vlan_2[0x1];
1847         u8 push_vlan_2[0x1];
1848         u8 reformat_and_vlan_action[0x1];
1849         u8 modify_and_vlan_action[0x1];
1850         u8 sw_owner[0x1];
1851         u8 reformat_l3_tunnel_to_l2[0x1];
1852         u8 reformat_l2_to_l3_tunnel[0x1];
1853         u8 reformat_and_modify_action[0x1];
1854         u8 reserved_at_15[0x9];
1855         u8 sw_owner_v2[0x1];
1856         u8 reserved_at_1f[0x1];
1857         u8 reserved_at_20[0x2];
1858         u8 log_max_ft_size[0x6];
1859         u8 log_max_modify_header_context[0x8];
1860         u8 max_modify_header_actions[0x8];
1861         u8 max_ft_level[0x8];
1862         u8 reserved_at_40[0x8];
1863         u8 log_max_ft_sampler_num[8];
1864         u8 metadata_reg_b_width[0x8];
1865         u8 metadata_reg_a_width[0x8];
1866         u8 reserved_at_60[0x18];
1867         u8 log_max_ft_num[0x8];
1868         u8 reserved_at_80[0x10];
1869         u8 log_max_flow_counter[0x8];
1870         u8 log_max_destination[0x8];
1871         u8 reserved_at_a0[0x18];
1872         u8 log_max_flow[0x8];
1873         u8 reserved_at_c0[0x140];
1874 };
1875
1876 struct mlx5_ifc_roce_caps_bits {
1877         u8 reserved_0[0x1e];
1878         u8 qp_ts_format[0x2];
1879         u8 reserved_at_20[0x7e0];
1880 };
1881
1882 /*
1883  * Table 1872 - Flow Table Fields Supported 2 Format
1884  */
1885 struct mlx5_ifc_ft_fields_support_2_bits {
1886         u8 reserved_at_0[0xf];
1887         u8 tunnel_header_2_3[0x1];
1888         u8 tunnel_header_0_1[0x1];
1889         u8 macsec_syndrome[0x1];
1890         u8 macsec_tag[0x1];
1891         u8 outer_lrh_sl[0x1];
1892         u8 inner_ipv4_ihl[0x1];
1893         u8 outer_ipv4_ihl[0x1];
1894         u8 psp_syndrome[0x1];
1895         u8 inner_l3_ok[0x1];
1896         u8 inner_l4_ok[0x1];
1897         u8 outer_l3_ok[0x1];
1898         u8 outer_l4_ok[0x1];
1899         u8 psp_header[0x1];
1900         u8 inner_ipv4_checksum_ok[0x1];
1901         u8 inner_l4_checksum_ok[0x1];
1902         u8 outer_ipv4_checksum_ok[0x1];
1903         u8 outer_l4_checksum_ok[0x1];
1904         u8 reserved_at_20[0x60];
1905 };
1906
1907 struct mlx5_ifc_flow_table_nic_cap_bits {
1908         u8 reserved_at_0[0x200];
1909         struct mlx5_ifc_flow_table_prop_layout_bits
1910                 flow_table_properties_nic_receive;
1911         struct mlx5_ifc_flow_table_prop_layout_bits
1912                 flow_table_properties_nic_receive_rdma;
1913         struct mlx5_ifc_flow_table_prop_layout_bits
1914                 flow_table_properties_nic_receive_sniffer;
1915         struct mlx5_ifc_flow_table_prop_layout_bits
1916                 flow_table_properties_nic_transmit;
1917         struct mlx5_ifc_flow_table_prop_layout_bits
1918                 flow_table_properties_nic_transmit_rdma;
1919         struct mlx5_ifc_flow_table_prop_layout_bits
1920                 flow_table_properties_nic_transmit_sniffer;
1921         u8 reserved_at_e00[0x600];
1922         struct mlx5_ifc_ft_fields_support_2_bits
1923                 ft_field_support_2_nic_receive;
1924 };
1925
1926 /*
1927  *  HCA Capabilities 2
1928  */
1929 struct mlx5_ifc_cmd_hca_cap_2_bits {
1930         u8 reserved_at_0[0x80]; /* End of DW4. */
1931         u8 reserved_at_80[0x3];
1932         u8 max_num_prog_sample_field[0x5];
1933         u8 reserved_at_88[0x3];
1934         u8 log_max_num_reserved_qpn[0x5];
1935         u8 reserved_at_90[0x3];
1936         u8 log_reserved_qpn_granularity[0x5];
1937         u8 reserved_at_98[0x3];
1938         u8 log_reserved_qpn_max_alloc[0x5]; /* End of DW5. */
1939         u8 max_reformat_insert_size[0x8];
1940         u8 max_reformat_insert_offset[0x8];
1941         u8 max_reformat_remove_size[0x8];
1942         u8 max_reformat_remove_offset[0x8]; /* End of DW6. */
1943         u8 reserved_at_c0[0x3];
1944         u8 log_min_stride_wqe_sz[0x5];
1945         u8 reserved_at_c8[0x3];
1946         u8 log_conn_track_granularity[0x5];
1947         u8 reserved_at_d0[0x3];
1948         u8 log_conn_track_max_alloc[0x5];
1949         u8 reserved_at_d8[0x3];
1950         u8 log_max_conn_track_offload[0x5];
1951         u8 reserved_at_e0[0x20]; /* End of DW7. */
1952         u8 reserved_at_100[0x700];
1953 };
1954
1955 struct mlx5_ifc_esw_cap_bits {
1956         u8 reserved_at_0[0x60];
1957
1958         u8 esw_manager_vport_number_valid[0x1];
1959         u8 reserved_at_61[0xf];
1960         u8 esw_manager_vport_number[0x10];
1961
1962         u8 reserved_at_80[0x780];
1963 };
1964
1965 union mlx5_ifc_hca_cap_union_bits {
1966         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1967         struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
1968         struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1969                per_protocol_networking_offload_caps;
1970         struct mlx5_ifc_qos_cap_bits qos_cap;
1971         struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
1972         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1973         struct mlx5_ifc_esw_cap_bits esw_cap;
1974         struct mlx5_ifc_roce_caps_bits roce_caps;
1975         u8 reserved_at_0[0x8000];
1976 };
1977
1978 struct mlx5_ifc_set_action_in_bits {
1979         u8 action_type[0x4];
1980         u8 field[0xc];
1981         u8 reserved_at_10[0x3];
1982         u8 offset[0x5];
1983         u8 reserved_at_18[0x3];
1984         u8 length[0x5];
1985         u8 data[0x20];
1986 };
1987
1988 struct mlx5_ifc_query_hca_cap_out_bits {
1989         u8 status[0x8];
1990         u8 reserved_at_8[0x18];
1991         u8 syndrome[0x20];
1992         u8 reserved_at_40[0x40];
1993         union mlx5_ifc_hca_cap_union_bits capability;
1994 };
1995
1996 struct mlx5_ifc_query_hca_cap_in_bits {
1997         u8 opcode[0x10];
1998         u8 reserved_at_10[0x10];
1999         u8 reserved_at_20[0x10];
2000         u8 op_mod[0x10];
2001         u8 reserved_at_40[0x40];
2002 };
2003
2004 struct mlx5_ifc_mac_address_layout_bits {
2005         u8 reserved_at_0[0x10];
2006         u8 mac_addr_47_32[0x10];
2007         u8 mac_addr_31_0[0x20];
2008 };
2009
2010 struct mlx5_ifc_nic_vport_context_bits {
2011         u8 reserved_at_0[0x5];
2012         u8 min_wqe_inline_mode[0x3];
2013         u8 reserved_at_8[0x15];
2014         u8 disable_mc_local_lb[0x1];
2015         u8 disable_uc_local_lb[0x1];
2016         u8 roce_en[0x1];
2017         u8 arm_change_event[0x1];
2018         u8 reserved_at_21[0x1a];
2019         u8 event_on_mtu[0x1];
2020         u8 event_on_promisc_change[0x1];
2021         u8 event_on_vlan_change[0x1];
2022         u8 event_on_mc_address_change[0x1];
2023         u8 event_on_uc_address_change[0x1];
2024         u8 reserved_at_40[0xc];
2025         u8 affiliation_criteria[0x4];
2026         u8 affiliated_vhca_id[0x10];
2027         u8 reserved_at_60[0xd0];
2028         u8 mtu[0x10];
2029         u8 system_image_guid[0x40];
2030         u8 port_guid[0x40];
2031         u8 node_guid[0x40];
2032         u8 reserved_at_200[0x140];
2033         u8 qkey_violation_counter[0x10];
2034         u8 reserved_at_350[0x430];
2035         u8 promisc_uc[0x1];
2036         u8 promisc_mc[0x1];
2037         u8 promisc_all[0x1];
2038         u8 reserved_at_783[0x2];
2039         u8 allowed_list_type[0x3];
2040         u8 reserved_at_788[0xc];
2041         u8 allowed_list_size[0xc];
2042         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2043         u8 reserved_at_7e0[0x20];
2044 };
2045
2046 struct mlx5_ifc_query_nic_vport_context_out_bits {
2047         u8 status[0x8];
2048         u8 reserved_at_8[0x18];
2049         u8 syndrome[0x20];
2050         u8 reserved_at_40[0x40];
2051         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
2052 };
2053
2054 struct mlx5_ifc_query_nic_vport_context_in_bits {
2055         u8 opcode[0x10];
2056         u8 reserved_at_10[0x10];
2057         u8 reserved_at_20[0x10];
2058         u8 op_mod[0x10];
2059         u8 other_vport[0x1];
2060         u8 reserved_at_41[0xf];
2061         u8 vport_number[0x10];
2062         u8 reserved_at_60[0x5];
2063         u8 allowed_list_type[0x3];
2064         u8 reserved_at_68[0x18];
2065 };
2066
2067 /*
2068  * lag_tx_port_affinity: 0 auto-selection, 1 PF1, 2 PF2 vice versa.
2069  * Each TIS binds to one PF by setting lag_tx_port_affinity (>0).
2070  * Once LAG enabled, we create multiple TISs and bind each one to
2071  * different PFs, then TIS[i] gets affinity i+1 and goes to PF i+1.
2072  */
2073 #define MLX5_IFC_LAG_MAP_TIS_AFFINITY(index, num) ((num) ? \
2074                                                     (index) % (num) + 1 : 0)
2075 struct mlx5_ifc_tisc_bits {
2076         u8 strict_lag_tx_port_affinity[0x1];
2077         u8 reserved_at_1[0x3];
2078         u8 lag_tx_port_affinity[0x04];
2079         u8 reserved_at_8[0x4];
2080         u8 prio[0x4];
2081         u8 reserved_at_10[0x10];
2082         u8 reserved_at_20[0x100];
2083         u8 reserved_at_120[0x8];
2084         u8 transport_domain[0x18];
2085         u8 reserved_at_140[0x8];
2086         u8 underlay_qpn[0x18];
2087         u8 reserved_at_160[0x3a0];
2088 };
2089
2090 struct mlx5_ifc_query_tis_out_bits {
2091         u8 status[0x8];
2092         u8 reserved_at_8[0x18];
2093         u8 syndrome[0x20];
2094         u8 reserved_at_40[0x40];
2095         struct mlx5_ifc_tisc_bits tis_context;
2096 };
2097
2098 struct mlx5_ifc_query_tis_in_bits {
2099         u8 opcode[0x10];
2100         u8 reserved_at_10[0x10];
2101         u8 reserved_at_20[0x10];
2102         u8 op_mod[0x10];
2103         u8 reserved_at_40[0x8];
2104         u8 tisn[0x18];
2105         u8 reserved_at_60[0x20];
2106 };
2107
2108 /* port_select_mode definition. */
2109 enum mlx5_lag_mode_type {
2110         MLX5_LAG_MODE_TIS = 0,
2111         MLX5_LAG_MODE_HASH = 1,
2112 };
2113
2114 struct mlx5_ifc_lag_context_bits {
2115         u8 fdb_selection_mode[0x1];
2116         u8 reserved_at_1[0x14];
2117         u8 port_select_mode[0x3];
2118         u8 reserved_at_18[0x5];
2119         u8 lag_state[0x3];
2120         u8 reserved_at_20[0x14];
2121         u8 tx_remap_affinity_2[0x4];
2122         u8 reserved_at_38[0x4];
2123         u8 tx_remap_affinity_1[0x4];
2124 };
2125
2126 struct mlx5_ifc_query_lag_in_bits {
2127         u8 opcode[0x10];
2128         u8 uid[0x10];
2129         u8 reserved_at_20[0x10];
2130         u8 op_mod[0x10];
2131         u8 reserved_at_40[0x40];
2132 };
2133
2134 struct mlx5_ifc_query_lag_out_bits {
2135         u8 status[0x8];
2136         u8 reserved_at_8[0x18];
2137         u8 syndrome[0x20];
2138         struct mlx5_ifc_lag_context_bits context;
2139 };
2140
2141 struct mlx5_ifc_alloc_transport_domain_out_bits {
2142         u8 status[0x8];
2143         u8 reserved_at_8[0x18];
2144         u8 syndrome[0x20];
2145         u8 reserved_at_40[0x8];
2146         u8 transport_domain[0x18];
2147         u8 reserved_at_60[0x20];
2148 };
2149
2150 struct mlx5_ifc_alloc_transport_domain_in_bits {
2151         u8 opcode[0x10];
2152         u8 reserved_at_10[0x10];
2153         u8 reserved_at_20[0x10];
2154         u8 op_mod[0x10];
2155         u8 reserved_at_40[0x40];
2156 };
2157
2158 enum {
2159         MLX5_WQ_TYPE_LINKED_LIST                = 0x0,
2160         MLX5_WQ_TYPE_CYCLIC                     = 0x1,
2161         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ    = 0x2,
2162         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ         = 0x3,
2163 };
2164
2165 enum {
2166         MLX5_WQ_END_PAD_MODE_NONE  = 0x0,
2167         MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
2168 };
2169
2170 struct mlx5_ifc_wq_bits {
2171         u8 wq_type[0x4];
2172         u8 wq_signature[0x1];
2173         u8 end_padding_mode[0x2];
2174         u8 cd_slave[0x1];
2175         u8 reserved_at_8[0x18];
2176         u8 hds_skip_first_sge[0x1];
2177         u8 log2_hds_buf_size[0x3];
2178         u8 reserved_at_24[0x7];
2179         u8 page_offset[0x5];
2180         u8 lwm[0x10];
2181         u8 reserved_at_40[0x8];
2182         u8 pd[0x18];
2183         u8 reserved_at_60[0x8];
2184         u8 uar_page[0x18];
2185         u8 dbr_addr[0x40];
2186         u8 hw_counter[0x20];
2187         u8 sw_counter[0x20];
2188         u8 reserved_at_100[0xc];
2189         u8 log_wq_stride[0x4];
2190         u8 reserved_at_110[0x3];
2191         u8 log_wq_pg_sz[0x5];
2192         u8 reserved_at_118[0x3];
2193         u8 log_wq_sz[0x5];
2194         u8 dbr_umem_valid[0x1];
2195         u8 wq_umem_valid[0x1];
2196         u8 reserved_at_122[0x1];
2197         u8 log_hairpin_num_packets[0x5];
2198         u8 reserved_at_128[0x3];
2199         u8 log_hairpin_data_sz[0x5];
2200         u8 reserved_at_130[0x4];
2201         u8 single_wqe_log_num_of_strides[0x4];
2202         u8 two_byte_shift_en[0x1];
2203         u8 reserved_at_139[0x4];
2204         u8 single_stride_log_num_of_bytes[0x3];
2205         u8 dbr_umem_id[0x20];
2206         u8 wq_umem_id[0x20];
2207         u8 wq_umem_offset[0x40];
2208         u8 reserved_at_1c0[0x440];
2209 };
2210
2211 enum {
2212         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2213         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2214 };
2215
2216 enum {
2217         MLX5_RQC_STATE_RST  = 0x0,
2218         MLX5_RQC_STATE_RDY  = 0x1,
2219         MLX5_RQC_STATE_ERR  = 0x3,
2220 };
2221
2222 struct mlx5_ifc_rqc_bits {
2223         u8 rlky[0x1];
2224         u8 delay_drop_en[0x1];
2225         u8 scatter_fcs[0x1];
2226         u8 vsd[0x1];
2227         u8 mem_rq_type[0x4];
2228         u8 state[0x4];
2229         u8 reserved_at_c[0x1];
2230         u8 flush_in_error_en[0x1];
2231         u8 hairpin[0x1];
2232         u8 reserved_at_f[0xB];
2233         u8 ts_format[0x02];
2234         u8 reserved_at_1c[0x4];
2235         u8 reserved_at_20[0x8];
2236         u8 user_index[0x18];
2237         u8 reserved_at_40[0x8];
2238         u8 cqn[0x18];
2239         u8 counter_set_id[0x8];
2240         u8 reserved_at_68[0x18];
2241         u8 reserved_at_80[0x8];
2242         u8 rmpn[0x18];
2243         u8 reserved_at_a0[0x8];
2244         u8 hairpin_peer_sq[0x18];
2245         u8 reserved_at_c0[0x10];
2246         u8 hairpin_peer_vhca[0x10];
2247         u8 reserved_at_e0[0xa0];
2248         struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
2249 };
2250
2251 struct mlx5_ifc_create_rq_out_bits {
2252         u8 status[0x8];
2253         u8 reserved_at_8[0x18];
2254         u8 syndrome[0x20];
2255         u8 reserved_at_40[0x8];
2256         u8 rqn[0x18];
2257         u8 reserved_at_60[0x20];
2258 };
2259
2260 struct mlx5_ifc_create_rq_in_bits {
2261         u8 opcode[0x10];
2262         u8 uid[0x10];
2263         u8 reserved_at_20[0x10];
2264         u8 op_mod[0x10];
2265         u8 reserved_at_40[0xc0];
2266         struct mlx5_ifc_rqc_bits ctx;
2267 };
2268
2269 struct mlx5_ifc_modify_rq_out_bits {
2270         u8 status[0x8];
2271         u8 reserved_at_8[0x18];
2272         u8 syndrome[0x20];
2273         u8 reserved_at_40[0x40];
2274 };
2275
2276 struct mlx5_ifc_query_rq_out_bits {
2277         u8 status[0x8];
2278         u8 reserved_at_8[0x18];
2279         u8 syndrome[0x20];
2280         u8 reserved_at_40[0xc0];
2281         struct mlx5_ifc_rqc_bits rq_context;
2282 };
2283
2284 struct mlx5_ifc_query_rq_in_bits {
2285         u8 opcode[0x10];
2286         u8 reserved_at_10[0x10];
2287         u8 reserved_at_20[0x10];
2288         u8 op_mod[0x10];
2289         u8 reserved_at_40[0x8];
2290         u8 rqn[0x18];
2291         u8 reserved_at_60[0x20];
2292 };
2293
2294 enum {
2295         MLX5_RMPC_STATE_RDY = 0x1,
2296         MLX5_RMPC_STATE_ERR = 0x3,
2297 };
2298
2299 struct mlx5_ifc_rmpc_bits {
2300         u8 reserved_at_0[0x8];
2301         u8 state[0x4];
2302         u8 reserved_at_c[0x14];
2303         u8 basic_cyclic_rcv_wqe[0x1];
2304         u8 reserved_at_21[0x1f];
2305         u8 reserved_at_40[0x140];
2306         struct mlx5_ifc_wq_bits wq;
2307 };
2308
2309 struct mlx5_ifc_query_rmp_out_bits {
2310         u8 status[0x8];
2311         u8 reserved_at_8[0x18];
2312         u8 syndrome[0x20];
2313         u8 reserved_at_40[0xc0];
2314         struct mlx5_ifc_rmpc_bits rmp_context;
2315 };
2316
2317 struct mlx5_ifc_query_rmp_in_bits {
2318         u8 opcode[0x10];
2319         u8 reserved_at_10[0x10];
2320         u8 reserved_at_20[0x10];
2321         u8 op_mod[0x10];
2322         u8 reserved_at_40[0x8];
2323         u8 rmpn[0x18];
2324         u8 reserved_at_60[0x20];
2325 };
2326
2327 struct mlx5_ifc_modify_rmp_out_bits {
2328         u8 status[0x8];
2329         u8 reserved_at_8[0x18];
2330         u8 syndrome[0x20];
2331         u8 reserved_at_40[0x40];
2332 };
2333
2334 struct mlx5_ifc_rmp_bitmask_bits {
2335         u8 reserved_at_0[0x20];
2336         u8 reserved_at_20[0x1f];
2337         u8 lwm[0x1];
2338 };
2339
2340 struct mlx5_ifc_modify_rmp_in_bits {
2341         u8 opcode[0x10];
2342         u8 uid[0x10];
2343         u8 reserved_at_20[0x10];
2344         u8 op_mod[0x10];
2345         u8 rmp_state[0x4];
2346         u8 reserved_at_44[0x4];
2347         u8 rmpn[0x18];
2348         u8 reserved_at_60[0x20];
2349         struct mlx5_ifc_rmp_bitmask_bits bitmask;
2350         u8 reserved_at_c0[0x40];
2351         struct mlx5_ifc_rmpc_bits ctx;
2352 };
2353
2354 struct mlx5_ifc_create_rmp_out_bits {
2355         u8 status[0x8];
2356         u8 reserved_at_8[0x18];
2357         u8 syndrome[0x20];
2358         u8 reserved_at_40[0x8];
2359         u8 rmpn[0x18];
2360         u8 reserved_at_60[0x20];
2361 };
2362
2363 struct mlx5_ifc_create_rmp_in_bits {
2364         u8 opcode[0x10];
2365         u8 uid[0x10];
2366         u8 reserved_at_20[0x10];
2367         u8 op_mod[0x10];
2368         u8 reserved_at_40[0xc0];
2369         struct mlx5_ifc_rmpc_bits ctx;
2370 };
2371
2372 struct mlx5_ifc_create_tis_out_bits {
2373         u8 status[0x8];
2374         u8 reserved_at_8[0x18];
2375         u8 syndrome[0x20];
2376         u8 reserved_at_40[0x8];
2377         u8 tisn[0x18];
2378         u8 reserved_at_60[0x20];
2379 };
2380
2381 struct mlx5_ifc_create_tis_in_bits {
2382         u8 opcode[0x10];
2383         u8 uid[0x10];
2384         u8 reserved_at_20[0x10];
2385         u8 op_mod[0x10];
2386         u8 reserved_at_40[0xc0];
2387         struct mlx5_ifc_tisc_bits ctx;
2388 };
2389
2390 enum {
2391         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
2392         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
2393         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
2394         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
2395 };
2396
2397 struct mlx5_ifc_modify_rq_in_bits {
2398         u8 opcode[0x10];
2399         u8 uid[0x10];
2400         u8 reserved_at_20[0x10];
2401         u8 op_mod[0x10];
2402         u8 rq_state[0x4];
2403         u8 reserved_at_44[0x4];
2404         u8 rqn[0x18];
2405         u8 reserved_at_60[0x20];
2406         u8 modify_bitmask[0x40];
2407         u8 reserved_at_c0[0x40];
2408         struct mlx5_ifc_rqc_bits ctx;
2409 };
2410
2411 enum {
2412         MLX5_L3_PROT_TYPE_IPV4 = 0,
2413         MLX5_L3_PROT_TYPE_IPV6 = 1,
2414 };
2415
2416 enum {
2417         MLX5_L4_PROT_TYPE_TCP = 0,
2418         MLX5_L4_PROT_TYPE_UDP = 1,
2419 };
2420
2421 enum {
2422         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
2423         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
2424         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
2425         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
2426         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
2427 };
2428
2429 struct mlx5_ifc_rx_hash_field_select_bits {
2430         u8 l3_prot_type[0x1];
2431         u8 l4_prot_type[0x1];
2432         u8 selected_fields[0x1e];
2433 };
2434
2435 enum {
2436         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2437         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2438 };
2439
2440 enum {
2441         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2442         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2443 };
2444
2445 enum {
2446         MLX5_RX_HASH_FN_NONE           = 0x0,
2447         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2448         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2449 };
2450
2451 enum {
2452         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
2453         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
2454 };
2455
2456 enum {
2457         MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4    = 0x0,
2458         MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2  = 0x1,
2459 };
2460
2461 struct mlx5_ifc_tirc_bits {
2462         u8 reserved_at_0[0x20];
2463         u8 disp_type[0x4];
2464         u8 reserved_at_24[0x1c];
2465         u8 reserved_at_40[0x40];
2466         u8 reserved_at_80[0x4];
2467         u8 lro_timeout_period_usecs[0x10];
2468         u8 lro_enable_mask[0x4];
2469         u8 lro_max_msg_sz[0x8];
2470         u8 reserved_at_a0[0x40];
2471         u8 reserved_at_e0[0x8];
2472         u8 inline_rqn[0x18];
2473         u8 rx_hash_symmetric[0x1];
2474         u8 reserved_at_101[0x1];
2475         u8 tunneled_offload_en[0x1];
2476         u8 reserved_at_103[0x5];
2477         u8 indirect_table[0x18];
2478         u8 rx_hash_fn[0x4];
2479         u8 reserved_at_124[0x2];
2480         u8 self_lb_block[0x2];
2481         u8 transport_domain[0x18];
2482         u8 rx_hash_toeplitz_key[10][0x20];
2483         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2484         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2485         u8 reserved_at_2c0[0x4c0];
2486 };
2487
2488 struct mlx5_ifc_create_tir_out_bits {
2489         u8 status[0x8];
2490         u8 reserved_at_8[0x18];
2491         u8 syndrome[0x20];
2492         u8 reserved_at_40[0x8];
2493         u8 tirn[0x18];
2494         u8 reserved_at_60[0x20];
2495 };
2496
2497 struct mlx5_ifc_create_tir_in_bits {
2498         u8 opcode[0x10];
2499         u8 uid[0x10];
2500         u8 reserved_at_20[0x10];
2501         u8 op_mod[0x10];
2502         u8 reserved_at_40[0xc0];
2503         struct mlx5_ifc_tirc_bits ctx;
2504 };
2505
2506 enum {
2507         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0,
2508         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1,
2509         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2,
2510         /* bit 3 - tunneled_offload_en modify not supported. */
2511         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4,
2512 };
2513
2514 struct mlx5_ifc_modify_tir_out_bits {
2515         u8 status[0x8];
2516         u8 reserved_at_8[0x18];
2517         u8 syndrome[0x20];
2518         u8 reserved_at_40[0x40];
2519 };
2520
2521 struct mlx5_ifc_modify_tir_in_bits {
2522         u8 opcode[0x10];
2523         u8 uid[0x10];
2524         u8 reserved_at_20[0x10];
2525         u8 op_mod[0x10];
2526         u8 reserved_at_40[0x8];
2527         u8 tirn[0x18];
2528         u8 reserved_at_60[0x20];
2529         u8 modify_bitmask[0x40];
2530         u8 reserved_at_c0[0x40];
2531         struct mlx5_ifc_tirc_bits ctx;
2532 };
2533
2534 enum {
2535         MLX5_INLINE_Q_TYPE_RQ = 0x0,
2536         MLX5_INLINE_Q_TYPE_VIRTQ = 0x1,
2537 };
2538
2539 struct mlx5_ifc_rq_num_bits {
2540         u8 reserved_at_0[0x8];
2541         u8 rq_num[0x18];
2542 };
2543
2544 struct mlx5_ifc_rqtc_bits {
2545         u8 reserved_at_0[0xa5];
2546         u8 list_q_type[0x3];
2547         u8 reserved_at_a8[0x8];
2548         u8 rqt_max_size[0x10];
2549         u8 reserved_at_c0[0x10];
2550         u8 rqt_actual_size[0x10];
2551         u8 reserved_at_e0[0x6a0];
2552         struct mlx5_ifc_rq_num_bits rq_num[];
2553 };
2554
2555 struct mlx5_ifc_create_rqt_out_bits {
2556         u8 status[0x8];
2557         u8 reserved_at_8[0x18];
2558         u8 syndrome[0x20];
2559         u8 reserved_at_40[0x8];
2560         u8 rqtn[0x18];
2561         u8 reserved_at_60[0x20];
2562 };
2563
2564 #ifdef PEDANTIC
2565 #pragma GCC diagnostic ignored "-Wpedantic"
2566 #endif
2567 struct mlx5_ifc_create_rqt_in_bits {
2568         u8 opcode[0x10];
2569         u8 uid[0x10];
2570         u8 reserved_at_20[0x10];
2571         u8 op_mod[0x10];
2572         u8 reserved_at_40[0xc0];
2573         struct mlx5_ifc_rqtc_bits rqt_context;
2574 };
2575
2576 struct mlx5_ifc_modify_rqt_in_bits {
2577         u8 opcode[0x10];
2578         u8 uid[0x10];
2579         u8 reserved_at_20[0x10];
2580         u8 op_mod[0x10];
2581         u8 reserved_at_40[0x8];
2582         u8 rqtn[0x18];
2583         u8 reserved_at_60[0x20];
2584         u8 modify_bitmask[0x40];
2585         u8 reserved_at_c0[0x40];
2586         struct mlx5_ifc_rqtc_bits rqt_context;
2587 };
2588 #ifdef PEDANTIC
2589 #pragma GCC diagnostic error "-Wpedantic"
2590 #endif
2591
2592 struct mlx5_ifc_modify_rqt_out_bits {
2593         u8 status[0x8];
2594         u8 reserved_at_8[0x18];
2595         u8 syndrome[0x20];
2596         u8 reserved_at_40[0x40];
2597 };
2598
2599 enum {
2600         MLX5_SQC_STATE_RST  = 0x0,
2601         MLX5_SQC_STATE_RDY  = 0x1,
2602         MLX5_SQC_STATE_ERR  = 0x3,
2603 };
2604
2605 struct mlx5_ifc_sqc_bits {
2606         u8 rlky[0x1];
2607         u8 cd_master[0x1];
2608         u8 fre[0x1];
2609         u8 flush_in_error_en[0x1];
2610         u8 allow_multi_pkt_send_wqe[0x1];
2611         u8 min_wqe_inline_mode[0x3];
2612         u8 state[0x4];
2613         u8 reg_umr[0x1];
2614         u8 allow_swp[0x1];
2615         u8 hairpin[0x1];
2616         u8 non_wire[0x1];
2617         u8 static_sq_wq[0x1];
2618         u8 reserved_at_11[0x9];
2619         u8 ts_format[0x02];
2620         u8 reserved_at_1c[0x4];
2621         u8 reserved_at_20[0x8];
2622         u8 user_index[0x18];
2623         u8 reserved_at_40[0x8];
2624         u8 cqn[0x18];
2625         u8 reserved_at_60[0x8];
2626         u8 hairpin_peer_rq[0x18];
2627         u8 reserved_at_80[0x10];
2628         u8 hairpin_peer_vhca[0x10];
2629         u8 reserved_at_a0[0x50];
2630         u8 packet_pacing_rate_limit_index[0x10];
2631         u8 tis_lst_sz[0x10];
2632         u8 reserved_at_110[0x10];
2633         u8 reserved_at_120[0x40];
2634         u8 reserved_at_160[0x8];
2635         u8 tis_num_0[0x18];
2636         struct mlx5_ifc_wq_bits wq;
2637 };
2638
2639 struct mlx5_ifc_query_sq_in_bits {
2640         u8 opcode[0x10];
2641         u8 reserved_at_10[0x10];
2642         u8 reserved_at_20[0x10];
2643         u8 op_mod[0x10];
2644         u8 reserved_at_40[0x8];
2645         u8 sqn[0x18];
2646         u8 reserved_at_60[0x20];
2647 };
2648
2649 struct mlx5_ifc_modify_sq_out_bits {
2650         u8 status[0x8];
2651         u8 reserved_at_8[0x18];
2652         u8 syndrome[0x20];
2653         u8 reserved_at_40[0x40];
2654 };
2655
2656 struct mlx5_ifc_modify_sq_in_bits {
2657         u8 opcode[0x10];
2658         u8 uid[0x10];
2659         u8 reserved_at_20[0x10];
2660         u8 op_mod[0x10];
2661         u8 sq_state[0x4];
2662         u8 reserved_at_44[0x4];
2663         u8 sqn[0x18];
2664         u8 reserved_at_60[0x20];
2665         u8 modify_bitmask[0x40];
2666         u8 reserved_at_c0[0x40];
2667         struct mlx5_ifc_sqc_bits ctx;
2668 };
2669
2670 struct mlx5_ifc_create_sq_out_bits {
2671         u8 status[0x8];
2672         u8 reserved_at_8[0x18];
2673         u8 syndrome[0x20];
2674         u8 reserved_at_40[0x8];
2675         u8 sqn[0x18];
2676         u8 reserved_at_60[0x20];
2677 };
2678
2679 struct mlx5_ifc_create_sq_in_bits {
2680         u8 opcode[0x10];
2681         u8 uid[0x10];
2682         u8 reserved_at_20[0x10];
2683         u8 op_mod[0x10];
2684         u8 reserved_at_40[0xc0];
2685         struct mlx5_ifc_sqc_bits ctx;
2686 };
2687
2688 enum {
2689         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
2690         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
2691         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
2692         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
2693         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
2694 };
2695
2696 struct mlx5_ifc_flow_meter_parameters_bits {
2697         u8 valid[0x1];
2698         u8 bucket_overflow[0x1];
2699         u8 start_color[0x2];
2700         u8 both_buckets_on_green[0x1];
2701         u8 meter_mode[0x2];
2702         u8 reserved_at_1[0x19];
2703         u8 reserved_at_2[0x20];
2704         u8 reserved_at_3[0x3];
2705         u8 cbs_exponent[0x5];
2706         u8 cbs_mantissa[0x8];
2707         u8 reserved_at_4[0x3];
2708         u8 cir_exponent[0x5];
2709         u8 cir_mantissa[0x8];
2710         u8 reserved_at_5[0x20];
2711         u8 reserved_at_6[0x3];
2712         u8 ebs_exponent[0x5];
2713         u8 ebs_mantissa[0x8];
2714         u8 reserved_at_7[0x3];
2715         u8 eir_exponent[0x5];
2716         u8 eir_mantissa[0x8];
2717         u8 reserved_at_8[0x60];
2718 };
2719 #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF)
2720 #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8
2721
2722 enum {
2723         MLX5_METER_MODE_IP_LEN = 0x0,
2724         MLX5_METER_MODE_L2_LEN = 0x1,
2725         MLX5_METER_MODE_L2_IPG_LEN = 0x2,
2726         MLX5_METER_MODE_PKT = 0x3,
2727 };
2728
2729 enum {
2730         MLX5_CQE_SIZE_64B = 0x0,
2731         MLX5_CQE_SIZE_128B = 0x1,
2732 };
2733
2734 struct mlx5_ifc_cqc_bits {
2735         u8 status[0x4];
2736         u8 as_notify[0x1];
2737         u8 initiator_src_dct[0x1];
2738         u8 dbr_umem_valid[0x1];
2739         u8 reserved_at_7[0x1];
2740         u8 cqe_sz[0x3];
2741         u8 cc[0x1];
2742         u8 reserved_at_c[0x1];
2743         u8 scqe_break_moderation_en[0x1];
2744         u8 oi[0x1];
2745         u8 cq_period_mode[0x2];
2746         u8 cqe_comp_en[0x1];
2747         u8 mini_cqe_res_format[0x2];
2748         u8 st[0x4];
2749         u8 reserved_at_18[0x1];
2750         u8 cqe_comp_layout[0x7];
2751         u8 dbr_umem_id[0x20];
2752         u8 reserved_at_40[0x14];
2753         u8 page_offset[0x6];
2754         u8 reserved_at_5a[0x2];
2755         u8 mini_cqe_res_format_ext[0x2];
2756         u8 cq_timestamp_format[0x2];
2757         u8 reserved_at_60[0x3];
2758         u8 log_cq_size[0x5];
2759         u8 uar_page[0x18];
2760         u8 reserved_at_80[0x4];
2761         u8 cq_period[0xc];
2762         u8 cq_max_count[0x10];
2763         u8 reserved_at_a0[0x18];
2764         u8 c_eqn[0x8];
2765         u8 reserved_at_c0[0x3];
2766         u8 log_page_size[0x5];
2767         u8 reserved_at_c8[0x18];
2768         u8 reserved_at_e0[0x20];
2769         u8 reserved_at_100[0x8];
2770         u8 last_notified_index[0x18];
2771         u8 reserved_at_120[0x8];
2772         u8 last_solicit_index[0x18];
2773         u8 reserved_at_140[0x8];
2774         u8 consumer_counter[0x18];
2775         u8 reserved_at_160[0x8];
2776         u8 producer_counter[0x18];
2777         u8 local_partition_id[0xc];
2778         u8 process_id[0x14];
2779         u8 reserved_at_1A0[0x20];
2780         u8 dbr_addr[0x40];
2781 };
2782
2783 struct mlx5_ifc_health_buffer_bits {
2784         u8 reserved_0[0x100];
2785         u8 assert_existptr[0x20];
2786         u8 assert_callra[0x20];
2787         u8 reserved_1[0x40];
2788         u8 fw_version[0x20];
2789         u8 hw_id[0x20];
2790         u8 reserved_2[0x20];
2791         u8 irisc_index[0x8];
2792         u8 synd[0x8];
2793         u8 ext_synd[0x10];
2794 };
2795
2796 struct mlx5_ifc_initial_seg_bits {
2797         u8 fw_rev_minor[0x10];
2798         u8 fw_rev_major[0x10];
2799         u8 cmd_interface_rev[0x10];
2800         u8 fw_rev_subminor[0x10];
2801         u8 reserved_0[0x40];
2802         u8 cmdq_phy_addr_63_32[0x20];
2803         u8 cmdq_phy_addr_31_12[0x14];
2804         u8 reserved_1[0x2];
2805         u8 nic_interface[0x2];
2806         u8 log_cmdq_size[0x4];
2807         u8 log_cmdq_stride[0x4];
2808         u8 command_doorbell_vector[0x20];
2809         u8 reserved_2[0xf00];
2810         u8 initializing[0x1];
2811         u8 nic_interface_supported[0x7];
2812         u8 reserved_4[0x18];
2813         struct mlx5_ifc_health_buffer_bits health_buffer;
2814         u8 no_dram_nic_offset[0x20];
2815         u8 reserved_5[0x6de0];
2816         u8 internal_timer_h[0x20];
2817         u8 internal_timer_l[0x20];
2818         u8 reserved_6[0x20];
2819         u8 reserved_7[0x1f];
2820         u8 clear_int[0x1];
2821         u8 health_syndrome[0x8];
2822         u8 health_counter[0x18];
2823         u8 reserved_8[0x17fc0];
2824 };
2825
2826 struct mlx5_ifc_create_cq_out_bits {
2827         u8 status[0x8];
2828         u8 reserved_at_8[0x18];
2829         u8 syndrome[0x20];
2830         u8 reserved_at_40[0x8];
2831         u8 cqn[0x18];
2832         u8 reserved_at_60[0x20];
2833 };
2834
2835 struct mlx5_ifc_create_cq_in_bits {
2836         u8 opcode[0x10];
2837         u8 uid[0x10];
2838         u8 reserved_at_20[0x10];
2839         u8 op_mod[0x10];
2840         u8 reserved_at_40[0x40];
2841         struct mlx5_ifc_cqc_bits cq_context;
2842         u8 cq_umem_offset[0x40];
2843         u8 cq_umem_id[0x20];
2844         u8 cq_umem_valid[0x1];
2845         u8 reserved_at_2e1[0x1f];
2846         u8 reserved_at_300[0x580];
2847         u8 pas[];
2848 };
2849
2850 enum {
2851         MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
2852         MLX5_GENERAL_OBJ_TYPE_DEK = 0x000c,
2853         MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
2854         MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
2855         MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d,
2856         MLX5_GENERAL_OBJ_TYPE_CREDENTIAL = 0x001e,
2857         MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN = 0x001f,
2858         MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,
2859         MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024,
2860         MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025,
2861         MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031,
2862 };
2863
2864 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
2865         u8 opcode[0x10];
2866         u8 reserved_at_10[0x20];
2867         u8 obj_type[0x10];
2868         u8 obj_id[0x20];
2869         u8 reserved_at_60[0x3];
2870         u8 log_obj_range[0x5];
2871         u8 reserved_at_58[0x18];
2872 };
2873
2874 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
2875         u8 status[0x8];
2876         u8 reserved_at_8[0x18];
2877         u8 syndrome[0x20];
2878         u8 obj_id[0x20];
2879         u8 reserved_at_60[0x20];
2880 };
2881
2882 struct mlx5_ifc_virtio_q_counters_bits {
2883         u8 modify_field_select[0x40];
2884         u8 reserved_at_40[0x40];
2885         u8 received_desc[0x40];
2886         u8 completed_desc[0x40];
2887         u8 error_cqes[0x20];
2888         u8 bad_desc_errors[0x20];
2889         u8 exceed_max_chain[0x20];
2890         u8 invalid_buffer[0x20];
2891         u8 reserved_at_180[0x50];
2892 };
2893
2894 struct mlx5_ifc_geneve_tlv_option_bits {
2895         u8 modify_field_select[0x40];
2896         u8 reserved_at_40[0x18];
2897         u8 geneve_option_fte_index[0x8];
2898         u8 option_class[0x10];
2899         u8 option_type[0x8];
2900         u8 reserved_at_78[0x3];
2901         u8 option_data_length[0x5];
2902         u8 reserved_at_80[0x180];
2903 };
2904
2905 struct mlx5_ifc_create_virtio_q_counters_in_bits {
2906         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2907         struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2908 };
2909
2910 struct mlx5_ifc_query_virtio_q_counters_out_bits {
2911         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2912         struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2913 };
2914
2915 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
2916         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2917         struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
2918 };
2919
2920 enum {
2921         MLX5_CRYPTO_KEY_SIZE_128b = 0x0,
2922         MLX5_CRYPTO_KEY_SIZE_256b = 0x1,
2923 };
2924
2925 enum {
2926         MLX5_CRYPTO_KEY_PURPOSE_TLS     = 0x1,
2927         MLX5_CRYPTO_KEY_PURPOSE_IPSEC   = 0x2,
2928         MLX5_CRYPTO_KEY_PURPOSE_AES_XTS = 0x3,
2929         MLX5_CRYPTO_KEY_PURPOSE_MACSEC  = 0x4,
2930         MLX5_CRYPTO_KEY_PURPOSE_GCM     = 0x5,
2931         MLX5_CRYPTO_KEY_PURPOSE_PSP     = 0x6,
2932 };
2933
2934 struct mlx5_ifc_dek_bits {
2935         u8 modify_field_select[0x40];
2936         u8 state[0x8];
2937         u8 reserved_at_48[0xc];
2938         u8 key_size[0x4];
2939         u8 has_keytag[0x1];
2940         u8 reserved_at_59[0x3];
2941         u8 key_purpose[0x4];
2942         u8 reserved_at_60[0x8];
2943         u8 pd[0x18];
2944         u8 reserved_at_80[0x100];
2945         u8 opaque[0x40];
2946         u8 reserved_at_1c0[0x40];
2947         u8 key[0x400];
2948         u8 reserved_at_600[0x200];
2949 };
2950
2951 struct mlx5_ifc_create_dek_in_bits {
2952         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2953         struct mlx5_ifc_dek_bits dek;
2954 };
2955
2956 struct mlx5_ifc_import_kek_bits {
2957         u8 modify_field_select[0x40];
2958         u8 state[0x8];
2959         u8 reserved_at_48[0xc];
2960         u8 key_size[0x4];
2961         u8 reserved_at_58[0x1a8];
2962         u8 key[0x400];
2963         u8 reserved_at_600[0x200];
2964 };
2965
2966 struct mlx5_ifc_create_import_kek_in_bits {
2967         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2968         struct mlx5_ifc_import_kek_bits import_kek;
2969 };
2970
2971 enum {
2972         MLX5_CREDENTIAL_ROLE_OFFICER = 0x0,
2973         MLX5_CREDENTIAL_ROLE_USER = 0x1,
2974 };
2975
2976 struct mlx5_ifc_credential_bits {
2977         u8 modify_field_select[0x40];
2978         u8 state[0x8];
2979         u8 reserved_at_48[0x10];
2980         u8 credential_role[0x8];
2981         u8 reserved_at_60[0x1a0];
2982         u8 credential[0x180];
2983         u8 reserved_at_380[0x480];
2984 };
2985
2986 struct mlx5_ifc_create_credential_in_bits {
2987         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2988         struct mlx5_ifc_credential_bits credential;
2989 };
2990
2991 struct mlx5_ifc_crypto_login_bits {
2992         u8 modify_field_select[0x40];
2993         u8 reserved_at_40[0x48];
2994         u8 credential_pointer[0x18];
2995         u8 reserved_at_a0[0x8];
2996         u8 session_import_kek_ptr[0x18];
2997         u8 reserved_at_c0[0x140];
2998         u8 credential[0x180];
2999         u8 reserved_at_380[0x480];
3000 };
3001
3002 struct mlx5_ifc_create_crypto_login_in_bits {
3003         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3004         struct mlx5_ifc_crypto_login_bits crypto_login;
3005 };
3006
3007 enum {
3008         MLX5_VIRTQ_STATE_INIT = 0,
3009         MLX5_VIRTQ_STATE_RDY = 1,
3010         MLX5_VIRTQ_STATE_SUSPEND = 2,
3011         MLX5_VIRTQ_STATE_ERROR = 3,
3012 };
3013
3014 enum {
3015         MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),
3016         MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),
3017         MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),
3018 };
3019
3020 struct mlx5_ifc_virtio_q_bits {
3021         u8 virtio_q_type[0x8];
3022         u8 reserved_at_8[0x5];
3023         u8 event_mode[0x3];
3024         u8 queue_index[0x10];
3025         u8 full_emulation[0x1];
3026         u8 virtio_version_1_0[0x1];
3027         u8 reserved_at_22[0x2];
3028         u8 offload_type[0x4];
3029         u8 event_qpn_or_msix[0x18];
3030         u8 doorbell_stride_idx[0x10];
3031         u8 queue_size[0x10];
3032         u8 device_emulation_id[0x20];
3033         u8 desc_addr[0x40];
3034         u8 used_addr[0x40];
3035         u8 available_addr[0x40];
3036         u8 virtio_q_mkey[0x20];
3037         u8 reserved_at_160[0x18];
3038         u8 error_type[0x8];
3039         u8 umem_1_id[0x20];
3040         u8 umem_1_size[0x20];
3041         u8 umem_1_offset[0x40];
3042         u8 umem_2_id[0x20];
3043         u8 umem_2_size[0x20];
3044         u8 umem_2_offset[0x40];
3045         u8 umem_3_id[0x20];
3046         u8 umem_3_size[0x20];
3047         u8 umem_3_offset[0x40];
3048         u8 counter_set_id[0x20];
3049         u8 reserved_at_320[0x8];
3050         u8 pd[0x18];
3051         u8 reserved_at_340[0x2];
3052         u8 queue_period_mode[0x2];
3053         u8 queue_period_us[0xc];
3054         u8 queue_max_count[0x10];
3055         u8 reserved_at_360[0xa0];
3056 };
3057
3058 struct mlx5_ifc_virtio_net_q_bits {
3059         u8 modify_field_select[0x40];
3060         u8 reserved_at_40[0x40];
3061         u8 tso_ipv4[0x1];
3062         u8 tso_ipv6[0x1];
3063         u8 tx_csum[0x1];
3064         u8 rx_csum[0x1];
3065         u8 reserved_at_84[0x6];
3066         u8 dirty_bitmap_dump_enable[0x1];
3067         u8 vhost_log_page[0x5];
3068         u8 reserved_at_90[0xc];
3069         u8 state[0x4];
3070         u8 reserved_at_a0[0x8];
3071         u8 tisn_or_qpn[0x18];
3072         u8 dirty_bitmap_mkey[0x20];
3073         u8 dirty_bitmap_size[0x20];
3074         u8 dirty_bitmap_addr[0x40];
3075         u8 hw_available_index[0x10];
3076         u8 hw_used_index[0x10];
3077         u8 reserved_at_160[0xa0];
3078         struct mlx5_ifc_virtio_q_bits virtio_q_context;
3079 };
3080
3081 struct mlx5_ifc_create_virtq_in_bits {
3082         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3083         struct mlx5_ifc_virtio_net_q_bits virtq;
3084 };
3085
3086 struct mlx5_ifc_query_virtq_out_bits {
3087         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3088         struct mlx5_ifc_virtio_net_q_bits virtq;
3089 };
3090
3091 struct mlx5_ifc_flow_hit_aso_bits {
3092         u8 modify_field_select[0x40];
3093         u8 reserved_at_40[0x48];
3094         u8 access_pd[0x18];
3095         u8 reserved_at_a0[0x160];
3096         u8 flag[0x200];
3097 };
3098
3099 struct mlx5_ifc_create_flow_hit_aso_in_bits {
3100         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3101         struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso;
3102 };
3103
3104 struct mlx5_ifc_flow_meter_aso_bits {
3105         u8 modify_field_select[0x40];
3106         u8 reserved_at_40[0x48];
3107         u8 access_pd[0x18];
3108         u8 reserved_at_a0[0x160];
3109         u8 parameters[0x200];
3110 };
3111
3112 struct mlx5_ifc_create_flow_meter_aso_in_bits {
3113         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3114         struct mlx5_ifc_flow_meter_aso_bits flow_meter_aso;
3115 };
3116
3117 struct mlx5_ifc_tcp_window_params_bits {
3118         u8 max_ack[0x20];
3119         u8 max_win[0x20];
3120         u8 reply_end[0x20];
3121         u8 sent_end[0x20];
3122 };
3123
3124 struct mlx5_ifc_conn_track_aso_bits {
3125         struct mlx5_ifc_tcp_window_params_bits reply_dir; /* End of DW3. */
3126         struct mlx5_ifc_tcp_window_params_bits original_dir; /* End of DW7. */
3127         u8 last_end[0x20]; /* End of DW8. */
3128         u8 last_ack[0x20]; /* End of DW9. */
3129         u8 last_seq[0x20]; /* End of DW10. */
3130         u8 last_win[0x10];
3131         u8 reserved_at_170[0xa];
3132         u8 last_dir[0x1];
3133         u8 last_index[0x5]; /* End of DW11. */
3134         u8 reserved_at_180[0x40]; /* End of DW13. */
3135         u8 reply_direction_tcp_scale[0x4];
3136         u8 reply_direction_tcp_close_initiated[0x1];
3137         u8 reply_direction_tcp_liberal_enabled[0x1];
3138         u8 reply_direction_tcp_data_unacked[0x1];
3139         u8 reply_direction_tcp_max_ack[0x1];
3140         u8 reserved_at_1c8[0x8];
3141         u8 original_direction_tcp_scale[0x4];
3142         u8 original_direction_tcp_close_initiated[0x1];
3143         u8 original_direction_tcp_liberal_enabled[0x1];
3144         u8 original_direction_tcp_data_unacked[0x1];
3145         u8 original_direction_tcp_max_ack[0x1];
3146         u8 reserved_at_1d8[0x8]; /* End of DW14. */
3147         u8 valid[0x1];
3148         u8 state[0x3];
3149         u8 freeze_track[0x1];
3150         u8 reserved_at_1e5[0xb];
3151         u8 reserved_at_1f0[0x1];
3152         u8 connection_assured[0x1];
3153         u8 sack_permitted[0x1];
3154         u8 challenged_acked[0x1];
3155         u8 heartbeat[0x1];
3156         u8 max_ack_window[0x3];
3157         u8 reserved_at_1f8[0x1];
3158         u8 retransmission_counter[0x3];
3159         u8 retranmission_limit_exceeded[0x1];
3160         u8 retranmission_limit[0x3]; /* End of DW15. */
3161 };
3162
3163 struct mlx5_ifc_conn_track_offload_bits {
3164         u8 modify_field_select[0x40];
3165         u8 reserved_at_40[0x40];
3166         u8 reserved_at_80[0x8];
3167         u8 conn_track_aso_access_pd[0x18];
3168         u8 reserved_at_a0[0x160];
3169         struct mlx5_ifc_conn_track_aso_bits conn_track_aso;
3170 };
3171
3172 struct mlx5_ifc_create_conn_track_aso_in_bits {
3173         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3174         struct mlx5_ifc_conn_track_offload_bits conn_track_offload;
3175 };
3176
3177 enum mlx5_access_aso_opc_mod {
3178         ASO_OPC_MOD_IPSEC = 0x0,
3179         ASO_OPC_MOD_CONNECTION_TRACKING = 0x1,
3180         ASO_OPC_MOD_POLICER = 0x2,
3181         ASO_OPC_MOD_RACE_AVOIDANCE = 0x3,
3182         ASO_OPC_MOD_FLOW_HIT = 0x4,
3183 };
3184
3185 #define ASO_CSEG_DATA_MASK_MODE_OFFSET  30
3186
3187 enum mlx5_aso_data_mask_mode {
3188         BITWISE_64BIT = 0x0,
3189         BYTEWISE_64BYTE = 0x1,
3190         CALCULATED_64BYTE = 0x2,
3191 };
3192
3193 #define ASO_CSEG_COND_0_OPER_OFFSET     20
3194 #define ASO_CSEG_COND_1_OPER_OFFSET     16
3195
3196 enum mlx5_aso_pre_cond_op {
3197         ASO_OP_ALWAYS_FALSE = 0x0,
3198         ASO_OP_ALWAYS_TRUE = 0x1,
3199         ASO_OP_EQUAL = 0x2,
3200         ASO_OP_NOT_EQUAL = 0x3,
3201         ASO_OP_GREATER_OR_EQUAL = 0x4,
3202         ASO_OP_LESSER_OR_EQUAL = 0x5,
3203         ASO_OP_LESSER = 0x6,
3204         ASO_OP_GREATER = 0x7,
3205         ASO_OP_CYCLIC_GREATER = 0x8,
3206         ASO_OP_CYCLIC_LESSER = 0x9,
3207 };
3208
3209 #define ASO_CSEG_COND_OPER_OFFSET       6
3210
3211 enum mlx5_aso_op {
3212         ASO_OPER_LOGICAL_AND = 0x0,
3213         ASO_OPER_LOGICAL_OR = 0x1,
3214 };
3215
3216 /* ASO WQE CTRL segment. */
3217 struct mlx5_aso_cseg {
3218         uint32_t va_h;
3219         uint32_t va_l_r;
3220         uint32_t lkey;
3221         uint32_t operand_masks;
3222         uint32_t condition_0_data;
3223         uint32_t condition_0_mask;
3224         uint32_t condition_1_data;
3225         uint32_t condition_1_mask;
3226         uint64_t bitwise_data;
3227         uint64_t data_mask;
3228 } __rte_packed;
3229
3230 /* A meter data segment - 2 per ASO WQE. */
3231 struct mlx5_aso_mtr_dseg {
3232         uint32_t v_bo_sc_bbog_mm;
3233         /*
3234          * bit 31: valid, 30: bucket overflow, 28-29: start color,
3235          * 27: both buckets on green, 24-25: meter mode.
3236          */
3237         uint32_t reserved;
3238         uint32_t cbs_cir;
3239         /*
3240          * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa,
3241          * bit 8-12: cir_exponent, bit 0-7 cir_mantissa.
3242          */
3243         uint32_t c_tokens;
3244         uint32_t ebs_eir;
3245         /*
3246          * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa,
3247          * bit 8-12: eir_exponent, bit 0-7 eir_mantissa.
3248          */
3249         uint32_t e_tokens;
3250         uint64_t timestamp;
3251 } __rte_packed;
3252
3253 #define ASO_DSEG_VALID_OFFSET 31
3254 #define ASO_DSEG_BO_OFFSET 30
3255 #define ASO_DSEG_SC_OFFSET 28
3256 #define ASO_DSEG_BBOG_OFFSET 27
3257 #define ASO_DSEG_MTR_MODE 24
3258 #define ASO_DSEG_CBS_EXP_OFFSET 24
3259 #define ASO_DSEG_CBS_MAN_OFFSET 16
3260 #define ASO_DSEG_XIR_EXP_MASK 0x1F
3261 #define ASO_DSEG_XIR_EXP_OFFSET 8
3262 #define ASO_DSEG_EBS_EXP_OFFSET 24
3263 #define ASO_DSEG_EBS_MAN_OFFSET 16
3264 #define ASO_DSEG_EXP_MASK 0x1F
3265 #define ASO_DSEG_MAN_MASK 0xFF
3266
3267 #define MLX5_ASO_WQE_DSEG_SIZE  0x40
3268 #define MLX5_ASO_METERS_PER_WQE 2
3269 #define MLX5_ASO_MTRS_PER_POOL 128
3270
3271 /* ASO WQE data segment. */
3272 struct mlx5_aso_dseg {
3273         union {
3274                 uint8_t data[MLX5_ASO_WQE_DSEG_SIZE];
3275                 struct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE];
3276         };
3277 } __rte_packed;
3278
3279 /* ASO WQE. */
3280 struct mlx5_aso_wqe {
3281         struct mlx5_wqe_cseg general_cseg;
3282         struct mlx5_aso_cseg aso_cseg;
3283         struct mlx5_aso_dseg aso_dseg;
3284 } __rte_packed;
3285
3286 enum {
3287         MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
3288 };
3289
3290 enum {
3291         MLX5_QP_ST_RC = 0x0,
3292 };
3293
3294 enum {
3295         MLX5_QP_PM_MIGRATED = 0x3,
3296 };
3297
3298 enum {
3299         MLX5_NON_ZERO_RQ = 0x0,
3300         MLX5_SRQ_RQ = 0x1,
3301         MLX5_CRQ_RQ = 0x2,
3302         MLX5_ZERO_LEN_RQ = 0x3,
3303 };
3304
3305 struct mlx5_ifc_ads_bits {
3306         u8 fl[0x1];
3307         u8 free_ar[0x1];
3308         u8 reserved_at_2[0xe];
3309         u8 pkey_index[0x10];
3310         u8 reserved_at_20[0x8];
3311         u8 grh[0x1];
3312         u8 mlid[0x7];
3313         u8 rlid[0x10];
3314         u8 ack_timeout[0x5];
3315         u8 reserved_at_45[0x3];
3316         u8 src_addr_index[0x8];
3317         u8 reserved_at_50[0x4];
3318         u8 stat_rate[0x4];
3319         u8 hop_limit[0x8];
3320         u8 reserved_at_60[0x4];
3321         u8 tclass[0x8];
3322         u8 flow_label[0x14];
3323         u8 rgid_rip[16][0x8];
3324         u8 reserved_at_100[0x4];
3325         u8 f_dscp[0x1];
3326         u8 f_ecn[0x1];
3327         u8 reserved_at_106[0x1];
3328         u8 f_eth_prio[0x1];
3329         u8 ecn[0x2];
3330         u8 dscp[0x6];
3331         u8 udp_sport[0x10];
3332         u8 dei_cfi[0x1];
3333         u8 eth_prio[0x3];
3334         u8 sl[0x4];
3335         u8 vhca_port_num[0x8];
3336         u8 rmac_47_32[0x10];
3337         u8 rmac_31_0[0x20];
3338 };
3339
3340 struct mlx5_ifc_qpc_bits {
3341         u8 state[0x4];
3342         u8 lag_tx_port_affinity[0x4];
3343         u8 st[0x8];
3344         u8 reserved_at_10[0x3];
3345         u8 pm_state[0x2];
3346         u8 reserved_at_15[0x1];
3347         u8 req_e2e_credit_mode[0x2];
3348         u8 offload_type[0x4];
3349         u8 end_padding_mode[0x2];
3350         u8 reserved_at_1e[0x2];
3351         u8 wq_signature[0x1];
3352         u8 block_lb_mc[0x1];
3353         u8 atomic_like_write_en[0x1];
3354         u8 latency_sensitive[0x1];
3355         u8 reserved_at_24[0x1];
3356         u8 drain_sigerr[0x1];
3357         u8 reserved_at_26[0x2];
3358         u8 pd[0x18];
3359         u8 mtu[0x3];
3360         u8 log_msg_max[0x5];
3361         u8 reserved_at_48[0x1];
3362         u8 log_rq_size[0x4];
3363         u8 log_rq_stride[0x3];
3364         u8 no_sq[0x1];
3365         u8 log_sq_size[0x4];
3366         u8 reserved_at_55[0x3];
3367         u8 ts_format[0x2];
3368         u8 reserved_at_5a[0x1];
3369         u8 rlky[0x1];
3370         u8 ulp_stateless_offload_mode[0x4];
3371         u8 counter_set_id[0x8];
3372         u8 uar_page[0x18];
3373         u8 reserved_at_80[0x8];
3374         u8 user_index[0x18];
3375         u8 reserved_at_a0[0x3];
3376         u8 log_page_size[0x5];
3377         u8 remote_qpn[0x18];
3378         struct mlx5_ifc_ads_bits primary_address_path;
3379         struct mlx5_ifc_ads_bits secondary_address_path;
3380         u8 log_ack_req_freq[0x4];
3381         u8 reserved_at_384[0x4];
3382         u8 log_sra_max[0x3];
3383         u8 reserved_at_38b[0x2];
3384         u8 retry_count[0x3];
3385         u8 rnr_retry[0x3];
3386         u8 reserved_at_393[0x1];
3387         u8 fre[0x1];
3388         u8 cur_rnr_retry[0x3];
3389         u8 cur_retry_count[0x3];
3390         u8 reserved_at_39b[0x5];
3391         u8 reserved_at_3a0[0x20];
3392         u8 reserved_at_3c0[0x8];
3393         u8 next_send_psn[0x18];
3394         u8 reserved_at_3e0[0x8];
3395         u8 cqn_snd[0x18];
3396         u8 reserved_at_400[0x8];
3397         u8 deth_sqpn[0x18];
3398         u8 reserved_at_420[0x20];
3399         u8 reserved_at_440[0x8];
3400         u8 last_acked_psn[0x18];
3401         u8 reserved_at_460[0x8];
3402         u8 ssn[0x18];
3403         u8 reserved_at_480[0x8];
3404         u8 log_rra_max[0x3];
3405         u8 reserved_at_48b[0x1];
3406         u8 atomic_mode[0x4];
3407         u8 rre[0x1];
3408         u8 rwe[0x1];
3409         u8 rae[0x1];
3410         u8 reserved_at_493[0x1];
3411         u8 page_offset[0x6];
3412         u8 reserved_at_49a[0x3];
3413         u8 cd_slave_receive[0x1];
3414         u8 cd_slave_send[0x1];
3415         u8 cd_master[0x1];
3416         u8 reserved_at_4a0[0x3];
3417         u8 min_rnr_nak[0x5];
3418         u8 next_rcv_psn[0x18];
3419         u8 reserved_at_4c0[0x8];
3420         u8 xrcd[0x18];
3421         u8 reserved_at_4e0[0x8];
3422         u8 cqn_rcv[0x18];
3423         u8 dbr_addr[0x40];
3424         u8 q_key[0x20];
3425         u8 reserved_at_560[0x5];
3426         u8 rq_type[0x3];
3427         u8 srqn_rmpn_xrqn[0x18];
3428         u8 reserved_at_580[0x8];
3429         u8 rmsn[0x18];
3430         u8 hw_sq_wqebb_counter[0x10];
3431         u8 sw_sq_wqebb_counter[0x10];
3432         u8 hw_rq_counter[0x20];
3433         u8 sw_rq_counter[0x20];
3434         u8 reserved_at_600[0x20];
3435         u8 reserved_at_620[0xf];
3436         u8 cgs[0x1];
3437         u8 cs_req[0x8];
3438         u8 cs_res[0x8];
3439         u8 dc_access_key[0x40];
3440         u8 reserved_at_680[0x3];
3441         u8 dbr_umem_valid[0x1];
3442         u8 reserved_at_684[0x9c];
3443         u8 dbr_umem_id[0x20];
3444 };
3445
3446 struct mlx5_ifc_create_qp_out_bits {
3447         u8 status[0x8];
3448         u8 reserved_at_8[0x18];
3449         u8 syndrome[0x20];
3450         u8 reserved_at_40[0x8];
3451         u8 qpn[0x18];
3452         u8 reserved_at_60[0x20];
3453 };
3454
3455 struct mlx5_ifc_qpc_extension_bits {
3456         u8 reserved_at_0[0x2];
3457         u8 mmo[0x1];
3458         u8 reserved_at_3[0x5fd];
3459 };
3460
3461 #ifdef PEDANTIC
3462 #pragma GCC diagnostic ignored "-Wpedantic"
3463 #endif
3464 struct mlx5_ifc_qpc_pas_list_bits {
3465         u8 pas[0][0x40];
3466 };
3467
3468 #ifdef PEDANTIC
3469 #pragma GCC diagnostic ignored "-Wpedantic"
3470 #endif
3471 struct mlx5_ifc_qpc_extension_and_pas_list_bits {
3472         struct mlx5_ifc_qpc_extension_bits qpc_data_extension;
3473         u8 pas[0][0x40];
3474 };
3475
3476
3477 #ifdef PEDANTIC
3478 #pragma GCC diagnostic ignored "-Wpedantic"
3479 #endif
3480 struct mlx5_ifc_create_qp_in_bits {
3481         u8 opcode[0x10];
3482         u8 uid[0x10];
3483         u8 reserved_at_20[0x10];
3484         u8 op_mod[0x10];
3485         u8 qpc_ext[0x1];
3486         u8 reserved_at_41[0x3f];
3487         u8 opt_param_mask[0x20];
3488         u8 reserved_at_a0[0x20];
3489         struct mlx5_ifc_qpc_bits qpc;
3490         u8 wq_umem_offset[0x40];
3491         u8 wq_umem_id[0x20];
3492         u8 wq_umem_valid[0x1];
3493         u8 reserved_at_861[0x1f];
3494         union {
3495                 struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list;
3496                 struct mlx5_ifc_qpc_extension_and_pas_list_bits
3497                                         qpc_extension_and_pas_list;
3498         };
3499 };
3500 #ifdef PEDANTIC
3501 #pragma GCC diagnostic error "-Wpedantic"
3502 #endif
3503
3504 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3505         u8 status[0x8];
3506         u8 reserved_at_8[0x18];
3507         u8 syndrome[0x20];
3508         u8 reserved_at_40[0x40];
3509 };
3510
3511 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3512         u8 opcode[0x10];
3513         u8 uid[0x10];
3514         u8 reserved_at_20[0x10];
3515         u8 op_mod[0x10];
3516         u8 reserved_at_40[0x8];
3517         u8 qpn[0x18];
3518         u8 reserved_at_60[0x20];
3519         u8 opt_param_mask[0x20];
3520         u8 reserved_at_a0[0x20];
3521         struct mlx5_ifc_qpc_bits qpc;
3522         u8 reserved_at_800[0x80];
3523 };
3524
3525 struct mlx5_ifc_sqd2rts_qp_out_bits {
3526         u8 status[0x8];
3527         u8 reserved_at_8[0x18];
3528         u8 syndrome[0x20];
3529         u8 reserved_at_40[0x40];
3530 };
3531
3532 struct mlx5_ifc_sqd2rts_qp_in_bits {
3533         u8 opcode[0x10];
3534         u8 uid[0x10];
3535         u8 reserved_at_20[0x10];
3536         u8 op_mod[0x10];
3537         u8 reserved_at_40[0x8];
3538         u8 qpn[0x18];
3539         u8 reserved_at_60[0x20];
3540         u8 opt_param_mask[0x20];
3541         u8 reserved_at_a0[0x20];
3542         struct mlx5_ifc_qpc_bits qpc;
3543         u8 reserved_at_800[0x80];
3544 };
3545
3546 struct mlx5_ifc_rts2rts_qp_out_bits {
3547         u8 status[0x8];
3548         u8 reserved_at_8[0x18];
3549         u8 syndrome[0x20];
3550         u8 reserved_at_40[0x40];
3551 };
3552
3553 struct mlx5_ifc_rts2rts_qp_in_bits {
3554         u8 opcode[0x10];
3555         u8 uid[0x10];
3556         u8 reserved_at_20[0x10];
3557         u8 op_mod[0x10];
3558         u8 reserved_at_40[0x8];
3559         u8 qpn[0x18];
3560         u8 reserved_at_60[0x20];
3561         u8 opt_param_mask[0x20];
3562         u8 reserved_at_a0[0x20];
3563         struct mlx5_ifc_qpc_bits qpc;
3564         u8 reserved_at_800[0x80];
3565 };
3566
3567 struct mlx5_ifc_rtr2rts_qp_out_bits {
3568         u8 status[0x8];
3569         u8 reserved_at_8[0x18];
3570         u8 syndrome[0x20];
3571         u8 reserved_at_40[0x40];
3572 };
3573
3574 struct mlx5_ifc_rtr2rts_qp_in_bits {
3575         u8 opcode[0x10];
3576         u8 uid[0x10];
3577         u8 reserved_at_20[0x10];
3578         u8 op_mod[0x10];
3579         u8 reserved_at_40[0x8];
3580         u8 qpn[0x18];
3581         u8 reserved_at_60[0x20];
3582         u8 opt_param_mask[0x20];
3583         u8 reserved_at_a0[0x20];
3584         struct mlx5_ifc_qpc_bits qpc;
3585         u8 reserved_at_800[0x80];
3586 };
3587
3588 struct mlx5_ifc_rst2init_qp_out_bits {
3589         u8 status[0x8];
3590         u8 reserved_at_8[0x18];
3591         u8 syndrome[0x20];
3592         u8 reserved_at_40[0x40];
3593 };
3594
3595 struct mlx5_ifc_rst2init_qp_in_bits {
3596         u8 opcode[0x10];
3597         u8 uid[0x10];
3598         u8 reserved_at_20[0x10];
3599         u8 op_mod[0x10];
3600         u8 reserved_at_40[0x8];
3601         u8 qpn[0x18];
3602         u8 reserved_at_60[0x20];
3603         u8 opt_param_mask[0x20];
3604         u8 reserved_at_a0[0x20];
3605         struct mlx5_ifc_qpc_bits qpc;
3606         u8 reserved_at_800[0x80];
3607 };
3608
3609 struct mlx5_ifc_init2rtr_qp_out_bits {
3610         u8 status[0x8];
3611         u8 reserved_at_8[0x18];
3612         u8 syndrome[0x20];
3613         u8 reserved_at_40[0x40];
3614 };
3615
3616 struct mlx5_ifc_init2rtr_qp_in_bits {
3617         u8 opcode[0x10];
3618         u8 uid[0x10];
3619         u8 reserved_at_20[0x10];
3620         u8 op_mod[0x10];
3621         u8 reserved_at_40[0x8];
3622         u8 qpn[0x18];
3623         u8 reserved_at_60[0x20];
3624         u8 opt_param_mask[0x20];
3625         u8 reserved_at_a0[0x20];
3626         struct mlx5_ifc_qpc_bits qpc;
3627         u8 reserved_at_800[0x80];
3628 };
3629
3630 struct mlx5_ifc_init2init_qp_out_bits {
3631         u8 status[0x8];
3632         u8 reserved_at_8[0x18];
3633         u8 syndrome[0x20];
3634         u8 reserved_at_40[0x40];
3635 };
3636
3637 struct mlx5_ifc_init2init_qp_in_bits {
3638         u8 opcode[0x10];
3639         u8 uid[0x10];
3640         u8 reserved_at_20[0x10];
3641         u8 op_mod[0x10];
3642         u8 reserved_at_40[0x8];
3643         u8 qpn[0x18];
3644         u8 reserved_at_60[0x20];
3645         u8 opt_param_mask[0x20];
3646         u8 reserved_at_a0[0x20];
3647         struct mlx5_ifc_qpc_bits qpc;
3648         u8 reserved_at_800[0x80];
3649 };
3650
3651 struct mlx5_ifc_dealloc_pd_out_bits {
3652         u8 status[0x8];
3653         u8 reserved_0[0x18];
3654         u8 syndrome[0x20];
3655         u8 reserved_1[0x40];
3656 };
3657
3658 struct mlx5_ifc_dealloc_pd_in_bits {
3659         u8 opcode[0x10];
3660         u8 reserved_0[0x10];
3661         u8 reserved_1[0x10];
3662         u8 op_mod[0x10];
3663         u8 reserved_2[0x8];
3664         u8 pd[0x18];
3665         u8 reserved_3[0x20];
3666 };
3667
3668 struct mlx5_ifc_alloc_pd_out_bits {
3669         u8 status[0x8];
3670         u8 reserved_0[0x18];
3671         u8 syndrome[0x20];
3672         u8 reserved_1[0x8];
3673         u8 pd[0x18];
3674         u8 reserved_2[0x20];
3675 };
3676
3677 struct mlx5_ifc_alloc_pd_in_bits {
3678         u8 opcode[0x10];
3679         u8 reserved_0[0x10];
3680         u8 reserved_1[0x10];
3681         u8 op_mod[0x10];
3682         u8 reserved_2[0x40];
3683 };
3684
3685 #ifdef PEDANTIC
3686 #pragma GCC diagnostic ignored "-Wpedantic"
3687 #endif
3688 struct mlx5_ifc_query_qp_out_bits {
3689         u8 status[0x8];
3690         u8 reserved_at_8[0x18];
3691         u8 syndrome[0x20];
3692         u8 reserved_at_40[0x40];
3693         u8 opt_param_mask[0x20];
3694         u8 reserved_at_a0[0x20];
3695         struct mlx5_ifc_qpc_bits qpc;
3696         u8 reserved_at_800[0x80];
3697         u8 pas[0][0x40];
3698 };
3699 #ifdef PEDANTIC
3700 #pragma GCC diagnostic error "-Wpedantic"
3701 #endif
3702
3703 struct mlx5_ifc_query_qp_in_bits {
3704         u8 opcode[0x10];
3705         u8 reserved_at_10[0x10];
3706         u8 reserved_at_20[0x10];
3707         u8 op_mod[0x10];
3708         u8 reserved_at_40[0x8];
3709         u8 qpn[0x18];
3710         u8 reserved_at_60[0x20];
3711 };
3712
3713 enum {
3714         MLX5_DATA_RATE = 0x0,
3715         MLX5_WQE_RATE = 0x1,
3716 };
3717
3718 struct mlx5_ifc_set_pp_rate_limit_context_bits {
3719         u8 rate_limit[0x20];
3720         u8 burst_upper_bound[0x20];
3721         u8 reserved_at_40[0xC];
3722         u8 rate_mode[0x4];
3723         u8 typical_packet_size[0x10];
3724         u8 reserved_at_60[0x120];
3725 };
3726
3727 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u
3728
3729 #ifdef PEDANTIC
3730 #pragma GCC diagnostic ignored "-Wpedantic"
3731 #endif
3732 struct mlx5_ifc_access_register_out_bits {
3733         u8 status[0x8];
3734         u8 reserved_at_8[0x18];
3735         u8 syndrome[0x20];
3736         u8 reserved_at_40[0x40];
3737         u8 register_data[0][0x20];
3738 };
3739
3740 struct mlx5_ifc_access_register_in_bits {
3741         u8 opcode[0x10];
3742         u8 reserved_at_10[0x10];
3743         u8 reserved_at_20[0x10];
3744         u8 op_mod[0x10];
3745         u8 reserved_at_40[0x10];
3746         u8 register_id[0x10];
3747         u8 argument[0x20];
3748         u8 register_data[0][0x20];
3749 };
3750 #ifdef PEDANTIC
3751 #pragma GCC diagnostic error "-Wpedantic"
3752 #endif
3753
3754 enum {
3755         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
3756         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
3757 };
3758
3759 enum {
3760         MLX5_REGISTER_ID_MTUTC  = 0x9055,
3761         MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002,
3762         MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003,
3763         MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004,
3764         MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005,
3765 };
3766
3767 struct mlx5_ifc_register_mtutc_bits {
3768         u8 time_stamp_mode[0x2];
3769         u8 time_stamp_state[0x2];
3770         u8 reserved_at_4[0x18];
3771         u8 operation[0x4];
3772         u8 freq_adjustment[0x20];
3773         u8 reserved_at_40[0x40];
3774         u8 utc_sec[0x20];
3775         u8 utc_nsec[0x20];
3776         u8 time_adjustment[0x20];
3777 };
3778
3779 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0
3780 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1
3781
3782 struct mlx5_ifc_crypto_operational_register_bits {
3783         u8 wrapped_crypto_operational[0x1];
3784         u8 reserved_at_1[0x1b];
3785         u8 kek_size[0x4];
3786         u8 reserved_at_20[0x20];
3787         u8 credential[0x140];
3788         u8 kek[0x100];
3789         u8 reserved_at_280[0x180];
3790 };
3791
3792 struct mlx5_ifc_crypto_commissioning_register_bits {
3793         u8 token[0x1]; /* TODO: add size after PRM update */
3794 };
3795
3796 struct mlx5_ifc_import_kek_handle_register_bits {
3797         struct mlx5_ifc_crypto_login_bits crypto_login_object;
3798         struct mlx5_ifc_import_kek_bits import_kek_object;
3799         u8 reserved_at_200[0x4];
3800         u8 write_operation[0x4];
3801         u8 import_kek_id[0x18];
3802         u8 reserved_at_220[0xe0];
3803 };
3804
3805 struct mlx5_ifc_credential_handle_register_bits {
3806         struct mlx5_ifc_crypto_login_bits crypto_login_object;
3807         struct mlx5_ifc_credential_bits credential_object;
3808         u8 reserved_at_200[0x4];
3809         u8 write_operation[0x4];
3810         u8 credential_id[0x18];
3811         u8 reserved_at_220[0xe0];
3812 };
3813
3814 enum {
3815         MLX5_REGISTER_ADD_OPERATION = 0x1,
3816         MLX5_REGISTER_DELETE_OPERATION = 0x2,
3817 };
3818
3819 struct mlx5_ifc_parse_graph_arc_bits {
3820         u8 start_inner_tunnel[0x1];
3821         u8 reserved_at_1[0x7];
3822         u8 arc_parse_graph_node[0x8];
3823         u8 compare_condition_value[0x10];
3824         u8 parse_graph_node_handle[0x20];
3825         u8 reserved_at_40[0x40];
3826 };
3827
3828 struct mlx5_ifc_parse_graph_flow_match_sample_bits {
3829         u8 flow_match_sample_en[0x1];
3830         u8 reserved_at_1[0x3];
3831         u8 flow_match_sample_offset_mode[0x4];
3832         u8 reserved_at_5[0x8];
3833         u8 flow_match_sample_field_offset[0x10];
3834         u8 reserved_at_32[0x4];
3835         u8 flow_match_sample_field_offset_shift[0x4];
3836         u8 flow_match_sample_field_base_offset[0x8];
3837         u8 reserved_at_48[0xd];
3838         u8 flow_match_sample_tunnel_mode[0x3];
3839         u8 flow_match_sample_field_offset_mask[0x20];
3840         u8 flow_match_sample_field_id[0x20];
3841 };
3842
3843 struct mlx5_ifc_parse_graph_flex_bits {
3844         u8 modify_field_select[0x40];
3845         u8 reserved_at_64[0x20];
3846         u8 header_length_base_value[0x10];
3847         u8 reserved_at_112[0x4];
3848         u8 header_length_field_shift[0x4];
3849         u8 reserved_at_120[0x4];
3850         u8 header_length_mode[0x4];
3851         u8 header_length_field_offset[0x10];
3852         u8 next_header_field_offset[0x10];
3853         u8 reserved_at_160[0x1b];
3854         u8 next_header_field_size[0x5];
3855         u8 header_length_field_mask[0x20];
3856         u8 reserved_at_224[0x20];
3857         struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8];
3858         struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8];
3859         struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8];
3860 };
3861
3862 struct mlx5_ifc_create_flex_parser_in_bits {
3863         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3864         struct mlx5_ifc_parse_graph_flex_bits flex;
3865 };
3866
3867 struct mlx5_ifc_create_flex_parser_out_bits {
3868         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3869         struct mlx5_ifc_parse_graph_flex_bits flex;
3870 };
3871
3872 struct mlx5_ifc_parse_graph_flex_out_bits {
3873         u8 status[0x8];
3874         u8 reserved_at_8[0x18];
3875         u8 syndrome[0x20];
3876         u8 reserved_at_40[0x40];
3877         struct mlx5_ifc_parse_graph_flex_bits capability;
3878 };
3879
3880 struct regexp_params_field_select_bits {
3881         u8 reserved_at_0[0x1d];
3882         u8 rof_mkey[0x1];
3883         u8 stop_engine[0x1];
3884         u8 reserved_at_1f[0x1];
3885 };
3886
3887 struct mlx5_ifc_regexp_params_bits {
3888         u8 reserved_at_0[0x1f];
3889         u8 stop_engine[0x1];
3890         u8 reserved_at_20[0x60];
3891         u8 rof_mkey[0x20];
3892         u8 rof_size[0x20];
3893         u8 rof_mkey_va[0x40];
3894         u8 reserved_at_100[0x80];
3895 };
3896
3897 struct mlx5_ifc_set_regexp_params_in_bits {
3898         u8 opcode[0x10];
3899         u8 uid[0x10];
3900         u8 reserved_at_20[0x10];
3901         u8 op_mod[0x10];
3902         u8 reserved_at_40[0x18];
3903         u8 engine_id[0x8];
3904         struct regexp_params_field_select_bits field_select;
3905         struct mlx5_ifc_regexp_params_bits regexp_params;
3906 };
3907
3908 struct mlx5_ifc_set_regexp_params_out_bits {
3909         u8 status[0x8];
3910         u8 reserved_at_8[0x18];
3911         u8 syndrome[0x20];
3912         u8 reserved_at_18[0x40];
3913 };
3914
3915 struct mlx5_ifc_query_regexp_params_in_bits {
3916         u8 opcode[0x10];
3917         u8 uid[0x10];
3918         u8 reserved_at_20[0x10];
3919         u8 op_mod[0x10];
3920         u8 reserved_at_40[0x18];
3921         u8 engine_id[0x8];
3922         u8 reserved[0x20];
3923 };
3924
3925 struct mlx5_ifc_query_regexp_params_out_bits {
3926         u8 status[0x8];
3927         u8 reserved_at_8[0x18];
3928         u8 syndrome[0x20];
3929         u8 reserved[0x40];
3930         struct mlx5_ifc_regexp_params_bits regexp_params;
3931 };
3932
3933 struct mlx5_ifc_set_regexp_register_in_bits {
3934         u8 opcode[0x10];
3935         u8 uid[0x10];
3936         u8 reserved_at_20[0x10];
3937         u8 op_mod[0x10];
3938         u8 reserved_at_40[0x18];
3939         u8 engine_id[0x8];
3940         u8 register_address[0x20];
3941         u8 register_data[0x20];
3942         u8 reserved[0x60];
3943 };
3944
3945 struct mlx5_ifc_set_regexp_register_out_bits {
3946         u8 status[0x8];
3947         u8 reserved_at_8[0x18];
3948         u8 syndrome[0x20];
3949         u8 reserved[0x40];
3950 };
3951
3952 struct mlx5_ifc_query_regexp_register_in_bits {
3953         u8 opcode[0x10];
3954         u8 uid[0x10];
3955         u8 reserved_at_20[0x10];
3956         u8 op_mod[0x10];
3957         u8 reserved_at_40[0x18];
3958         u8 engine_id[0x8];
3959         u8 register_address[0x20];
3960 };
3961
3962 struct mlx5_ifc_query_regexp_register_out_bits {
3963         u8 status[0x8];
3964         u8 reserved_at_8[0x18];
3965         u8 syndrome[0x20];
3966         u8 reserved[0x20];
3967         u8 register_data[0x20];
3968 };
3969
3970 /* Queue counters. */
3971 struct mlx5_ifc_alloc_q_counter_out_bits {
3972         u8 status[0x8];
3973         u8 reserved_at_8[0x18];
3974         u8 syndrome[0x20];
3975         u8 reserved_at_40[0x18];
3976         u8 counter_set_id[0x8];
3977         u8 reserved_at_60[0x20];
3978 };
3979
3980 struct mlx5_ifc_alloc_q_counter_in_bits {
3981         u8 opcode[0x10];
3982         u8 uid[0x10];
3983         u8 reserved_at_20[0x10];
3984         u8 op_mod[0x10];
3985         u8 reserved_at_40[0x40];
3986 };
3987
3988 struct mlx5_ifc_query_q_counter_out_bits {
3989         u8 status[0x8];
3990         u8 reserved_at_8[0x18];
3991         u8 syndrome[0x20];
3992         u8 reserved_at_40[0x40];
3993         u8 rx_write_requests[0x20];
3994         u8 reserved_at_a0[0x20];
3995         u8 rx_read_requests[0x20];
3996         u8 reserved_at_e0[0x20];
3997         u8 rx_atomic_requests[0x20];
3998         u8 reserved_at_120[0x20];
3999         u8 rx_dct_connect[0x20];
4000         u8 reserved_at_160[0x20];
4001         u8 out_of_buffer[0x20];
4002         u8 reserved_at_1a0[0x20];
4003         u8 out_of_sequence[0x20];
4004         u8 reserved_at_1e0[0x20];
4005         u8 duplicate_request[0x20];
4006         u8 reserved_at_220[0x20];
4007         u8 rnr_nak_retry_err[0x20];
4008         u8 reserved_at_260[0x20];
4009         u8 packet_seq_err[0x20];
4010         u8 reserved_at_2a0[0x20];
4011         u8 implied_nak_seq_err[0x20];
4012         u8 reserved_at_2e0[0x20];
4013         u8 local_ack_timeout_err[0x20];
4014         u8 reserved_at_320[0xa0];
4015         u8 resp_local_length_error[0x20];
4016         u8 req_local_length_error[0x20];
4017         u8 resp_local_qp_error[0x20];
4018         u8 local_operation_error[0x20];
4019         u8 resp_local_protection[0x20];
4020         u8 req_local_protection[0x20];
4021         u8 resp_cqe_error[0x20];
4022         u8 req_cqe_error[0x20];
4023         u8 req_mw_binding[0x20];
4024         u8 req_bad_response[0x20];
4025         u8 req_remote_invalid_request[0x20];
4026         u8 resp_remote_invalid_request[0x20];
4027         u8 req_remote_access_errors[0x20];
4028         u8 resp_remote_access_errors[0x20];
4029         u8 req_remote_operation_errors[0x20];
4030         u8 req_transport_retries_exceeded[0x20];
4031         u8 cq_overflow[0x20];
4032         u8 resp_cqe_flush_error[0x20];
4033         u8 req_cqe_flush_error[0x20];
4034         u8 reserved_at_620[0x1e0];
4035 };
4036
4037 struct mlx5_ifc_query_q_counter_in_bits {
4038         u8 opcode[0x10];
4039         u8 uid[0x10];
4040         u8 reserved_at_20[0x10];
4041         u8 op_mod[0x10];
4042         u8 reserved_at_40[0x80];
4043         u8 clear[0x1];
4044         u8 reserved_at_c1[0x1f];
4045         u8 reserved_at_e0[0x18];
4046         u8 counter_set_id[0x8];
4047 };
4048
4049 /* CQE format mask. */
4050 #define MLX5E_CQE_FORMAT_MASK 0xc
4051
4052 /* MPW opcode. */
4053 #define MLX5_OPC_MOD_MPW 0x01
4054
4055 /* Compressed Rx CQE structure. */
4056 struct mlx5_mini_cqe8 {
4057         union {
4058                 uint32_t rx_hash_result;
4059                 struct {
4060                         union {
4061                                 uint16_t checksum;
4062                                 uint16_t flow_tag_high;
4063                                 struct {
4064                                         uint8_t reserved;
4065                                         uint8_t hdr_type;
4066                                 };
4067                         };
4068                         uint16_t stride_idx;
4069                 };
4070                 struct {
4071                         uint16_t wqe_counter;
4072                         uint8_t  s_wqe_opcode;
4073                         uint8_t  reserved;
4074                 } s_wqe_info;
4075         };
4076         union {
4077                 uint32_t byte_cnt_flow;
4078                 uint32_t byte_cnt;
4079         };
4080 };
4081
4082 /* Mini CQE responder format. */
4083 enum {
4084         MLX5_CQE_RESP_FORMAT_HASH = 0x0,
4085         MLX5_CQE_RESP_FORMAT_CSUM = 0x1,
4086         MLX5_CQE_RESP_FORMAT_FTAG_STRIDX = 0x2,
4087         MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3,
4088         MLX5_CQE_RESP_FORMAT_L34H_STRIDX = 0x4,
4089 };
4090
4091 /* srTCM PRM flow meter parameters. */
4092 enum {
4093         MLX5_FLOW_COLOR_RED = 0,
4094         MLX5_FLOW_COLOR_YELLOW,
4095         MLX5_FLOW_COLOR_GREEN,
4096         MLX5_FLOW_COLOR_UNDEFINED,
4097 };
4098
4099 /* Maximum value of srTCM & trTCM metering parameters. */
4100 #define MLX5_SRTCM_XBS_MAX (0xFF * (1ULL << 0x1F))
4101 #define MLX5_SRTCM_XIR_MAX (8 * (1ULL << 30) * 0xFF)
4102
4103 /* The bits meter color use. */
4104 #define MLX5_MTR_COLOR_BITS 8
4105
4106 /* The bit size of one register. */
4107 #define MLX5_REG_BITS 32
4108
4109 /* Idle bits for non-color usage in color register. */
4110 #define MLX5_MTR_IDLE_BITS_IN_COLOR_REG (MLX5_REG_BITS - MLX5_MTR_COLOR_BITS)
4111
4112 /* Length mode of dynamic flex parser graph node. */
4113 enum mlx5_parse_graph_node_len_mode {
4114         MLX5_GRAPH_NODE_LEN_FIXED = 0x0,
4115         MLX5_GRAPH_NODE_LEN_FIELD = 0x1,
4116         MLX5_GRAPH_NODE_LEN_BITMASK = 0x2,
4117 };
4118
4119 /* Offset mode of the samples of flex parser. */
4120 enum mlx5_parse_graph_flow_match_sample_offset_mode {
4121         MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0,
4122         MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1,
4123         MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2,
4124 };
4125
4126 enum mlx5_parse_graph_flow_match_sample_tunnel_mode {
4127         MLX5_GRAPH_SAMPLE_TUNNEL_OUTER = 0x0,
4128         MLX5_GRAPH_SAMPLE_TUNNEL_INNER = 0x1,
4129         MLX5_GRAPH_SAMPLE_TUNNEL_FIRST = 0x2
4130 };
4131
4132 /* Node index for an input / output arc of the flex parser graph. */
4133 enum mlx5_parse_graph_arc_node_index {
4134         MLX5_GRAPH_ARC_NODE_NULL = 0x0,
4135         MLX5_GRAPH_ARC_NODE_HEAD = 0x1,
4136         MLX5_GRAPH_ARC_NODE_MAC = 0x2,
4137         MLX5_GRAPH_ARC_NODE_IP = 0x3,
4138         MLX5_GRAPH_ARC_NODE_GRE = 0x4,
4139         MLX5_GRAPH_ARC_NODE_UDP = 0x5,
4140         MLX5_GRAPH_ARC_NODE_MPLS = 0x6,
4141         MLX5_GRAPH_ARC_NODE_TCP = 0x7,
4142         MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8,
4143         MLX5_GRAPH_ARC_NODE_GENEVE = 0x9,
4144         MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa,
4145         MLX5_GRAPH_ARC_NODE_IPV4 = 0xb,
4146         MLX5_GRAPH_ARC_NODE_IPV6 = 0xc,
4147         MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f,
4148 };
4149
4150 #define MLX5_PARSE_GRAPH_FLOW_SAMPLE_MAX 8
4151 #define MLX5_PARSE_GRAPH_IN_ARC_MAX 8
4152 #define MLX5_PARSE_GRAPH_OUT_ARC_MAX 8
4153
4154 /**
4155  * Convert a user mark to flow mark.
4156  *
4157  * @param val
4158  *   Mark value to convert.
4159  *
4160  * @return
4161  *   Converted mark value.
4162  */
4163 static inline uint32_t
4164 mlx5_flow_mark_set(uint32_t val)
4165 {
4166         uint32_t ret;
4167
4168         /*
4169          * Add one to the user value to differentiate un-marked flows from
4170          * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
4171          * remains untouched.
4172          */
4173         if (val != MLX5_FLOW_MARK_DEFAULT)
4174                 ++val;
4175 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
4176         /*
4177          * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
4178          * word, byte-swapped by the kernel on little-endian systems. In this
4179          * case, left-shifting the resulting big-endian value ensures the
4180          * least significant 24 bits are retained when converting it back.
4181          */
4182         ret = rte_cpu_to_be_32(val) >> 8;
4183 #else
4184         ret = val;
4185 #endif
4186         return ret;
4187 }
4188
4189 /**
4190  * Convert a mark to user mark.
4191  *
4192  * @param val
4193  *   Mark value to convert.
4194  *
4195  * @return
4196  *   Converted mark value.
4197  */
4198 static inline uint32_t
4199 mlx5_flow_mark_get(uint32_t val)
4200 {
4201         /*
4202          * Subtract one from the retrieved value. It was added by
4203          * mlx5_flow_mark_set() to distinguish unmarked flows.
4204          */
4205 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
4206         return (val >> 8) - 1;
4207 #else
4208         return val - 1;
4209 #endif
4210 }
4211
4212 /**
4213  * Convert a timestamp format to configure settings in the queue context.
4214  *
4215  * @param val
4216  *   timestamp format supported by the queue.
4217  *
4218  * @return
4219  *   Converted timestamp format settings.
4220  */
4221 static inline uint32_t
4222 mlx5_ts_format_conv(uint32_t ts_format)
4223 {
4224         return ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ?
4225                         MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
4226                         MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
4227 }
4228
4229 #endif /* RTE_PMD_MLX5_PRM_H_ */