1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2016 6WIND S.A.
3 * Copyright 2016 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_PRM_H_
7 #define RTE_PMD_MLX5_PRM_H_
11 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
13 #pragma GCC diagnostic ignored "-Wpedantic"
15 #include <infiniband/mlx5dv.h>
17 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_byteorder.h>
23 #include "mlx5_autoconf.h"
25 /* RSS hash key size. */
26 #define MLX5_RSS_HASH_KEY_LEN 40
28 /* Get CQE owner bit. */
29 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
32 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
35 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
37 /* Get CQE solicited event. */
38 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
40 /* Invalidate a CQE. */
41 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
43 /* WQE Segment sizes in bytes. */
44 #define MLX5_WSEG_SIZE 16u
45 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
46 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
47 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
49 /* WQE/WQEBB size in bytes. */
50 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
53 * Max size of a WQE session.
54 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
55 * the WQE size field in Control Segment is 6 bits wide.
57 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
60 * Default minimum number of Tx queues for inlining packets.
61 * If there are less queues as specified we assume we have
62 * no enough CPU resources (cycles) to perform inlining,
63 * the PCIe throughput is not supposed as bottleneck and
64 * inlining is disabled.
66 #define MLX5_INLINE_MAX_TXQS 8u
67 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
70 * Default packet length threshold to be inlined with
71 * enhanced MPW. If packet length exceeds the threshold
72 * the data are not inlined. Should be aligned in WQEBB
73 * boundary with accounting the title Control and Ethernet
76 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
77 MLX5_DSEG_MIN_INLINE_SIZE)
79 * Maximal inline data length sent with enhanced MPW.
80 * Is based on maximal WQE size.
82 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
83 MLX5_WQE_CSEG_SIZE - \
84 MLX5_WQE_ESEG_SIZE - \
85 MLX5_WQE_DSEG_SIZE + \
86 MLX5_DSEG_MIN_INLINE_SIZE)
88 * Minimal amount of packets to be sent with EMPW.
89 * This limits the minimal required size of sent EMPW.
90 * If there are no enough resources to built minimal
91 * EMPW the sending loop exits.
93 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
95 * Maximal amount of packets to be sent with EMPW.
96 * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
97 * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
98 * without CQE generation request, being multiplied by
99 * MLX5_TX_COMP_MAX_CQE it may cause significant latency
100 * in tx burst routine at the moment of freeing multiple mbufs.
102 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
103 #define MLX5_MPW_MAX_PACKETS 6
104 #define MLX5_MPW_INLINE_MAX_PACKETS 2
107 * Default packet length threshold to be inlined with
108 * ordinary SEND. Inlining saves the MR key search
109 * and extra PCIe data fetch transaction, but eats the
112 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
113 MLX5_ESEG_MIN_INLINE_SIZE - \
114 MLX5_WQE_CSEG_SIZE - \
115 MLX5_WQE_ESEG_SIZE - \
118 * Maximal inline data length sent with ordinary SEND.
119 * Is based on maximal WQE size.
121 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
122 MLX5_WQE_CSEG_SIZE - \
123 MLX5_WQE_ESEG_SIZE - \
124 MLX5_WQE_DSEG_SIZE + \
125 MLX5_ESEG_MIN_INLINE_SIZE)
127 /* Missed in mlv5dv.h, should define here. */
128 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
130 /* CQE value to inform that VLAN is stripped. */
131 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
134 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
137 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
140 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
143 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
146 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
148 /* IP is fragmented. */
149 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
151 /* L2 header is valid. */
152 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
154 /* L3 header is valid. */
155 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
157 /* L4 header is valid. */
158 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
160 /* Outer packet, 0 IPv4, 1 IPv6. */
161 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
163 /* Tunnel packet bit in the CQE. */
164 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
166 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
167 #define MLX5_CQE_LRO_PUSH_MASK 0x40
169 /* Mask for L4 type in the CQE hdr_type_etc field. */
170 #define MLX5_CQE_L4_TYPE_MASK 0x70
172 /* The bit index of L4 type in CQE hdr_type_etc field. */
173 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
175 /* L4 type to indicate TCP packet without acknowledgment. */
176 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
178 /* L4 type to indicate TCP packet with acknowledgment. */
179 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
181 /* Inner L3 checksum offload (Tunneled packets only). */
182 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
184 /* Inner L4 checksum offload (Tunneled packets only). */
185 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
187 /* Outer L4 type is TCP. */
188 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5)
190 /* Outer L4 type is UDP. */
191 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5)
193 /* Outer L3 type is IPV4. */
194 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
196 /* Outer L3 type is IPV6. */
197 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
199 /* Inner L4 type is TCP. */
200 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
202 /* Inner L4 type is UDP. */
203 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
205 /* Inner L3 type is IPV4. */
206 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
208 /* Inner L3 type is IPV6. */
209 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
211 /* VLAN insertion flag. */
212 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
214 /* Data inline segment flag. */
215 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
217 /* Is flow mark valid. */
218 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
219 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
221 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
224 /* INVALID is used by packets matching no flow rules. */
225 #define MLX5_FLOW_MARK_INVALID 0
227 /* Maximum allowed value to mark a packet. */
228 #define MLX5_FLOW_MARK_MAX 0xfffff0
230 /* Default mark value used when none is provided. */
231 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
233 /* Default mark mask for metadata legacy mode. */
234 #define MLX5_FLOW_MARK_MASK 0xffffff
236 /* Maximum number of DS in WQE. Limited by 6-bit field. */
237 #define MLX5_DSEG_MAX 63
239 /* The completion mode offset in the WQE control segment line 2. */
240 #define MLX5_COMP_MODE_OFFSET 2
242 /* Amount of data bytes in minimal inline data segment. */
243 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
245 /* Amount of data bytes in minimal inline eth segment. */
246 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
248 /* Amount of data bytes after eth data segment. */
249 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
251 /* The maximum log value of segments per RQ WQE. */
252 #define MLX5_MAX_LOG_RQ_SEGS 5u
254 /* The alignment needed for WQ buffer. */
255 #define MLX5_WQE_BUF_ALIGNMENT 512
257 /* Completion mode. */
258 enum mlx5_completion_mode {
259 MLX5_COMP_ONLY_ERR = 0x0,
260 MLX5_COMP_ONLY_FIRST_ERR = 0x1,
261 MLX5_COMP_ALWAYS = 0x2,
262 MLX5_COMP_CQE_AND_EQE = 0x3,
269 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
272 /* WQE Control segment. */
273 struct mlx5_wqe_cseg {
278 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
280 /* Header of data segment. Minimal size Data Segment */
281 struct mlx5_wqe_dseg {
284 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
292 /* Subset of struct WQE Ethernet Segment. */
293 struct mlx5_wqe_eseg {
301 uint16_t inline_hdr_sz;
303 uint16_t inline_data;
310 uint32_t flow_metadata;
316 /* The title WQEBB, header of WQE. */
319 struct mlx5_wqe_cseg cseg;
322 struct mlx5_wqe_eseg eseg;
324 struct mlx5_wqe_dseg dseg[2];
325 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
329 /* WQE for Multi-Packet RQ. */
330 struct mlx5_wqe_mprq {
331 struct mlx5_wqe_srq_next_seg next_seg;
332 struct mlx5_wqe_data_seg dseg;
335 #define MLX5_MPRQ_LEN_MASK 0x000ffff
336 #define MLX5_MPRQ_LEN_SHIFT 0
337 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
338 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
339 #define MLX5_MPRQ_FILLER_MASK 0x80000000
340 #define MLX5_MPRQ_FILLER_SHIFT 31
342 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
344 /* CQ element structure - should be equal to the cache line size */
346 #if (RTE_CACHE_LINE_SIZE == 128)
352 uint8_t lro_tcppsh_abort_dupack;
354 uint16_t lro_tcp_win;
355 uint32_t lro_ack_seq_num;
356 uint32_t rx_hash_res;
357 uint8_t rx_hash_type;
361 uint16_t hdr_type_etc;
365 uint32_t flow_table_metadata;
369 uint32_t sop_drop_qpn;
370 uint16_t wqe_counter;
375 /* Adding direct verbs to data-path. */
377 /* CQ sequence number mask. */
378 #define MLX5_CQ_SQN_MASK 0x3
380 /* CQ sequence number index. */
381 #define MLX5_CQ_SQN_OFFSET 28
383 /* CQ doorbell index mask. */
384 #define MLX5_CI_MASK 0xffffff
386 /* CQ doorbell offset. */
387 #define MLX5_CQ_ARM_DB 1
389 /* CQ doorbell offset*/
390 #define MLX5_CQ_DOORBELL 0x20
392 /* CQE format value. */
393 #define MLX5_COMPRESSED 0x3
395 /* Action type of header modification. */
397 MLX5_MODIFICATION_TYPE_SET = 0x1,
398 MLX5_MODIFICATION_TYPE_ADD = 0x2,
399 MLX5_MODIFICATION_TYPE_COPY = 0x3,
402 /* The field of packet to be modified. */
403 enum mlx5_modification_field {
404 MLX5_MODI_OUT_NONE = -1,
405 MLX5_MODI_OUT_SMAC_47_16 = 1,
406 MLX5_MODI_OUT_SMAC_15_0,
407 MLX5_MODI_OUT_ETHERTYPE,
408 MLX5_MODI_OUT_DMAC_47_16,
409 MLX5_MODI_OUT_DMAC_15_0,
410 MLX5_MODI_OUT_IP_DSCP,
411 MLX5_MODI_OUT_TCP_FLAGS,
412 MLX5_MODI_OUT_TCP_SPORT,
413 MLX5_MODI_OUT_TCP_DPORT,
414 MLX5_MODI_OUT_IPV4_TTL,
415 MLX5_MODI_OUT_UDP_SPORT,
416 MLX5_MODI_OUT_UDP_DPORT,
417 MLX5_MODI_OUT_SIPV6_127_96,
418 MLX5_MODI_OUT_SIPV6_95_64,
419 MLX5_MODI_OUT_SIPV6_63_32,
420 MLX5_MODI_OUT_SIPV6_31_0,
421 MLX5_MODI_OUT_DIPV6_127_96,
422 MLX5_MODI_OUT_DIPV6_95_64,
423 MLX5_MODI_OUT_DIPV6_63_32,
424 MLX5_MODI_OUT_DIPV6_31_0,
427 MLX5_MODI_OUT_FIRST_VID,
428 MLX5_MODI_IN_SMAC_47_16 = 0x31,
429 MLX5_MODI_IN_SMAC_15_0,
430 MLX5_MODI_IN_ETHERTYPE,
431 MLX5_MODI_IN_DMAC_47_16,
432 MLX5_MODI_IN_DMAC_15_0,
433 MLX5_MODI_IN_IP_DSCP,
434 MLX5_MODI_IN_TCP_FLAGS,
435 MLX5_MODI_IN_TCP_SPORT,
436 MLX5_MODI_IN_TCP_DPORT,
437 MLX5_MODI_IN_IPV4_TTL,
438 MLX5_MODI_IN_UDP_SPORT,
439 MLX5_MODI_IN_UDP_DPORT,
440 MLX5_MODI_IN_SIPV6_127_96,
441 MLX5_MODI_IN_SIPV6_95_64,
442 MLX5_MODI_IN_SIPV6_63_32,
443 MLX5_MODI_IN_SIPV6_31_0,
444 MLX5_MODI_IN_DIPV6_127_96,
445 MLX5_MODI_IN_DIPV6_95_64,
446 MLX5_MODI_IN_DIPV6_63_32,
447 MLX5_MODI_IN_DIPV6_31_0,
450 MLX5_MODI_OUT_IPV6_HOPLIMIT,
451 MLX5_MODI_IN_IPV6_HOPLIMIT,
452 MLX5_MODI_META_DATA_REG_A,
453 MLX5_MODI_META_DATA_REG_B = 0x50,
454 MLX5_MODI_META_REG_C_0,
455 MLX5_MODI_META_REG_C_1,
456 MLX5_MODI_META_REG_C_2,
457 MLX5_MODI_META_REG_C_3,
458 MLX5_MODI_META_REG_C_4,
459 MLX5_MODI_META_REG_C_5,
460 MLX5_MODI_META_REG_C_6,
461 MLX5_MODI_META_REG_C_7,
462 MLX5_MODI_OUT_TCP_SEQ_NUM,
463 MLX5_MODI_IN_TCP_SEQ_NUM,
464 MLX5_MODI_OUT_TCP_ACK_NUM,
465 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
468 /* Total number of metadata reg_c's. */
469 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1)
485 /* Modification sub command. */
486 struct mlx5_modification_cmd {
490 unsigned int length:5;
491 unsigned int rsvd0:3;
492 unsigned int offset:5;
493 unsigned int rsvd1:3;
494 unsigned int field:12;
495 unsigned int action_type:4;
502 unsigned int rsvd2:8;
503 unsigned int dst_offset:5;
504 unsigned int rsvd3:3;
505 unsigned int dst_field:12;
506 unsigned int rsvd4:4;
511 typedef uint32_t u32;
512 typedef uint16_t u16;
515 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
516 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
517 #define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \
518 (&(__mlx5_nullp(typ)->fld)))
519 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
520 (__mlx5_bit_off(typ, fld) & 0x1f))
521 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
522 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
523 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
524 __mlx5_dw_bit_off(typ, fld))
525 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
526 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
527 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
528 (__mlx5_bit_off(typ, fld) & 0xf))
529 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
530 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
531 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
532 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
533 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
535 /* insert a value to a struct */
536 #define MLX5_SET(typ, p, fld, v) \
539 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
540 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
541 __mlx5_dw_off(typ, fld))) & \
542 (~__mlx5_dw_mask(typ, fld))) | \
543 (((_v) & __mlx5_mask(typ, fld)) << \
544 __mlx5_dw_bit_off(typ, fld))); \
547 #define MLX5_SET64(typ, p, fld, v) \
549 assert(__mlx5_bit_sz(typ, fld) == 64); \
550 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = \
551 rte_cpu_to_be_64(v); \
554 #define MLX5_GET(typ, p, fld) \
555 ((rte_be_to_cpu_32(*((__be32 *)(p) +\
556 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
557 __mlx5_mask(typ, fld))
558 #define MLX5_GET16(typ, p, fld) \
559 ((rte_be_to_cpu_16(*((__be16 *)(p) + \
560 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
561 __mlx5_mask16(typ, fld))
562 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((__be64 *)(p) + \
563 __mlx5_64_off(typ, fld)))
564 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
566 struct mlx5_ifc_fte_match_set_misc_bits {
567 u8 gre_c_present[0x1];
568 u8 reserved_at_1[0x1];
569 u8 gre_k_present[0x1];
570 u8 gre_s_present[0x1];
571 u8 source_vhci_port[0x4];
573 u8 reserved_at_20[0x10];
574 u8 source_port[0x10];
575 u8 outer_second_prio[0x3];
576 u8 outer_second_cfi[0x1];
577 u8 outer_second_vid[0xc];
578 u8 inner_second_prio[0x3];
579 u8 inner_second_cfi[0x1];
580 u8 inner_second_vid[0xc];
581 u8 outer_second_cvlan_tag[0x1];
582 u8 inner_second_cvlan_tag[0x1];
583 u8 outer_second_svlan_tag[0x1];
584 u8 inner_second_svlan_tag[0x1];
585 u8 reserved_at_64[0xc];
586 u8 gre_protocol[0x10];
590 u8 reserved_at_b8[0x8];
592 u8 reserved_at_e4[0x7];
594 u8 reserved_at_e0[0xc];
595 u8 outer_ipv6_flow_label[0x14];
596 u8 reserved_at_100[0xc];
597 u8 inner_ipv6_flow_label[0x14];
598 u8 reserved_at_120[0xa];
599 u8 geneve_opt_len[0x6];
600 u8 geneve_protocol_type[0x10];
601 u8 reserved_at_140[0xc0];
604 struct mlx5_ifc_ipv4_layout_bits {
605 u8 reserved_at_0[0x60];
609 struct mlx5_ifc_ipv6_layout_bits {
613 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
614 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
615 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
616 u8 reserved_at_0[0x80];
619 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
638 u8 reserved_at_c0[0x20];
641 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
642 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
645 struct mlx5_ifc_fte_match_mpls_bits {
652 struct mlx5_ifc_fte_match_set_misc2_bits {
653 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
654 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
655 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
656 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
657 u8 metadata_reg_c_7[0x20];
658 u8 metadata_reg_c_6[0x20];
659 u8 metadata_reg_c_5[0x20];
660 u8 metadata_reg_c_4[0x20];
661 u8 metadata_reg_c_3[0x20];
662 u8 metadata_reg_c_2[0x20];
663 u8 metadata_reg_c_1[0x20];
664 u8 metadata_reg_c_0[0x20];
665 u8 metadata_reg_a[0x20];
666 u8 metadata_reg_b[0x20];
667 u8 reserved_at_1c0[0x40];
670 struct mlx5_ifc_fte_match_set_misc3_bits {
671 u8 inner_tcp_seq_num[0x20];
672 u8 outer_tcp_seq_num[0x20];
673 u8 inner_tcp_ack_num[0x20];
674 u8 outer_tcp_ack_num[0x20];
675 u8 reserved_at_auto1[0x8];
676 u8 outer_vxlan_gpe_vni[0x18];
677 u8 outer_vxlan_gpe_next_protocol[0x8];
678 u8 outer_vxlan_gpe_flags[0x8];
679 u8 reserved_at_a8[0x10];
680 u8 icmp_header_data[0x20];
681 u8 icmpv6_header_data[0x20];
686 u8 reserved_at_120[0x20];
688 u8 gtpu_msg_type[0x08];
689 u8 gtpu_msg_flags[0x08];
690 u8 reserved_at_170[0x90];
694 struct mlx5_ifc_fte_match_param_bits {
695 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
696 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
697 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
698 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
699 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
703 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
704 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
705 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
706 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
707 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT
711 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
712 MLX5_CMD_OP_CREATE_MKEY = 0x200,
713 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
714 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
715 MLX5_CMD_OP_CREATE_TIR = 0x900,
716 MLX5_CMD_OP_CREATE_SQ = 0X904,
717 MLX5_CMD_OP_MODIFY_SQ = 0X905,
718 MLX5_CMD_OP_CREATE_RQ = 0x908,
719 MLX5_CMD_OP_MODIFY_RQ = 0x909,
720 MLX5_CMD_OP_CREATE_TIS = 0x912,
721 MLX5_CMD_OP_QUERY_TIS = 0x915,
722 MLX5_CMD_OP_CREATE_RQT = 0x916,
723 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
724 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
728 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
732 struct mlx5_ifc_alloc_flow_counter_out_bits {
734 u8 reserved_at_8[0x18];
736 u8 flow_counter_id[0x20];
737 u8 reserved_at_60[0x20];
740 struct mlx5_ifc_alloc_flow_counter_in_bits {
742 u8 reserved_at_10[0x10];
743 u8 reserved_at_20[0x10];
745 u8 flow_counter_id[0x20];
746 u8 reserved_at_40[0x18];
747 u8 flow_counter_bulk[0x8];
750 struct mlx5_ifc_dealloc_flow_counter_out_bits {
752 u8 reserved_at_8[0x18];
754 u8 reserved_at_40[0x40];
757 struct mlx5_ifc_dealloc_flow_counter_in_bits {
759 u8 reserved_at_10[0x10];
760 u8 reserved_at_20[0x10];
762 u8 flow_counter_id[0x20];
763 u8 reserved_at_60[0x20];
766 struct mlx5_ifc_traffic_counter_bits {
771 struct mlx5_ifc_query_flow_counter_out_bits {
773 u8 reserved_at_8[0x18];
775 u8 reserved_at_40[0x40];
776 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
779 struct mlx5_ifc_query_flow_counter_in_bits {
781 u8 reserved_at_10[0x10];
782 u8 reserved_at_20[0x10];
784 u8 reserved_at_40[0x20];
788 u8 dump_to_memory[0x1];
789 u8 num_of_counters[0x1e];
790 u8 flow_counter_id[0x20];
793 struct mlx5_ifc_mkc_bits {
794 u8 reserved_at_0[0x1];
796 u8 reserved_at_2[0x1];
797 u8 access_mode_4_2[0x3];
798 u8 reserved_at_6[0x7];
799 u8 relaxed_ordering_write[0x1];
800 u8 reserved_at_e[0x1];
801 u8 small_fence_on_rdma_read_response[0x1];
808 u8 access_mode_1_0[0x2];
809 u8 reserved_at_18[0x8];
814 u8 reserved_at_40[0x20];
819 u8 reserved_at_63[0x2];
820 u8 expected_sigerr_count[0x1];
821 u8 reserved_at_66[0x1];
829 u8 bsf_octword_size[0x20];
831 u8 reserved_at_120[0x80];
833 u8 translations_octword_size[0x20];
835 u8 reserved_at_1c0[0x1b];
836 u8 log_page_size[0x5];
838 u8 reserved_at_1e0[0x20];
841 struct mlx5_ifc_create_mkey_out_bits {
843 u8 reserved_at_8[0x18];
847 u8 reserved_at_40[0x8];
850 u8 reserved_at_60[0x20];
853 struct mlx5_ifc_create_mkey_in_bits {
855 u8 reserved_at_10[0x10];
857 u8 reserved_at_20[0x10];
860 u8 reserved_at_40[0x20];
863 u8 reserved_at_61[0x1f];
865 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
867 u8 reserved_at_280[0x80];
869 u8 translations_octword_actual_size[0x20];
871 u8 mkey_umem_id[0x20];
873 u8 mkey_umem_offset[0x40];
875 u8 reserved_at_380[0x500];
877 u8 klm_pas_mtt[][0x20];
881 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
882 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
883 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
884 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
888 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q = (1ULL << 0xd),
892 MLX5_HCA_CAP_OPMOD_GET_MAX = 0,
893 MLX5_HCA_CAP_OPMOD_GET_CUR = 1,
897 MLX5_CAP_INLINE_MODE_L2,
898 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
899 MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
903 MLX5_INLINE_MODE_NONE,
906 MLX5_INLINE_MODE_TCP_UDP,
907 MLX5_INLINE_MODE_RESERVED4,
908 MLX5_INLINE_MODE_INNER_L2,
909 MLX5_INLINE_MODE_INNER_IP,
910 MLX5_INLINE_MODE_INNER_TCP_UDP,
913 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
914 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
915 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
916 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
917 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
918 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
919 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
920 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
921 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
922 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
923 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
925 struct mlx5_ifc_cmd_hca_cap_bits {
926 u8 reserved_at_0[0x30];
928 u8 reserved_at_40[0x40];
929 u8 log_max_srq_sz[0x8];
930 u8 log_max_qp_sz[0x8];
931 u8 reserved_at_90[0xb];
933 u8 reserved_at_a0[0xb];
935 u8 reserved_at_b0[0x10];
936 u8 reserved_at_c0[0x8];
937 u8 log_max_cq_sz[0x8];
938 u8 reserved_at_d0[0xb];
940 u8 log_max_eq_sz[0x8];
941 u8 reserved_at_e8[0x2];
942 u8 log_max_mkey[0x6];
943 u8 reserved_at_f0[0x8];
944 u8 dump_fill_mkey[0x1];
945 u8 reserved_at_f9[0x3];
947 u8 max_indirection[0x8];
948 u8 fixed_buffer_size[0x1];
949 u8 log_max_mrw_sz[0x7];
950 u8 force_teardown[0x1];
951 u8 reserved_at_111[0x1];
952 u8 log_max_bsf_list_size[0x6];
953 u8 umr_extended_translation_offset[0x1];
955 u8 log_max_klm_list_size[0x6];
956 u8 reserved_at_120[0xa];
957 u8 log_max_ra_req_dc[0x6];
958 u8 reserved_at_130[0xa];
959 u8 log_max_ra_res_dc[0x6];
960 u8 reserved_at_140[0xa];
961 u8 log_max_ra_req_qp[0x6];
962 u8 reserved_at_150[0xa];
963 u8 log_max_ra_res_qp[0x6];
965 u8 cc_query_allowed[0x1];
966 u8 cc_modify_allowed[0x1];
968 u8 cache_line_128byte[0x1];
969 u8 reserved_at_165[0xa];
971 u8 gid_table_size[0x10];
972 u8 out_of_seq_cnt[0x1];
973 u8 vport_counters[0x1];
974 u8 retransmission_q_counters[0x1];
976 u8 modify_rq_counter_set_id[0x1];
977 u8 rq_delay_drop[0x1];
979 u8 pkey_table_size[0x10];
980 u8 vport_group_manager[0x1];
981 u8 vhca_group_manager[0x1];
984 u8 vnic_env_queue_counters[0x1];
986 u8 nic_flow_table[0x1];
987 u8 eswitch_manager[0x1];
988 u8 device_memory[0x1];
991 u8 local_ca_ack_delay[0x5];
992 u8 port_module_event[0x1];
993 u8 enhanced_error_q_counters[0x1];
995 u8 reserved_at_1b3[0x1];
996 u8 disable_link_up[0x1];
1000 u8 reserved_at_1c0[0x1];
1003 u8 log_max_msg[0x5];
1004 u8 reserved_at_1c8[0x4];
1006 u8 temp_warn_event[0x1];
1008 u8 general_notification_event[0x1];
1009 u8 reserved_at_1d3[0x2];
1013 u8 reserved_at_1d8[0x1];
1021 u8 stat_rate_support[0x10];
1022 u8 reserved_at_1f0[0xc];
1023 u8 cqe_version[0x4];
1024 u8 compact_address_vector[0x1];
1025 u8 striding_rq[0x1];
1026 u8 reserved_at_202[0x1];
1027 u8 ipoib_enhanced_offloads[0x1];
1028 u8 ipoib_basic_offloads[0x1];
1029 u8 reserved_at_205[0x1];
1030 u8 repeated_block_disabled[0x1];
1031 u8 umr_modify_entity_size_disabled[0x1];
1032 u8 umr_modify_atomic_disabled[0x1];
1033 u8 umr_indirect_mkey_disabled[0x1];
1035 u8 reserved_at_20c[0x3];
1036 u8 drain_sigerr[0x1];
1037 u8 cmdif_checksum[0x2];
1039 u8 reserved_at_213[0x1];
1040 u8 wq_signature[0x1];
1041 u8 sctr_data_cqe[0x1];
1042 u8 reserved_at_216[0x1];
1048 u8 eth_net_offloads[0x1];
1051 u8 reserved_at_21f[0x1];
1054 u8 cq_moderation[0x1];
1055 u8 reserved_at_223[0x3];
1056 u8 cq_eq_remap[0x1];
1058 u8 block_lb_mc[0x1];
1059 u8 reserved_at_229[0x1];
1060 u8 scqe_break_moderation[0x1];
1061 u8 cq_period_start_from_cqe[0x1];
1063 u8 reserved_at_22d[0x1];
1065 u8 vector_calc[0x1];
1066 u8 umr_ptr_rlky[0x1];
1068 u8 reserved_at_232[0x4];
1071 u8 set_deth_sqpn[0x1];
1072 u8 reserved_at_239[0x3];
1078 u8 reserved_at_241[0x9];
1080 u8 reserved_at_250[0x8];
1083 u8 driver_version[0x1];
1084 u8 pad_tx_eth_packet[0x1];
1085 u8 reserved_at_263[0x8];
1086 u8 log_bf_reg_size[0x5];
1087 u8 reserved_at_270[0xb];
1089 u8 num_lag_ports[0x4];
1090 u8 reserved_at_280[0x10];
1091 u8 max_wqe_sz_sq[0x10];
1092 u8 reserved_at_2a0[0x10];
1093 u8 max_wqe_sz_rq[0x10];
1094 u8 max_flow_counter_31_16[0x10];
1095 u8 max_wqe_sz_sq_dc[0x10];
1096 u8 reserved_at_2e0[0x7];
1097 u8 max_qp_mcg[0x19];
1098 u8 reserved_at_300[0x10];
1099 u8 flow_counter_bulk_alloc[0x08];
1100 u8 log_max_mcg[0x8];
1101 u8 reserved_at_320[0x3];
1102 u8 log_max_transport_domain[0x5];
1103 u8 reserved_at_328[0x3];
1105 u8 reserved_at_330[0xb];
1106 u8 log_max_xrcd[0x5];
1107 u8 nic_receive_steering_discard[0x1];
1108 u8 receive_discard_vport_down[0x1];
1109 u8 transmit_discard_vport_down[0x1];
1110 u8 reserved_at_343[0x5];
1111 u8 log_max_flow_counter_bulk[0x8];
1112 u8 max_flow_counter_15_0[0x10];
1114 u8 flow_counters_dump[0x1];
1115 u8 reserved_at_360[0x1];
1117 u8 reserved_at_368[0x3];
1119 u8 reserved_at_370[0x3];
1120 u8 log_max_tir[0x5];
1121 u8 reserved_at_378[0x3];
1122 u8 log_max_tis[0x5];
1123 u8 basic_cyclic_rcv_wqe[0x1];
1124 u8 reserved_at_381[0x2];
1125 u8 log_max_rmp[0x5];
1126 u8 reserved_at_388[0x3];
1127 u8 log_max_rqt[0x5];
1128 u8 reserved_at_390[0x3];
1129 u8 log_max_rqt_size[0x5];
1130 u8 reserved_at_398[0x3];
1131 u8 log_max_tis_per_sq[0x5];
1132 u8 ext_stride_num_range[0x1];
1133 u8 reserved_at_3a1[0x2];
1134 u8 log_max_stride_sz_rq[0x5];
1135 u8 reserved_at_3a8[0x3];
1136 u8 log_min_stride_sz_rq[0x5];
1137 u8 reserved_at_3b0[0x3];
1138 u8 log_max_stride_sz_sq[0x5];
1139 u8 reserved_at_3b8[0x3];
1140 u8 log_min_stride_sz_sq[0x5];
1142 u8 reserved_at_3c1[0x2];
1143 u8 log_max_hairpin_queues[0x5];
1144 u8 reserved_at_3c8[0x3];
1145 u8 log_max_hairpin_wq_data_sz[0x5];
1146 u8 reserved_at_3d0[0x3];
1147 u8 log_max_hairpin_num_packets[0x5];
1148 u8 reserved_at_3d8[0x3];
1149 u8 log_max_wq_sz[0x5];
1150 u8 nic_vport_change_event[0x1];
1151 u8 disable_local_lb_uc[0x1];
1152 u8 disable_local_lb_mc[0x1];
1153 u8 log_min_hairpin_wq_data_sz[0x5];
1154 u8 reserved_at_3e8[0x3];
1155 u8 log_max_vlan_list[0x5];
1156 u8 reserved_at_3f0[0x3];
1157 u8 log_max_current_mc_list[0x5];
1158 u8 reserved_at_3f8[0x3];
1159 u8 log_max_current_uc_list[0x5];
1160 u8 general_obj_types[0x40];
1161 u8 reserved_at_440[0x20];
1162 u8 reserved_at_460[0x10];
1163 u8 max_num_eqs[0x10];
1164 u8 reserved_at_480[0x3];
1165 u8 log_max_l2_table[0x5];
1166 u8 reserved_at_488[0x8];
1167 u8 log_uar_page_sz[0x10];
1168 u8 reserved_at_4a0[0x20];
1169 u8 device_frequency_mhz[0x20];
1170 u8 device_frequency_khz[0x20];
1171 u8 reserved_at_500[0x20];
1172 u8 num_of_uars_per_page[0x20];
1173 u8 flex_parser_protocols[0x20];
1174 u8 reserved_at_560[0x20];
1175 u8 reserved_at_580[0x3c];
1176 u8 mini_cqe_resp_stride_index[0x1];
1177 u8 cqe_128_always[0x1];
1178 u8 cqe_compression_128[0x1];
1179 u8 cqe_compression[0x1];
1180 u8 cqe_compression_timeout[0x10];
1181 u8 cqe_compression_max_num[0x10];
1182 u8 reserved_at_5e0[0x10];
1183 u8 tag_matching[0x1];
1184 u8 rndv_offload_rc[0x1];
1185 u8 rndv_offload_dc[0x1];
1186 u8 log_tag_matching_list_sz[0x5];
1187 u8 reserved_at_5f8[0x3];
1188 u8 log_max_xrq[0x5];
1189 u8 affiliate_nic_vport_criteria[0x8];
1190 u8 native_port_num[0x8];
1191 u8 num_vhca_ports[0x8];
1192 u8 reserved_at_618[0x6];
1193 u8 sw_owner_id[0x1];
1194 u8 reserved_at_61f[0x1e1];
1197 struct mlx5_ifc_qos_cap_bits {
1198 u8 packet_pacing[0x1];
1199 u8 esw_scheduling[0x1];
1200 u8 esw_bw_share[0x1];
1201 u8 esw_rate_limit[0x1];
1202 u8 reserved_at_4[0x1];
1203 u8 packet_pacing_burst_bound[0x1];
1204 u8 packet_pacing_typical_size[0x1];
1205 u8 flow_meter_srtcm[0x1];
1206 u8 reserved_at_8[0x8];
1207 u8 log_max_flow_meter[0x8];
1208 u8 flow_meter_reg_id[0x8];
1209 u8 reserved_at_25[0x8];
1210 u8 flow_meter_reg_share[0x1];
1211 u8 reserved_at_2e[0x17];
1212 u8 packet_pacing_max_rate[0x20];
1213 u8 packet_pacing_min_rate[0x20];
1214 u8 reserved_at_80[0x10];
1215 u8 packet_pacing_rate_table_size[0x10];
1216 u8 esw_element_type[0x10];
1217 u8 esw_tsar_type[0x10];
1218 u8 reserved_at_c0[0x10];
1219 u8 max_qos_para_vport[0x10];
1220 u8 max_tsar_bw_share[0x20];
1221 u8 reserved_at_100[0x6e8];
1224 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1228 u8 lro_psh_flag[0x1];
1229 u8 lro_time_stamp[0x1];
1230 u8 lro_max_msg_sz_mode[0x2];
1231 u8 wqe_vlan_insert[0x1];
1232 u8 self_lb_en_modifiable[0x1];
1235 u8 max_lso_cap[0x5];
1236 u8 multi_pkt_send_wqe[0x2];
1237 u8 wqe_inline_mode[0x2];
1238 u8 rss_ind_tbl_cap[0x4];
1240 u8 scatter_fcs[0x1];
1241 u8 enhanced_multi_pkt_send_wqe[0x1];
1242 u8 tunnel_lso_const_out_ip_id[0x1];
1243 u8 tunnel_lro_gre[0x1];
1244 u8 tunnel_lro_vxlan[0x1];
1245 u8 tunnel_stateless_gre[0x1];
1246 u8 tunnel_stateless_vxlan[0x1];
1250 u8 reserved_at_23[0x8];
1251 u8 tunnel_stateless_gtp[0x1];
1252 u8 reserved_at_25[0x4];
1253 u8 max_vxlan_udp_ports[0x8];
1254 u8 reserved_at_38[0x6];
1255 u8 max_geneve_opt_len[0x1];
1256 u8 tunnel_stateless_geneve_rx[0x1];
1257 u8 reserved_at_40[0x10];
1258 u8 lro_min_mss_size[0x10];
1259 u8 reserved_at_60[0x120];
1260 u8 lro_timer_supported_periods[4][0x20];
1261 u8 reserved_at_200[0x600];
1265 MLX5_VIRTQ_TYPE_SPLIT = 0,
1266 MLX5_VIRTQ_TYPE_PACKED = 1,
1270 MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0,
1271 MLX5_VIRTQ_EVENT_MODE_QP = 1,
1272 MLX5_VIRTQ_EVENT_MODE_MSIX = 2,
1275 struct mlx5_ifc_virtio_emulation_cap_bits {
1276 u8 desc_tunnel_offload_type[0x1];
1277 u8 eth_frame_offload_type[0x1];
1278 u8 virtio_version_1_0[0x1];
1283 u8 reserved_at_7[0x1][0x9];
1285 u8 virtio_queue_type[0x8];
1286 u8 reserved_at_20[0x13];
1287 u8 log_doorbell_stride[0x5];
1288 u8 reserved_at_3b[0x3];
1289 u8 log_doorbell_bar_size[0x5];
1290 u8 doorbell_bar_offset[0x40];
1291 u8 reserved_at_80[0x8];
1292 u8 max_num_virtio_queues[0x18];
1293 u8 reserved_at_a0[0x60];
1294 u8 umem_1_buffer_param_a[0x20];
1295 u8 umem_1_buffer_param_b[0x20];
1296 u8 umem_2_buffer_param_a[0x20];
1297 u8 umem_2_buffer_param_b[0x20];
1298 u8 umem_3_buffer_param_a[0x20];
1299 u8 umem_3_buffer_param_b[0x20];
1300 u8 reserved_at_1c0[0x620];
1303 union mlx5_ifc_hca_cap_union_bits {
1304 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1305 struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1306 per_protocol_networking_offload_caps;
1307 struct mlx5_ifc_qos_cap_bits qos_cap;
1308 struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
1309 u8 reserved_at_0[0x8000];
1312 struct mlx5_ifc_query_hca_cap_out_bits {
1314 u8 reserved_at_8[0x18];
1316 u8 reserved_at_40[0x40];
1317 union mlx5_ifc_hca_cap_union_bits capability;
1320 struct mlx5_ifc_query_hca_cap_in_bits {
1322 u8 reserved_at_10[0x10];
1323 u8 reserved_at_20[0x10];
1325 u8 reserved_at_40[0x40];
1328 struct mlx5_ifc_mac_address_layout_bits {
1329 u8 reserved_at_0[0x10];
1330 u8 mac_addr_47_32[0x10];
1331 u8 mac_addr_31_0[0x20];
1334 struct mlx5_ifc_nic_vport_context_bits {
1335 u8 reserved_at_0[0x5];
1336 u8 min_wqe_inline_mode[0x3];
1337 u8 reserved_at_8[0x15];
1338 u8 disable_mc_local_lb[0x1];
1339 u8 disable_uc_local_lb[0x1];
1341 u8 arm_change_event[0x1];
1342 u8 reserved_at_21[0x1a];
1343 u8 event_on_mtu[0x1];
1344 u8 event_on_promisc_change[0x1];
1345 u8 event_on_vlan_change[0x1];
1346 u8 event_on_mc_address_change[0x1];
1347 u8 event_on_uc_address_change[0x1];
1348 u8 reserved_at_40[0xc];
1349 u8 affiliation_criteria[0x4];
1350 u8 affiliated_vhca_id[0x10];
1351 u8 reserved_at_60[0xd0];
1353 u8 system_image_guid[0x40];
1356 u8 reserved_at_200[0x140];
1357 u8 qkey_violation_counter[0x10];
1358 u8 reserved_at_350[0x430];
1361 u8 promisc_all[0x1];
1362 u8 reserved_at_783[0x2];
1363 u8 allowed_list_type[0x3];
1364 u8 reserved_at_788[0xc];
1365 u8 allowed_list_size[0xc];
1366 struct mlx5_ifc_mac_address_layout_bits permanent_address;
1367 u8 reserved_at_7e0[0x20];
1370 struct mlx5_ifc_query_nic_vport_context_out_bits {
1372 u8 reserved_at_8[0x18];
1374 u8 reserved_at_40[0x40];
1375 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
1378 struct mlx5_ifc_query_nic_vport_context_in_bits {
1380 u8 reserved_at_10[0x10];
1381 u8 reserved_at_20[0x10];
1383 u8 other_vport[0x1];
1384 u8 reserved_at_41[0xf];
1385 u8 vport_number[0x10];
1386 u8 reserved_at_60[0x5];
1387 u8 allowed_list_type[0x3];
1388 u8 reserved_at_68[0x18];
1391 struct mlx5_ifc_tisc_bits {
1392 u8 strict_lag_tx_port_affinity[0x1];
1393 u8 reserved_at_1[0x3];
1394 u8 lag_tx_port_affinity[0x04];
1395 u8 reserved_at_8[0x4];
1397 u8 reserved_at_10[0x10];
1398 u8 reserved_at_20[0x100];
1399 u8 reserved_at_120[0x8];
1400 u8 transport_domain[0x18];
1401 u8 reserved_at_140[0x8];
1402 u8 underlay_qpn[0x18];
1403 u8 reserved_at_160[0x3a0];
1406 struct mlx5_ifc_query_tis_out_bits {
1408 u8 reserved_at_8[0x18];
1410 u8 reserved_at_40[0x40];
1411 struct mlx5_ifc_tisc_bits tis_context;
1414 struct mlx5_ifc_query_tis_in_bits {
1416 u8 reserved_at_10[0x10];
1417 u8 reserved_at_20[0x10];
1419 u8 reserved_at_40[0x8];
1421 u8 reserved_at_60[0x20];
1424 struct mlx5_ifc_alloc_transport_domain_out_bits {
1426 u8 reserved_at_8[0x18];
1428 u8 reserved_at_40[0x8];
1429 u8 transport_domain[0x18];
1430 u8 reserved_at_60[0x20];
1433 struct mlx5_ifc_alloc_transport_domain_in_bits {
1435 u8 reserved_at_10[0x10];
1436 u8 reserved_at_20[0x10];
1438 u8 reserved_at_40[0x40];
1442 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1443 MLX5_WQ_TYPE_CYCLIC = 0x1,
1444 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1445 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1449 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1450 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1453 struct mlx5_ifc_wq_bits {
1455 u8 wq_signature[0x1];
1456 u8 end_padding_mode[0x2];
1458 u8 reserved_at_8[0x18];
1459 u8 hds_skip_first_sge[0x1];
1460 u8 log2_hds_buf_size[0x3];
1461 u8 reserved_at_24[0x7];
1462 u8 page_offset[0x5];
1464 u8 reserved_at_40[0x8];
1466 u8 reserved_at_60[0x8];
1469 u8 hw_counter[0x20];
1470 u8 sw_counter[0x20];
1471 u8 reserved_at_100[0xc];
1472 u8 log_wq_stride[0x4];
1473 u8 reserved_at_110[0x3];
1474 u8 log_wq_pg_sz[0x5];
1475 u8 reserved_at_118[0x3];
1477 u8 dbr_umem_valid[0x1];
1478 u8 wq_umem_valid[0x1];
1479 u8 reserved_at_122[0x1];
1480 u8 log_hairpin_num_packets[0x5];
1481 u8 reserved_at_128[0x3];
1482 u8 log_hairpin_data_sz[0x5];
1483 u8 reserved_at_130[0x4];
1484 u8 single_wqe_log_num_of_strides[0x4];
1485 u8 two_byte_shift_en[0x1];
1486 u8 reserved_at_139[0x4];
1487 u8 single_stride_log_num_of_bytes[0x3];
1488 u8 dbr_umem_id[0x20];
1489 u8 wq_umem_id[0x20];
1490 u8 wq_umem_offset[0x40];
1491 u8 reserved_at_1c0[0x440];
1495 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1496 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
1500 MLX5_RQC_STATE_RST = 0x0,
1501 MLX5_RQC_STATE_RDY = 0x1,
1502 MLX5_RQC_STATE_ERR = 0x3,
1505 struct mlx5_ifc_rqc_bits {
1507 u8 delay_drop_en[0x1];
1508 u8 scatter_fcs[0x1];
1510 u8 mem_rq_type[0x4];
1512 u8 reserved_at_c[0x1];
1513 u8 flush_in_error_en[0x1];
1515 u8 reserved_at_f[0x11];
1516 u8 reserved_at_20[0x8];
1517 u8 user_index[0x18];
1518 u8 reserved_at_40[0x8];
1520 u8 counter_set_id[0x8];
1521 u8 reserved_at_68[0x18];
1522 u8 reserved_at_80[0x8];
1524 u8 reserved_at_a0[0x8];
1525 u8 hairpin_peer_sq[0x18];
1526 u8 reserved_at_c0[0x10];
1527 u8 hairpin_peer_vhca[0x10];
1528 u8 reserved_at_e0[0xa0];
1529 struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
1532 struct mlx5_ifc_create_rq_out_bits {
1534 u8 reserved_at_8[0x18];
1536 u8 reserved_at_40[0x8];
1538 u8 reserved_at_60[0x20];
1541 struct mlx5_ifc_create_rq_in_bits {
1544 u8 reserved_at_20[0x10];
1546 u8 reserved_at_40[0xc0];
1547 struct mlx5_ifc_rqc_bits ctx;
1550 struct mlx5_ifc_modify_rq_out_bits {
1552 u8 reserved_at_8[0x18];
1554 u8 reserved_at_40[0x40];
1557 struct mlx5_ifc_create_tis_out_bits {
1559 u8 reserved_at_8[0x18];
1561 u8 reserved_at_40[0x8];
1563 u8 reserved_at_60[0x20];
1566 struct mlx5_ifc_create_tis_in_bits {
1569 u8 reserved_at_20[0x10];
1571 u8 reserved_at_40[0xc0];
1572 struct mlx5_ifc_tisc_bits ctx;
1576 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
1577 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
1578 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
1579 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
1582 struct mlx5_ifc_modify_rq_in_bits {
1585 u8 reserved_at_20[0x10];
1588 u8 reserved_at_44[0x4];
1590 u8 reserved_at_60[0x20];
1591 u8 modify_bitmask[0x40];
1592 u8 reserved_at_c0[0x40];
1593 struct mlx5_ifc_rqc_bits ctx;
1597 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1598 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1599 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1600 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1601 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1604 struct mlx5_ifc_rx_hash_field_select_bits {
1605 u8 l3_prot_type[0x1];
1606 u8 l4_prot_type[0x1];
1607 u8 selected_fields[0x1e];
1611 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
1612 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
1616 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
1617 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
1621 MLX5_RX_HASH_FN_NONE = 0x0,
1622 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
1623 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
1627 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
1628 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
1632 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 = 0x0,
1633 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2 = 0x1,
1636 struct mlx5_ifc_tirc_bits {
1637 u8 reserved_at_0[0x20];
1639 u8 reserved_at_24[0x1c];
1640 u8 reserved_at_40[0x40];
1641 u8 reserved_at_80[0x4];
1642 u8 lro_timeout_period_usecs[0x10];
1643 u8 lro_enable_mask[0x4];
1644 u8 lro_max_msg_sz[0x8];
1645 u8 reserved_at_a0[0x40];
1646 u8 reserved_at_e0[0x8];
1647 u8 inline_rqn[0x18];
1648 u8 rx_hash_symmetric[0x1];
1649 u8 reserved_at_101[0x1];
1650 u8 tunneled_offload_en[0x1];
1651 u8 reserved_at_103[0x5];
1652 u8 indirect_table[0x18];
1654 u8 reserved_at_124[0x2];
1655 u8 self_lb_block[0x2];
1656 u8 transport_domain[0x18];
1657 u8 rx_hash_toeplitz_key[10][0x20];
1658 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1659 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1660 u8 reserved_at_2c0[0x4c0];
1663 struct mlx5_ifc_create_tir_out_bits {
1665 u8 reserved_at_8[0x18];
1667 u8 reserved_at_40[0x8];
1669 u8 reserved_at_60[0x20];
1672 struct mlx5_ifc_create_tir_in_bits {
1675 u8 reserved_at_20[0x10];
1677 u8 reserved_at_40[0xc0];
1678 struct mlx5_ifc_tirc_bits ctx;
1681 struct mlx5_ifc_rq_num_bits {
1682 u8 reserved_at_0[0x8];
1686 struct mlx5_ifc_rqtc_bits {
1687 u8 reserved_at_0[0xa0];
1688 u8 reserved_at_a0[0x10];
1689 u8 rqt_max_size[0x10];
1690 u8 reserved_at_c0[0x10];
1691 u8 rqt_actual_size[0x10];
1692 u8 reserved_at_e0[0x6a0];
1693 struct mlx5_ifc_rq_num_bits rq_num[];
1696 struct mlx5_ifc_create_rqt_out_bits {
1698 u8 reserved_at_8[0x18];
1700 u8 reserved_at_40[0x8];
1702 u8 reserved_at_60[0x20];
1706 #pragma GCC diagnostic ignored "-Wpedantic"
1708 struct mlx5_ifc_create_rqt_in_bits {
1711 u8 reserved_at_20[0x10];
1713 u8 reserved_at_40[0xc0];
1714 struct mlx5_ifc_rqtc_bits rqt_context;
1717 #pragma GCC diagnostic error "-Wpedantic"
1721 MLX5_SQC_STATE_RST = 0x0,
1722 MLX5_SQC_STATE_RDY = 0x1,
1723 MLX5_SQC_STATE_ERR = 0x3,
1726 struct mlx5_ifc_sqc_bits {
1730 u8 flush_in_error_en[0x1];
1731 u8 allow_multi_pkt_send_wqe[0x1];
1732 u8 min_wqe_inline_mode[0x3];
1737 u8 reserved_at_f[0x11];
1738 u8 reserved_at_20[0x8];
1739 u8 user_index[0x18];
1740 u8 reserved_at_40[0x8];
1742 u8 reserved_at_60[0x8];
1743 u8 hairpin_peer_rq[0x18];
1744 u8 reserved_at_80[0x10];
1745 u8 hairpin_peer_vhca[0x10];
1746 u8 reserved_at_a0[0x50];
1747 u8 packet_pacing_rate_limit_index[0x10];
1748 u8 tis_lst_sz[0x10];
1749 u8 reserved_at_110[0x10];
1750 u8 reserved_at_120[0x40];
1751 u8 reserved_at_160[0x8];
1753 struct mlx5_ifc_wq_bits wq;
1756 struct mlx5_ifc_query_sq_in_bits {
1758 u8 reserved_at_10[0x10];
1759 u8 reserved_at_20[0x10];
1761 u8 reserved_at_40[0x8];
1763 u8 reserved_at_60[0x20];
1766 struct mlx5_ifc_modify_sq_out_bits {
1768 u8 reserved_at_8[0x18];
1770 u8 reserved_at_40[0x40];
1773 struct mlx5_ifc_modify_sq_in_bits {
1776 u8 reserved_at_20[0x10];
1779 u8 reserved_at_44[0x4];
1781 u8 reserved_at_60[0x20];
1782 u8 modify_bitmask[0x40];
1783 u8 reserved_at_c0[0x40];
1784 struct mlx5_ifc_sqc_bits ctx;
1787 struct mlx5_ifc_create_sq_out_bits {
1789 u8 reserved_at_8[0x18];
1791 u8 reserved_at_40[0x8];
1793 u8 reserved_at_60[0x20];
1796 struct mlx5_ifc_create_sq_in_bits {
1799 u8 reserved_at_20[0x10];
1801 u8 reserved_at_40[0xc0];
1802 struct mlx5_ifc_sqc_bits ctx;
1806 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
1807 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
1808 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
1809 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
1810 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
1813 struct mlx5_ifc_flow_meter_parameters_bits {
1814 u8 valid[0x1]; // 00h
1815 u8 bucket_overflow[0x1];
1816 u8 start_color[0x2];
1817 u8 both_buckets_on_green[0x1];
1819 u8 reserved_at_1[0x19];
1820 u8 reserved_at_2[0x20]; //04h
1821 u8 reserved_at_3[0x3];
1822 u8 cbs_exponent[0x5]; // 08h
1823 u8 cbs_mantissa[0x8];
1824 u8 reserved_at_4[0x3];
1825 u8 cir_exponent[0x5];
1826 u8 cir_mantissa[0x8];
1827 u8 reserved_at_5[0x20]; // 0Ch
1828 u8 reserved_at_6[0x3];
1829 u8 ebs_exponent[0x5]; // 10h
1830 u8 ebs_mantissa[0x8];
1831 u8 reserved_at_7[0x3];
1832 u8 eir_exponent[0x5];
1833 u8 eir_mantissa[0x8];
1834 u8 reserved_at_8[0x60]; // 14h-1Ch
1837 /* CQE format mask. */
1838 #define MLX5E_CQE_FORMAT_MASK 0xc
1841 #define MLX5_OPC_MOD_MPW 0x01
1843 /* Compressed Rx CQE structure. */
1844 struct mlx5_mini_cqe8 {
1846 uint32_t rx_hash_result;
1849 uint16_t stride_idx;
1852 uint16_t wqe_counter;
1853 uint8_t s_wqe_opcode;
1860 /* srTCM PRM flow meter parameters. */
1862 MLX5_FLOW_COLOR_RED = 0,
1863 MLX5_FLOW_COLOR_YELLOW,
1864 MLX5_FLOW_COLOR_GREEN,
1865 MLX5_FLOW_COLOR_UNDEFINED,
1868 /* Maximum value of srTCM metering parameters. */
1869 #define MLX5_SRTCM_CBS_MAX (0xFF * (1ULL << 0x1F))
1870 #define MLX5_SRTCM_CIR_MAX (8 * (1ULL << 30) * 0xFF)
1871 #define MLX5_SRTCM_EBS_MAX 0
1873 /* The bits meter color use. */
1874 #define MLX5_MTR_COLOR_BITS 8
1877 * Convert a user mark to flow mark.
1880 * Mark value to convert.
1883 * Converted mark value.
1885 static inline uint32_t
1886 mlx5_flow_mark_set(uint32_t val)
1891 * Add one to the user value to differentiate un-marked flows from
1892 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
1893 * remains untouched.
1895 if (val != MLX5_FLOW_MARK_DEFAULT)
1897 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1899 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
1900 * word, byte-swapped by the kernel on little-endian systems. In this
1901 * case, left-shifting the resulting big-endian value ensures the
1902 * least significant 24 bits are retained when converting it back.
1904 ret = rte_cpu_to_be_32(val) >> 8;
1912 * Convert a mark to user mark.
1915 * Mark value to convert.
1918 * Converted mark value.
1920 static inline uint32_t
1921 mlx5_flow_mark_get(uint32_t val)
1924 * Subtract one from the retrieved value. It was added by
1925 * mlx5_flow_mark_set() to distinguish unmarked flows.
1927 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
1928 return (val >> 8) - 1;
1934 #endif /* RTE_PMD_MLX5_PRM_H_ */