drivers/common/mlx5/mlx5_prm.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2016 6WIND S.A.
   3  * Copyright 2016 Mellanox Technologies, Ltd
   4  */
   5
   6 #ifndef RTE_PMD_MLX5_PRM_H_
   7 #define RTE_PMD_MLX5_PRM_H_
   8
   9 #include <unistd.h>
  10
  11 #include <rte_vect.h>
  12 #include <rte_byteorder.h>
  13
  14 #include <mlx5_glue.h>
  15 #include "mlx5_autoconf.h"
  16
  17 /* RSS hash key size. */
  18 #define MLX5_RSS_HASH_KEY_LEN 40
  19
  20 /* Get CQE owner bit. */
  21 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
  22
  23 /* Get CQE format. */
  24 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
  25
  26 /* Get CQE opcode. */
  27 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
  28
  29 /* Get CQE solicited event. */
  30 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
  31
  32 /* Invalidate a CQE. */
  33 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
  34
  35 /* Hardware index widths. */
  36 #define MLX5_CQ_INDEX_WIDTH 24
  37 #define MLX5_WQ_INDEX_WIDTH 16
  38
  39 /* WQE Segment sizes in bytes. */
  40 #define MLX5_WSEG_SIZE 16u
  41 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
  42 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
  43 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
  44
  45 /* WQE/WQEBB size in bytes. */
  46 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
  47
  48 /*
  49  * Max size of a WQE session.
  50  * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
  51  * the WQE size field in Control Segment is 6 bits wide.
  52  */
  53 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
  54
  55 /*
  56  * Default minimum number of Tx queues for inlining packets.
  57  * If there are less queues as specified we assume we have
  58  * no enough CPU resources (cycles) to perform inlining,
  59  * the PCIe throughput is not supposed as bottleneck and
  60  * inlining is disabled.
  61  */
  62 #define MLX5_INLINE_MAX_TXQS 8u
  63 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
  64
  65 /*
  66  * Default packet length threshold to be inlined with
  67  * enhanced MPW. If packet length exceeds the threshold
  68  * the data are not inlined. Should be aligned in WQEBB
  69  * boundary with accounting the title Control and Ethernet
  70  * segments.
  71  */
  72 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
  73                                   MLX5_DSEG_MIN_INLINE_SIZE)
  74 /*
  75  * Maximal inline data length sent with enhanced MPW.
  76  * Is based on maximal WQE size.
  77  */
  78 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
  79                                   MLX5_WQE_CSEG_SIZE - \
  80                                   MLX5_WQE_ESEG_SIZE - \
  81                                   MLX5_WQE_DSEG_SIZE + \
  82                                   MLX5_DSEG_MIN_INLINE_SIZE)
  83 /*
  84  * Minimal amount of packets to be sent with EMPW.
  85  * This limits the minimal required size of sent EMPW.
  86  * If there are no enough resources to built minimal
  87  * EMPW the sending loop exits.
  88  */
  89 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
  90 /*
  91  * Maximal amount of packets to be sent with EMPW.
  92  * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
  93  * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
  94  * without CQE generation request, being multiplied by
  95  * MLX5_TX_COMP_MAX_CQE it may cause significant latency
  96  * in tx burst routine at the moment of freeing multiple mbufs.
  97  */
  98 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
  99 #define MLX5_MPW_MAX_PACKETS 6
 100 #define MLX5_MPW_INLINE_MAX_PACKETS 6
 101
 102 /*
 103  * Default packet length threshold to be inlined with
 104  * ordinary SEND. Inlining saves the MR key search
 105  * and extra PCIe data fetch transaction, but eats the
 106  * CPU cycles.
 107  */
 108 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
 109                                   MLX5_ESEG_MIN_INLINE_SIZE - \
 110                                   MLX5_WQE_CSEG_SIZE - \
 111                                   MLX5_WQE_ESEG_SIZE - \
 112                                   MLX5_WQE_DSEG_SIZE)
 113 /*
 114  * Maximal inline data length sent with ordinary SEND.
 115  * Is based on maximal WQE size.
 116  */
 117 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
 118                                   MLX5_WQE_CSEG_SIZE - \
 119                                   MLX5_WQE_ESEG_SIZE - \
 120                                   MLX5_WQE_DSEG_SIZE + \
 121                                   MLX5_ESEG_MIN_INLINE_SIZE)
 122
 123 /* Missed in mlx5dv.h, should define here. */
 124 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW
 125 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
 126 #endif
 127
 128 #ifndef HAVE_MLX5_OPCODE_SEND_EN
 129 #define MLX5_OPCODE_SEND_EN 0x17u
 130 #endif
 131
 132 #ifndef HAVE_MLX5_OPCODE_WAIT
 133 #define MLX5_OPCODE_WAIT 0x0fu
 134 #endif
 135
 136 #ifndef HAVE_MLX5_OPCODE_ACCESS_ASO
 137 #define MLX5_OPCODE_ACCESS_ASO 0x2du
 138 #endif
 139
 140 /* CQE value to inform that VLAN is stripped. */
 141 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
 142
 143 /* IPv4 options. */
 144 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
 145
 146 /* IPv6 packet. */
 147 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
 148
 149 /* IPv4 packet. */
 150 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
 151
 152 /* TCP packet. */
 153 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
 154
 155 /* UDP packet. */
 156 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
 157
 158 /* IP is fragmented. */
 159 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
 160
 161 /* L2 header is valid. */
 162 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
 163
 164 /* L3 header is valid. */
 165 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
 166
 167 /* L4 header is valid. */
 168 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
 169
 170 /* Outer packet, 0 IPv4, 1 IPv6. */
 171 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
 172
 173 /* Tunnel packet bit in the CQE. */
 174 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
 175
 176 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
 177 #define MLX5_CQE_LRO_PUSH_MASK 0x40
 178
 179 /* Mask for L4 type in the CQE hdr_type_etc field. */
 180 #define MLX5_CQE_L4_TYPE_MASK 0x70
 181
 182 /* The bit index of L4 type in CQE hdr_type_etc field. */
 183 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
 184
 185 /* L4 type to indicate TCP packet without acknowledgment. */
 186 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
 187
 188 /* L4 type to indicate TCP packet with acknowledgment. */
 189 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
 190
 191 /* Inner L3 checksum offload (Tunneled packets only). */
 192 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
 193
 194 /* Inner L4 checksum offload (Tunneled packets only). */
 195 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
 196
 197 /* Outer L4 type is TCP. */
 198 #define MLX5_ETH_WQE_L4_OUTER_TCP  (0u << 5)
 199
 200 /* Outer L4 type is UDP. */
 201 #define MLX5_ETH_WQE_L4_OUTER_UDP  (1u << 5)
 202
 203 /* Outer L3 type is IPV4. */
 204 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
 205
 206 /* Outer L3 type is IPV6. */
 207 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
 208
 209 /* Inner L4 type is TCP. */
 210 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
 211
 212 /* Inner L4 type is UDP. */
 213 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
 214
 215 /* Inner L3 type is IPV4. */
 216 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
 217
 218 /* Inner L3 type is IPV6. */
 219 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
 220
 221 /* VLAN insertion flag. */
 222 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
 223
 224 /* Data inline segment flag. */
 225 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
 226
 227 /* Is flow mark valid. */
 228 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
 229 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
 230 #else
 231 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
 232 #endif
 233
 234 /* INVALID is used by packets matching no flow rules. */
 235 #define MLX5_FLOW_MARK_INVALID 0
 236
 237 /* Maximum allowed value to mark a packet. */
 238 #define MLX5_FLOW_MARK_MAX 0xfffff0
 239
 240 /* Default mark value used when none is provided. */
 241 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
 242
 243 /* Default mark mask for metadata legacy mode. */
 244 #define MLX5_FLOW_MARK_MASK 0xffffff
 245
 246 /* Byte length mask when mark is enable in miniCQE */
 247 #define MLX5_LEN_WITH_MARK_MASK 0xffffff00
 248
 249 /* Maximum number of DS in WQE. Limited by 6-bit field. */
 250 #define MLX5_DSEG_MAX 63
 251
 252 /* The completion mode offset in the WQE control segment line 2. */
 253 #define MLX5_COMP_MODE_OFFSET 2
 254
 255 /* Amount of data bytes in minimal inline data segment. */
 256 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
 257
 258 /* Amount of data bytes in minimal inline eth segment. */
 259 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
 260
 261 /* Amount of data bytes after eth data segment. */
 262 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
 263
 264 /* The maximum log value of segments per RQ WQE. */
 265 #define MLX5_MAX_LOG_RQ_SEGS 5u
 266
 267 /* Log 2 of the default size of a WQE for Multi-Packet RQ. */
 268 #define MLX5_MPRQ_LOG_MIN_STRIDE_WQE_SIZE 14U
 269
 270 /* The alignment needed for WQ buffer. */
 271 #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size()
 272
 273 /* The alignment needed for CQ buffer. */
 274 #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size()
 275
 276 /* Completion mode. */
 277 enum mlx5_completion_mode {
 278         MLX5_COMP_ONLY_ERR = 0x0,
 279         MLX5_COMP_ONLY_FIRST_ERR = 0x1,
 280         MLX5_COMP_ALWAYS = 0x2,
 281         MLX5_COMP_CQE_AND_EQE = 0x3,
 282 };
 283
 284 /* MPW mode. */
 285 enum mlx5_mpw_mode {
 286         MLX5_MPW_DISABLED,
 287         MLX5_MPW,
 288         MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
 289 };
 290
 291 /* WQE Control segment. */
 292 struct mlx5_wqe_cseg {
 293         uint32_t opcode;
 294         uint32_t sq_ds;
 295         uint32_t flags;
 296         uint32_t misc;
 297 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
 298
 299 /*
 300  * WQE CSEG opcode field size is 32 bits, divided:
 301  * Bits 31:24 OPC_MOD
 302  * Bits 23:8 wqe_index
 303  * Bits 7:0 OPCODE
 304  */
 305 #define WQE_CSEG_OPC_MOD_OFFSET         24
 306 #define WQE_CSEG_WQE_INDEX_OFFSET        8
 307
 308 /* Header of data segment. Minimal size Data Segment */
 309 struct mlx5_wqe_dseg {
 310         uint32_t bcount;
 311         union {
 312                 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
 313                 struct {
 314                         uint32_t lkey;
 315                         uint64_t pbuf;
 316                 } __rte_packed;
 317         };
 318 } __rte_packed;
 319
 320 /* Subset of struct WQE Ethernet Segment. */
 321 struct mlx5_wqe_eseg {
 322         union {
 323                 struct {
 324                         uint32_t swp_offs;
 325                         uint8_t cs_flags;
 326                         uint8_t swp_flags;
 327                         uint16_t mss;
 328                         uint32_t metadata;
 329                         uint16_t inline_hdr_sz;
 330                         union {
 331                                 uint16_t inline_data;
 332                                 uint16_t vlan_tag;
 333                         };
 334                 } __rte_packed;
 335                 struct {
 336                         uint32_t offsets;
 337                         uint32_t flags;
 338                         uint32_t flow_metadata;
 339                         uint32_t inline_hdr;
 340                 } __rte_packed;
 341         };
 342 } __rte_packed;
 343
 344 struct mlx5_wqe_qseg {
 345         uint32_t reserved0;
 346         uint32_t reserved1;
 347         uint32_t max_index;
 348         uint32_t qpn_cqn;
 349 } __rte_packed;
 350
 351 /* The title WQEBB, header of WQE. */
 352 struct mlx5_wqe {
 353         union {
 354                 struct mlx5_wqe_cseg cseg;
 355                 uint32_t ctrl[4];
 356         };
 357         struct mlx5_wqe_eseg eseg;
 358         union {
 359                 struct mlx5_wqe_dseg dseg[2];
 360                 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
 361         };
 362 } __rte_packed;
 363
 364 /* WQE for Multi-Packet RQ. */
 365 struct mlx5_wqe_mprq {
 366         struct mlx5_wqe_srq_next_seg next_seg;
 367         struct mlx5_wqe_data_seg dseg;
 368 };
 369
 370 #define MLX5_MPRQ_LEN_MASK 0x000ffff
 371 #define MLX5_MPRQ_LEN_SHIFT 0
 372 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
 373 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
 374 #define MLX5_MPRQ_FILLER_MASK 0x80000000
 375 #define MLX5_MPRQ_FILLER_SHIFT 31
 376
 377 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
 378
 379 /* CQ element structure - should be equal to the cache line size */
 380 struct mlx5_cqe {
 381 #if (RTE_CACHE_LINE_SIZE == 128)
 382         uint8_t padding[64];
 383 #endif
 384         uint8_t pkt_info;
 385         uint8_t rsvd0;
 386         uint16_t wqe_id;
 387         uint8_t lro_tcppsh_abort_dupack;
 388         uint8_t lro_min_ttl;
 389         uint16_t lro_tcp_win;
 390         uint32_t lro_ack_seq_num;
 391         uint32_t rx_hash_res;
 392         uint8_t rx_hash_type;
 393         uint8_t rsvd1[3];
 394         uint16_t csum;
 395         uint8_t rsvd2[6];
 396         uint16_t hdr_type_etc;
 397         uint16_t vlan_info;
 398         uint8_t lro_num_seg;
 399         union {
 400                 uint8_t user_index_bytes[3];
 401                 struct {
 402                         uint8_t user_index_hi;
 403                         uint16_t user_index_low;
 404                 } __rte_packed;
 405         };
 406         uint32_t flow_table_metadata;
 407         uint8_t rsvd4[4];
 408         uint32_t byte_cnt;
 409         uint64_t timestamp;
 410         uint32_t sop_drop_qpn;
 411         uint16_t wqe_counter;
 412         uint8_t rsvd5;
 413         uint8_t op_own;
 414 };
 415
 416 struct mlx5_cqe_ts {
 417         uint64_t timestamp;
 418         uint32_t sop_drop_qpn;
 419         uint16_t wqe_counter;
 420         uint8_t rsvd5;
 421         uint8_t op_own;
 422 };
 423
 424 struct mlx5_wqe_rseg {
 425         uint64_t raddr;
 426         uint32_t rkey;
 427         uint32_t reserved;
 428 } __rte_packed;
 429
 430 #define MLX5_UMRC_IF_OFFSET 31u
 431 #define MLX5_UMRC_KO_OFFSET 16u
 432 #define MLX5_UMRC_TO_BS_OFFSET 0u
 433
 434 struct mlx5_wqe_umr_cseg {
 435         uint32_t if_cf_toe_cq_res;
 436         uint32_t ko_to_bs;
 437         uint64_t mkey_mask;
 438         uint32_t rsvd1[8];
 439 } __rte_packed;
 440
 441 struct mlx5_wqe_mkey_cseg {
 442         uint32_t fr_res_af_sf;
 443         uint32_t qpn_mkey;
 444         uint32_t reserved2;
 445         uint32_t flags_pd;
 446         uint64_t start_addr;
 447         uint64_t len;
 448         uint32_t bsf_octword_size;
 449         uint32_t reserved3[4];
 450         uint32_t translations_octword_size;
 451         uint32_t res4_lps;
 452         uint32_t reserved;
 453 } __rte_packed;
 454
 455 enum {
 456         MLX5_BSF_SIZE_16B = 0x0,
 457         MLX5_BSF_SIZE_32B = 0x1,
 458         MLX5_BSF_SIZE_64B = 0x2,
 459         MLX5_BSF_SIZE_128B = 0x3,
 460 };
 461
 462 enum {
 463         MLX5_BSF_P_TYPE_SIGNATURE = 0x0,
 464         MLX5_BSF_P_TYPE_CRYPTO = 0x1,
 465 };
 466
 467 enum {
 468         MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0,
 469         MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1,
 470         MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2,
 471         MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3,
 472 };
 473
 474 enum {
 475         MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0,
 476 };
 477
 478 enum {
 479         MLX5_BLOCK_SIZE_512B    = 0x1,
 480         MLX5_BLOCK_SIZE_520B    = 0x2,
 481         MLX5_BLOCK_SIZE_4096B   = 0x3,
 482         MLX5_BLOCK_SIZE_4160B   = 0x4,
 483         MLX5_BLOCK_SIZE_1MB     = 0x5,
 484         MLX5_BLOCK_SIZE_4048B   = 0x6,
 485 };
 486
 487 #define MLX5_BSF_SIZE_OFFSET            30
 488 #define MLX5_BSF_P_TYPE_OFFSET          24
 489 #define MLX5_ENCRYPTION_ORDER_OFFSET    16
 490 #define MLX5_BLOCK_SIZE_OFFSET          24
 491
 492 struct mlx5_wqe_umr_bsf_seg {
 493         /*
 494          * bs_bpt_eo_es contains:
 495          * bs   bsf_size                2 bits at MLX5_BSF_SIZE_OFFSET
 496          * bpt  bsf_p_type              2 bits at MLX5_BSF_P_TYPE_OFFSET
 497          * eo   encryption_order        4 bits at MLX5_ENCRYPTION_ORDER_OFFSET
 498          * es   encryption_standard     4 bits at offset 0
 499          */
 500         uint32_t bs_bpt_eo_es;
 501         uint32_t raw_data_size;
 502         /*
 503          * bsp_res contains:
 504          * bsp  crypto_block_size_pointer       8 bits at MLX5_BLOCK_SIZE_OFFSET
 505          * res  reserved 24 bits
 506          */
 507         uint32_t bsp_res;
 508         uint32_t reserved0;
 509         uint8_t xts_initial_tweak[16];
 510         /*
 511          * res_dp contains:
 512          * res  reserved 8 bits
 513          * dp   dek_pointer             24 bits at offset 0
 514          */
 515         uint32_t res_dp;
 516         uint32_t reserved1;
 517         uint64_t keytag;
 518         uint32_t reserved2[4];
 519 } __rte_packed;
 520
 521 #ifdef PEDANTIC
 522 #pragma GCC diagnostic ignored "-Wpedantic"
 523 #endif
 524
 525 struct mlx5_umr_wqe {
 526         struct mlx5_wqe_cseg ctr;
 527         struct mlx5_wqe_umr_cseg ucseg;
 528         struct mlx5_wqe_mkey_cseg mkc;
 529         union {
 530                 struct mlx5_wqe_dseg kseg[0];
 531                 struct mlx5_wqe_umr_bsf_seg bsf[0];
 532         };
 533 } __rte_packed;
 534
 535 struct mlx5_rdma_write_wqe {
 536         struct mlx5_wqe_cseg ctr;
 537         struct mlx5_wqe_rseg rseg;
 538         struct mlx5_wqe_dseg dseg[0];
 539 } __rte_packed;
 540
 541 #ifdef PEDANTIC
 542 #pragma GCC diagnostic error "-Wpedantic"
 543 #endif
 544
 545 /* GGA */
 546 /* MMO metadata segment */
 547
 548 #define MLX5_OPCODE_MMO 0x2fu
 549 #define MLX5_OPC_MOD_MMO_REGEX 0x4u
 550 #define MLX5_OPC_MOD_MMO_COMP 0x2u
 551 #define MLX5_OPC_MOD_MMO_DECOMP 0x3u
 552 #define MLX5_OPC_MOD_MMO_DMA 0x1u
 553
 554 #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u
 555 #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u
 556 #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u
 557 #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u
 558 #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS)
 559 #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u
 560 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u
 561 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u
 562
 563 struct mlx5_wqe_metadata_seg {
 564         uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */
 565         uint32_t lkey;
 566         uint64_t addr;
 567 };
 568
 569 struct mlx5_gga_wqe {
 570         uint32_t opcode;
 571         uint32_t sq_ds;
 572         uint32_t flags;
 573         uint32_t gga_ctrl1;  /* ws 12-15, bs 16-19, dyns 20-23. */
 574         uint32_t gga_ctrl2;
 575         uint32_t opaque_lkey;
 576         uint64_t opaque_vaddr;
 577         struct mlx5_wqe_dseg gather;
 578         struct mlx5_wqe_dseg scatter;
 579 } __rte_packed;
 580
 581 struct mlx5_gga_compress_opaque {
 582         uint32_t syndrom;
 583         uint32_t reserved0;
 584         uint32_t scattered_length;
 585         uint32_t gathered_length;
 586         uint64_t scatter_crc;
 587         uint64_t gather_crc;
 588         uint32_t crc32;
 589         uint32_t adler32;
 590         uint8_t reserved1[216];
 591 } __rte_packed;
 592
 593 struct mlx5_ifc_regexp_mmo_control_bits {
 594         uint8_t reserved_at_31[0x2];
 595         uint8_t le[0x1];
 596         uint8_t reserved_at_28[0x1];
 597         uint8_t subset_id_0[0xc];
 598         uint8_t reserved_at_16[0x4];
 599         uint8_t subset_id_1[0xc];
 600         uint8_t ctrl[0x4];
 601         uint8_t subset_id_2[0xc];
 602         uint8_t reserved_at_16_1[0x4];
 603         uint8_t subset_id_3[0xc];
 604 };
 605
 606 struct mlx5_ifc_regexp_metadata_bits {
 607         uint8_t rof_version[0x10];
 608         uint8_t latency_count[0x10];
 609         uint8_t instruction_count[0x10];
 610         uint8_t primary_thread_count[0x10];
 611         uint8_t match_count[0x8];
 612         uint8_t detected_match_count[0x8];
 613         uint8_t status[0x10];
 614         uint8_t job_id[0x20];
 615         uint8_t reserved[0x80];
 616 };
 617
 618 struct mlx5_ifc_regexp_match_tuple_bits {
 619         uint8_t length[0x10];
 620         uint8_t start_ptr[0x10];
 621         uint8_t rule_id[0x20];
 622 };
 623
 624 /* Adding direct verbs to data-path. */
 625
 626 /* CQ sequence number mask. */
 627 #define MLX5_CQ_SQN_MASK 0x3
 628
 629 /* CQ sequence number index. */
 630 #define MLX5_CQ_SQN_OFFSET 28
 631
 632 /* CQ doorbell index mask. */
 633 #define MLX5_CI_MASK 0xffffff
 634
 635 /* CQ doorbell offset. */
 636 #define MLX5_CQ_ARM_DB 1
 637
 638 /* CQ doorbell offset*/
 639 #define MLX5_CQ_DOORBELL 0x20
 640
 641 /* CQE format value. */
 642 #define MLX5_COMPRESSED 0x3
 643
 644 /* CQ doorbell cmd types. */
 645 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24)
 646 #define MLX5_CQ_DBR_CMD_ALL (0 << 24)
 647
 648 /* Action type of header modification. */
 649 enum {
 650         MLX5_MODIFICATION_TYPE_SET = 0x1,
 651         MLX5_MODIFICATION_TYPE_ADD = 0x2,
 652         MLX5_MODIFICATION_TYPE_COPY = 0x3,
 653 };
 654
 655 /* The field of packet to be modified. */
 656 enum mlx5_modification_field {
 657         MLX5_MODI_OUT_NONE = -1,
 658         MLX5_MODI_OUT_SMAC_47_16 = 1,
 659         MLX5_MODI_OUT_SMAC_15_0,
 660         MLX5_MODI_OUT_ETHERTYPE,
 661         MLX5_MODI_OUT_DMAC_47_16,
 662         MLX5_MODI_OUT_DMAC_15_0,
 663         MLX5_MODI_OUT_IP_DSCP,
 664         MLX5_MODI_OUT_TCP_FLAGS,
 665         MLX5_MODI_OUT_TCP_SPORT,
 666         MLX5_MODI_OUT_TCP_DPORT,
 667         MLX5_MODI_OUT_IPV4_TTL,
 668         MLX5_MODI_OUT_UDP_SPORT,
 669         MLX5_MODI_OUT_UDP_DPORT,
 670         MLX5_MODI_OUT_SIPV6_127_96,
 671         MLX5_MODI_OUT_SIPV6_95_64,
 672         MLX5_MODI_OUT_SIPV6_63_32,
 673         MLX5_MODI_OUT_SIPV6_31_0,
 674         MLX5_MODI_OUT_DIPV6_127_96,
 675         MLX5_MODI_OUT_DIPV6_95_64,
 676         MLX5_MODI_OUT_DIPV6_63_32,
 677         MLX5_MODI_OUT_DIPV6_31_0,
 678         MLX5_MODI_OUT_SIPV4,
 679         MLX5_MODI_OUT_DIPV4,
 680         MLX5_MODI_OUT_FIRST_VID,
 681         MLX5_MODI_IN_SMAC_47_16 = 0x31,
 682         MLX5_MODI_IN_SMAC_15_0,
 683         MLX5_MODI_IN_ETHERTYPE,
 684         MLX5_MODI_IN_DMAC_47_16,
 685         MLX5_MODI_IN_DMAC_15_0,
 686         MLX5_MODI_IN_IP_DSCP,
 687         MLX5_MODI_IN_TCP_FLAGS,
 688         MLX5_MODI_IN_TCP_SPORT,
 689         MLX5_MODI_IN_TCP_DPORT,
 690         MLX5_MODI_IN_IPV4_TTL,
 691         MLX5_MODI_IN_UDP_SPORT,
 692         MLX5_MODI_IN_UDP_DPORT,
 693         MLX5_MODI_IN_SIPV6_127_96,
 694         MLX5_MODI_IN_SIPV6_95_64,
 695         MLX5_MODI_IN_SIPV6_63_32,
 696         MLX5_MODI_IN_SIPV6_31_0,
 697         MLX5_MODI_IN_DIPV6_127_96,
 698         MLX5_MODI_IN_DIPV6_95_64,
 699         MLX5_MODI_IN_DIPV6_63_32,
 700         MLX5_MODI_IN_DIPV6_31_0,
 701         MLX5_MODI_IN_SIPV4,
 702         MLX5_MODI_IN_DIPV4,
 703         MLX5_MODI_OUT_IPV6_HOPLIMIT,
 704         MLX5_MODI_IN_IPV6_HOPLIMIT,
 705         MLX5_MODI_META_DATA_REG_A,
 706         MLX5_MODI_META_DATA_REG_B = 0x50,
 707         MLX5_MODI_META_REG_C_0,
 708         MLX5_MODI_META_REG_C_1,
 709         MLX5_MODI_META_REG_C_2,
 710         MLX5_MODI_META_REG_C_3,
 711         MLX5_MODI_META_REG_C_4,
 712         MLX5_MODI_META_REG_C_5,
 713         MLX5_MODI_META_REG_C_6,
 714         MLX5_MODI_META_REG_C_7,
 715         MLX5_MODI_OUT_TCP_SEQ_NUM,
 716         MLX5_MODI_IN_TCP_SEQ_NUM,
 717         MLX5_MODI_OUT_TCP_ACK_NUM,
 718         MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
 719         MLX5_MODI_GTP_TEID = 0x6E,
 720 };
 721
 722 /* Total number of metadata reg_c's. */
 723 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1)
 724
 725 enum modify_reg {
 726         REG_NON = 0,
 727         REG_A,
 728         REG_B,
 729         REG_C_0,
 730         REG_C_1,
 731         REG_C_2,
 732         REG_C_3,
 733         REG_C_4,
 734         REG_C_5,
 735         REG_C_6,
 736         REG_C_7,
 737 };
 738
 739 /* Modification sub command. */
 740 struct mlx5_modification_cmd {
 741         union {
 742                 uint32_t data0;
 743                 struct {
 744                         unsigned int length:5;
 745                         unsigned int rsvd0:3;
 746                         unsigned int offset:5;
 747                         unsigned int rsvd1:3;
 748                         unsigned int field:12;
 749                         unsigned int action_type:4;
 750                 };
 751         };
 752         union {
 753                 uint32_t data1;
 754                 uint8_t data[4];
 755                 struct {
 756                         unsigned int rsvd2:8;
 757                         unsigned int dst_offset:5;
 758                         unsigned int rsvd3:3;
 759                         unsigned int dst_field:12;
 760                         unsigned int rsvd4:4;
 761                 };
 762         };
 763 };
 764
 765 typedef uint64_t u64;
 766 typedef uint32_t u32;
 767 typedef uint16_t u16;
 768 typedef uint8_t u8;
 769
 770 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
 771 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
 772 #define __mlx5_bit_off(typ, fld) ((unsigned int)(uintptr_t) \
 773                                   (&(__mlx5_nullp(typ)->fld)))
 774 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
 775                                     (__mlx5_bit_off(typ, fld) & 0x1f))
 776 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
 777 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
 778 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
 779                                   __mlx5_dw_bit_off(typ, fld))
 780 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
 781 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
 782 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
 783                                     (__mlx5_bit_off(typ, fld) & 0xf))
 784 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
 785 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \
 786                                   __mlx5_16_bit_off(typ, fld))
 787 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
 788 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
 789 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
 790 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
 791
 792 /* insert a value to a struct */
 793 #define MLX5_SET(typ, p, fld, v) \
 794         do { \
 795                 u32 _v = v; \
 796                 *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \
 797                 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
 798                                   __mlx5_dw_off(typ, fld))) & \
 799                                   (~__mlx5_dw_mask(typ, fld))) | \
 800                                  (((_v) & __mlx5_mask(typ, fld)) << \
 801                                    __mlx5_dw_bit_off(typ, fld))); \
 802         } while (0)
 803
 804 #define MLX5_SET64(typ, p, fld, v) \
 805         do { \
 806                 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \
 807                 *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \
 808                         rte_cpu_to_be_64(v); \
 809         } while (0)
 810
 811 #define MLX5_SET16(typ, p, fld, v) \
 812         do { \
 813                 u16 _v = v; \
 814                 *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \
 815                 rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
 816                                   __mlx5_16_off(typ, fld))) & \
 817                                   (~__mlx5_16_mask(typ, fld))) | \
 818                                  (((_v) & __mlx5_mask16(typ, fld)) << \
 819                                   __mlx5_16_bit_off(typ, fld))); \
 820         } while (0)
 821
 822 #define MLX5_GET_VOLATILE(typ, p, fld) \
 823         ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\
 824         __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
 825         __mlx5_mask(typ, fld))
 826 #define MLX5_GET(typ, p, fld) \
 827         ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\
 828         __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
 829         __mlx5_mask(typ, fld))
 830 #define MLX5_GET16(typ, p, fld) \
 831         ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
 832           __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
 833          __mlx5_mask16(typ, fld))
 834 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \
 835                                                    __mlx5_64_off(typ, fld)))
 836 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
 837 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
 838
 839 struct mlx5_ifc_fte_match_set_misc_bits {
 840         u8 gre_c_present[0x1];
 841         u8 reserved_at_1[0x1];
 842         u8 gre_k_present[0x1];
 843         u8 gre_s_present[0x1];
 844         u8 source_vhci_port[0x4];
 845         u8 source_sqn[0x18];
 846         u8 reserved_at_20[0x10];
 847         u8 source_port[0x10];
 848         u8 outer_second_prio[0x3];
 849         u8 outer_second_cfi[0x1];
 850         u8 outer_second_vid[0xc];
 851         u8 inner_second_prio[0x3];
 852         u8 inner_second_cfi[0x1];
 853         u8 inner_second_vid[0xc];
 854         u8 outer_second_cvlan_tag[0x1];
 855         u8 inner_second_cvlan_tag[0x1];
 856         u8 outer_second_svlan_tag[0x1];
 857         u8 inner_second_svlan_tag[0x1];
 858         u8 reserved_at_64[0xc];
 859         u8 gre_protocol[0x10];
 860         u8 gre_key_h[0x18];
 861         u8 gre_key_l[0x8];
 862         u8 vxlan_vni[0x18];
 863         u8 reserved_at_b8[0x8];
 864         u8 geneve_vni[0x18];
 865         u8 reserved_at_e4[0x6];
 866         u8 geneve_tlv_option_0_exist[0x1];
 867         u8 geneve_oam[0x1];
 868         u8 reserved_at_e0[0xc];
 869         u8 outer_ipv6_flow_label[0x14];
 870         u8 reserved_at_100[0xc];
 871         u8 inner_ipv6_flow_label[0x14];
 872         u8 reserved_at_120[0xa];
 873         u8 geneve_opt_len[0x6];
 874         u8 geneve_protocol_type[0x10];
 875         u8 reserved_at_140[0xc0];
 876 };
 877
 878 struct mlx5_ifc_ipv4_layout_bits {
 879         u8 reserved_at_0[0x60];
 880         u8 ipv4[0x20];
 881 };
 882
 883 struct mlx5_ifc_ipv6_layout_bits {
 884         u8 ipv6[16][0x8];
 885 };
 886
 887 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 888         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 889         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 890         u8 reserved_at_0[0x80];
 891 };
 892
 893 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 894         u8 smac_47_16[0x20];
 895         u8 smac_15_0[0x10];
 896         u8 ethertype[0x10];
 897         u8 dmac_47_16[0x20];
 898         u8 dmac_15_0[0x10];
 899         u8 first_prio[0x3];
 900         u8 first_cfi[0x1];
 901         u8 first_vid[0xc];
 902         u8 ip_protocol[0x8];
 903         u8 ip_dscp[0x6];
 904         u8 ip_ecn[0x2];
 905         u8 cvlan_tag[0x1];
 906         u8 svlan_tag[0x1];
 907         u8 frag[0x1];
 908         u8 ip_version[0x4];
 909         u8 tcp_flags[0x9];
 910         u8 tcp_sport[0x10];
 911         u8 tcp_dport[0x10];
 912         u8 reserved_at_c0[0x10];
 913         u8 ipv4_ihl[0x4];
 914         u8 l3_ok[0x1];
 915         u8 l4_ok[0x1];
 916         u8 ipv4_checksum_ok[0x1];
 917         u8 l4_checksum_ok[0x1];
 918         u8 ip_ttl_hoplimit[0x8];
 919         u8 udp_sport[0x10];
 920         u8 udp_dport[0x10];
 921         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 922         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 923 };
 924
 925 struct mlx5_ifc_fte_match_mpls_bits {
 926         u8 mpls_label[0x14];
 927         u8 mpls_exp[0x3];
 928         u8 mpls_s_bos[0x1];
 929         u8 mpls_ttl[0x8];
 930 };
 931
 932 struct mlx5_ifc_fte_match_set_misc2_bits {
 933         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 934         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 935         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 936         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 937         u8 metadata_reg_c_7[0x20];
 938         u8 metadata_reg_c_6[0x20];
 939         u8 metadata_reg_c_5[0x20];
 940         u8 metadata_reg_c_4[0x20];
 941         u8 metadata_reg_c_3[0x20];
 942         u8 metadata_reg_c_2[0x20];
 943         u8 metadata_reg_c_1[0x20];
 944         u8 metadata_reg_c_0[0x20];
 945         u8 metadata_reg_a[0x20];
 946         u8 metadata_reg_b[0x20];
 947         u8 reserved_at_1c0[0x40];
 948 };
 949
 950 struct mlx5_ifc_fte_match_set_misc3_bits {
 951         u8 inner_tcp_seq_num[0x20];
 952         u8 outer_tcp_seq_num[0x20];
 953         u8 inner_tcp_ack_num[0x20];
 954         u8 outer_tcp_ack_num[0x20];
 955         u8 reserved_at_auto1[0x8];
 956         u8 outer_vxlan_gpe_vni[0x18];
 957         u8 outer_vxlan_gpe_next_protocol[0x8];
 958         u8 outer_vxlan_gpe_flags[0x8];
 959         u8 reserved_at_a8[0x10];
 960         u8 icmp_header_data[0x20];
 961         u8 icmpv6_header_data[0x20];
 962         u8 icmp_type[0x8];
 963         u8 icmp_code[0x8];
 964         u8 icmpv6_type[0x8];
 965         u8 icmpv6_code[0x8];
 966         u8 geneve_tlv_option_0_data[0x20];
 967         u8 gtpu_teid[0x20];
 968         u8 gtpu_msg_type[0x08];
 969         u8 gtpu_msg_flags[0x08];
 970         u8 reserved_at_170[0x10];
 971         u8 gtpu_dw_2[0x20];
 972         u8 gtpu_first_ext_dw_0[0x20];
 973         u8 gtpu_dw_0[0x20];
 974         u8 reserved_at_240[0x20];
 975
 976 };
 977
 978 struct mlx5_ifc_fte_match_set_misc4_bits {
 979         u8 prog_sample_field_value_0[0x20];
 980         u8 prog_sample_field_id_0[0x20];
 981         u8 prog_sample_field_value_1[0x20];
 982         u8 prog_sample_field_id_1[0x20];
 983         u8 prog_sample_field_value_2[0x20];
 984         u8 prog_sample_field_id_2[0x20];
 985         u8 prog_sample_field_value_3[0x20];
 986         u8 prog_sample_field_id_3[0x20];
 987         u8 prog_sample_field_value_4[0x20];
 988         u8 prog_sample_field_id_4[0x20];
 989         u8 prog_sample_field_value_5[0x20];
 990         u8 prog_sample_field_id_5[0x20];
 991         u8 prog_sample_field_value_6[0x20];
 992         u8 prog_sample_field_id_6[0x20];
 993         u8 prog_sample_field_value_7[0x20];
 994         u8 prog_sample_field_id_7[0x20];
 995 };
 996
 997 struct mlx5_ifc_fte_match_set_misc5_bits {
 998         u8 macsec_tag_0[0x20];
 999         u8 macsec_tag_1[0x20];
1000         u8 macsec_tag_2[0x20];
1001         u8 macsec_tag_3[0x20];
1002         u8 tunnel_header_0[0x20];
1003         u8 tunnel_header_1[0x20];
1004         u8 tunnel_header_2[0x20];
1005         u8 tunnel_header_3[0x20];
1006         u8 reserved[0x100];
1007 };
1008
1009 /* Flow matcher. */
1010 struct mlx5_ifc_fte_match_param_bits {
1011         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1012         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1013         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1014         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1015         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1016         struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
1017         struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5;
1018 /*
1019  * Add reserved bit to match the struct size with the size defined in PRM.
1020  * This extension is not required in Linux.
1021  */
1022 #ifndef HAVE_INFINIBAND_VERBS_H
1023         u8 reserved_0[0x200];
1024 #endif
1025 };
1026
1027 struct mlx5_ifc_dest_format_struct_bits {
1028         u8 destination_type[0x8];
1029         u8 destination_id[0x18];
1030         u8 reserved_0[0x20];
1031 };
1032
1033 enum {
1034         MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
1035         MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
1036         MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
1037         MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
1038         MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT,
1039         MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT,
1040         MLX5_MATCH_CRITERIA_ENABLE_MISC5_BIT,
1041 };
1042
1043 enum {
1044         MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
1045         MLX5_CMD_OP_CREATE_MKEY = 0x200,
1046         MLX5_CMD_OP_CREATE_CQ = 0x400,
1047         MLX5_CMD_OP_CREATE_QP = 0x500,
1048         MLX5_CMD_OP_RST2INIT_QP = 0x502,
1049         MLX5_CMD_OP_INIT2RTR_QP = 0x503,
1050         MLX5_CMD_OP_RTR2RTS_QP = 0x504,
1051         MLX5_CMD_OP_RTS2RTS_QP = 0x505,
1052         MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
1053         MLX5_CMD_OP_QP_2ERR = 0x507,
1054         MLX5_CMD_OP_QP_2RST = 0x50A,
1055         MLX5_CMD_OP_QUERY_QP = 0x50B,
1056         MLX5_CMD_OP_SQD2RTS_QP = 0x50C,
1057         MLX5_CMD_OP_INIT2INIT_QP = 0x50E,
1058         MLX5_CMD_OP_SUSPEND_QP = 0x50F,
1059         MLX5_CMD_OP_RESUME_QP = 0x510,
1060         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
1061         MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
1062         MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
1063         MLX5_CMD_OP_ALLOC_PD = 0x800,
1064         MLX5_CMD_OP_DEALLOC_PD = 0x801,
1065         MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
1066         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
1067         MLX5_CMD_OP_QUERY_LAG = 0x842,
1068         MLX5_CMD_OP_CREATE_TIR = 0x900,
1069         MLX5_CMD_OP_MODIFY_TIR = 0x901,
1070         MLX5_CMD_OP_CREATE_SQ = 0X904,
1071         MLX5_CMD_OP_MODIFY_SQ = 0X905,
1072         MLX5_CMD_OP_CREATE_RQ = 0x908,
1073         MLX5_CMD_OP_MODIFY_RQ = 0x909,
1074         MLX5_CMD_OP_QUERY_RQ = 0x90b,
1075         MLX5_CMD_OP_CREATE_RMP = 0x90c,
1076         MLX5_CMD_OP_MODIFY_RMP = 0x90d,
1077         MLX5_CMD_OP_DESTROY_RMP = 0x90e,
1078         MLX5_CMD_OP_QUERY_RMP = 0x90f,
1079         MLX5_CMD_OP_CREATE_TIS = 0x912,
1080         MLX5_CMD_OP_QUERY_TIS = 0x915,
1081         MLX5_CMD_OP_CREATE_RQT = 0x916,
1082         MLX5_CMD_OP_MODIFY_RQT = 0x917,
1083         MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
1084         MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
1085         MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
1086         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
1087         MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
1088         MLX5_CMD_SET_REGEX_PARAMS = 0xb04,
1089         MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,
1090         MLX5_CMD_SET_REGEX_REGISTERS = 0xb06,
1091         MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
1092         MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c,
1093 };
1094
1095 enum {
1096         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
1097         MLX5_MKC_ACCESS_MODE_KLM   = 0x2,
1098         MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3,
1099 };
1100
1101 #define MLX5_ADAPTER_PAGE_SHIFT 12
1102 #define MLX5_LOG_RQ_STRIDE_SHIFT 4
1103 /**
1104  * The batch counter dcs id starts from 0x800000 and none batch counter
1105  * starts from 0. As currently, the counter is changed to be indexed by
1106  * pool index and the offset of the counter in the pool counters_raw array.
1107  * It means now the counter index is same for batch and none batch counter.
1108  * Add the 0x800000 batch counter offset to the batch counter index helps
1109  * indicate the counter index is from batch or none batch container pool.
1110  */
1111 #define MLX5_CNT_BATCH_OFFSET 0x800000
1112
1113 /* The counter batch query requires ID align with 4. */
1114 #define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4
1115
1116 /* Flow counters. */
1117 struct mlx5_ifc_alloc_flow_counter_out_bits {
1118         u8 status[0x8];
1119         u8 reserved_at_8[0x18];
1120         u8 syndrome[0x20];
1121         u8 flow_counter_id[0x20];
1122         u8 reserved_at_60[0x20];
1123 };
1124
1125 struct mlx5_ifc_alloc_flow_counter_in_bits {
1126         u8 opcode[0x10];
1127         u8 reserved_at_10[0x10];
1128         u8 reserved_at_20[0x10];
1129         u8 op_mod[0x10];
1130         u8 flow_counter_id[0x20];
1131         u8 reserved_at_40[0x18];
1132         u8 flow_counter_bulk[0x8];
1133 };
1134
1135 struct mlx5_ifc_dealloc_flow_counter_out_bits {
1136         u8 status[0x8];
1137         u8 reserved_at_8[0x18];
1138         u8 syndrome[0x20];
1139         u8 reserved_at_40[0x40];
1140 };
1141
1142 struct mlx5_ifc_dealloc_flow_counter_in_bits {
1143         u8 opcode[0x10];
1144         u8 reserved_at_10[0x10];
1145         u8 reserved_at_20[0x10];
1146         u8 op_mod[0x10];
1147         u8 flow_counter_id[0x20];
1148         u8 reserved_at_60[0x20];
1149 };
1150
1151 struct mlx5_ifc_traffic_counter_bits {
1152         u8 packets[0x40];
1153         u8 octets[0x40];
1154 };
1155
1156 struct mlx5_ifc_query_flow_counter_out_bits {
1157         u8 status[0x8];
1158         u8 reserved_at_8[0x18];
1159         u8 syndrome[0x20];
1160         u8 reserved_at_40[0x40];
1161         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
1162 };
1163
1164 struct mlx5_ifc_query_flow_counter_in_bits {
1165         u8 opcode[0x10];
1166         u8 reserved_at_10[0x10];
1167         u8 reserved_at_20[0x10];
1168         u8 op_mod[0x10];
1169         u8 reserved_at_40[0x20];
1170         u8 mkey[0x20];
1171         u8 address[0x40];
1172         u8 clear[0x1];
1173         u8 dump_to_memory[0x1];
1174         u8 num_of_counters[0x1e];
1175         u8 flow_counter_id[0x20];
1176 };
1177
1178 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u
1179 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u
1180
1181 struct mlx5_ifc_klm_bits {
1182         u8 byte_count[0x20];
1183         u8 mkey[0x20];
1184         u8 address[0x40];
1185 };
1186
1187 struct mlx5_ifc_mkc_bits {
1188         u8 reserved_at_0[0x1];
1189         u8 free[0x1];
1190         u8 reserved_at_2[0x1];
1191         u8 access_mode_4_2[0x3];
1192         u8 reserved_at_6[0x7];
1193         u8 relaxed_ordering_write[0x1];
1194         u8 reserved_at_e[0x1];
1195         u8 small_fence_on_rdma_read_response[0x1];
1196         u8 umr_en[0x1];
1197         u8 a[0x1];
1198         u8 rw[0x1];
1199         u8 rr[0x1];
1200         u8 lw[0x1];
1201         u8 lr[0x1];
1202         u8 access_mode_1_0[0x2];
1203         u8 reserved_at_18[0x8];
1204         u8 qpn[0x18];
1205         u8 mkey_7_0[0x8];
1206         u8 reserved_at_40[0x20];
1207         u8 length64[0x1];
1208         u8 bsf_en[0x1];
1209         u8 sync_umr[0x1];
1210         u8 reserved_at_63[0x2];
1211         u8 expected_sigerr_count[0x1];
1212         u8 reserved_at_66[0x1];
1213         u8 en_rinval[0x1];
1214         u8 pd[0x18];
1215         u8 start_addr[0x40];
1216         u8 len[0x40];
1217         u8 bsf_octword_size[0x20];
1218         u8 reserved_at_120[0x80];
1219         u8 translations_octword_size[0x20];
1220         u8 reserved_at_1c0[0x19];
1221         u8 relaxed_ordering_read[0x1];
1222         u8 reserved_at_1da[0x1];
1223         u8 log_page_size[0x5];
1224         u8 reserved_at_1e0[0x3];
1225         u8 crypto_en[0x2];
1226         u8 reserved_at_1e5[0x1b];
1227 };
1228
1229 /* Range of values for MKEY context crypto_en field. */
1230 enum {
1231         MLX5_MKEY_CRYPTO_DISABLED = 0x0,
1232         MLX5_MKEY_CRYPTO_ENABLED = 0x1,
1233 };
1234
1235 struct mlx5_ifc_create_mkey_out_bits {
1236         u8 status[0x8];
1237         u8 reserved_at_8[0x18];
1238         u8 syndrome[0x20];
1239         u8 reserved_at_40[0x8];
1240         u8 mkey_index[0x18];
1241         u8 reserved_at_60[0x20];
1242 };
1243
1244 struct mlx5_ifc_create_mkey_in_bits {
1245         u8 opcode[0x10];
1246         u8 reserved_at_10[0x10];
1247         u8 reserved_at_20[0x10];
1248         u8 op_mod[0x10];
1249         u8 reserved_at_40[0x20];
1250         u8 pg_access[0x1];
1251         u8 reserved_at_61[0x1f];
1252         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
1253         u8 reserved_at_280[0x80];
1254         u8 translations_octword_actual_size[0x20];
1255         u8 mkey_umem_id[0x20];
1256         u8 mkey_umem_offset[0x40];
1257         u8 reserved_at_380[0x500];
1258         u8 klm_pas_mtt[][0x20];
1259 };
1260
1261 enum {
1262         MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
1263         MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
1264         MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
1265         MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1,
1266         MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,
1267         MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
1268         MLX5_GET_HCA_CAP_OP_MOD_PARSE_GRAPH_NODE_CAP = 0x1C << 1,
1269         MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE_2 = 0x20 << 1,
1270 };
1271
1272 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \
1273                         (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ)
1274 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \
1275                         (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS)
1276 #define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \
1277                         (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH)
1278 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \
1279                         (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO)
1280 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO \
1281                         (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO)
1282 #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \
1283                         (1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT)
1284 #define MLX5_GENERAL_OBJ_TYPES_CAP_CONN_TRACK_OFFLOAD \
1285                         (1ULL << MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD)
1286 #define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \
1287                         (1ULL << MLX5_GENERAL_OBJ_TYPE_DEK)
1288 #define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \
1289                         (1ULL << MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK)
1290 #define MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL \
1291                         (1ULL << MLX5_GENERAL_OBJ_TYPE_CREDENTIAL)
1292 #define MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN \
1293                         (1ULL << MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN)
1294
1295 enum {
1296         MLX5_HCA_CAP_OPMOD_GET_MAX   = 0,
1297         MLX5_HCA_CAP_OPMOD_GET_CUR   = 1,
1298 };
1299
1300 enum {
1301         MLX5_CAP_INLINE_MODE_L2,
1302         MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
1303         MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
1304 };
1305
1306 enum {
1307         MLX5_INLINE_MODE_NONE,
1308         MLX5_INLINE_MODE_L2,
1309         MLX5_INLINE_MODE_IP,
1310         MLX5_INLINE_MODE_TCP_UDP,
1311         MLX5_INLINE_MODE_RESERVED4,
1312         MLX5_INLINE_MODE_INNER_L2,
1313         MLX5_INLINE_MODE_INNER_IP,
1314         MLX5_INLINE_MODE_INNER_TCP_UDP,
1315 };
1316
1317 /* The supported timestamp formats reported in HCA attributes. */
1318 enum {
1319         MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR = 0x0,
1320         MLX5_HCA_CAP_TIMESTAMP_FORMAT_RT = 0x1,
1321         MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR_RT = 0x2,
1322 };
1323
1324 /* The timestamp format attributes to configure queues (RQ/SQ/QP). */
1325 enum {
1326         MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
1327         MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
1328         MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
1329 };
1330
1331 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
1332 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
1333 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
1334 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
1335 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
1336 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
1337 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
1338 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
1339 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
1340 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
1341 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
1342
1343 /* The device steering logic format. */
1344 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 0x0
1345 #define MLX5_STEERING_LOGIC_FORMAT_CONNECTX_6DX 0x1
1346
1347 struct mlx5_ifc_cmd_hca_cap_bits {
1348         u8 reserved_at_0[0x20];
1349         u8 hca_cap_2[0x1];
1350         u8 reserved_at_21[0xf];
1351         u8 vhca_id[0x10];
1352         u8 reserved_at_40[0x20];
1353         u8 reserved_at_60[0x3];
1354         u8 log_regexp_scatter_gather_size[0x5];
1355         u8 reserved_at_68[0x3];
1356         u8 log_dma_mmo_size[0x5];
1357         u8 reserved_at_70[0x3];
1358         u8 log_compress_mmo_size[0x5];
1359         u8 reserved_at_78[0x3];
1360         u8 log_decompress_mmo_size[0x5];
1361         u8 log_max_srq_sz[0x8];
1362         u8 log_max_qp_sz[0x8];
1363         u8 reserved_at_90[0x9];
1364         u8 wqe_index_ignore_cap[0x1];
1365         u8 dynamic_qp_allocation[0x1];
1366         u8 log_max_qp[0x5];
1367         u8 reserved_at_a0[0x4];
1368         u8 regexp_num_of_engines[0x4];
1369         u8 reserved_at_a8[0x1];
1370         u8 reg_c_preserve[0x1];
1371         u8 reserved_at_aa[0x1];
1372         u8 log_max_srq[0x5];
1373         u8 reserved_at_b0[0xb];
1374         u8 scatter_fcs_w_decap_disable[0x1];
1375         u8 reserved_at_bc[0x4];
1376         u8 reserved_at_c0[0x8];
1377         u8 log_max_cq_sz[0x8];
1378         u8 reserved_at_d0[0x2];
1379         u8 access_register_user[0x1];
1380         u8 reserved_at_d3[0x8];
1381         u8 log_max_cq[0x5];
1382         u8 log_max_eq_sz[0x8];
1383         u8 relaxed_ordering_write[0x1];
1384         u8 relaxed_ordering_read[0x1];
1385         u8 log_max_mkey[0x6];
1386         u8 reserved_at_f0[0x8];
1387         u8 dump_fill_mkey[0x1];
1388         u8 reserved_at_f9[0x3];
1389         u8 log_max_eq[0x4];
1390         u8 max_indirection[0x8];
1391         u8 fixed_buffer_size[0x1];
1392         u8 log_max_mrw_sz[0x7];
1393         u8 force_teardown[0x1];
1394         u8 reserved_at_111[0x1];
1395         u8 log_max_bsf_list_size[0x6];
1396         u8 umr_extended_translation_offset[0x1];
1397         u8 null_mkey[0x1];
1398         u8 log_max_klm_list_size[0x6];
1399         u8 non_wire_sq[0x1];
1400         u8 reserved_at_121[0x9];
1401         u8 log_max_ra_req_dc[0x6];
1402         u8 reserved_at_130[0x3];
1403         u8 log_max_static_sq_wq[0x5];
1404         u8 reserved_at_138[0x2];
1405         u8 log_max_ra_res_dc[0x6];
1406         u8 reserved_at_140[0xa];
1407         u8 log_max_ra_req_qp[0x6];
1408         u8 rtr2rts_qp_counters_set_id[0x1];
1409         u8 rts2rts_udp_sport[0x1];
1410         u8 rts2rts_lag_tx_port_affinity[0x1];
1411         u8 dma_mmo_sq[0x1];
1412         u8 compress_min_block_size[0x4];
1413         u8 compress_mmo_sq[0x1];
1414         u8 decompress_mmo_sq[0x1];
1415         u8 log_max_ra_res_qp[0x6];
1416         u8 end_pad[0x1];
1417         u8 cc_query_allowed[0x1];
1418         u8 cc_modify_allowed[0x1];
1419         u8 start_pad[0x1];
1420         u8 cache_line_128byte[0x1];
1421         u8 reserved_at_165[0xa];
1422         u8 qcam_reg[0x1];
1423         u8 gid_table_size[0x10];
1424         u8 out_of_seq_cnt[0x1];
1425         u8 vport_counters[0x1];
1426         u8 retransmission_q_counters[0x1];
1427         u8 debug[0x1];
1428         u8 modify_rq_counter_set_id[0x1];
1429         u8 rq_delay_drop[0x1];
1430         u8 max_qp_cnt[0xa];
1431         u8 pkey_table_size[0x10];
1432         u8 vport_group_manager[0x1];
1433         u8 vhca_group_manager[0x1];
1434         u8 ib_virt[0x1];
1435         u8 eth_virt[0x1];
1436         u8 vnic_env_queue_counters[0x1];
1437         u8 ets[0x1];
1438         u8 nic_flow_table[0x1];
1439         u8 eswitch_manager[0x1];
1440         u8 device_memory[0x1];
1441         u8 mcam_reg[0x1];
1442         u8 pcam_reg[0x1];
1443         u8 local_ca_ack_delay[0x5];
1444         u8 port_module_event[0x1];
1445         u8 enhanced_error_q_counters[0x1];
1446         u8 ports_check[0x1];
1447         u8 reserved_at_1b3[0x1];
1448         u8 disable_link_up[0x1];
1449         u8 beacon_led[0x1];
1450         u8 port_type[0x2];
1451         u8 num_ports[0x8];
1452         u8 reserved_at_1c0[0x1];
1453         u8 pps[0x1];
1454         u8 pps_modify[0x1];
1455         u8 log_max_msg[0x5];
1456         u8 reserved_at_1c8[0x4];
1457         u8 max_tc[0x4];
1458         u8 temp_warn_event[0x1];
1459         u8 dcbx[0x1];
1460         u8 general_notification_event[0x1];
1461         u8 reserved_at_1d3[0x2];
1462         u8 fpga[0x1];
1463         u8 rol_s[0x1];
1464         u8 rol_g[0x1];
1465         u8 reserved_at_1d8[0x1];
1466         u8 wol_s[0x1];
1467         u8 wol_g[0x1];
1468         u8 wol_a[0x1];
1469         u8 wol_b[0x1];
1470         u8 wol_m[0x1];
1471         u8 wol_u[0x1];
1472         u8 wol_p[0x1];
1473         u8 stat_rate_support[0x10];
1474         u8 reserved_at_1f0[0xc];
1475         u8 cqe_version[0x4];
1476         u8 compact_address_vector[0x1];
1477         u8 striding_rq[0x1];
1478         u8 reserved_at_202[0x1];
1479         u8 ipoib_enhanced_offloads[0x1];
1480         u8 ipoib_basic_offloads[0x1];
1481         u8 reserved_at_205[0x1];
1482         u8 repeated_block_disabled[0x1];
1483         u8 umr_modify_entity_size_disabled[0x1];
1484         u8 umr_modify_atomic_disabled[0x1];
1485         u8 umr_indirect_mkey_disabled[0x1];
1486         u8 umr_fence[0x2];
1487         u8 reserved_at_20c[0x3];
1488         u8 drain_sigerr[0x1];
1489         u8 cmdif_checksum[0x2];
1490         u8 sigerr_cqe[0x1];
1491         u8 reserved_at_213[0x1];
1492         u8 wq_signature[0x1];
1493         u8 sctr_data_cqe[0x1];
1494         u8 reserved_at_216[0x1];
1495         u8 sho[0x1];
1496         u8 tph[0x1];
1497         u8 rf[0x1];
1498         u8 dct[0x1];
1499         u8 qos[0x1];
1500         u8 eth_net_offloads[0x1];
1501         u8 roce[0x1];
1502         u8 atomic[0x1];
1503         u8 reserved_at_21f[0x1];
1504         u8 cq_oi[0x1];
1505         u8 cq_resize[0x1];
1506         u8 cq_moderation[0x1];
1507         u8 reserved_at_223[0x3];
1508         u8 cq_eq_remap[0x1];
1509         u8 pg[0x1];
1510         u8 block_lb_mc[0x1];
1511         u8 reserved_at_229[0x1];
1512         u8 scqe_break_moderation[0x1];
1513         u8 cq_period_start_from_cqe[0x1];
1514         u8 cd[0x1];
1515         u8 reserved_at_22d[0x1];
1516         u8 apm[0x1];
1517         u8 vector_calc[0x1];
1518         u8 umr_ptr_rlky[0x1];
1519         u8 imaicl[0x1];
1520         u8 reserved_at_232[0x4];
1521         u8 qkv[0x1];
1522         u8 pkv[0x1];
1523         u8 set_deth_sqpn[0x1];
1524         u8 reserved_at_239[0x3];
1525         u8 xrc[0x1];
1526         u8 ud[0x1];
1527         u8 uc[0x1];
1528         u8 rc[0x1];
1529         u8 uar_4k[0x1];
1530         u8 reserved_at_241[0x8];
1531         u8 regexp_params[0x1];
1532         u8 uar_sz[0x6];
1533         u8 port_selection_cap[0x1];
1534         u8 reserved_at_251[0x7];
1535         u8 log_pg_sz[0x8];
1536         u8 bf[0x1];
1537         u8 driver_version[0x1];
1538         u8 pad_tx_eth_packet[0x1];
1539         u8 reserved_at_263[0x8];
1540         u8 log_bf_reg_size[0x5];
1541         u8 reserved_at_270[0xb];
1542         u8 lag_master[0x1];
1543         u8 num_lag_ports[0x4];
1544         u8 reserved_at_280[0x10];
1545         u8 max_wqe_sz_sq[0x10];
1546         u8 reserved_at_2a0[0xc];
1547         u8 regexp_mmo_sq[0x1];
1548         u8 regexp_version[0x3];
1549         u8 max_wqe_sz_rq[0x10];
1550         u8 max_flow_counter_31_16[0x10];
1551         u8 max_wqe_sz_sq_dc[0x10];
1552         u8 reserved_at_2e0[0x7];
1553         u8 max_qp_mcg[0x19];
1554         u8 reserved_at_300[0x10];
1555         u8 flow_counter_bulk_alloc[0x08];
1556         u8 log_max_mcg[0x8];
1557         u8 reserved_at_320[0x3];
1558         u8 log_max_transport_domain[0x5];
1559         u8 reserved_at_328[0x3];
1560         u8 log_max_pd[0x5];
1561         u8 reserved_at_330[0xb];
1562         u8 log_max_xrcd[0x5];
1563         u8 nic_receive_steering_discard[0x1];
1564         u8 receive_discard_vport_down[0x1];
1565         u8 transmit_discard_vport_down[0x1];
1566         u8 reserved_at_343[0x5];
1567         u8 log_max_flow_counter_bulk[0x8];
1568         u8 max_flow_counter_15_0[0x10];
1569         u8 modify_tis[0x1];
1570         u8 flow_counters_dump[0x1];
1571         u8 reserved_at_360[0x1];
1572         u8 log_max_rq[0x5];
1573         u8 reserved_at_368[0x3];
1574         u8 log_max_sq[0x5];
1575         u8 reserved_at_370[0x3];
1576         u8 log_max_tir[0x5];
1577         u8 reserved_at_378[0x3];
1578         u8 log_max_tis[0x5];
1579         u8 basic_cyclic_rcv_wqe[0x1];
1580         u8 reserved_at_381[0x1];
1581         u8 mem_rq_rmp[0x1];
1582         u8 log_max_rmp[0x5];
1583         u8 reserved_at_388[0x3];
1584         u8 log_max_rqt[0x5];
1585         u8 reserved_at_390[0x3];
1586         u8 log_max_rqt_size[0x5];
1587         u8 reserved_at_398[0x3];
1588         u8 log_max_tis_per_sq[0x5];
1589         u8 ext_stride_num_range[0x1];
1590         u8 reserved_at_3a1[0x2];
1591         u8 log_max_stride_sz_rq[0x5];
1592         u8 reserved_at_3a8[0x3];
1593         u8 log_min_stride_sz_rq[0x5];
1594         u8 reserved_at_3b0[0x3];
1595         u8 log_max_stride_sz_sq[0x5];
1596         u8 reserved_at_3b8[0x3];
1597         u8 log_min_stride_sz_sq[0x5];
1598         u8 hairpin[0x1];
1599         u8 reserved_at_3c1[0x2];
1600         u8 log_max_hairpin_queues[0x5];
1601         u8 reserved_at_3c8[0x3];
1602         u8 log_max_hairpin_wq_data_sz[0x5];
1603         u8 reserved_at_3d0[0x3];
1604         u8 log_max_hairpin_num_packets[0x5];
1605         u8 reserved_at_3d8[0x3];
1606         u8 log_max_wq_sz[0x5];
1607         u8 nic_vport_change_event[0x1];
1608         u8 disable_local_lb_uc[0x1];
1609         u8 disable_local_lb_mc[0x1];
1610         u8 log_min_hairpin_wq_data_sz[0x5];
1611         u8 reserved_at_3e8[0x3];
1612         u8 log_max_vlan_list[0x5];
1613         u8 reserved_at_3f0[0x3];
1614         u8 log_max_current_mc_list[0x5];
1615         u8 reserved_at_3f8[0x3];
1616         u8 log_max_current_uc_list[0x5];
1617         u8 general_obj_types[0x40];
1618         u8 sq_ts_format[0x2];
1619         u8 rq_ts_format[0x2];
1620         u8 steering_format_version[0x4];
1621         u8 reserved_at_448[0x18];
1622         u8 reserved_at_460[0x8];
1623         u8 aes_xts[0x1];
1624         u8 crypto[0x1];
1625         u8 reserved_at_46a[0x6];
1626         u8 max_num_eqs[0x10];
1627         u8 reserved_at_480[0x3];
1628         u8 log_max_l2_table[0x5];
1629         u8 reserved_at_488[0x8];
1630         u8 log_uar_page_sz[0x10];
1631         u8 reserved_at_4a0[0x20];
1632         u8 device_frequency_mhz[0x20];
1633         u8 device_frequency_khz[0x20];
1634         u8 reserved_at_500[0x20];
1635         u8 num_of_uars_per_page[0x20];
1636         u8 flex_parser_protocols[0x20];
1637         u8 max_geneve_tlv_options[0x8];
1638         u8 reserved_at_568[0x3];
1639         u8 max_geneve_tlv_option_data_len[0x5];
1640         u8 reserved_at_570[0x49];
1641         u8 mini_cqe_resp_l3_l4_tag[0x1];
1642         u8 mini_cqe_resp_flow_tag[0x1];
1643         u8 enhanced_cqe_compression[0x1];
1644         u8 mini_cqe_resp_stride_index[0x1];
1645         u8 cqe_128_always[0x1];
1646         u8 cqe_compression_128[0x1];
1647         u8 cqe_compression[0x1];
1648         u8 cqe_compression_timeout[0x10];
1649         u8 cqe_compression_max_num[0x10];
1650         u8 reserved_at_5e0[0x10];
1651         u8 tag_matching[0x1];
1652         u8 rndv_offload_rc[0x1];
1653         u8 rndv_offload_dc[0x1];
1654         u8 log_tag_matching_list_sz[0x5];
1655         u8 reserved_at_5f8[0x3];
1656         u8 log_max_xrq[0x5];
1657         u8 affiliate_nic_vport_criteria[0x8];
1658         u8 native_port_num[0x8];
1659         u8 num_vhca_ports[0x8];
1660         u8 reserved_at_618[0x6];
1661         u8 sw_owner_id[0x1];
1662         u8 reserved_at_61f[0x129];
1663         u8 dma_mmo_qp[0x1];
1664         u8 regexp_mmo_qp[0x1];
1665         u8 compress_mmo_qp[0x1];
1666         u8 decompress_mmo_qp[0x1];
1667         u8 reserved_at_624[0xd4];
1668 };
1669
1670 struct mlx5_ifc_qos_cap_bits {
1671         u8 packet_pacing[0x1];
1672         u8 esw_scheduling[0x1];
1673         u8 esw_bw_share[0x1];
1674         u8 esw_rate_limit[0x1];
1675         u8 reserved_at_4[0x1];
1676         u8 packet_pacing_burst_bound[0x1];
1677         u8 packet_pacing_typical_size[0x1];
1678         u8 flow_meter_old[0x1];
1679         u8 reserved_at_8[0x8];
1680         u8 log_max_flow_meter[0x8];
1681         u8 flow_meter_reg_id[0x8];
1682         u8 wqe_rate_pp[0x1];
1683         u8 reserved_at_25[0x7];
1684         u8 flow_meter[0x1];
1685         u8 reserved_at_2e[0x17];
1686         u8 packet_pacing_max_rate[0x20];
1687         u8 packet_pacing_min_rate[0x20];
1688         u8 reserved_at_80[0x10];
1689         u8 packet_pacing_rate_table_size[0x10];
1690         u8 esw_element_type[0x10];
1691         u8 esw_tsar_type[0x10];
1692         u8 reserved_at_c0[0x10];
1693         u8 max_qos_para_vport[0x10];
1694         u8 max_tsar_bw_share[0x20];
1695         u8 nic_element_type[0x10];
1696         u8 nic_tsar_type[0x10];
1697         u8 reserved_at_120[0x3];
1698         u8 log_meter_aso_granularity[0x5];
1699         u8 reserved_at_128[0x3];
1700         u8 log_meter_aso_max_alloc[0x5];
1701         u8 reserved_at_130[0x3];
1702         u8 log_max_num_meter_aso[0x5];
1703         u8 reserved_at_138[0x6b0];
1704 };
1705
1706 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1707         u8 csum_cap[0x1];
1708         u8 vlan_cap[0x1];
1709         u8 lro_cap[0x1];
1710         u8 lro_psh_flag[0x1];
1711         u8 lro_time_stamp[0x1];
1712         u8 lro_max_msg_sz_mode[0x2];
1713         u8 wqe_vlan_insert[0x1];
1714         u8 self_lb_en_modifiable[0x1];
1715         u8 self_lb_mc[0x1];
1716         u8 self_lb_uc[0x1];
1717         u8 max_lso_cap[0x5];
1718         u8 multi_pkt_send_wqe[0x2];
1719         u8 wqe_inline_mode[0x2];
1720         u8 rss_ind_tbl_cap[0x4];
1721         u8 reg_umr_sq[0x1];
1722         u8 scatter_fcs[0x1];
1723         u8 enhanced_multi_pkt_send_wqe[0x1];
1724         u8 tunnel_lso_const_out_ip_id[0x1];
1725         u8 tunnel_lro_gre[0x1];
1726         u8 tunnel_lro_vxlan[0x1];
1727         u8 tunnel_stateless_gre[0x1];
1728         u8 tunnel_stateless_vxlan[0x1];
1729         u8 swp[0x1];
1730         u8 swp_csum[0x1];
1731         u8 swp_lso[0x1];
1732         u8 reserved_at_23[0x8];
1733         u8 tunnel_stateless_gtp[0x1];
1734         u8 reserved_at_25[0x4];
1735         u8 max_vxlan_udp_ports[0x8];
1736         u8 reserved_at_38[0x6];
1737         u8 max_geneve_opt_len[0x1];
1738         u8 tunnel_stateless_geneve_rx[0x1];
1739         u8 reserved_at_40[0x10];
1740         u8 lro_min_mss_size[0x10];
1741         u8 reserved_at_60[0x120];
1742         u8 lro_timer_supported_periods[4][0x20];
1743         u8 reserved_at_200[0x600];
1744 };
1745
1746 enum {
1747         MLX5_VIRTQ_TYPE_SPLIT = 0,
1748         MLX5_VIRTQ_TYPE_PACKED = 1,
1749 };
1750
1751 enum {
1752         MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0,
1753         MLX5_VIRTQ_EVENT_MODE_QP = 1,
1754         MLX5_VIRTQ_EVENT_MODE_MSIX = 2,
1755 };
1756
1757 struct mlx5_ifc_virtio_emulation_cap_bits {
1758         u8 desc_tunnel_offload_type[0x1];
1759         u8 eth_frame_offload_type[0x1];
1760         u8 virtio_version_1_0[0x1];
1761         u8 tso_ipv4[0x1];
1762         u8 tso_ipv6[0x1];
1763         u8 tx_csum[0x1];
1764         u8 rx_csum[0x1];
1765         u8 reserved_at_7[0x1][0x9];
1766         u8 event_mode[0x8];
1767         u8 virtio_queue_type[0x8];
1768         u8 reserved_at_20[0x13];
1769         u8 log_doorbell_stride[0x5];
1770         u8 reserved_at_3b[0x3];
1771         u8 log_doorbell_bar_size[0x5];
1772         u8 doorbell_bar_offset[0x40];
1773         u8 reserved_at_80[0x8];
1774         u8 max_num_virtio_queues[0x18];
1775         u8 reserved_at_a0[0x60];
1776         u8 umem_1_buffer_param_a[0x20];
1777         u8 umem_1_buffer_param_b[0x20];
1778         u8 umem_2_buffer_param_a[0x20];
1779         u8 umem_2_buffer_param_b[0x20];
1780         u8 umem_3_buffer_param_a[0x20];
1781         u8 umem_3_buffer_param_b[0x20];
1782         u8 reserved_at_1c0[0x620];
1783 };
1784
1785 /**
1786  * PARSE_GRAPH_NODE Capabilities Field Descriptions
1787  */
1788 struct mlx5_ifc_parse_graph_node_cap_bits {
1789         u8 node_in[0x20];
1790         u8 node_out[0x20];
1791         u8 header_length_mode[0x10];
1792         u8 sample_offset_mode[0x10];
1793         u8 max_num_arc_in[0x08];
1794         u8 max_num_arc_out[0x08];
1795         u8 max_num_sample[0x08];
1796         u8 reserved_at_78[0x07];
1797         u8 sample_id_in_out[0x1];
1798         u8 max_base_header_length[0x10];
1799         u8 reserved_at_90[0x08];
1800         u8 max_sample_base_offset[0x08];
1801         u8 max_next_header_offset[0x10];
1802         u8 reserved_at_b0[0x08];
1803         u8 header_length_mask_width[0x08];
1804 };
1805
1806 struct mlx5_ifc_flow_table_prop_layout_bits {
1807         u8 ft_support[0x1];
1808         u8 flow_tag[0x1];
1809         u8 flow_counter[0x1];
1810         u8 flow_modify_en[0x1];
1811         u8 modify_root[0x1];
1812         u8 identified_miss_table[0x1];
1813         u8 flow_table_modify[0x1];
1814         u8 reformat[0x1];
1815         u8 decap[0x1];
1816         u8 reset_root_to_default[0x1];
1817         u8 pop_vlan[0x1];
1818         u8 push_vlan[0x1];
1819         u8 fpga_vendor_acceleration[0x1];
1820         u8 pop_vlan_2[0x1];
1821         u8 push_vlan_2[0x1];
1822         u8 reformat_and_vlan_action[0x1];
1823         u8 modify_and_vlan_action[0x1];
1824         u8 sw_owner[0x1];
1825         u8 reformat_l3_tunnel_to_l2[0x1];
1826         u8 reformat_l2_to_l3_tunnel[0x1];
1827         u8 reformat_and_modify_action[0x1];
1828         u8 reserved_at_15[0x9];
1829         u8 sw_owner_v2[0x1];
1830         u8 reserved_at_1f[0x1];
1831         u8 reserved_at_20[0x2];
1832         u8 log_max_ft_size[0x6];
1833         u8 log_max_modify_header_context[0x8];
1834         u8 max_modify_header_actions[0x8];
1835         u8 max_ft_level[0x8];
1836         u8 reserved_at_40[0x8];
1837         u8 log_max_ft_sampler_num[8];
1838         u8 metadata_reg_b_width[0x8];
1839         u8 metadata_reg_a_width[0x8];
1840         u8 reserved_at_60[0x18];
1841         u8 log_max_ft_num[0x8];
1842         u8 reserved_at_80[0x10];
1843         u8 log_max_flow_counter[0x8];
1844         u8 log_max_destination[0x8];
1845         u8 reserved_at_a0[0x18];
1846         u8 log_max_flow[0x8];
1847         u8 reserved_at_c0[0x140];
1848 };
1849
1850 struct mlx5_ifc_roce_caps_bits {
1851         u8 reserved_0[0x1e];
1852         u8 qp_ts_format[0x2];
1853         u8 reserved_at_20[0x7e0];
1854 };
1855
1856 /*
1857  * Table 1872 - Flow Table Fields Supported 2 Format
1858  */
1859 struct mlx5_ifc_ft_fields_support_2_bits {
1860         u8 reserved_at_0[0xf];
1861         u8 tunnel_header_2_3[0x1];
1862         u8 tunnel_header_0_1[0x1];
1863         u8 macsec_syndrome[0x1];
1864         u8 macsec_tag[0x1];
1865         u8 outer_lrh_sl[0x1];
1866         u8 inner_ipv4_ihl[0x1];
1867         u8 outer_ipv4_ihl[0x1];
1868         u8 psp_syndrome[0x1];
1869         u8 inner_l3_ok[0x1];
1870         u8 inner_l4_ok[0x1];
1871         u8 outer_l3_ok[0x1];
1872         u8 outer_l4_ok[0x1];
1873         u8 psp_header[0x1];
1874         u8 inner_ipv4_checksum_ok[0x1];
1875         u8 inner_l4_checksum_ok[0x1];
1876         u8 outer_ipv4_checksum_ok[0x1];
1877         u8 outer_l4_checksum_ok[0x1];
1878         u8 reserved_at_20[0x60];
1879 };
1880
1881 struct mlx5_ifc_flow_table_nic_cap_bits {
1882         u8 reserved_at_0[0x200];
1883         struct mlx5_ifc_flow_table_prop_layout_bits
1884                 flow_table_properties_nic_receive;
1885         struct mlx5_ifc_flow_table_prop_layout_bits
1886                 flow_table_properties_nic_receive_rdma;
1887         struct mlx5_ifc_flow_table_prop_layout_bits
1888                 flow_table_properties_nic_receive_sniffer;
1889         struct mlx5_ifc_flow_table_prop_layout_bits
1890                 flow_table_properties_nic_transmit;
1891         struct mlx5_ifc_flow_table_prop_layout_bits
1892                 flow_table_properties_nic_transmit_rdma;
1893         struct mlx5_ifc_flow_table_prop_layout_bits
1894                 flow_table_properties_nic_transmit_sniffer;
1895         u8 reserved_at_e00[0x600];
1896         struct mlx5_ifc_ft_fields_support_2_bits
1897                 ft_field_support_2_nic_receive;
1898 };
1899
1900 /*
1901  *  HCA Capabilities 2
1902  */
1903 struct mlx5_ifc_cmd_hca_cap_2_bits {
1904         u8 reserved_at_0[0x80]; /* End of DW4. */
1905         u8 reserved_at_80[0x3];
1906         u8 max_num_prog_sample_field[0x5];
1907         u8 reserved_at_88[0x3];
1908         u8 log_max_num_reserved_qpn[0x5];
1909         u8 reserved_at_90[0x3];
1910         u8 log_reserved_qpn_granularity[0x5];
1911         u8 reserved_at_98[0x3];
1912         u8 log_reserved_qpn_max_alloc[0x5]; /* End of DW5. */
1913         u8 max_reformat_insert_size[0x8];
1914         u8 max_reformat_insert_offset[0x8];
1915         u8 max_reformat_remove_size[0x8];
1916         u8 max_reformat_remove_offset[0x8]; /* End of DW6. */
1917         u8 reserved_at_c0[0x3];
1918         u8 log_min_stride_wqe_sz[0x5];
1919         u8 reserved_at_c8[0x3];
1920         u8 log_conn_track_granularity[0x5];
1921         u8 reserved_at_d0[0x3];
1922         u8 log_conn_track_max_alloc[0x5];
1923         u8 reserved_at_d8[0x3];
1924         u8 log_max_conn_track_offload[0x5];
1925         u8 reserved_at_e0[0x20]; /* End of DW7. */
1926         u8 reserved_at_100[0x700];
1927 };
1928
1929 union mlx5_ifc_hca_cap_union_bits {
1930         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1931         struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2;
1932         struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1933                per_protocol_networking_offload_caps;
1934         struct mlx5_ifc_qos_cap_bits qos_cap;
1935         struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
1936         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1937         struct mlx5_ifc_roce_caps_bits roce_caps;
1938         u8 reserved_at_0[0x8000];
1939 };
1940
1941 struct mlx5_ifc_set_action_in_bits {
1942         u8 action_type[0x4];
1943         u8 field[0xc];
1944         u8 reserved_at_10[0x3];
1945         u8 offset[0x5];
1946         u8 reserved_at_18[0x3];
1947         u8 length[0x5];
1948         u8 data[0x20];
1949 };
1950
1951 struct mlx5_ifc_query_hca_cap_out_bits {
1952         u8 status[0x8];
1953         u8 reserved_at_8[0x18];
1954         u8 syndrome[0x20];
1955         u8 reserved_at_40[0x40];
1956         union mlx5_ifc_hca_cap_union_bits capability;
1957 };
1958
1959 struct mlx5_ifc_query_hca_cap_in_bits {
1960         u8 opcode[0x10];
1961         u8 reserved_at_10[0x10];
1962         u8 reserved_at_20[0x10];
1963         u8 op_mod[0x10];
1964         u8 reserved_at_40[0x40];
1965 };
1966
1967 struct mlx5_ifc_mac_address_layout_bits {
1968         u8 reserved_at_0[0x10];
1969         u8 mac_addr_47_32[0x10];
1970         u8 mac_addr_31_0[0x20];
1971 };
1972
1973 struct mlx5_ifc_nic_vport_context_bits {
1974         u8 reserved_at_0[0x5];
1975         u8 min_wqe_inline_mode[0x3];
1976         u8 reserved_at_8[0x15];
1977         u8 disable_mc_local_lb[0x1];
1978         u8 disable_uc_local_lb[0x1];
1979         u8 roce_en[0x1];
1980         u8 arm_change_event[0x1];
1981         u8 reserved_at_21[0x1a];
1982         u8 event_on_mtu[0x1];
1983         u8 event_on_promisc_change[0x1];
1984         u8 event_on_vlan_change[0x1];
1985         u8 event_on_mc_address_change[0x1];
1986         u8 event_on_uc_address_change[0x1];
1987         u8 reserved_at_40[0xc];
1988         u8 affiliation_criteria[0x4];
1989         u8 affiliated_vhca_id[0x10];
1990         u8 reserved_at_60[0xd0];
1991         u8 mtu[0x10];
1992         u8 system_image_guid[0x40];
1993         u8 port_guid[0x40];
1994         u8 node_guid[0x40];
1995         u8 reserved_at_200[0x140];
1996         u8 qkey_violation_counter[0x10];
1997         u8 reserved_at_350[0x430];
1998         u8 promisc_uc[0x1];
1999         u8 promisc_mc[0x1];
2000         u8 promisc_all[0x1];
2001         u8 reserved_at_783[0x2];
2002         u8 allowed_list_type[0x3];
2003         u8 reserved_at_788[0xc];
2004         u8 allowed_list_size[0xc];
2005         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2006         u8 reserved_at_7e0[0x20];
2007 };
2008
2009 struct mlx5_ifc_query_nic_vport_context_out_bits {
2010         u8 status[0x8];
2011         u8 reserved_at_8[0x18];
2012         u8 syndrome[0x20];
2013         u8 reserved_at_40[0x40];
2014         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
2015 };
2016
2017 struct mlx5_ifc_query_nic_vport_context_in_bits {
2018         u8 opcode[0x10];
2019         u8 reserved_at_10[0x10];
2020         u8 reserved_at_20[0x10];
2021         u8 op_mod[0x10];
2022         u8 other_vport[0x1];
2023         u8 reserved_at_41[0xf];
2024         u8 vport_number[0x10];
2025         u8 reserved_at_60[0x5];
2026         u8 allowed_list_type[0x3];
2027         u8 reserved_at_68[0x18];
2028 };
2029
2030 /*
2031  * lag_tx_port_affinity: 0 auto-selection, 1 PF1, 2 PF2 vice versa.
2032  * Each TIS binds to one PF by setting lag_tx_port_affinity (>0).
2033  * Once LAG enabled, we create multiple TISs and bind each one to
2034  * different PFs, then TIS[i] gets affinity i+1 and goes to PF i+1.
2035  */
2036 #define MLX5_IFC_LAG_MAP_TIS_AFFINITY(index, num) ((num) ? \
2037                                                     (index) % (num) + 1 : 0)
2038 struct mlx5_ifc_tisc_bits {
2039         u8 strict_lag_tx_port_affinity[0x1];
2040         u8 reserved_at_1[0x3];
2041         u8 lag_tx_port_affinity[0x04];
2042         u8 reserved_at_8[0x4];
2043         u8 prio[0x4];
2044         u8 reserved_at_10[0x10];
2045         u8 reserved_at_20[0x100];
2046         u8 reserved_at_120[0x8];
2047         u8 transport_domain[0x18];
2048         u8 reserved_at_140[0x8];
2049         u8 underlay_qpn[0x18];
2050         u8 reserved_at_160[0x3a0];
2051 };
2052
2053 struct mlx5_ifc_query_tis_out_bits {
2054         u8 status[0x8];
2055         u8 reserved_at_8[0x18];
2056         u8 syndrome[0x20];
2057         u8 reserved_at_40[0x40];
2058         struct mlx5_ifc_tisc_bits tis_context;
2059 };
2060
2061 struct mlx5_ifc_query_tis_in_bits {
2062         u8 opcode[0x10];
2063         u8 reserved_at_10[0x10];
2064         u8 reserved_at_20[0x10];
2065         u8 op_mod[0x10];
2066         u8 reserved_at_40[0x8];
2067         u8 tisn[0x18];
2068         u8 reserved_at_60[0x20];
2069 };
2070
2071 /* port_select_mode definition. */
2072 enum mlx5_lag_mode_type {
2073         MLX5_LAG_MODE_TIS = 0,
2074         MLX5_LAG_MODE_HASH = 1,
2075 };
2076
2077 struct mlx5_ifc_lag_context_bits {
2078         u8 fdb_selection_mode[0x1];
2079         u8 reserved_at_1[0x14];
2080         u8 port_select_mode[0x3];
2081         u8 reserved_at_18[0x5];
2082         u8 lag_state[0x3];
2083         u8 reserved_at_20[0x14];
2084         u8 tx_remap_affinity_2[0x4];
2085         u8 reserved_at_38[0x4];
2086         u8 tx_remap_affinity_1[0x4];
2087 };
2088
2089 struct mlx5_ifc_query_lag_in_bits {
2090         u8 opcode[0x10];
2091         u8 uid[0x10];
2092         u8 reserved_at_20[0x10];
2093         u8 op_mod[0x10];
2094         u8 reserved_at_40[0x40];
2095 };
2096
2097 struct mlx5_ifc_query_lag_out_bits {
2098         u8 status[0x8];
2099         u8 reserved_at_8[0x18];
2100         u8 syndrome[0x20];
2101         struct mlx5_ifc_lag_context_bits context;
2102 };
2103
2104 struct mlx5_ifc_alloc_transport_domain_out_bits {
2105         u8 status[0x8];
2106         u8 reserved_at_8[0x18];
2107         u8 syndrome[0x20];
2108         u8 reserved_at_40[0x8];
2109         u8 transport_domain[0x18];
2110         u8 reserved_at_60[0x20];
2111 };
2112
2113 struct mlx5_ifc_alloc_transport_domain_in_bits {
2114         u8 opcode[0x10];
2115         u8 reserved_at_10[0x10];
2116         u8 reserved_at_20[0x10];
2117         u8 op_mod[0x10];
2118         u8 reserved_at_40[0x40];
2119 };
2120
2121 enum {
2122         MLX5_WQ_TYPE_LINKED_LIST                = 0x0,
2123         MLX5_WQ_TYPE_CYCLIC                     = 0x1,
2124         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ    = 0x2,
2125         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ         = 0x3,
2126 };
2127
2128 enum {
2129         MLX5_WQ_END_PAD_MODE_NONE  = 0x0,
2130         MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
2131 };
2132
2133 struct mlx5_ifc_wq_bits {
2134         u8 wq_type[0x4];
2135         u8 wq_signature[0x1];
2136         u8 end_padding_mode[0x2];
2137         u8 cd_slave[0x1];
2138         u8 reserved_at_8[0x18];
2139         u8 hds_skip_first_sge[0x1];
2140         u8 log2_hds_buf_size[0x3];
2141         u8 reserved_at_24[0x7];
2142         u8 page_offset[0x5];
2143         u8 lwm[0x10];
2144         u8 reserved_at_40[0x8];
2145         u8 pd[0x18];
2146         u8 reserved_at_60[0x8];
2147         u8 uar_page[0x18];
2148         u8 dbr_addr[0x40];
2149         u8 hw_counter[0x20];
2150         u8 sw_counter[0x20];
2151         u8 reserved_at_100[0xc];
2152         u8 log_wq_stride[0x4];
2153         u8 reserved_at_110[0x3];
2154         u8 log_wq_pg_sz[0x5];
2155         u8 reserved_at_118[0x3];
2156         u8 log_wq_sz[0x5];
2157         u8 dbr_umem_valid[0x1];
2158         u8 wq_umem_valid[0x1];
2159         u8 reserved_at_122[0x1];
2160         u8 log_hairpin_num_packets[0x5];
2161         u8 reserved_at_128[0x3];
2162         u8 log_hairpin_data_sz[0x5];
2163         u8 reserved_at_130[0x4];
2164         u8 single_wqe_log_num_of_strides[0x4];
2165         u8 two_byte_shift_en[0x1];
2166         u8 reserved_at_139[0x4];
2167         u8 single_stride_log_num_of_bytes[0x3];
2168         u8 dbr_umem_id[0x20];
2169         u8 wq_umem_id[0x20];
2170         u8 wq_umem_offset[0x40];
2171         u8 reserved_at_1c0[0x440];
2172 };
2173
2174 enum {
2175         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2176         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2177 };
2178
2179 enum {
2180         MLX5_RQC_STATE_RST  = 0x0,
2181         MLX5_RQC_STATE_RDY  = 0x1,
2182         MLX5_RQC_STATE_ERR  = 0x3,
2183 };
2184
2185 struct mlx5_ifc_rqc_bits {
2186         u8 rlky[0x1];
2187         u8 delay_drop_en[0x1];
2188         u8 scatter_fcs[0x1];
2189         u8 vsd[0x1];
2190         u8 mem_rq_type[0x4];
2191         u8 state[0x4];
2192         u8 reserved_at_c[0x1];
2193         u8 flush_in_error_en[0x1];
2194         u8 hairpin[0x1];
2195         u8 reserved_at_f[0xB];
2196         u8 ts_format[0x02];
2197         u8 reserved_at_1c[0x4];
2198         u8 reserved_at_20[0x8];
2199         u8 user_index[0x18];
2200         u8 reserved_at_40[0x8];
2201         u8 cqn[0x18];
2202         u8 counter_set_id[0x8];
2203         u8 reserved_at_68[0x18];
2204         u8 reserved_at_80[0x8];
2205         u8 rmpn[0x18];
2206         u8 reserved_at_a0[0x8];
2207         u8 hairpin_peer_sq[0x18];
2208         u8 reserved_at_c0[0x10];
2209         u8 hairpin_peer_vhca[0x10];
2210         u8 reserved_at_e0[0xa0];
2211         struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
2212 };
2213
2214 struct mlx5_ifc_create_rq_out_bits {
2215         u8 status[0x8];
2216         u8 reserved_at_8[0x18];
2217         u8 syndrome[0x20];
2218         u8 reserved_at_40[0x8];
2219         u8 rqn[0x18];
2220         u8 reserved_at_60[0x20];
2221 };
2222
2223 struct mlx5_ifc_create_rq_in_bits {
2224         u8 opcode[0x10];
2225         u8 uid[0x10];
2226         u8 reserved_at_20[0x10];
2227         u8 op_mod[0x10];
2228         u8 reserved_at_40[0xc0];
2229         struct mlx5_ifc_rqc_bits ctx;
2230 };
2231
2232 struct mlx5_ifc_modify_rq_out_bits {
2233         u8 status[0x8];
2234         u8 reserved_at_8[0x18];
2235         u8 syndrome[0x20];
2236         u8 reserved_at_40[0x40];
2237 };
2238
2239 struct mlx5_ifc_query_rq_out_bits {
2240         u8 status[0x8];
2241         u8 reserved_at_8[0x18];
2242         u8 syndrome[0x20];
2243         u8 reserved_at_40[0xc0];
2244         struct mlx5_ifc_rqc_bits rq_context;
2245 };
2246
2247 struct mlx5_ifc_query_rq_in_bits {
2248         u8 opcode[0x10];
2249         u8 reserved_at_10[0x10];
2250         u8 reserved_at_20[0x10];
2251         u8 op_mod[0x10];
2252         u8 reserved_at_40[0x8];
2253         u8 rqn[0x18];
2254         u8 reserved_at_60[0x20];
2255 };
2256
2257 enum {
2258         MLX5_RMPC_STATE_RDY = 0x1,
2259         MLX5_RMPC_STATE_ERR = 0x3,
2260 };
2261
2262 struct mlx5_ifc_rmpc_bits {
2263         u8 reserved_at_0[0x8];
2264         u8 state[0x4];
2265         u8 reserved_at_c[0x14];
2266         u8 basic_cyclic_rcv_wqe[0x1];
2267         u8 reserved_at_21[0x1f];
2268         u8 reserved_at_40[0x140];
2269         struct mlx5_ifc_wq_bits wq;
2270 };
2271
2272 struct mlx5_ifc_query_rmp_out_bits {
2273         u8 status[0x8];
2274         u8 reserved_at_8[0x18];
2275         u8 syndrome[0x20];
2276         u8 reserved_at_40[0xc0];
2277         struct mlx5_ifc_rmpc_bits rmp_context;
2278 };
2279
2280 struct mlx5_ifc_query_rmp_in_bits {
2281         u8 opcode[0x10];
2282         u8 reserved_at_10[0x10];
2283         u8 reserved_at_20[0x10];
2284         u8 op_mod[0x10];
2285         u8 reserved_at_40[0x8];
2286         u8 rmpn[0x18];
2287         u8 reserved_at_60[0x20];
2288 };
2289
2290 struct mlx5_ifc_modify_rmp_out_bits {
2291         u8 status[0x8];
2292         u8 reserved_at_8[0x18];
2293         u8 syndrome[0x20];
2294         u8 reserved_at_40[0x40];
2295 };
2296
2297 struct mlx5_ifc_rmp_bitmask_bits {
2298         u8 reserved_at_0[0x20];
2299         u8 reserved_at_20[0x1f];
2300         u8 lwm[0x1];
2301 };
2302
2303 struct mlx5_ifc_modify_rmp_in_bits {
2304         u8 opcode[0x10];
2305         u8 uid[0x10];
2306         u8 reserved_at_20[0x10];
2307         u8 op_mod[0x10];
2308         u8 rmp_state[0x4];
2309         u8 reserved_at_44[0x4];
2310         u8 rmpn[0x18];
2311         u8 reserved_at_60[0x20];
2312         struct mlx5_ifc_rmp_bitmask_bits bitmask;
2313         u8 reserved_at_c0[0x40];
2314         struct mlx5_ifc_rmpc_bits ctx;
2315 };
2316
2317 struct mlx5_ifc_create_rmp_out_bits {
2318         u8 status[0x8];
2319         u8 reserved_at_8[0x18];
2320         u8 syndrome[0x20];
2321         u8 reserved_at_40[0x8];
2322         u8 rmpn[0x18];
2323         u8 reserved_at_60[0x20];
2324 };
2325
2326 struct mlx5_ifc_create_rmp_in_bits {
2327         u8 opcode[0x10];
2328         u8 uid[0x10];
2329         u8 reserved_at_20[0x10];
2330         u8 op_mod[0x10];
2331         u8 reserved_at_40[0xc0];
2332         struct mlx5_ifc_rmpc_bits ctx;
2333 };
2334
2335 struct mlx5_ifc_create_tis_out_bits {
2336         u8 status[0x8];
2337         u8 reserved_at_8[0x18];
2338         u8 syndrome[0x20];
2339         u8 reserved_at_40[0x8];
2340         u8 tisn[0x18];
2341         u8 reserved_at_60[0x20];
2342 };
2343
2344 struct mlx5_ifc_create_tis_in_bits {
2345         u8 opcode[0x10];
2346         u8 uid[0x10];
2347         u8 reserved_at_20[0x10];
2348         u8 op_mod[0x10];
2349         u8 reserved_at_40[0xc0];
2350         struct mlx5_ifc_tisc_bits ctx;
2351 };
2352
2353 enum {
2354         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
2355         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
2356         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
2357         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
2358 };
2359
2360 struct mlx5_ifc_modify_rq_in_bits {
2361         u8 opcode[0x10];
2362         u8 uid[0x10];
2363         u8 reserved_at_20[0x10];
2364         u8 op_mod[0x10];
2365         u8 rq_state[0x4];
2366         u8 reserved_at_44[0x4];
2367         u8 rqn[0x18];
2368         u8 reserved_at_60[0x20];
2369         u8 modify_bitmask[0x40];
2370         u8 reserved_at_c0[0x40];
2371         struct mlx5_ifc_rqc_bits ctx;
2372 };
2373
2374 enum {
2375         MLX5_L3_PROT_TYPE_IPV4 = 0,
2376         MLX5_L3_PROT_TYPE_IPV6 = 1,
2377 };
2378
2379 enum {
2380         MLX5_L4_PROT_TYPE_TCP = 0,
2381         MLX5_L4_PROT_TYPE_UDP = 1,
2382 };
2383
2384 enum {
2385         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
2386         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
2387         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
2388         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
2389         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
2390 };
2391
2392 struct mlx5_ifc_rx_hash_field_select_bits {
2393         u8 l3_prot_type[0x1];
2394         u8 l4_prot_type[0x1];
2395         u8 selected_fields[0x1e];
2396 };
2397
2398 enum {
2399         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2400         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2401 };
2402
2403 enum {
2404         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2405         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2406 };
2407
2408 enum {
2409         MLX5_RX_HASH_FN_NONE           = 0x0,
2410         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2411         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2412 };
2413
2414 enum {
2415         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
2416         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
2417 };
2418
2419 enum {
2420         MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4    = 0x0,
2421         MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2  = 0x1,
2422 };
2423
2424 struct mlx5_ifc_tirc_bits {
2425         u8 reserved_at_0[0x20];
2426         u8 disp_type[0x4];
2427         u8 reserved_at_24[0x1c];
2428         u8 reserved_at_40[0x40];
2429         u8 reserved_at_80[0x4];
2430         u8 lro_timeout_period_usecs[0x10];
2431         u8 lro_enable_mask[0x4];
2432         u8 lro_max_msg_sz[0x8];
2433         u8 reserved_at_a0[0x40];
2434         u8 reserved_at_e0[0x8];
2435         u8 inline_rqn[0x18];
2436         u8 rx_hash_symmetric[0x1];
2437         u8 reserved_at_101[0x1];
2438         u8 tunneled_offload_en[0x1];
2439         u8 reserved_at_103[0x5];
2440         u8 indirect_table[0x18];
2441         u8 rx_hash_fn[0x4];
2442         u8 reserved_at_124[0x2];
2443         u8 self_lb_block[0x2];
2444         u8 transport_domain[0x18];
2445         u8 rx_hash_toeplitz_key[10][0x20];
2446         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2447         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2448         u8 reserved_at_2c0[0x4c0];
2449 };
2450
2451 struct mlx5_ifc_create_tir_out_bits {
2452         u8 status[0x8];
2453         u8 reserved_at_8[0x18];
2454         u8 syndrome[0x20];
2455         u8 reserved_at_40[0x8];
2456         u8 tirn[0x18];
2457         u8 reserved_at_60[0x20];
2458 };
2459
2460 struct mlx5_ifc_create_tir_in_bits {
2461         u8 opcode[0x10];
2462         u8 uid[0x10];
2463         u8 reserved_at_20[0x10];
2464         u8 op_mod[0x10];
2465         u8 reserved_at_40[0xc0];
2466         struct mlx5_ifc_tirc_bits ctx;
2467 };
2468
2469 enum {
2470         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0,
2471         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1,
2472         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2,
2473         /* bit 3 - tunneled_offload_en modify not supported. */
2474         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4,
2475 };
2476
2477 struct mlx5_ifc_modify_tir_out_bits {
2478         u8 status[0x8];
2479         u8 reserved_at_8[0x18];
2480         u8 syndrome[0x20];
2481         u8 reserved_at_40[0x40];
2482 };
2483
2484 struct mlx5_ifc_modify_tir_in_bits {
2485         u8 opcode[0x10];
2486         u8 uid[0x10];
2487         u8 reserved_at_20[0x10];
2488         u8 op_mod[0x10];
2489         u8 reserved_at_40[0x8];
2490         u8 tirn[0x18];
2491         u8 reserved_at_60[0x20];
2492         u8 modify_bitmask[0x40];
2493         u8 reserved_at_c0[0x40];
2494         struct mlx5_ifc_tirc_bits ctx;
2495 };
2496
2497 enum {
2498         MLX5_INLINE_Q_TYPE_RQ = 0x0,
2499         MLX5_INLINE_Q_TYPE_VIRTQ = 0x1,
2500 };
2501
2502 struct mlx5_ifc_rq_num_bits {
2503         u8 reserved_at_0[0x8];
2504         u8 rq_num[0x18];
2505 };
2506
2507 struct mlx5_ifc_rqtc_bits {
2508         u8 reserved_at_0[0xa5];
2509         u8 list_q_type[0x3];
2510         u8 reserved_at_a8[0x8];
2511         u8 rqt_max_size[0x10];
2512         u8 reserved_at_c0[0x10];
2513         u8 rqt_actual_size[0x10];
2514         u8 reserved_at_e0[0x6a0];
2515         struct mlx5_ifc_rq_num_bits rq_num[];
2516 };
2517
2518 struct mlx5_ifc_create_rqt_out_bits {
2519         u8 status[0x8];
2520         u8 reserved_at_8[0x18];
2521         u8 syndrome[0x20];
2522         u8 reserved_at_40[0x8];
2523         u8 rqtn[0x18];
2524         u8 reserved_at_60[0x20];
2525 };
2526
2527 #ifdef PEDANTIC
2528 #pragma GCC diagnostic ignored "-Wpedantic"
2529 #endif
2530 struct mlx5_ifc_create_rqt_in_bits {
2531         u8 opcode[0x10];
2532         u8 uid[0x10];
2533         u8 reserved_at_20[0x10];
2534         u8 op_mod[0x10];
2535         u8 reserved_at_40[0xc0];
2536         struct mlx5_ifc_rqtc_bits rqt_context;
2537 };
2538
2539 struct mlx5_ifc_modify_rqt_in_bits {
2540         u8 opcode[0x10];
2541         u8 uid[0x10];
2542         u8 reserved_at_20[0x10];
2543         u8 op_mod[0x10];
2544         u8 reserved_at_40[0x8];
2545         u8 rqtn[0x18];
2546         u8 reserved_at_60[0x20];
2547         u8 modify_bitmask[0x40];
2548         u8 reserved_at_c0[0x40];
2549         struct mlx5_ifc_rqtc_bits rqt_context;
2550 };
2551 #ifdef PEDANTIC
2552 #pragma GCC diagnostic error "-Wpedantic"
2553 #endif
2554
2555 struct mlx5_ifc_modify_rqt_out_bits {
2556         u8 status[0x8];
2557         u8 reserved_at_8[0x18];
2558         u8 syndrome[0x20];
2559         u8 reserved_at_40[0x40];
2560 };
2561
2562 enum {
2563         MLX5_SQC_STATE_RST  = 0x0,
2564         MLX5_SQC_STATE_RDY  = 0x1,
2565         MLX5_SQC_STATE_ERR  = 0x3,
2566 };
2567
2568 struct mlx5_ifc_sqc_bits {
2569         u8 rlky[0x1];
2570         u8 cd_master[0x1];
2571         u8 fre[0x1];
2572         u8 flush_in_error_en[0x1];
2573         u8 allow_multi_pkt_send_wqe[0x1];
2574         u8 min_wqe_inline_mode[0x3];
2575         u8 state[0x4];
2576         u8 reg_umr[0x1];
2577         u8 allow_swp[0x1];
2578         u8 hairpin[0x1];
2579         u8 non_wire[0x1];
2580         u8 static_sq_wq[0x1];
2581         u8 reserved_at_11[0x9];
2582         u8 ts_format[0x02];
2583         u8 reserved_at_1c[0x4];
2584         u8 reserved_at_20[0x8];
2585         u8 user_index[0x18];
2586         u8 reserved_at_40[0x8];
2587         u8 cqn[0x18];
2588         u8 reserved_at_60[0x8];
2589         u8 hairpin_peer_rq[0x18];
2590         u8 reserved_at_80[0x10];
2591         u8 hairpin_peer_vhca[0x10];
2592         u8 reserved_at_a0[0x50];
2593         u8 packet_pacing_rate_limit_index[0x10];
2594         u8 tis_lst_sz[0x10];
2595         u8 reserved_at_110[0x10];
2596         u8 reserved_at_120[0x40];
2597         u8 reserved_at_160[0x8];
2598         u8 tis_num_0[0x18];
2599         struct mlx5_ifc_wq_bits wq;
2600 };
2601
2602 struct mlx5_ifc_query_sq_in_bits {
2603         u8 opcode[0x10];
2604         u8 reserved_at_10[0x10];
2605         u8 reserved_at_20[0x10];
2606         u8 op_mod[0x10];
2607         u8 reserved_at_40[0x8];
2608         u8 sqn[0x18];
2609         u8 reserved_at_60[0x20];
2610 };
2611
2612 struct mlx5_ifc_modify_sq_out_bits {
2613         u8 status[0x8];
2614         u8 reserved_at_8[0x18];
2615         u8 syndrome[0x20];
2616         u8 reserved_at_40[0x40];
2617 };
2618
2619 struct mlx5_ifc_modify_sq_in_bits {
2620         u8 opcode[0x10];
2621         u8 uid[0x10];
2622         u8 reserved_at_20[0x10];
2623         u8 op_mod[0x10];
2624         u8 sq_state[0x4];
2625         u8 reserved_at_44[0x4];
2626         u8 sqn[0x18];
2627         u8 reserved_at_60[0x20];
2628         u8 modify_bitmask[0x40];
2629         u8 reserved_at_c0[0x40];
2630         struct mlx5_ifc_sqc_bits ctx;
2631 };
2632
2633 struct mlx5_ifc_create_sq_out_bits {
2634         u8 status[0x8];
2635         u8 reserved_at_8[0x18];
2636         u8 syndrome[0x20];
2637         u8 reserved_at_40[0x8];
2638         u8 sqn[0x18];
2639         u8 reserved_at_60[0x20];
2640 };
2641
2642 struct mlx5_ifc_create_sq_in_bits {
2643         u8 opcode[0x10];
2644         u8 uid[0x10];
2645         u8 reserved_at_20[0x10];
2646         u8 op_mod[0x10];
2647         u8 reserved_at_40[0xc0];
2648         struct mlx5_ifc_sqc_bits ctx;
2649 };
2650
2651 enum {
2652         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
2653         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
2654         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
2655         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
2656         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
2657 };
2658
2659 struct mlx5_ifc_flow_meter_parameters_bits {
2660         u8 valid[0x1];
2661         u8 bucket_overflow[0x1];
2662         u8 start_color[0x2];
2663         u8 both_buckets_on_green[0x1];
2664         u8 meter_mode[0x2];
2665         u8 reserved_at_1[0x19];
2666         u8 reserved_at_2[0x20];
2667         u8 reserved_at_3[0x3];
2668         u8 cbs_exponent[0x5];
2669         u8 cbs_mantissa[0x8];
2670         u8 reserved_at_4[0x3];
2671         u8 cir_exponent[0x5];
2672         u8 cir_mantissa[0x8];
2673         u8 reserved_at_5[0x20];
2674         u8 reserved_at_6[0x3];
2675         u8 ebs_exponent[0x5];
2676         u8 ebs_mantissa[0x8];
2677         u8 reserved_at_7[0x3];
2678         u8 eir_exponent[0x5];
2679         u8 eir_mantissa[0x8];
2680         u8 reserved_at_8[0x60];
2681 };
2682 #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF)
2683 #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8
2684
2685 enum {
2686         MLX5_METER_MODE_IP_LEN = 0x0,
2687         MLX5_METER_MODE_L2_LEN = 0x1,
2688         MLX5_METER_MODE_L2_IPG_LEN = 0x2,
2689         MLX5_METER_MODE_PKT = 0x3,
2690 };
2691
2692 enum {
2693         MLX5_CQE_SIZE_64B = 0x0,
2694         MLX5_CQE_SIZE_128B = 0x1,
2695 };
2696
2697 struct mlx5_ifc_cqc_bits {
2698         u8 status[0x4];
2699         u8 as_notify[0x1];
2700         u8 initiator_src_dct[0x1];
2701         u8 dbr_umem_valid[0x1];
2702         u8 reserved_at_7[0x1];
2703         u8 cqe_sz[0x3];
2704         u8 cc[0x1];
2705         u8 reserved_at_c[0x1];
2706         u8 scqe_break_moderation_en[0x1];
2707         u8 oi[0x1];
2708         u8 cq_period_mode[0x2];
2709         u8 cqe_comp_en[0x1];
2710         u8 mini_cqe_res_format[0x2];
2711         u8 st[0x4];
2712         u8 reserved_at_18[0x1];
2713         u8 cqe_comp_layout[0x7];
2714         u8 dbr_umem_id[0x20];
2715         u8 reserved_at_40[0x14];
2716         u8 page_offset[0x6];
2717         u8 reserved_at_5a[0x2];
2718         u8 mini_cqe_res_format_ext[0x2];
2719         u8 cq_timestamp_format[0x2];
2720         u8 reserved_at_60[0x3];
2721         u8 log_cq_size[0x5];
2722         u8 uar_page[0x18];
2723         u8 reserved_at_80[0x4];
2724         u8 cq_period[0xc];
2725         u8 cq_max_count[0x10];
2726         u8 reserved_at_a0[0x18];
2727         u8 c_eqn[0x8];
2728         u8 reserved_at_c0[0x3];
2729         u8 log_page_size[0x5];
2730         u8 reserved_at_c8[0x18];
2731         u8 reserved_at_e0[0x20];
2732         u8 reserved_at_100[0x8];
2733         u8 last_notified_index[0x18];
2734         u8 reserved_at_120[0x8];
2735         u8 last_solicit_index[0x18];
2736         u8 reserved_at_140[0x8];
2737         u8 consumer_counter[0x18];
2738         u8 reserved_at_160[0x8];
2739         u8 producer_counter[0x18];
2740         u8 local_partition_id[0xc];
2741         u8 process_id[0x14];
2742         u8 reserved_at_1A0[0x20];
2743         u8 dbr_addr[0x40];
2744 };
2745
2746 struct mlx5_ifc_health_buffer_bits {
2747         u8 reserved_0[0x100];
2748         u8 assert_existptr[0x20];
2749         u8 assert_callra[0x20];
2750         u8 reserved_1[0x40];
2751         u8 fw_version[0x20];
2752         u8 hw_id[0x20];
2753         u8 reserved_2[0x20];
2754         u8 irisc_index[0x8];
2755         u8 synd[0x8];
2756         u8 ext_synd[0x10];
2757 };
2758
2759 struct mlx5_ifc_initial_seg_bits {
2760         u8 fw_rev_minor[0x10];
2761         u8 fw_rev_major[0x10];
2762         u8 cmd_interface_rev[0x10];
2763         u8 fw_rev_subminor[0x10];
2764         u8 reserved_0[0x40];
2765         u8 cmdq_phy_addr_63_32[0x20];
2766         u8 cmdq_phy_addr_31_12[0x14];
2767         u8 reserved_1[0x2];
2768         u8 nic_interface[0x2];
2769         u8 log_cmdq_size[0x4];
2770         u8 log_cmdq_stride[0x4];
2771         u8 command_doorbell_vector[0x20];
2772         u8 reserved_2[0xf00];
2773         u8 initializing[0x1];
2774         u8 nic_interface_supported[0x7];
2775         u8 reserved_4[0x18];
2776         struct mlx5_ifc_health_buffer_bits health_buffer;
2777         u8 no_dram_nic_offset[0x20];
2778         u8 reserved_5[0x6de0];
2779         u8 internal_timer_h[0x20];
2780         u8 internal_timer_l[0x20];
2781         u8 reserved_6[0x20];
2782         u8 reserved_7[0x1f];
2783         u8 clear_int[0x1];
2784         u8 health_syndrome[0x8];
2785         u8 health_counter[0x18];
2786         u8 reserved_8[0x17fc0];
2787 };
2788
2789 struct mlx5_ifc_create_cq_out_bits {
2790         u8 status[0x8];
2791         u8 reserved_at_8[0x18];
2792         u8 syndrome[0x20];
2793         u8 reserved_at_40[0x8];
2794         u8 cqn[0x18];
2795         u8 reserved_at_60[0x20];
2796 };
2797
2798 struct mlx5_ifc_create_cq_in_bits {
2799         u8 opcode[0x10];
2800         u8 uid[0x10];
2801         u8 reserved_at_20[0x10];
2802         u8 op_mod[0x10];
2803         u8 reserved_at_40[0x40];
2804         struct mlx5_ifc_cqc_bits cq_context;
2805         u8 cq_umem_offset[0x40];
2806         u8 cq_umem_id[0x20];
2807         u8 cq_umem_valid[0x1];
2808         u8 reserved_at_2e1[0x1f];
2809         u8 reserved_at_300[0x580];
2810         u8 pas[];
2811 };
2812
2813 enum {
2814         MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
2815         MLX5_GENERAL_OBJ_TYPE_DEK = 0x000c,
2816         MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
2817         MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
2818         MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d,
2819         MLX5_GENERAL_OBJ_TYPE_CREDENTIAL = 0x001e,
2820         MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN = 0x001f,
2821         MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,
2822         MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024,
2823         MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025,
2824         MLX5_GENERAL_OBJ_TYPE_CONN_TRACK_OFFLOAD = 0x0031,
2825 };
2826
2827 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
2828         u8 opcode[0x10];
2829         u8 reserved_at_10[0x20];
2830         u8 obj_type[0x10];
2831         u8 obj_id[0x20];
2832         u8 reserved_at_60[0x3];
2833         u8 log_obj_range[0x5];
2834         u8 reserved_at_58[0x18];
2835 };
2836
2837 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
2838         u8 status[0x8];
2839         u8 reserved_at_8[0x18];
2840         u8 syndrome[0x20];
2841         u8 obj_id[0x20];
2842         u8 reserved_at_60[0x20];
2843 };
2844
2845 struct mlx5_ifc_virtio_q_counters_bits {
2846         u8 modify_field_select[0x40];
2847         u8 reserved_at_40[0x40];
2848         u8 received_desc[0x40];
2849         u8 completed_desc[0x40];
2850         u8 error_cqes[0x20];
2851         u8 bad_desc_errors[0x20];
2852         u8 exceed_max_chain[0x20];
2853         u8 invalid_buffer[0x20];
2854         u8 reserved_at_180[0x50];
2855 };
2856
2857 struct mlx5_ifc_geneve_tlv_option_bits {
2858         u8 modify_field_select[0x40];
2859         u8 reserved_at_40[0x18];
2860         u8 geneve_option_fte_index[0x8];
2861         u8 option_class[0x10];
2862         u8 option_type[0x8];
2863         u8 reserved_at_78[0x3];
2864         u8 option_data_length[0x5];
2865         u8 reserved_at_80[0x180];
2866 };
2867
2868 struct mlx5_ifc_create_virtio_q_counters_in_bits {
2869         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2870         struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2871 };
2872
2873 struct mlx5_ifc_query_virtio_q_counters_out_bits {
2874         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2875         struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2876 };
2877
2878 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
2879         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2880         struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
2881 };
2882
2883 enum {
2884         MLX5_CRYPTO_KEY_SIZE_128b = 0x0,
2885         MLX5_CRYPTO_KEY_SIZE_256b = 0x1,
2886 };
2887
2888 enum {
2889         MLX5_CRYPTO_KEY_PURPOSE_TLS     = 0x1,
2890         MLX5_CRYPTO_KEY_PURPOSE_IPSEC   = 0x2,
2891         MLX5_CRYPTO_KEY_PURPOSE_AES_XTS = 0x3,
2892         MLX5_CRYPTO_KEY_PURPOSE_MACSEC  = 0x4,
2893         MLX5_CRYPTO_KEY_PURPOSE_GCM     = 0x5,
2894         MLX5_CRYPTO_KEY_PURPOSE_PSP     = 0x6,
2895 };
2896
2897 struct mlx5_ifc_dek_bits {
2898         u8 modify_field_select[0x40];
2899         u8 state[0x8];
2900         u8 reserved_at_48[0xc];
2901         u8 key_size[0x4];
2902         u8 has_keytag[0x1];
2903         u8 reserved_at_59[0x3];
2904         u8 key_purpose[0x4];
2905         u8 reserved_at_60[0x8];
2906         u8 pd[0x18];
2907         u8 reserved_at_80[0x100];
2908         u8 opaque[0x40];
2909         u8 reserved_at_1c0[0x40];
2910         u8 key[0x400];
2911         u8 reserved_at_600[0x200];
2912 };
2913
2914 struct mlx5_ifc_create_dek_in_bits {
2915         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2916         struct mlx5_ifc_dek_bits dek;
2917 };
2918
2919 struct mlx5_ifc_import_kek_bits {
2920         u8 modify_field_select[0x40];
2921         u8 state[0x8];
2922         u8 reserved_at_48[0xc];
2923         u8 key_size[0x4];
2924         u8 reserved_at_58[0x1a8];
2925         u8 key[0x400];
2926         u8 reserved_at_600[0x200];
2927 };
2928
2929 struct mlx5_ifc_create_import_kek_in_bits {
2930         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2931         struct mlx5_ifc_import_kek_bits import_kek;
2932 };
2933
2934 enum {
2935         MLX5_CREDENTIAL_ROLE_OFFICER = 0x0,
2936         MLX5_CREDENTIAL_ROLE_USER = 0x1,
2937 };
2938
2939 struct mlx5_ifc_credential_bits {
2940         u8 modify_field_select[0x40];
2941         u8 state[0x8];
2942         u8 reserved_at_48[0x10];
2943         u8 credential_role[0x8];
2944         u8 reserved_at_60[0x1a0];
2945         u8 credential[0x180];
2946         u8 reserved_at_380[0x480];
2947 };
2948
2949 struct mlx5_ifc_create_credential_in_bits {
2950         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2951         struct mlx5_ifc_credential_bits credential;
2952 };
2953
2954 struct mlx5_ifc_crypto_login_bits {
2955         u8 modify_field_select[0x40];
2956         u8 reserved_at_40[0x48];
2957         u8 credential_pointer[0x18];
2958         u8 reserved_at_a0[0x8];
2959         u8 session_import_kek_ptr[0x18];
2960         u8 reserved_at_c0[0x140];
2961         u8 credential[0x180];
2962         u8 reserved_at_380[0x480];
2963 };
2964
2965 struct mlx5_ifc_create_crypto_login_in_bits {
2966         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2967         struct mlx5_ifc_crypto_login_bits crypto_login;
2968 };
2969
2970 enum {
2971         MLX5_VIRTQ_STATE_INIT = 0,
2972         MLX5_VIRTQ_STATE_RDY = 1,
2973         MLX5_VIRTQ_STATE_SUSPEND = 2,
2974         MLX5_VIRTQ_STATE_ERROR = 3,
2975 };
2976
2977 enum {
2978         MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),
2979         MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),
2980         MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),
2981 };
2982
2983 struct mlx5_ifc_virtio_q_bits {
2984         u8 virtio_q_type[0x8];
2985         u8 reserved_at_8[0x5];
2986         u8 event_mode[0x3];
2987         u8 queue_index[0x10];
2988         u8 full_emulation[0x1];
2989         u8 virtio_version_1_0[0x1];
2990         u8 reserved_at_22[0x2];
2991         u8 offload_type[0x4];
2992         u8 event_qpn_or_msix[0x18];
2993         u8 doorbell_stride_idx[0x10];
2994         u8 queue_size[0x10];
2995         u8 device_emulation_id[0x20];
2996         u8 desc_addr[0x40];
2997         u8 used_addr[0x40];
2998         u8 available_addr[0x40];
2999         u8 virtio_q_mkey[0x20];
3000         u8 reserved_at_160[0x18];
3001         u8 error_type[0x8];
3002         u8 umem_1_id[0x20];
3003         u8 umem_1_size[0x20];
3004         u8 umem_1_offset[0x40];
3005         u8 umem_2_id[0x20];
3006         u8 umem_2_size[0x20];
3007         u8 umem_2_offset[0x40];
3008         u8 umem_3_id[0x20];
3009         u8 umem_3_size[0x20];
3010         u8 umem_3_offset[0x40];
3011         u8 counter_set_id[0x20];
3012         u8 reserved_at_320[0x8];
3013         u8 pd[0x18];
3014         u8 reserved_at_340[0x2];
3015         u8 queue_period_mode[0x2];
3016         u8 queue_period_us[0xc];
3017         u8 queue_max_count[0x10];
3018         u8 reserved_at_360[0xa0];
3019 };
3020
3021 struct mlx5_ifc_virtio_net_q_bits {
3022         u8 modify_field_select[0x40];
3023         u8 reserved_at_40[0x40];
3024         u8 tso_ipv4[0x1];
3025         u8 tso_ipv6[0x1];
3026         u8 tx_csum[0x1];
3027         u8 rx_csum[0x1];
3028         u8 reserved_at_84[0x6];
3029         u8 dirty_bitmap_dump_enable[0x1];
3030         u8 vhost_log_page[0x5];
3031         u8 reserved_at_90[0xc];
3032         u8 state[0x4];
3033         u8 reserved_at_a0[0x8];
3034         u8 tisn_or_qpn[0x18];
3035         u8 dirty_bitmap_mkey[0x20];
3036         u8 dirty_bitmap_size[0x20];
3037         u8 dirty_bitmap_addr[0x40];
3038         u8 hw_available_index[0x10];
3039         u8 hw_used_index[0x10];
3040         u8 reserved_at_160[0xa0];
3041         struct mlx5_ifc_virtio_q_bits virtio_q_context;
3042 };
3043
3044 struct mlx5_ifc_create_virtq_in_bits {
3045         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3046         struct mlx5_ifc_virtio_net_q_bits virtq;
3047 };
3048
3049 struct mlx5_ifc_query_virtq_out_bits {
3050         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3051         struct mlx5_ifc_virtio_net_q_bits virtq;
3052 };
3053
3054 struct mlx5_ifc_flow_hit_aso_bits {
3055         u8 modify_field_select[0x40];
3056         u8 reserved_at_40[0x48];
3057         u8 access_pd[0x18];
3058         u8 reserved_at_a0[0x160];
3059         u8 flag[0x200];
3060 };
3061
3062 struct mlx5_ifc_create_flow_hit_aso_in_bits {
3063         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3064         struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso;
3065 };
3066
3067 struct mlx5_ifc_flow_meter_aso_bits {
3068         u8 modify_field_select[0x40];
3069         u8 reserved_at_40[0x48];
3070         u8 access_pd[0x18];
3071         u8 reserved_at_a0[0x160];
3072         u8 parameters[0x200];
3073 };
3074
3075 struct mlx5_ifc_create_flow_meter_aso_in_bits {
3076         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3077         struct mlx5_ifc_flow_meter_aso_bits flow_meter_aso;
3078 };
3079
3080 struct mlx5_ifc_tcp_window_params_bits {
3081         u8 max_ack[0x20];
3082         u8 max_win[0x20];
3083         u8 reply_end[0x20];
3084         u8 sent_end[0x20];
3085 };
3086
3087 struct mlx5_ifc_conn_track_aso_bits {
3088         struct mlx5_ifc_tcp_window_params_bits reply_dir; /* End of DW3. */
3089         struct mlx5_ifc_tcp_window_params_bits original_dir; /* End of DW7. */
3090         u8 last_end[0x20]; /* End of DW8. */
3091         u8 last_ack[0x20]; /* End of DW9. */
3092         u8 last_seq[0x20]; /* End of DW10. */
3093         u8 last_win[0x10];
3094         u8 reserved_at_170[0xa];
3095         u8 last_dir[0x1];
3096         u8 last_index[0x5]; /* End of DW11. */
3097         u8 reserved_at_180[0x40]; /* End of DW13. */
3098         u8 reply_direction_tcp_scale[0x4];
3099         u8 reply_direction_tcp_close_initiated[0x1];
3100         u8 reply_direction_tcp_liberal_enabled[0x1];
3101         u8 reply_direction_tcp_data_unacked[0x1];
3102         u8 reply_direction_tcp_max_ack[0x1];
3103         u8 reserved_at_1c8[0x8];
3104         u8 original_direction_tcp_scale[0x4];
3105         u8 original_direction_tcp_close_initiated[0x1];
3106         u8 original_direction_tcp_liberal_enabled[0x1];
3107         u8 original_direction_tcp_data_unacked[0x1];
3108         u8 original_direction_tcp_max_ack[0x1];
3109         u8 reserved_at_1d8[0x8]; /* End of DW14. */
3110         u8 valid[0x1];
3111         u8 state[0x3];
3112         u8 freeze_track[0x1];
3113         u8 reserved_at_1e5[0xb];
3114         u8 reserved_at_1f0[0x1];
3115         u8 connection_assured[0x1];
3116         u8 sack_permitted[0x1];
3117         u8 challenged_acked[0x1];
3118         u8 heartbeat[0x1];
3119         u8 max_ack_window[0x3];
3120         u8 reserved_at_1f8[0x1];
3121         u8 retransmission_counter[0x3];
3122         u8 retranmission_limit_exceeded[0x1];
3123         u8 retranmission_limit[0x3]; /* End of DW15. */
3124 };
3125
3126 struct mlx5_ifc_conn_track_offload_bits {
3127         u8 modify_field_select[0x40];
3128         u8 reserved_at_40[0x40];
3129         u8 reserved_at_80[0x8];
3130         u8 conn_track_aso_access_pd[0x18];
3131         u8 reserved_at_a0[0x160];
3132         struct mlx5_ifc_conn_track_aso_bits conn_track_aso;
3133 };
3134
3135 struct mlx5_ifc_create_conn_track_aso_in_bits {
3136         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3137         struct mlx5_ifc_conn_track_offload_bits conn_track_offload;
3138 };
3139
3140 enum mlx5_access_aso_opc_mod {
3141         ASO_OPC_MOD_IPSEC = 0x0,
3142         ASO_OPC_MOD_CONNECTION_TRACKING = 0x1,
3143         ASO_OPC_MOD_POLICER = 0x2,
3144         ASO_OPC_MOD_RACE_AVOIDANCE = 0x3,
3145         ASO_OPC_MOD_FLOW_HIT = 0x4,
3146 };
3147
3148 #define ASO_CSEG_DATA_MASK_MODE_OFFSET  30
3149
3150 enum mlx5_aso_data_mask_mode {
3151         BITWISE_64BIT = 0x0,
3152         BYTEWISE_64BYTE = 0x1,
3153         CALCULATED_64BYTE = 0x2,
3154 };
3155
3156 #define ASO_CSEG_COND_0_OPER_OFFSET     20
3157 #define ASO_CSEG_COND_1_OPER_OFFSET     16
3158
3159 enum mlx5_aso_pre_cond_op {
3160         ASO_OP_ALWAYS_FALSE = 0x0,
3161         ASO_OP_ALWAYS_TRUE = 0x1,
3162         ASO_OP_EQUAL = 0x2,
3163         ASO_OP_NOT_EQUAL = 0x3,
3164         ASO_OP_GREATER_OR_EQUAL = 0x4,
3165         ASO_OP_LESSER_OR_EQUAL = 0x5,
3166         ASO_OP_LESSER = 0x6,
3167         ASO_OP_GREATER = 0x7,
3168         ASO_OP_CYCLIC_GREATER = 0x8,
3169         ASO_OP_CYCLIC_LESSER = 0x9,
3170 };
3171
3172 #define ASO_CSEG_COND_OPER_OFFSET       6
3173
3174 enum mlx5_aso_op {
3175         ASO_OPER_LOGICAL_AND = 0x0,
3176         ASO_OPER_LOGICAL_OR = 0x1,
3177 };
3178
3179 /* ASO WQE CTRL segment. */
3180 struct mlx5_aso_cseg {
3181         uint32_t va_h;
3182         uint32_t va_l_r;
3183         uint32_t lkey;
3184         uint32_t operand_masks;
3185         uint32_t condition_0_data;
3186         uint32_t condition_0_mask;
3187         uint32_t condition_1_data;
3188         uint32_t condition_1_mask;
3189         uint64_t bitwise_data;
3190         uint64_t data_mask;
3191 } __rte_packed;
3192
3193 /* A meter data segment - 2 per ASO WQE. */
3194 struct mlx5_aso_mtr_dseg {
3195         uint32_t v_bo_sc_bbog_mm;
3196         /*
3197          * bit 31: valid, 30: bucket overflow, 28-29: start color,
3198          * 27: both buckets on green, 24-25: meter mode.
3199          */
3200         uint32_t reserved;
3201         uint32_t cbs_cir;
3202         /*
3203          * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa,
3204          * bit 8-12: cir_exponent, bit 0-7 cir_mantissa.
3205          */
3206         uint32_t c_tokens;
3207         uint32_t ebs_eir;
3208         /*
3209          * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa,
3210          * bit 8-12: eir_exponent, bit 0-7 eir_mantissa.
3211          */
3212         uint32_t e_tokens;
3213         uint64_t timestamp;
3214 } __rte_packed;
3215
3216 #define ASO_DSEG_VALID_OFFSET 31
3217 #define ASO_DSEG_BO_OFFSET 30
3218 #define ASO_DSEG_SC_OFFSET 28
3219 #define ASO_DSEG_BBOG_OFFSET 27
3220 #define ASO_DSEG_MTR_MODE 24
3221 #define ASO_DSEG_CBS_EXP_OFFSET 24
3222 #define ASO_DSEG_CBS_MAN_OFFSET 16
3223 #define ASO_DSEG_XIR_EXP_MASK 0x1F
3224 #define ASO_DSEG_XIR_EXP_OFFSET 8
3225 #define ASO_DSEG_EBS_EXP_OFFSET 24
3226 #define ASO_DSEG_EBS_MAN_OFFSET 16
3227 #define ASO_DSEG_EXP_MASK 0x1F
3228 #define ASO_DSEG_MAN_MASK 0xFF
3229
3230 #define MLX5_ASO_WQE_DSEG_SIZE  0x40
3231 #define MLX5_ASO_METERS_PER_WQE 2
3232 #define MLX5_ASO_MTRS_PER_POOL 128
3233
3234 /* ASO WQE data segment. */
3235 struct mlx5_aso_dseg {
3236         union {
3237                 uint8_t data[MLX5_ASO_WQE_DSEG_SIZE];
3238                 struct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE];
3239         };
3240 } __rte_packed;
3241
3242 /* ASO WQE. */
3243 struct mlx5_aso_wqe {
3244         struct mlx5_wqe_cseg general_cseg;
3245         struct mlx5_aso_cseg aso_cseg;
3246         struct mlx5_aso_dseg aso_dseg;
3247 } __rte_packed;
3248
3249 enum {
3250         MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
3251 };
3252
3253 enum {
3254         MLX5_QP_ST_RC = 0x0,
3255 };
3256
3257 enum {
3258         MLX5_QP_PM_MIGRATED = 0x3,
3259 };
3260
3261 enum {
3262         MLX5_NON_ZERO_RQ = 0x0,
3263         MLX5_SRQ_RQ = 0x1,
3264         MLX5_CRQ_RQ = 0x2,
3265         MLX5_ZERO_LEN_RQ = 0x3,
3266 };
3267
3268 struct mlx5_ifc_ads_bits {
3269         u8 fl[0x1];
3270         u8 free_ar[0x1];
3271         u8 reserved_at_2[0xe];
3272         u8 pkey_index[0x10];
3273         u8 reserved_at_20[0x8];
3274         u8 grh[0x1];
3275         u8 mlid[0x7];
3276         u8 rlid[0x10];
3277         u8 ack_timeout[0x5];
3278         u8 reserved_at_45[0x3];
3279         u8 src_addr_index[0x8];
3280         u8 reserved_at_50[0x4];
3281         u8 stat_rate[0x4];
3282         u8 hop_limit[0x8];
3283         u8 reserved_at_60[0x4];
3284         u8 tclass[0x8];
3285         u8 flow_label[0x14];
3286         u8 rgid_rip[16][0x8];
3287         u8 reserved_at_100[0x4];
3288         u8 f_dscp[0x1];
3289         u8 f_ecn[0x1];
3290         u8 reserved_at_106[0x1];
3291         u8 f_eth_prio[0x1];
3292         u8 ecn[0x2];
3293         u8 dscp[0x6];
3294         u8 udp_sport[0x10];
3295         u8 dei_cfi[0x1];
3296         u8 eth_prio[0x3];
3297         u8 sl[0x4];
3298         u8 vhca_port_num[0x8];
3299         u8 rmac_47_32[0x10];
3300         u8 rmac_31_0[0x20];
3301 };
3302
3303 struct mlx5_ifc_qpc_bits {
3304         u8 state[0x4];
3305         u8 lag_tx_port_affinity[0x4];
3306         u8 st[0x8];
3307         u8 reserved_at_10[0x3];
3308         u8 pm_state[0x2];
3309         u8 reserved_at_15[0x1];
3310         u8 req_e2e_credit_mode[0x2];
3311         u8 offload_type[0x4];
3312         u8 end_padding_mode[0x2];
3313         u8 reserved_at_1e[0x2];
3314         u8 wq_signature[0x1];
3315         u8 block_lb_mc[0x1];
3316         u8 atomic_like_write_en[0x1];
3317         u8 latency_sensitive[0x1];
3318         u8 reserved_at_24[0x1];
3319         u8 drain_sigerr[0x1];
3320         u8 reserved_at_26[0x2];
3321         u8 pd[0x18];
3322         u8 mtu[0x3];
3323         u8 log_msg_max[0x5];
3324         u8 reserved_at_48[0x1];
3325         u8 log_rq_size[0x4];
3326         u8 log_rq_stride[0x3];
3327         u8 no_sq[0x1];
3328         u8 log_sq_size[0x4];
3329         u8 reserved_at_55[0x3];
3330         u8 ts_format[0x2];
3331         u8 reserved_at_5a[0x1];
3332         u8 rlky[0x1];
3333         u8 ulp_stateless_offload_mode[0x4];
3334         u8 counter_set_id[0x8];
3335         u8 uar_page[0x18];
3336         u8 reserved_at_80[0x8];
3337         u8 user_index[0x18];
3338         u8 reserved_at_a0[0x3];
3339         u8 log_page_size[0x5];
3340         u8 remote_qpn[0x18];
3341         struct mlx5_ifc_ads_bits primary_address_path;
3342         struct mlx5_ifc_ads_bits secondary_address_path;
3343         u8 log_ack_req_freq[0x4];
3344         u8 reserved_at_384[0x4];
3345         u8 log_sra_max[0x3];
3346         u8 reserved_at_38b[0x2];
3347         u8 retry_count[0x3];
3348         u8 rnr_retry[0x3];
3349         u8 reserved_at_393[0x1];
3350         u8 fre[0x1];
3351         u8 cur_rnr_retry[0x3];
3352         u8 cur_retry_count[0x3];
3353         u8 reserved_at_39b[0x5];
3354         u8 reserved_at_3a0[0x20];
3355         u8 reserved_at_3c0[0x8];
3356         u8 next_send_psn[0x18];
3357         u8 reserved_at_3e0[0x8];
3358         u8 cqn_snd[0x18];
3359         u8 reserved_at_400[0x8];
3360         u8 deth_sqpn[0x18];
3361         u8 reserved_at_420[0x20];
3362         u8 reserved_at_440[0x8];
3363         u8 last_acked_psn[0x18];
3364         u8 reserved_at_460[0x8];
3365         u8 ssn[0x18];
3366         u8 reserved_at_480[0x8];
3367         u8 log_rra_max[0x3];
3368         u8 reserved_at_48b[0x1];
3369         u8 atomic_mode[0x4];
3370         u8 rre[0x1];
3371         u8 rwe[0x1];
3372         u8 rae[0x1];
3373         u8 reserved_at_493[0x1];
3374         u8 page_offset[0x6];
3375         u8 reserved_at_49a[0x3];
3376         u8 cd_slave_receive[0x1];
3377         u8 cd_slave_send[0x1];
3378         u8 cd_master[0x1];
3379         u8 reserved_at_4a0[0x3];
3380         u8 min_rnr_nak[0x5];
3381         u8 next_rcv_psn[0x18];
3382         u8 reserved_at_4c0[0x8];
3383         u8 xrcd[0x18];
3384         u8 reserved_at_4e0[0x8];
3385         u8 cqn_rcv[0x18];
3386         u8 dbr_addr[0x40];
3387         u8 q_key[0x20];
3388         u8 reserved_at_560[0x5];
3389         u8 rq_type[0x3];
3390         u8 srqn_rmpn_xrqn[0x18];
3391         u8 reserved_at_580[0x8];
3392         u8 rmsn[0x18];
3393         u8 hw_sq_wqebb_counter[0x10];
3394         u8 sw_sq_wqebb_counter[0x10];
3395         u8 hw_rq_counter[0x20];
3396         u8 sw_rq_counter[0x20];
3397         u8 reserved_at_600[0x20];
3398         u8 reserved_at_620[0xf];
3399         u8 cgs[0x1];
3400         u8 cs_req[0x8];
3401         u8 cs_res[0x8];
3402         u8 dc_access_key[0x40];
3403         u8 reserved_at_680[0x3];
3404         u8 dbr_umem_valid[0x1];
3405         u8 reserved_at_684[0x9c];
3406         u8 dbr_umem_id[0x20];
3407 };
3408
3409 struct mlx5_ifc_create_qp_out_bits {
3410         u8 status[0x8];
3411         u8 reserved_at_8[0x18];
3412         u8 syndrome[0x20];
3413         u8 reserved_at_40[0x8];
3414         u8 qpn[0x18];
3415         u8 reserved_at_60[0x20];
3416 };
3417
3418 struct mlx5_ifc_qpc_extension_bits {
3419         u8 reserved_at_0[0x2];
3420         u8 mmo[0x1];
3421         u8 reserved_at_3[0x5fd];
3422 };
3423
3424 #ifdef PEDANTIC
3425 #pragma GCC diagnostic ignored "-Wpedantic"
3426 #endif
3427 struct mlx5_ifc_qpc_pas_list_bits {
3428         u8 pas[0][0x40];
3429 };
3430
3431 #ifdef PEDANTIC
3432 #pragma GCC diagnostic ignored "-Wpedantic"
3433 #endif
3434 struct mlx5_ifc_qpc_extension_and_pas_list_bits {
3435         struct mlx5_ifc_qpc_extension_bits qpc_data_extension;
3436         u8 pas[0][0x40];
3437 };
3438
3439
3440 #ifdef PEDANTIC
3441 #pragma GCC diagnostic ignored "-Wpedantic"
3442 #endif
3443 struct mlx5_ifc_create_qp_in_bits {
3444         u8 opcode[0x10];
3445         u8 uid[0x10];
3446         u8 reserved_at_20[0x10];
3447         u8 op_mod[0x10];
3448         u8 qpc_ext[0x1];
3449         u8 reserved_at_41[0x3f];
3450         u8 opt_param_mask[0x20];
3451         u8 reserved_at_a0[0x20];
3452         struct mlx5_ifc_qpc_bits qpc;
3453         u8 wq_umem_offset[0x40];
3454         u8 wq_umem_id[0x20];
3455         u8 wq_umem_valid[0x1];
3456         u8 reserved_at_861[0x1f];
3457         union {
3458                 struct mlx5_ifc_qpc_pas_list_bits qpc_pas_list;
3459                 struct mlx5_ifc_qpc_extension_and_pas_list_bits
3460                                         qpc_extension_and_pas_list;
3461         };
3462 };
3463 #ifdef PEDANTIC
3464 #pragma GCC diagnostic error "-Wpedantic"
3465 #endif
3466
3467 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3468         u8 status[0x8];
3469         u8 reserved_at_8[0x18];
3470         u8 syndrome[0x20];
3471         u8 reserved_at_40[0x40];
3472 };
3473
3474 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3475         u8 opcode[0x10];
3476         u8 uid[0x10];
3477         u8 reserved_at_20[0x10];
3478         u8 op_mod[0x10];
3479         u8 reserved_at_40[0x8];
3480         u8 qpn[0x18];
3481         u8 reserved_at_60[0x20];
3482         u8 opt_param_mask[0x20];
3483         u8 reserved_at_a0[0x20];
3484         struct mlx5_ifc_qpc_bits qpc;
3485         u8 reserved_at_800[0x80];
3486 };
3487
3488 struct mlx5_ifc_sqd2rts_qp_out_bits {
3489         u8 status[0x8];
3490         u8 reserved_at_8[0x18];
3491         u8 syndrome[0x20];
3492         u8 reserved_at_40[0x40];
3493 };
3494
3495 struct mlx5_ifc_sqd2rts_qp_in_bits {
3496         u8 opcode[0x10];
3497         u8 uid[0x10];
3498         u8 reserved_at_20[0x10];
3499         u8 op_mod[0x10];
3500         u8 reserved_at_40[0x8];
3501         u8 qpn[0x18];
3502         u8 reserved_at_60[0x20];
3503         u8 opt_param_mask[0x20];
3504         u8 reserved_at_a0[0x20];
3505         struct mlx5_ifc_qpc_bits qpc;
3506         u8 reserved_at_800[0x80];
3507 };
3508
3509 struct mlx5_ifc_rts2rts_qp_out_bits {
3510         u8 status[0x8];
3511         u8 reserved_at_8[0x18];
3512         u8 syndrome[0x20];
3513         u8 reserved_at_40[0x40];
3514 };
3515
3516 struct mlx5_ifc_rts2rts_qp_in_bits {
3517         u8 opcode[0x10];
3518         u8 uid[0x10];
3519         u8 reserved_at_20[0x10];
3520         u8 op_mod[0x10];
3521         u8 reserved_at_40[0x8];
3522         u8 qpn[0x18];
3523         u8 reserved_at_60[0x20];
3524         u8 opt_param_mask[0x20];
3525         u8 reserved_at_a0[0x20];
3526         struct mlx5_ifc_qpc_bits qpc;
3527         u8 reserved_at_800[0x80];
3528 };
3529
3530 struct mlx5_ifc_rtr2rts_qp_out_bits {
3531         u8 status[0x8];
3532         u8 reserved_at_8[0x18];
3533         u8 syndrome[0x20];
3534         u8 reserved_at_40[0x40];
3535 };
3536
3537 struct mlx5_ifc_rtr2rts_qp_in_bits {
3538         u8 opcode[0x10];
3539         u8 uid[0x10];
3540         u8 reserved_at_20[0x10];
3541         u8 op_mod[0x10];
3542         u8 reserved_at_40[0x8];
3543         u8 qpn[0x18];
3544         u8 reserved_at_60[0x20];
3545         u8 opt_param_mask[0x20];
3546         u8 reserved_at_a0[0x20];
3547         struct mlx5_ifc_qpc_bits qpc;
3548         u8 reserved_at_800[0x80];
3549 };
3550
3551 struct mlx5_ifc_rst2init_qp_out_bits {
3552         u8 status[0x8];
3553         u8 reserved_at_8[0x18];
3554         u8 syndrome[0x20];
3555         u8 reserved_at_40[0x40];
3556 };
3557
3558 struct mlx5_ifc_rst2init_qp_in_bits {
3559         u8 opcode[0x10];
3560         u8 uid[0x10];
3561         u8 reserved_at_20[0x10];
3562         u8 op_mod[0x10];
3563         u8 reserved_at_40[0x8];
3564         u8 qpn[0x18];
3565         u8 reserved_at_60[0x20];
3566         u8 opt_param_mask[0x20];
3567         u8 reserved_at_a0[0x20];
3568         struct mlx5_ifc_qpc_bits qpc;
3569         u8 reserved_at_800[0x80];
3570 };
3571
3572 struct mlx5_ifc_init2rtr_qp_out_bits {
3573         u8 status[0x8];
3574         u8 reserved_at_8[0x18];
3575         u8 syndrome[0x20];
3576         u8 reserved_at_40[0x40];
3577 };
3578
3579 struct mlx5_ifc_init2rtr_qp_in_bits {
3580         u8 opcode[0x10];
3581         u8 uid[0x10];
3582         u8 reserved_at_20[0x10];
3583         u8 op_mod[0x10];
3584         u8 reserved_at_40[0x8];
3585         u8 qpn[0x18];
3586         u8 reserved_at_60[0x20];
3587         u8 opt_param_mask[0x20];
3588         u8 reserved_at_a0[0x20];
3589         struct mlx5_ifc_qpc_bits qpc;
3590         u8 reserved_at_800[0x80];
3591 };
3592
3593 struct mlx5_ifc_init2init_qp_out_bits {
3594         u8 status[0x8];
3595         u8 reserved_at_8[0x18];
3596         u8 syndrome[0x20];
3597         u8 reserved_at_40[0x40];
3598 };
3599
3600 struct mlx5_ifc_init2init_qp_in_bits {
3601         u8 opcode[0x10];
3602         u8 uid[0x10];
3603         u8 reserved_at_20[0x10];
3604         u8 op_mod[0x10];
3605         u8 reserved_at_40[0x8];
3606         u8 qpn[0x18];
3607         u8 reserved_at_60[0x20];
3608         u8 opt_param_mask[0x20];
3609         u8 reserved_at_a0[0x20];
3610         struct mlx5_ifc_qpc_bits qpc;
3611         u8 reserved_at_800[0x80];
3612 };
3613
3614 struct mlx5_ifc_dealloc_pd_out_bits {
3615         u8 status[0x8];
3616         u8 reserved_0[0x18];
3617         u8 syndrome[0x20];
3618         u8 reserved_1[0x40];
3619 };
3620
3621 struct mlx5_ifc_dealloc_pd_in_bits {
3622         u8 opcode[0x10];
3623         u8 reserved_0[0x10];
3624         u8 reserved_1[0x10];
3625         u8 op_mod[0x10];
3626         u8 reserved_2[0x8];
3627         u8 pd[0x18];
3628         u8 reserved_3[0x20];
3629 };
3630
3631 struct mlx5_ifc_alloc_pd_out_bits {
3632         u8 status[0x8];
3633         u8 reserved_0[0x18];
3634         u8 syndrome[0x20];
3635         u8 reserved_1[0x8];
3636         u8 pd[0x18];
3637         u8 reserved_2[0x20];
3638 };
3639
3640 struct mlx5_ifc_alloc_pd_in_bits {
3641         u8 opcode[0x10];
3642         u8 reserved_0[0x10];
3643         u8 reserved_1[0x10];
3644         u8 op_mod[0x10];
3645         u8 reserved_2[0x40];
3646 };
3647
3648 #ifdef PEDANTIC
3649 #pragma GCC diagnostic ignored "-Wpedantic"
3650 #endif
3651 struct mlx5_ifc_query_qp_out_bits {
3652         u8 status[0x8];
3653         u8 reserved_at_8[0x18];
3654         u8 syndrome[0x20];
3655         u8 reserved_at_40[0x40];
3656         u8 opt_param_mask[0x20];
3657         u8 reserved_at_a0[0x20];
3658         struct mlx5_ifc_qpc_bits qpc;
3659         u8 reserved_at_800[0x80];
3660         u8 pas[0][0x40];
3661 };
3662 #ifdef PEDANTIC
3663 #pragma GCC diagnostic error "-Wpedantic"
3664 #endif
3665
3666 struct mlx5_ifc_query_qp_in_bits {
3667         u8 opcode[0x10];
3668         u8 reserved_at_10[0x10];
3669         u8 reserved_at_20[0x10];
3670         u8 op_mod[0x10];
3671         u8 reserved_at_40[0x8];
3672         u8 qpn[0x18];
3673         u8 reserved_at_60[0x20];
3674 };
3675
3676 enum {
3677         MLX5_DATA_RATE = 0x0,
3678         MLX5_WQE_RATE = 0x1,
3679 };
3680
3681 struct mlx5_ifc_set_pp_rate_limit_context_bits {
3682         u8 rate_limit[0x20];
3683         u8 burst_upper_bound[0x20];
3684         u8 reserved_at_40[0xC];
3685         u8 rate_mode[0x4];
3686         u8 typical_packet_size[0x10];
3687         u8 reserved_at_60[0x120];
3688 };
3689
3690 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u
3691
3692 #ifdef PEDANTIC
3693 #pragma GCC diagnostic ignored "-Wpedantic"
3694 #endif
3695 struct mlx5_ifc_access_register_out_bits {
3696         u8 status[0x8];
3697         u8 reserved_at_8[0x18];
3698         u8 syndrome[0x20];
3699         u8 reserved_at_40[0x40];
3700         u8 register_data[0][0x20];
3701 };
3702
3703 struct mlx5_ifc_access_register_in_bits {
3704         u8 opcode[0x10];
3705         u8 reserved_at_10[0x10];
3706         u8 reserved_at_20[0x10];
3707         u8 op_mod[0x10];
3708         u8 reserved_at_40[0x10];
3709         u8 register_id[0x10];
3710         u8 argument[0x20];
3711         u8 register_data[0][0x20];
3712 };
3713 #ifdef PEDANTIC
3714 #pragma GCC diagnostic error "-Wpedantic"
3715 #endif
3716
3717 enum {
3718         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
3719         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
3720 };
3721
3722 enum {
3723         MLX5_REGISTER_ID_MTUTC  = 0x9055,
3724         MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002,
3725         MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003,
3726         MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004,
3727         MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005,
3728 };
3729
3730 struct mlx5_ifc_register_mtutc_bits {
3731         u8 time_stamp_mode[0x2];
3732         u8 time_stamp_state[0x2];
3733         u8 reserved_at_4[0x18];
3734         u8 operation[0x4];
3735         u8 freq_adjustment[0x20];
3736         u8 reserved_at_40[0x40];
3737         u8 utc_sec[0x20];
3738         u8 utc_nsec[0x20];
3739         u8 time_adjustment[0x20];
3740 };
3741
3742 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0
3743 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1
3744
3745 struct mlx5_ifc_crypto_operational_register_bits {
3746         u8 wrapped_crypto_operational[0x1];
3747         u8 reserved_at_1[0x1b];
3748         u8 kek_size[0x4];
3749         u8 reserved_at_20[0x20];
3750         u8 credential[0x140];
3751         u8 kek[0x100];
3752         u8 reserved_at_280[0x180];
3753 };
3754
3755 struct mlx5_ifc_crypto_commissioning_register_bits {
3756         u8 token[0x1]; /* TODO: add size after PRM update */
3757 };
3758
3759 struct mlx5_ifc_import_kek_handle_register_bits {
3760         struct mlx5_ifc_crypto_login_bits crypto_login_object;
3761         struct mlx5_ifc_import_kek_bits import_kek_object;
3762         u8 reserved_at_200[0x4];
3763         u8 write_operation[0x4];
3764         u8 import_kek_id[0x18];
3765         u8 reserved_at_220[0xe0];
3766 };
3767
3768 struct mlx5_ifc_credential_handle_register_bits {
3769         struct mlx5_ifc_crypto_login_bits crypto_login_object;
3770         struct mlx5_ifc_credential_bits credential_object;
3771         u8 reserved_at_200[0x4];
3772         u8 write_operation[0x4];
3773         u8 credential_id[0x18];
3774         u8 reserved_at_220[0xe0];
3775 };
3776
3777 enum {
3778         MLX5_REGISTER_ADD_OPERATION = 0x1,
3779         MLX5_REGISTER_DELETE_OPERATION = 0x2,
3780 };
3781
3782 struct mlx5_ifc_parse_graph_arc_bits {
3783         u8 start_inner_tunnel[0x1];
3784         u8 reserved_at_1[0x7];
3785         u8 arc_parse_graph_node[0x8];
3786         u8 compare_condition_value[0x10];
3787         u8 parse_graph_node_handle[0x20];
3788         u8 reserved_at_40[0x40];
3789 };
3790
3791 struct mlx5_ifc_parse_graph_flow_match_sample_bits {
3792         u8 flow_match_sample_en[0x1];
3793         u8 reserved_at_1[0x3];
3794         u8 flow_match_sample_offset_mode[0x4];
3795         u8 reserved_at_5[0x8];
3796         u8 flow_match_sample_field_offset[0x10];
3797         u8 reserved_at_32[0x4];
3798         u8 flow_match_sample_field_offset_shift[0x4];
3799         u8 flow_match_sample_field_base_offset[0x8];
3800         u8 reserved_at_48[0xd];
3801         u8 flow_match_sample_tunnel_mode[0x3];
3802         u8 flow_match_sample_field_offset_mask[0x20];
3803         u8 flow_match_sample_field_id[0x20];
3804 };
3805
3806 struct mlx5_ifc_parse_graph_flex_bits {
3807         u8 modify_field_select[0x40];
3808         u8 reserved_at_64[0x20];
3809         u8 header_length_base_value[0x10];
3810         u8 reserved_at_112[0x4];
3811         u8 header_length_field_shift[0x4];
3812         u8 reserved_at_120[0x4];
3813         u8 header_length_mode[0x4];
3814         u8 header_length_field_offset[0x10];
3815         u8 next_header_field_offset[0x10];
3816         u8 reserved_at_160[0x1b];
3817         u8 next_header_field_size[0x5];
3818         u8 header_length_field_mask[0x20];
3819         u8 reserved_at_224[0x20];
3820         struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8];
3821         struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8];
3822         struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8];
3823 };
3824
3825 struct mlx5_ifc_create_flex_parser_in_bits {
3826         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3827         struct mlx5_ifc_parse_graph_flex_bits flex;
3828 };
3829
3830 struct mlx5_ifc_create_flex_parser_out_bits {
3831         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3832         struct mlx5_ifc_parse_graph_flex_bits flex;
3833 };
3834
3835 struct mlx5_ifc_parse_graph_flex_out_bits {
3836         u8 status[0x8];
3837         u8 reserved_at_8[0x18];
3838         u8 syndrome[0x20];
3839         u8 reserved_at_40[0x40];
3840         struct mlx5_ifc_parse_graph_flex_bits capability;
3841 };
3842
3843 struct regexp_params_field_select_bits {
3844         u8 reserved_at_0[0x1d];
3845         u8 rof_mkey[0x1];
3846         u8 stop_engine[0x1];
3847         u8 reserved_at_1f[0x1];
3848 };
3849
3850 struct mlx5_ifc_regexp_params_bits {
3851         u8 reserved_at_0[0x1f];
3852         u8 stop_engine[0x1];
3853         u8 reserved_at_20[0x60];
3854         u8 rof_mkey[0x20];
3855         u8 rof_size[0x20];
3856         u8 rof_mkey_va[0x40];
3857         u8 reserved_at_100[0x80];
3858 };
3859
3860 struct mlx5_ifc_set_regexp_params_in_bits {
3861         u8 opcode[0x10];
3862         u8 uid[0x10];
3863         u8 reserved_at_20[0x10];
3864         u8 op_mod[0x10];
3865         u8 reserved_at_40[0x18];
3866         u8 engine_id[0x8];
3867         struct regexp_params_field_select_bits field_select;
3868         struct mlx5_ifc_regexp_params_bits regexp_params;
3869 };
3870
3871 struct mlx5_ifc_set_regexp_params_out_bits {
3872         u8 status[0x8];
3873         u8 reserved_at_8[0x18];
3874         u8 syndrome[0x20];
3875         u8 reserved_at_18[0x40];
3876 };
3877
3878 struct mlx5_ifc_query_regexp_params_in_bits {
3879         u8 opcode[0x10];
3880         u8 uid[0x10];
3881         u8 reserved_at_20[0x10];
3882         u8 op_mod[0x10];
3883         u8 reserved_at_40[0x18];
3884         u8 engine_id[0x8];
3885         u8 reserved[0x20];
3886 };
3887
3888 struct mlx5_ifc_query_regexp_params_out_bits {
3889         u8 status[0x8];
3890         u8 reserved_at_8[0x18];
3891         u8 syndrome[0x20];
3892         u8 reserved[0x40];
3893         struct mlx5_ifc_regexp_params_bits regexp_params;
3894 };
3895
3896 struct mlx5_ifc_set_regexp_register_in_bits {
3897         u8 opcode[0x10];
3898         u8 uid[0x10];
3899         u8 reserved_at_20[0x10];
3900         u8 op_mod[0x10];
3901         u8 reserved_at_40[0x18];
3902         u8 engine_id[0x8];
3903         u8 register_address[0x20];
3904         u8 register_data[0x20];
3905         u8 reserved[0x60];
3906 };
3907
3908 struct mlx5_ifc_set_regexp_register_out_bits {
3909         u8 status[0x8];
3910         u8 reserved_at_8[0x18];
3911         u8 syndrome[0x20];
3912         u8 reserved[0x40];
3913 };
3914
3915 struct mlx5_ifc_query_regexp_register_in_bits {
3916         u8 opcode[0x10];
3917         u8 uid[0x10];
3918         u8 reserved_at_20[0x10];
3919         u8 op_mod[0x10];
3920         u8 reserved_at_40[0x18];
3921         u8 engine_id[0x8];
3922         u8 register_address[0x20];
3923 };
3924
3925 struct mlx5_ifc_query_regexp_register_out_bits {
3926         u8 status[0x8];
3927         u8 reserved_at_8[0x18];
3928         u8 syndrome[0x20];
3929         u8 reserved[0x20];
3930         u8 register_data[0x20];
3931 };
3932
3933 /* Queue counters. */
3934 struct mlx5_ifc_alloc_q_counter_out_bits {
3935         u8 status[0x8];
3936         u8 reserved_at_8[0x18];
3937         u8 syndrome[0x20];
3938         u8 reserved_at_40[0x18];
3939         u8 counter_set_id[0x8];
3940         u8 reserved_at_60[0x20];
3941 };
3942
3943 struct mlx5_ifc_alloc_q_counter_in_bits {
3944         u8 opcode[0x10];
3945         u8 uid[0x10];
3946         u8 reserved_at_20[0x10];
3947         u8 op_mod[0x10];
3948         u8 reserved_at_40[0x40];
3949 };
3950
3951 struct mlx5_ifc_query_q_counter_out_bits {
3952         u8 status[0x8];
3953         u8 reserved_at_8[0x18];
3954         u8 syndrome[0x20];
3955         u8 reserved_at_40[0x40];
3956         u8 rx_write_requests[0x20];
3957         u8 reserved_at_a0[0x20];
3958         u8 rx_read_requests[0x20];
3959         u8 reserved_at_e0[0x20];
3960         u8 rx_atomic_requests[0x20];
3961         u8 reserved_at_120[0x20];
3962         u8 rx_dct_connect[0x20];
3963         u8 reserved_at_160[0x20];
3964         u8 out_of_buffer[0x20];
3965         u8 reserved_at_1a0[0x20];
3966         u8 out_of_sequence[0x20];
3967         u8 reserved_at_1e0[0x20];
3968         u8 duplicate_request[0x20];
3969         u8 reserved_at_220[0x20];
3970         u8 rnr_nak_retry_err[0x20];
3971         u8 reserved_at_260[0x20];
3972         u8 packet_seq_err[0x20];
3973         u8 reserved_at_2a0[0x20];
3974         u8 implied_nak_seq_err[0x20];
3975         u8 reserved_at_2e0[0x20];
3976         u8 local_ack_timeout_err[0x20];
3977         u8 reserved_at_320[0xa0];
3978         u8 resp_local_length_error[0x20];
3979         u8 req_local_length_error[0x20];
3980         u8 resp_local_qp_error[0x20];
3981         u8 local_operation_error[0x20];
3982         u8 resp_local_protection[0x20];
3983         u8 req_local_protection[0x20];
3984         u8 resp_cqe_error[0x20];
3985         u8 req_cqe_error[0x20];
3986         u8 req_mw_binding[0x20];
3987         u8 req_bad_response[0x20];
3988         u8 req_remote_invalid_request[0x20];
3989         u8 resp_remote_invalid_request[0x20];
3990         u8 req_remote_access_errors[0x20];
3991         u8 resp_remote_access_errors[0x20];
3992         u8 req_remote_operation_errors[0x20];
3993         u8 req_transport_retries_exceeded[0x20];
3994         u8 cq_overflow[0x20];
3995         u8 resp_cqe_flush_error[0x20];
3996         u8 req_cqe_flush_error[0x20];
3997         u8 reserved_at_620[0x1e0];
3998 };
3999
4000 struct mlx5_ifc_query_q_counter_in_bits {
4001         u8 opcode[0x10];
4002         u8 uid[0x10];
4003         u8 reserved_at_20[0x10];
4004         u8 op_mod[0x10];
4005         u8 reserved_at_40[0x80];
4006         u8 clear[0x1];
4007         u8 reserved_at_c1[0x1f];
4008         u8 reserved_at_e0[0x18];
4009         u8 counter_set_id[0x8];
4010 };
4011
4012 /* CQE format mask. */
4013 #define MLX5E_CQE_FORMAT_MASK 0xc
4014
4015 /* MPW opcode. */
4016 #define MLX5_OPC_MOD_MPW 0x01
4017
4018 /* Compressed Rx CQE structure. */
4019 struct mlx5_mini_cqe8 {
4020         union {
4021                 uint32_t rx_hash_result;
4022                 struct {
4023                         union {
4024                                 uint16_t checksum;
4025                                 uint16_t flow_tag_high;
4026                                 struct {
4027                                         uint8_t reserved;
4028                                         uint8_t hdr_type;
4029                                 };
4030                         };
4031                         uint16_t stride_idx;
4032                 };
4033                 struct {
4034                         uint16_t wqe_counter;
4035                         uint8_t  s_wqe_opcode;
4036                         uint8_t  reserved;
4037                 } s_wqe_info;
4038         };
4039         union {
4040                 uint32_t byte_cnt_flow;
4041                 uint32_t byte_cnt;
4042         };
4043 };
4044
4045 /* Mini CQE responder format. */
4046 enum {
4047         MLX5_CQE_RESP_FORMAT_HASH = 0x0,
4048         MLX5_CQE_RESP_FORMAT_CSUM = 0x1,
4049         MLX5_CQE_RESP_FORMAT_FTAG_STRIDX = 0x2,
4050         MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3,
4051         MLX5_CQE_RESP_FORMAT_L34H_STRIDX = 0x4,
4052 };
4053
4054 /* srTCM PRM flow meter parameters. */
4055 enum {
4056         MLX5_FLOW_COLOR_RED = 0,
4057         MLX5_FLOW_COLOR_YELLOW,
4058         MLX5_FLOW_COLOR_GREEN,
4059         MLX5_FLOW_COLOR_UNDEFINED,
4060 };
4061
4062 /* Maximum value of srTCM & trTCM metering parameters. */
4063 #define MLX5_SRTCM_XBS_MAX (0xFF * (1ULL << 0x1F))
4064 #define MLX5_SRTCM_XIR_MAX (8 * (1ULL << 30) * 0xFF)
4065
4066 /* The bits meter color use. */
4067 #define MLX5_MTR_COLOR_BITS 8
4068
4069 /* The bit size of one register. */
4070 #define MLX5_REG_BITS 32
4071
4072 /* Idle bits for non-color usage in color register. */
4073 #define MLX5_MTR_IDLE_BITS_IN_COLOR_REG (MLX5_REG_BITS - MLX5_MTR_COLOR_BITS)
4074
4075 /* Length mode of dynamic flex parser graph node. */
4076 enum mlx5_parse_graph_node_len_mode {
4077         MLX5_GRAPH_NODE_LEN_FIXED = 0x0,
4078         MLX5_GRAPH_NODE_LEN_FIELD = 0x1,
4079         MLX5_GRAPH_NODE_LEN_BITMASK = 0x2,
4080 };
4081
4082 /* Offset mode of the samples of flex parser. */
4083 enum mlx5_parse_graph_flow_match_sample_offset_mode {
4084         MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0,
4085         MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1,
4086         MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2,
4087 };
4088
4089 enum mlx5_parse_graph_flow_match_sample_tunnel_mode {
4090         MLX5_GRAPH_SAMPLE_TUNNEL_OUTER = 0x0,
4091         MLX5_GRAPH_SAMPLE_TUNNEL_INNER = 0x1,
4092         MLX5_GRAPH_SAMPLE_TUNNEL_FIRST = 0x2
4093 };
4094
4095 /* Node index for an input / output arc of the flex parser graph. */
4096 enum mlx5_parse_graph_arc_node_index {
4097         MLX5_GRAPH_ARC_NODE_NULL = 0x0,
4098         MLX5_GRAPH_ARC_NODE_HEAD = 0x1,
4099         MLX5_GRAPH_ARC_NODE_MAC = 0x2,
4100         MLX5_GRAPH_ARC_NODE_IP = 0x3,
4101         MLX5_GRAPH_ARC_NODE_GRE = 0x4,
4102         MLX5_GRAPH_ARC_NODE_UDP = 0x5,
4103         MLX5_GRAPH_ARC_NODE_MPLS = 0x6,
4104         MLX5_GRAPH_ARC_NODE_TCP = 0x7,
4105         MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8,
4106         MLX5_GRAPH_ARC_NODE_GENEVE = 0x9,
4107         MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa,
4108         MLX5_GRAPH_ARC_NODE_IPV4 = 0xb,
4109         MLX5_GRAPH_ARC_NODE_IPV6 = 0xc,
4110         MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f,
4111 };
4112
4113 #define MLX5_PARSE_GRAPH_FLOW_SAMPLE_MAX 8
4114 #define MLX5_PARSE_GRAPH_IN_ARC_MAX 8
4115 #define MLX5_PARSE_GRAPH_OUT_ARC_MAX 8
4116
4117 /**
4118  * Convert a user mark to flow mark.
4119  *
4120  * @param val
4121  *   Mark value to convert.
4122  *
4123  * @return
4124  *   Converted mark value.
4125  */
4126 static inline uint32_t
4127 mlx5_flow_mark_set(uint32_t val)
4128 {
4129         uint32_t ret;
4130
4131         /*
4132          * Add one to the user value to differentiate un-marked flows from
4133          * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
4134          * remains untouched.
4135          */
4136         if (val != MLX5_FLOW_MARK_DEFAULT)
4137                 ++val;
4138 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
4139         /*
4140          * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
4141          * word, byte-swapped by the kernel on little-endian systems. In this
4142          * case, left-shifting the resulting big-endian value ensures the
4143          * least significant 24 bits are retained when converting it back.
4144          */
4145         ret = rte_cpu_to_be_32(val) >> 8;
4146 #else
4147         ret = val;
4148 #endif
4149         return ret;
4150 }
4151
4152 /**
4153  * Convert a mark to user mark.
4154  *
4155  * @param val
4156  *   Mark value to convert.
4157  *
4158  * @return
4159  *   Converted mark value.
4160  */
4161 static inline uint32_t
4162 mlx5_flow_mark_get(uint32_t val)
4163 {
4164         /*
4165          * Subtract one from the retrieved value. It was added by
4166          * mlx5_flow_mark_set() to distinguish unmarked flows.
4167          */
4168 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
4169         return (val >> 8) - 1;
4170 #else
4171         return val - 1;
4172 #endif
4173 }
4174
4175 /**
4176  * Convert a timestamp format to configure settings in the queue context.
4177  *
4178  * @param val
4179  *   timestamp format supported by the queue.
4180  *
4181  * @return
4182  *   Converted timestamp format settings.
4183  */
4184 static inline uint32_t
4185 mlx5_ts_format_conv(uint32_t ts_format)
4186 {
4187         return ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ?
4188                         MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
4189                         MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
4190 }
4191
4192 #endif /* RTE_PMD_MLX5_PRM_H_ */