1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2016 6WIND S.A.
3 * Copyright 2016 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_PRM_H_
7 #define RTE_PMD_MLX5_PRM_H_
11 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
13 #pragma GCC diagnostic ignored "-Wpedantic"
15 #include <infiniband/mlx5dv.h>
17 #pragma GCC diagnostic error "-Wpedantic"
21 #include <rte_byteorder.h>
23 #include "mlx5_autoconf.h"
25 /* RSS hash key size. */
26 #define MLX5_RSS_HASH_KEY_LEN 40
28 /* Get CQE owner bit. */
29 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
32 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
35 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
37 /* Get CQE solicited event. */
38 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
40 /* Invalidate a CQE. */
41 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
43 /* WQE Segment sizes in bytes. */
44 #define MLX5_WSEG_SIZE 16u
45 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
46 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
47 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
49 /* WQE/WQEBB size in bytes. */
50 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
53 * Max size of a WQE session.
54 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
55 * the WQE size field in Control Segment is 6 bits wide.
57 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
60 * Default minimum number of Tx queues for inlining packets.
61 * If there are less queues as specified we assume we have
62 * no enough CPU resources (cycles) to perform inlining,
63 * the PCIe throughput is not supposed as bottleneck and
64 * inlining is disabled.
66 #define MLX5_INLINE_MAX_TXQS 8u
67 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
70 * Default packet length threshold to be inlined with
71 * enhanced MPW. If packet length exceeds the threshold
72 * the data are not inlined. Should be aligned in WQEBB
73 * boundary with accounting the title Control and Ethernet
76 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
77 MLX5_DSEG_MIN_INLINE_SIZE)
79 * Maximal inline data length sent with enhanced MPW.
80 * Is based on maximal WQE size.
82 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
83 MLX5_WQE_CSEG_SIZE - \
84 MLX5_WQE_ESEG_SIZE - \
85 MLX5_WQE_DSEG_SIZE + \
86 MLX5_DSEG_MIN_INLINE_SIZE)
88 * Minimal amount of packets to be sent with EMPW.
89 * This limits the minimal required size of sent EMPW.
90 * If there are no enough resources to built minimal
91 * EMPW the sending loop exits.
93 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
95 * Maximal amount of packets to be sent with EMPW.
96 * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
97 * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
98 * without CQE generation request, being multiplied by
99 * MLX5_TX_COMP_MAX_CQE it may cause significant latency
100 * in tx burst routine at the moment of freeing multiple mbufs.
102 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
103 #define MLX5_MPW_MAX_PACKETS 6
104 #define MLX5_MPW_INLINE_MAX_PACKETS 2
107 * Default packet length threshold to be inlined with
108 * ordinary SEND. Inlining saves the MR key search
109 * and extra PCIe data fetch transaction, but eats the
112 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
113 MLX5_ESEG_MIN_INLINE_SIZE - \
114 MLX5_WQE_CSEG_SIZE - \
115 MLX5_WQE_ESEG_SIZE - \
118 * Maximal inline data length sent with ordinary SEND.
119 * Is based on maximal WQE size.
121 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
122 MLX5_WQE_CSEG_SIZE - \
123 MLX5_WQE_ESEG_SIZE - \
124 MLX5_WQE_DSEG_SIZE + \
125 MLX5_ESEG_MIN_INLINE_SIZE)
127 /* Missed in mlv5dv.h, should define here. */
128 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
130 /* CQE value to inform that VLAN is stripped. */
131 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
134 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
137 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
140 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
143 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
146 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
148 /* IP is fragmented. */
149 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
151 /* L2 header is valid. */
152 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
154 /* L3 header is valid. */
155 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
157 /* L4 header is valid. */
158 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
160 /* Outer packet, 0 IPv4, 1 IPv6. */
161 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
163 /* Tunnel packet bit in the CQE. */
164 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
166 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
167 #define MLX5_CQE_LRO_PUSH_MASK 0x40
169 /* Mask for L4 type in the CQE hdr_type_etc field. */
170 #define MLX5_CQE_L4_TYPE_MASK 0x70
172 /* The bit index of L4 type in CQE hdr_type_etc field. */
173 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
175 /* L4 type to indicate TCP packet without acknowledgment. */
176 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
178 /* L4 type to indicate TCP packet with acknowledgment. */
179 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
181 /* Inner L3 checksum offload (Tunneled packets only). */
182 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
184 /* Inner L4 checksum offload (Tunneled packets only). */
185 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
187 /* Outer L4 type is TCP. */
188 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5)
190 /* Outer L4 type is UDP. */
191 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5)
193 /* Outer L3 type is IPV4. */
194 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
196 /* Outer L3 type is IPV6. */
197 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
199 /* Inner L4 type is TCP. */
200 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
202 /* Inner L4 type is UDP. */
203 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
205 /* Inner L3 type is IPV4. */
206 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
208 /* Inner L3 type is IPV6. */
209 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
211 /* VLAN insertion flag. */
212 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
214 /* Data inline segment flag. */
215 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
217 /* Is flow mark valid. */
218 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
219 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
221 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
224 /* INVALID is used by packets matching no flow rules. */
225 #define MLX5_FLOW_MARK_INVALID 0
227 /* Maximum allowed value to mark a packet. */
228 #define MLX5_FLOW_MARK_MAX 0xfffff0
230 /* Default mark value used when none is provided. */
231 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
233 /* Default mark mask for metadata legacy mode. */
234 #define MLX5_FLOW_MARK_MASK 0xffffff
236 /* Maximum number of DS in WQE. Limited by 6-bit field. */
237 #define MLX5_DSEG_MAX 63
239 /* The completion mode offset in the WQE control segment line 2. */
240 #define MLX5_COMP_MODE_OFFSET 2
242 /* Amount of data bytes in minimal inline data segment. */
243 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
245 /* Amount of data bytes in minimal inline eth segment. */
246 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
248 /* Amount of data bytes after eth data segment. */
249 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
251 /* The maximum log value of segments per RQ WQE. */
252 #define MLX5_MAX_LOG_RQ_SEGS 5u
254 /* The alignment needed for WQ buffer. */
255 #define MLX5_WQE_BUF_ALIGNMENT 512
257 /* Completion mode. */
258 enum mlx5_completion_mode {
259 MLX5_COMP_ONLY_ERR = 0x0,
260 MLX5_COMP_ONLY_FIRST_ERR = 0x1,
261 MLX5_COMP_ALWAYS = 0x2,
262 MLX5_COMP_CQE_AND_EQE = 0x3,
269 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
272 /* WQE Control segment. */
273 struct mlx5_wqe_cseg {
278 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
280 /* Header of data segment. Minimal size Data Segment */
281 struct mlx5_wqe_dseg {
284 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
292 /* Subset of struct WQE Ethernet Segment. */
293 struct mlx5_wqe_eseg {
301 uint16_t inline_hdr_sz;
303 uint16_t inline_data;
310 uint32_t flow_metadata;
316 /* The title WQEBB, header of WQE. */
319 struct mlx5_wqe_cseg cseg;
322 struct mlx5_wqe_eseg eseg;
324 struct mlx5_wqe_dseg dseg[2];
325 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
329 /* WQE for Multi-Packet RQ. */
330 struct mlx5_wqe_mprq {
331 struct mlx5_wqe_srq_next_seg next_seg;
332 struct mlx5_wqe_data_seg dseg;
335 #define MLX5_MPRQ_LEN_MASK 0x000ffff
336 #define MLX5_MPRQ_LEN_SHIFT 0
337 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
338 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
339 #define MLX5_MPRQ_FILLER_MASK 0x80000000
340 #define MLX5_MPRQ_FILLER_SHIFT 31
342 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
344 /* CQ element structure - should be equal to the cache line size */
346 #if (RTE_CACHE_LINE_SIZE == 128)
352 uint8_t lro_tcppsh_abort_dupack;
354 uint16_t lro_tcp_win;
355 uint32_t lro_ack_seq_num;
356 uint32_t rx_hash_res;
357 uint8_t rx_hash_type;
361 uint16_t hdr_type_etc;
365 uint32_t flow_table_metadata;
369 uint32_t sop_drop_qpn;
370 uint16_t wqe_counter;
375 /* Adding direct verbs to data-path. */
377 /* CQ sequence number mask. */
378 #define MLX5_CQ_SQN_MASK 0x3
380 /* CQ sequence number index. */
381 #define MLX5_CQ_SQN_OFFSET 28
383 /* CQ doorbell index mask. */
384 #define MLX5_CI_MASK 0xffffff
386 /* CQ doorbell offset. */
387 #define MLX5_CQ_ARM_DB 1
389 /* CQ doorbell offset*/
390 #define MLX5_CQ_DOORBELL 0x20
392 /* CQE format value. */
393 #define MLX5_COMPRESSED 0x3
395 /* Action type of header modification. */
397 MLX5_MODIFICATION_TYPE_SET = 0x1,
398 MLX5_MODIFICATION_TYPE_ADD = 0x2,
399 MLX5_MODIFICATION_TYPE_COPY = 0x3,
402 /* The field of packet to be modified. */
403 enum mlx5_modification_field {
404 MLX5_MODI_OUT_NONE = -1,
405 MLX5_MODI_OUT_SMAC_47_16 = 1,
406 MLX5_MODI_OUT_SMAC_15_0,
407 MLX5_MODI_OUT_ETHERTYPE,
408 MLX5_MODI_OUT_DMAC_47_16,
409 MLX5_MODI_OUT_DMAC_15_0,
410 MLX5_MODI_OUT_IP_DSCP,
411 MLX5_MODI_OUT_TCP_FLAGS,
412 MLX5_MODI_OUT_TCP_SPORT,
413 MLX5_MODI_OUT_TCP_DPORT,
414 MLX5_MODI_OUT_IPV4_TTL,
415 MLX5_MODI_OUT_UDP_SPORT,
416 MLX5_MODI_OUT_UDP_DPORT,
417 MLX5_MODI_OUT_SIPV6_127_96,
418 MLX5_MODI_OUT_SIPV6_95_64,
419 MLX5_MODI_OUT_SIPV6_63_32,
420 MLX5_MODI_OUT_SIPV6_31_0,
421 MLX5_MODI_OUT_DIPV6_127_96,
422 MLX5_MODI_OUT_DIPV6_95_64,
423 MLX5_MODI_OUT_DIPV6_63_32,
424 MLX5_MODI_OUT_DIPV6_31_0,
427 MLX5_MODI_OUT_FIRST_VID,
428 MLX5_MODI_IN_SMAC_47_16 = 0x31,
429 MLX5_MODI_IN_SMAC_15_0,
430 MLX5_MODI_IN_ETHERTYPE,
431 MLX5_MODI_IN_DMAC_47_16,
432 MLX5_MODI_IN_DMAC_15_0,
433 MLX5_MODI_IN_IP_DSCP,
434 MLX5_MODI_IN_TCP_FLAGS,
435 MLX5_MODI_IN_TCP_SPORT,
436 MLX5_MODI_IN_TCP_DPORT,
437 MLX5_MODI_IN_IPV4_TTL,
438 MLX5_MODI_IN_UDP_SPORT,
439 MLX5_MODI_IN_UDP_DPORT,
440 MLX5_MODI_IN_SIPV6_127_96,
441 MLX5_MODI_IN_SIPV6_95_64,
442 MLX5_MODI_IN_SIPV6_63_32,
443 MLX5_MODI_IN_SIPV6_31_0,
444 MLX5_MODI_IN_DIPV6_127_96,
445 MLX5_MODI_IN_DIPV6_95_64,
446 MLX5_MODI_IN_DIPV6_63_32,
447 MLX5_MODI_IN_DIPV6_31_0,
450 MLX5_MODI_OUT_IPV6_HOPLIMIT,
451 MLX5_MODI_IN_IPV6_HOPLIMIT,
452 MLX5_MODI_META_DATA_REG_A,
453 MLX5_MODI_META_DATA_REG_B = 0x50,
454 MLX5_MODI_META_REG_C_0,
455 MLX5_MODI_META_REG_C_1,
456 MLX5_MODI_META_REG_C_2,
457 MLX5_MODI_META_REG_C_3,
458 MLX5_MODI_META_REG_C_4,
459 MLX5_MODI_META_REG_C_5,
460 MLX5_MODI_META_REG_C_6,
461 MLX5_MODI_META_REG_C_7,
462 MLX5_MODI_OUT_TCP_SEQ_NUM,
463 MLX5_MODI_IN_TCP_SEQ_NUM,
464 MLX5_MODI_OUT_TCP_ACK_NUM,
465 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
468 /* Total number of metadata reg_c's. */
469 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1)
485 /* Modification sub command. */
486 struct mlx5_modification_cmd {
490 unsigned int length:5;
491 unsigned int rsvd0:3;
492 unsigned int offset:5;
493 unsigned int rsvd1:3;
494 unsigned int field:12;
495 unsigned int action_type:4;
502 unsigned int rsvd2:8;
503 unsigned int dst_offset:5;
504 unsigned int rsvd3:3;
505 unsigned int dst_field:12;
506 unsigned int rsvd4:4;
511 typedef uint32_t u32;
512 typedef uint16_t u16;
515 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
516 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
517 #define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \
518 (&(__mlx5_nullp(typ)->fld)))
519 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
520 (__mlx5_bit_off(typ, fld) & 0x1f))
521 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
522 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
523 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
524 __mlx5_dw_bit_off(typ, fld))
525 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
526 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
527 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
528 (__mlx5_bit_off(typ, fld) & 0xf))
529 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
530 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \
531 __mlx5_16_bit_off(typ, fld))
532 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
533 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
534 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
535 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
537 /* insert a value to a struct */
538 #define MLX5_SET(typ, p, fld, v) \
541 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
542 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
543 __mlx5_dw_off(typ, fld))) & \
544 (~__mlx5_dw_mask(typ, fld))) | \
545 (((_v) & __mlx5_mask(typ, fld)) << \
546 __mlx5_dw_bit_off(typ, fld))); \
549 #define MLX5_SET64(typ, p, fld, v) \
551 assert(__mlx5_bit_sz(typ, fld) == 64); \
552 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = \
553 rte_cpu_to_be_64(v); \
556 #define MLX5_SET16(typ, p, fld, v) \
559 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
560 rte_cpu_to_be_16((rte_be_to_cpu_16(*((__be16 *)(p) + \
561 __mlx5_16_off(typ, fld))) & \
562 (~__mlx5_16_mask(typ, fld))) | \
563 (((_v) & __mlx5_mask16(typ, fld)) << \
564 __mlx5_16_bit_off(typ, fld))); \
567 #define MLX5_GET(typ, p, fld) \
568 ((rte_be_to_cpu_32(*((__be32 *)(p) +\
569 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
570 __mlx5_mask(typ, fld))
571 #define MLX5_GET16(typ, p, fld) \
572 ((rte_be_to_cpu_16(*((__be16 *)(p) + \
573 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
574 __mlx5_mask16(typ, fld))
575 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((__be64 *)(p) + \
576 __mlx5_64_off(typ, fld)))
577 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
579 struct mlx5_ifc_fte_match_set_misc_bits {
580 u8 gre_c_present[0x1];
581 u8 reserved_at_1[0x1];
582 u8 gre_k_present[0x1];
583 u8 gre_s_present[0x1];
584 u8 source_vhci_port[0x4];
586 u8 reserved_at_20[0x10];
587 u8 source_port[0x10];
588 u8 outer_second_prio[0x3];
589 u8 outer_second_cfi[0x1];
590 u8 outer_second_vid[0xc];
591 u8 inner_second_prio[0x3];
592 u8 inner_second_cfi[0x1];
593 u8 inner_second_vid[0xc];
594 u8 outer_second_cvlan_tag[0x1];
595 u8 inner_second_cvlan_tag[0x1];
596 u8 outer_second_svlan_tag[0x1];
597 u8 inner_second_svlan_tag[0x1];
598 u8 reserved_at_64[0xc];
599 u8 gre_protocol[0x10];
603 u8 reserved_at_b8[0x8];
605 u8 reserved_at_e4[0x7];
607 u8 reserved_at_e0[0xc];
608 u8 outer_ipv6_flow_label[0x14];
609 u8 reserved_at_100[0xc];
610 u8 inner_ipv6_flow_label[0x14];
611 u8 reserved_at_120[0xa];
612 u8 geneve_opt_len[0x6];
613 u8 geneve_protocol_type[0x10];
614 u8 reserved_at_140[0xc0];
617 struct mlx5_ifc_ipv4_layout_bits {
618 u8 reserved_at_0[0x60];
622 struct mlx5_ifc_ipv6_layout_bits {
626 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
627 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
628 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
629 u8 reserved_at_0[0x80];
632 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
651 u8 reserved_at_c0[0x20];
654 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
655 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
658 struct mlx5_ifc_fte_match_mpls_bits {
665 struct mlx5_ifc_fte_match_set_misc2_bits {
666 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
667 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
668 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
669 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
670 u8 metadata_reg_c_7[0x20];
671 u8 metadata_reg_c_6[0x20];
672 u8 metadata_reg_c_5[0x20];
673 u8 metadata_reg_c_4[0x20];
674 u8 metadata_reg_c_3[0x20];
675 u8 metadata_reg_c_2[0x20];
676 u8 metadata_reg_c_1[0x20];
677 u8 metadata_reg_c_0[0x20];
678 u8 metadata_reg_a[0x20];
679 u8 metadata_reg_b[0x20];
680 u8 reserved_at_1c0[0x40];
683 struct mlx5_ifc_fte_match_set_misc3_bits {
684 u8 inner_tcp_seq_num[0x20];
685 u8 outer_tcp_seq_num[0x20];
686 u8 inner_tcp_ack_num[0x20];
687 u8 outer_tcp_ack_num[0x20];
688 u8 reserved_at_auto1[0x8];
689 u8 outer_vxlan_gpe_vni[0x18];
690 u8 outer_vxlan_gpe_next_protocol[0x8];
691 u8 outer_vxlan_gpe_flags[0x8];
692 u8 reserved_at_a8[0x10];
693 u8 icmp_header_data[0x20];
694 u8 icmpv6_header_data[0x20];
699 u8 reserved_at_120[0x20];
701 u8 gtpu_msg_type[0x08];
702 u8 gtpu_msg_flags[0x08];
703 u8 reserved_at_170[0x90];
707 struct mlx5_ifc_fte_match_param_bits {
708 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
709 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
710 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
711 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
712 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
716 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
717 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
718 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
719 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
720 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT
724 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
725 MLX5_CMD_OP_CREATE_MKEY = 0x200,
726 MLX5_CMD_OP_CREATE_CQ = 0x400,
727 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
728 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
729 MLX5_CMD_OP_CREATE_TIR = 0x900,
730 MLX5_CMD_OP_CREATE_SQ = 0X904,
731 MLX5_CMD_OP_MODIFY_SQ = 0X905,
732 MLX5_CMD_OP_CREATE_RQ = 0x908,
733 MLX5_CMD_OP_MODIFY_RQ = 0x909,
734 MLX5_CMD_OP_CREATE_TIS = 0x912,
735 MLX5_CMD_OP_QUERY_TIS = 0x915,
736 MLX5_CMD_OP_CREATE_RQT = 0x916,
737 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
738 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
739 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
740 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
741 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
745 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
746 MLX5_MKC_ACCESS_MODE_KLM = 0x2,
747 MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3,
751 struct mlx5_ifc_alloc_flow_counter_out_bits {
753 u8 reserved_at_8[0x18];
755 u8 flow_counter_id[0x20];
756 u8 reserved_at_60[0x20];
759 struct mlx5_ifc_alloc_flow_counter_in_bits {
761 u8 reserved_at_10[0x10];
762 u8 reserved_at_20[0x10];
764 u8 flow_counter_id[0x20];
765 u8 reserved_at_40[0x18];
766 u8 flow_counter_bulk[0x8];
769 struct mlx5_ifc_dealloc_flow_counter_out_bits {
771 u8 reserved_at_8[0x18];
773 u8 reserved_at_40[0x40];
776 struct mlx5_ifc_dealloc_flow_counter_in_bits {
778 u8 reserved_at_10[0x10];
779 u8 reserved_at_20[0x10];
781 u8 flow_counter_id[0x20];
782 u8 reserved_at_60[0x20];
785 struct mlx5_ifc_traffic_counter_bits {
790 struct mlx5_ifc_query_flow_counter_out_bits {
792 u8 reserved_at_8[0x18];
794 u8 reserved_at_40[0x40];
795 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
798 struct mlx5_ifc_query_flow_counter_in_bits {
800 u8 reserved_at_10[0x10];
801 u8 reserved_at_20[0x10];
803 u8 reserved_at_40[0x20];
807 u8 dump_to_memory[0x1];
808 u8 num_of_counters[0x1e];
809 u8 flow_counter_id[0x20];
812 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u
813 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u
816 struct mlx5_ifc_klm_bits {
822 struct mlx5_ifc_mkc_bits {
823 u8 reserved_at_0[0x1];
825 u8 reserved_at_2[0x1];
826 u8 access_mode_4_2[0x3];
827 u8 reserved_at_6[0x7];
828 u8 relaxed_ordering_write[0x1];
829 u8 reserved_at_e[0x1];
830 u8 small_fence_on_rdma_read_response[0x1];
837 u8 access_mode_1_0[0x2];
838 u8 reserved_at_18[0x8];
843 u8 reserved_at_40[0x20];
848 u8 reserved_at_63[0x2];
849 u8 expected_sigerr_count[0x1];
850 u8 reserved_at_66[0x1];
858 u8 bsf_octword_size[0x20];
860 u8 reserved_at_120[0x80];
862 u8 translations_octword_size[0x20];
864 u8 reserved_at_1c0[0x1b];
865 u8 log_page_size[0x5];
867 u8 reserved_at_1e0[0x20];
870 struct mlx5_ifc_create_mkey_out_bits {
872 u8 reserved_at_8[0x18];
876 u8 reserved_at_40[0x8];
879 u8 reserved_at_60[0x20];
882 struct mlx5_ifc_create_mkey_in_bits {
884 u8 reserved_at_10[0x10];
886 u8 reserved_at_20[0x10];
889 u8 reserved_at_40[0x20];
892 u8 reserved_at_61[0x1f];
894 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
896 u8 reserved_at_280[0x80];
898 u8 translations_octword_actual_size[0x20];
900 u8 mkey_umem_id[0x20];
902 u8 mkey_umem_offset[0x40];
904 u8 reserved_at_380[0x500];
906 u8 klm_pas_mtt[][0x20];
910 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
911 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
912 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
913 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
917 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q = (1ULL << 0xd),
921 MLX5_HCA_CAP_OPMOD_GET_MAX = 0,
922 MLX5_HCA_CAP_OPMOD_GET_CUR = 1,
926 MLX5_CAP_INLINE_MODE_L2,
927 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
928 MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
932 MLX5_INLINE_MODE_NONE,
935 MLX5_INLINE_MODE_TCP_UDP,
936 MLX5_INLINE_MODE_RESERVED4,
937 MLX5_INLINE_MODE_INNER_L2,
938 MLX5_INLINE_MODE_INNER_IP,
939 MLX5_INLINE_MODE_INNER_TCP_UDP,
942 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
943 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
944 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
945 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
946 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
947 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
948 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
949 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
950 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
951 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
952 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
954 struct mlx5_ifc_cmd_hca_cap_bits {
955 u8 reserved_at_0[0x30];
957 u8 reserved_at_40[0x40];
958 u8 log_max_srq_sz[0x8];
959 u8 log_max_qp_sz[0x8];
960 u8 reserved_at_90[0xb];
962 u8 reserved_at_a0[0xb];
964 u8 reserved_at_b0[0x10];
965 u8 reserved_at_c0[0x8];
966 u8 log_max_cq_sz[0x8];
967 u8 reserved_at_d0[0xb];
969 u8 log_max_eq_sz[0x8];
970 u8 reserved_at_e8[0x2];
971 u8 log_max_mkey[0x6];
972 u8 reserved_at_f0[0x8];
973 u8 dump_fill_mkey[0x1];
974 u8 reserved_at_f9[0x3];
976 u8 max_indirection[0x8];
977 u8 fixed_buffer_size[0x1];
978 u8 log_max_mrw_sz[0x7];
979 u8 force_teardown[0x1];
980 u8 reserved_at_111[0x1];
981 u8 log_max_bsf_list_size[0x6];
982 u8 umr_extended_translation_offset[0x1];
984 u8 log_max_klm_list_size[0x6];
985 u8 reserved_at_120[0xa];
986 u8 log_max_ra_req_dc[0x6];
987 u8 reserved_at_130[0xa];
988 u8 log_max_ra_res_dc[0x6];
989 u8 reserved_at_140[0xa];
990 u8 log_max_ra_req_qp[0x6];
991 u8 reserved_at_150[0xa];
992 u8 log_max_ra_res_qp[0x6];
994 u8 cc_query_allowed[0x1];
995 u8 cc_modify_allowed[0x1];
997 u8 cache_line_128byte[0x1];
998 u8 reserved_at_165[0xa];
1000 u8 gid_table_size[0x10];
1001 u8 out_of_seq_cnt[0x1];
1002 u8 vport_counters[0x1];
1003 u8 retransmission_q_counters[0x1];
1005 u8 modify_rq_counter_set_id[0x1];
1006 u8 rq_delay_drop[0x1];
1008 u8 pkey_table_size[0x10];
1009 u8 vport_group_manager[0x1];
1010 u8 vhca_group_manager[0x1];
1013 u8 vnic_env_queue_counters[0x1];
1015 u8 nic_flow_table[0x1];
1016 u8 eswitch_manager[0x1];
1017 u8 device_memory[0x1];
1020 u8 local_ca_ack_delay[0x5];
1021 u8 port_module_event[0x1];
1022 u8 enhanced_error_q_counters[0x1];
1023 u8 ports_check[0x1];
1024 u8 reserved_at_1b3[0x1];
1025 u8 disable_link_up[0x1];
1029 u8 reserved_at_1c0[0x1];
1032 u8 log_max_msg[0x5];
1033 u8 reserved_at_1c8[0x4];
1035 u8 temp_warn_event[0x1];
1037 u8 general_notification_event[0x1];
1038 u8 reserved_at_1d3[0x2];
1042 u8 reserved_at_1d8[0x1];
1050 u8 stat_rate_support[0x10];
1051 u8 reserved_at_1f0[0xc];
1052 u8 cqe_version[0x4];
1053 u8 compact_address_vector[0x1];
1054 u8 striding_rq[0x1];
1055 u8 reserved_at_202[0x1];
1056 u8 ipoib_enhanced_offloads[0x1];
1057 u8 ipoib_basic_offloads[0x1];
1058 u8 reserved_at_205[0x1];
1059 u8 repeated_block_disabled[0x1];
1060 u8 umr_modify_entity_size_disabled[0x1];
1061 u8 umr_modify_atomic_disabled[0x1];
1062 u8 umr_indirect_mkey_disabled[0x1];
1064 u8 reserved_at_20c[0x3];
1065 u8 drain_sigerr[0x1];
1066 u8 cmdif_checksum[0x2];
1068 u8 reserved_at_213[0x1];
1069 u8 wq_signature[0x1];
1070 u8 sctr_data_cqe[0x1];
1071 u8 reserved_at_216[0x1];
1077 u8 eth_net_offloads[0x1];
1080 u8 reserved_at_21f[0x1];
1083 u8 cq_moderation[0x1];
1084 u8 reserved_at_223[0x3];
1085 u8 cq_eq_remap[0x1];
1087 u8 block_lb_mc[0x1];
1088 u8 reserved_at_229[0x1];
1089 u8 scqe_break_moderation[0x1];
1090 u8 cq_period_start_from_cqe[0x1];
1092 u8 reserved_at_22d[0x1];
1094 u8 vector_calc[0x1];
1095 u8 umr_ptr_rlky[0x1];
1097 u8 reserved_at_232[0x4];
1100 u8 set_deth_sqpn[0x1];
1101 u8 reserved_at_239[0x3];
1107 u8 reserved_at_241[0x9];
1109 u8 reserved_at_250[0x8];
1112 u8 driver_version[0x1];
1113 u8 pad_tx_eth_packet[0x1];
1114 u8 reserved_at_263[0x8];
1115 u8 log_bf_reg_size[0x5];
1116 u8 reserved_at_270[0xb];
1118 u8 num_lag_ports[0x4];
1119 u8 reserved_at_280[0x10];
1120 u8 max_wqe_sz_sq[0x10];
1121 u8 reserved_at_2a0[0x10];
1122 u8 max_wqe_sz_rq[0x10];
1123 u8 max_flow_counter_31_16[0x10];
1124 u8 max_wqe_sz_sq_dc[0x10];
1125 u8 reserved_at_2e0[0x7];
1126 u8 max_qp_mcg[0x19];
1127 u8 reserved_at_300[0x10];
1128 u8 flow_counter_bulk_alloc[0x08];
1129 u8 log_max_mcg[0x8];
1130 u8 reserved_at_320[0x3];
1131 u8 log_max_transport_domain[0x5];
1132 u8 reserved_at_328[0x3];
1134 u8 reserved_at_330[0xb];
1135 u8 log_max_xrcd[0x5];
1136 u8 nic_receive_steering_discard[0x1];
1137 u8 receive_discard_vport_down[0x1];
1138 u8 transmit_discard_vport_down[0x1];
1139 u8 reserved_at_343[0x5];
1140 u8 log_max_flow_counter_bulk[0x8];
1141 u8 max_flow_counter_15_0[0x10];
1143 u8 flow_counters_dump[0x1];
1144 u8 reserved_at_360[0x1];
1146 u8 reserved_at_368[0x3];
1148 u8 reserved_at_370[0x3];
1149 u8 log_max_tir[0x5];
1150 u8 reserved_at_378[0x3];
1151 u8 log_max_tis[0x5];
1152 u8 basic_cyclic_rcv_wqe[0x1];
1153 u8 reserved_at_381[0x2];
1154 u8 log_max_rmp[0x5];
1155 u8 reserved_at_388[0x3];
1156 u8 log_max_rqt[0x5];
1157 u8 reserved_at_390[0x3];
1158 u8 log_max_rqt_size[0x5];
1159 u8 reserved_at_398[0x3];
1160 u8 log_max_tis_per_sq[0x5];
1161 u8 ext_stride_num_range[0x1];
1162 u8 reserved_at_3a1[0x2];
1163 u8 log_max_stride_sz_rq[0x5];
1164 u8 reserved_at_3a8[0x3];
1165 u8 log_min_stride_sz_rq[0x5];
1166 u8 reserved_at_3b0[0x3];
1167 u8 log_max_stride_sz_sq[0x5];
1168 u8 reserved_at_3b8[0x3];
1169 u8 log_min_stride_sz_sq[0x5];
1171 u8 reserved_at_3c1[0x2];
1172 u8 log_max_hairpin_queues[0x5];
1173 u8 reserved_at_3c8[0x3];
1174 u8 log_max_hairpin_wq_data_sz[0x5];
1175 u8 reserved_at_3d0[0x3];
1176 u8 log_max_hairpin_num_packets[0x5];
1177 u8 reserved_at_3d8[0x3];
1178 u8 log_max_wq_sz[0x5];
1179 u8 nic_vport_change_event[0x1];
1180 u8 disable_local_lb_uc[0x1];
1181 u8 disable_local_lb_mc[0x1];
1182 u8 log_min_hairpin_wq_data_sz[0x5];
1183 u8 reserved_at_3e8[0x3];
1184 u8 log_max_vlan_list[0x5];
1185 u8 reserved_at_3f0[0x3];
1186 u8 log_max_current_mc_list[0x5];
1187 u8 reserved_at_3f8[0x3];
1188 u8 log_max_current_uc_list[0x5];
1189 u8 general_obj_types[0x40];
1190 u8 reserved_at_440[0x20];
1191 u8 reserved_at_460[0x10];
1192 u8 max_num_eqs[0x10];
1193 u8 reserved_at_480[0x3];
1194 u8 log_max_l2_table[0x5];
1195 u8 reserved_at_488[0x8];
1196 u8 log_uar_page_sz[0x10];
1197 u8 reserved_at_4a0[0x20];
1198 u8 device_frequency_mhz[0x20];
1199 u8 device_frequency_khz[0x20];
1200 u8 reserved_at_500[0x20];
1201 u8 num_of_uars_per_page[0x20];
1202 u8 flex_parser_protocols[0x20];
1203 u8 reserved_at_560[0x20];
1204 u8 reserved_at_580[0x3c];
1205 u8 mini_cqe_resp_stride_index[0x1];
1206 u8 cqe_128_always[0x1];
1207 u8 cqe_compression_128[0x1];
1208 u8 cqe_compression[0x1];
1209 u8 cqe_compression_timeout[0x10];
1210 u8 cqe_compression_max_num[0x10];
1211 u8 reserved_at_5e0[0x10];
1212 u8 tag_matching[0x1];
1213 u8 rndv_offload_rc[0x1];
1214 u8 rndv_offload_dc[0x1];
1215 u8 log_tag_matching_list_sz[0x5];
1216 u8 reserved_at_5f8[0x3];
1217 u8 log_max_xrq[0x5];
1218 u8 affiliate_nic_vport_criteria[0x8];
1219 u8 native_port_num[0x8];
1220 u8 num_vhca_ports[0x8];
1221 u8 reserved_at_618[0x6];
1222 u8 sw_owner_id[0x1];
1223 u8 reserved_at_61f[0x1e1];
1226 struct mlx5_ifc_qos_cap_bits {
1227 u8 packet_pacing[0x1];
1228 u8 esw_scheduling[0x1];
1229 u8 esw_bw_share[0x1];
1230 u8 esw_rate_limit[0x1];
1231 u8 reserved_at_4[0x1];
1232 u8 packet_pacing_burst_bound[0x1];
1233 u8 packet_pacing_typical_size[0x1];
1234 u8 flow_meter_srtcm[0x1];
1235 u8 reserved_at_8[0x8];
1236 u8 log_max_flow_meter[0x8];
1237 u8 flow_meter_reg_id[0x8];
1238 u8 reserved_at_25[0x8];
1239 u8 flow_meter_reg_share[0x1];
1240 u8 reserved_at_2e[0x17];
1241 u8 packet_pacing_max_rate[0x20];
1242 u8 packet_pacing_min_rate[0x20];
1243 u8 reserved_at_80[0x10];
1244 u8 packet_pacing_rate_table_size[0x10];
1245 u8 esw_element_type[0x10];
1246 u8 esw_tsar_type[0x10];
1247 u8 reserved_at_c0[0x10];
1248 u8 max_qos_para_vport[0x10];
1249 u8 max_tsar_bw_share[0x20];
1250 u8 reserved_at_100[0x6e8];
1253 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1257 u8 lro_psh_flag[0x1];
1258 u8 lro_time_stamp[0x1];
1259 u8 lro_max_msg_sz_mode[0x2];
1260 u8 wqe_vlan_insert[0x1];
1261 u8 self_lb_en_modifiable[0x1];
1264 u8 max_lso_cap[0x5];
1265 u8 multi_pkt_send_wqe[0x2];
1266 u8 wqe_inline_mode[0x2];
1267 u8 rss_ind_tbl_cap[0x4];
1269 u8 scatter_fcs[0x1];
1270 u8 enhanced_multi_pkt_send_wqe[0x1];
1271 u8 tunnel_lso_const_out_ip_id[0x1];
1272 u8 tunnel_lro_gre[0x1];
1273 u8 tunnel_lro_vxlan[0x1];
1274 u8 tunnel_stateless_gre[0x1];
1275 u8 tunnel_stateless_vxlan[0x1];
1279 u8 reserved_at_23[0x8];
1280 u8 tunnel_stateless_gtp[0x1];
1281 u8 reserved_at_25[0x4];
1282 u8 max_vxlan_udp_ports[0x8];
1283 u8 reserved_at_38[0x6];
1284 u8 max_geneve_opt_len[0x1];
1285 u8 tunnel_stateless_geneve_rx[0x1];
1286 u8 reserved_at_40[0x10];
1287 u8 lro_min_mss_size[0x10];
1288 u8 reserved_at_60[0x120];
1289 u8 lro_timer_supported_periods[4][0x20];
1290 u8 reserved_at_200[0x600];
1294 MLX5_VIRTQ_TYPE_SPLIT = 0,
1295 MLX5_VIRTQ_TYPE_PACKED = 1,
1299 MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0,
1300 MLX5_VIRTQ_EVENT_MODE_QP = 1,
1301 MLX5_VIRTQ_EVENT_MODE_MSIX = 2,
1304 struct mlx5_ifc_virtio_emulation_cap_bits {
1305 u8 desc_tunnel_offload_type[0x1];
1306 u8 eth_frame_offload_type[0x1];
1307 u8 virtio_version_1_0[0x1];
1312 u8 reserved_at_7[0x1][0x9];
1314 u8 virtio_queue_type[0x8];
1315 u8 reserved_at_20[0x13];
1316 u8 log_doorbell_stride[0x5];
1317 u8 reserved_at_3b[0x3];
1318 u8 log_doorbell_bar_size[0x5];
1319 u8 doorbell_bar_offset[0x40];
1320 u8 reserved_at_80[0x8];
1321 u8 max_num_virtio_queues[0x18];
1322 u8 reserved_at_a0[0x60];
1323 u8 umem_1_buffer_param_a[0x20];
1324 u8 umem_1_buffer_param_b[0x20];
1325 u8 umem_2_buffer_param_a[0x20];
1326 u8 umem_2_buffer_param_b[0x20];
1327 u8 umem_3_buffer_param_a[0x20];
1328 u8 umem_3_buffer_param_b[0x20];
1329 u8 reserved_at_1c0[0x620];
1332 union mlx5_ifc_hca_cap_union_bits {
1333 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1334 struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1335 per_protocol_networking_offload_caps;
1336 struct mlx5_ifc_qos_cap_bits qos_cap;
1337 struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
1338 u8 reserved_at_0[0x8000];
1341 struct mlx5_ifc_query_hca_cap_out_bits {
1343 u8 reserved_at_8[0x18];
1345 u8 reserved_at_40[0x40];
1346 union mlx5_ifc_hca_cap_union_bits capability;
1349 struct mlx5_ifc_query_hca_cap_in_bits {
1351 u8 reserved_at_10[0x10];
1352 u8 reserved_at_20[0x10];
1354 u8 reserved_at_40[0x40];
1357 struct mlx5_ifc_mac_address_layout_bits {
1358 u8 reserved_at_0[0x10];
1359 u8 mac_addr_47_32[0x10];
1360 u8 mac_addr_31_0[0x20];
1363 struct mlx5_ifc_nic_vport_context_bits {
1364 u8 reserved_at_0[0x5];
1365 u8 min_wqe_inline_mode[0x3];
1366 u8 reserved_at_8[0x15];
1367 u8 disable_mc_local_lb[0x1];
1368 u8 disable_uc_local_lb[0x1];
1370 u8 arm_change_event[0x1];
1371 u8 reserved_at_21[0x1a];
1372 u8 event_on_mtu[0x1];
1373 u8 event_on_promisc_change[0x1];
1374 u8 event_on_vlan_change[0x1];
1375 u8 event_on_mc_address_change[0x1];
1376 u8 event_on_uc_address_change[0x1];
1377 u8 reserved_at_40[0xc];
1378 u8 affiliation_criteria[0x4];
1379 u8 affiliated_vhca_id[0x10];
1380 u8 reserved_at_60[0xd0];
1382 u8 system_image_guid[0x40];
1385 u8 reserved_at_200[0x140];
1386 u8 qkey_violation_counter[0x10];
1387 u8 reserved_at_350[0x430];
1390 u8 promisc_all[0x1];
1391 u8 reserved_at_783[0x2];
1392 u8 allowed_list_type[0x3];
1393 u8 reserved_at_788[0xc];
1394 u8 allowed_list_size[0xc];
1395 struct mlx5_ifc_mac_address_layout_bits permanent_address;
1396 u8 reserved_at_7e0[0x20];
1399 struct mlx5_ifc_query_nic_vport_context_out_bits {
1401 u8 reserved_at_8[0x18];
1403 u8 reserved_at_40[0x40];
1404 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
1407 struct mlx5_ifc_query_nic_vport_context_in_bits {
1409 u8 reserved_at_10[0x10];
1410 u8 reserved_at_20[0x10];
1412 u8 other_vport[0x1];
1413 u8 reserved_at_41[0xf];
1414 u8 vport_number[0x10];
1415 u8 reserved_at_60[0x5];
1416 u8 allowed_list_type[0x3];
1417 u8 reserved_at_68[0x18];
1420 struct mlx5_ifc_tisc_bits {
1421 u8 strict_lag_tx_port_affinity[0x1];
1422 u8 reserved_at_1[0x3];
1423 u8 lag_tx_port_affinity[0x04];
1424 u8 reserved_at_8[0x4];
1426 u8 reserved_at_10[0x10];
1427 u8 reserved_at_20[0x100];
1428 u8 reserved_at_120[0x8];
1429 u8 transport_domain[0x18];
1430 u8 reserved_at_140[0x8];
1431 u8 underlay_qpn[0x18];
1432 u8 reserved_at_160[0x3a0];
1435 struct mlx5_ifc_query_tis_out_bits {
1437 u8 reserved_at_8[0x18];
1439 u8 reserved_at_40[0x40];
1440 struct mlx5_ifc_tisc_bits tis_context;
1443 struct mlx5_ifc_query_tis_in_bits {
1445 u8 reserved_at_10[0x10];
1446 u8 reserved_at_20[0x10];
1448 u8 reserved_at_40[0x8];
1450 u8 reserved_at_60[0x20];
1453 struct mlx5_ifc_alloc_transport_domain_out_bits {
1455 u8 reserved_at_8[0x18];
1457 u8 reserved_at_40[0x8];
1458 u8 transport_domain[0x18];
1459 u8 reserved_at_60[0x20];
1462 struct mlx5_ifc_alloc_transport_domain_in_bits {
1464 u8 reserved_at_10[0x10];
1465 u8 reserved_at_20[0x10];
1467 u8 reserved_at_40[0x40];
1471 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1472 MLX5_WQ_TYPE_CYCLIC = 0x1,
1473 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1474 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1478 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1479 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1482 struct mlx5_ifc_wq_bits {
1484 u8 wq_signature[0x1];
1485 u8 end_padding_mode[0x2];
1487 u8 reserved_at_8[0x18];
1488 u8 hds_skip_first_sge[0x1];
1489 u8 log2_hds_buf_size[0x3];
1490 u8 reserved_at_24[0x7];
1491 u8 page_offset[0x5];
1493 u8 reserved_at_40[0x8];
1495 u8 reserved_at_60[0x8];
1498 u8 hw_counter[0x20];
1499 u8 sw_counter[0x20];
1500 u8 reserved_at_100[0xc];
1501 u8 log_wq_stride[0x4];
1502 u8 reserved_at_110[0x3];
1503 u8 log_wq_pg_sz[0x5];
1504 u8 reserved_at_118[0x3];
1506 u8 dbr_umem_valid[0x1];
1507 u8 wq_umem_valid[0x1];
1508 u8 reserved_at_122[0x1];
1509 u8 log_hairpin_num_packets[0x5];
1510 u8 reserved_at_128[0x3];
1511 u8 log_hairpin_data_sz[0x5];
1512 u8 reserved_at_130[0x4];
1513 u8 single_wqe_log_num_of_strides[0x4];
1514 u8 two_byte_shift_en[0x1];
1515 u8 reserved_at_139[0x4];
1516 u8 single_stride_log_num_of_bytes[0x3];
1517 u8 dbr_umem_id[0x20];
1518 u8 wq_umem_id[0x20];
1519 u8 wq_umem_offset[0x40];
1520 u8 reserved_at_1c0[0x440];
1524 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1525 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
1529 MLX5_RQC_STATE_RST = 0x0,
1530 MLX5_RQC_STATE_RDY = 0x1,
1531 MLX5_RQC_STATE_ERR = 0x3,
1534 struct mlx5_ifc_rqc_bits {
1536 u8 delay_drop_en[0x1];
1537 u8 scatter_fcs[0x1];
1539 u8 mem_rq_type[0x4];
1541 u8 reserved_at_c[0x1];
1542 u8 flush_in_error_en[0x1];
1544 u8 reserved_at_f[0x11];
1545 u8 reserved_at_20[0x8];
1546 u8 user_index[0x18];
1547 u8 reserved_at_40[0x8];
1549 u8 counter_set_id[0x8];
1550 u8 reserved_at_68[0x18];
1551 u8 reserved_at_80[0x8];
1553 u8 reserved_at_a0[0x8];
1554 u8 hairpin_peer_sq[0x18];
1555 u8 reserved_at_c0[0x10];
1556 u8 hairpin_peer_vhca[0x10];
1557 u8 reserved_at_e0[0xa0];
1558 struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
1561 struct mlx5_ifc_create_rq_out_bits {
1563 u8 reserved_at_8[0x18];
1565 u8 reserved_at_40[0x8];
1567 u8 reserved_at_60[0x20];
1570 struct mlx5_ifc_create_rq_in_bits {
1573 u8 reserved_at_20[0x10];
1575 u8 reserved_at_40[0xc0];
1576 struct mlx5_ifc_rqc_bits ctx;
1579 struct mlx5_ifc_modify_rq_out_bits {
1581 u8 reserved_at_8[0x18];
1583 u8 reserved_at_40[0x40];
1586 struct mlx5_ifc_create_tis_out_bits {
1588 u8 reserved_at_8[0x18];
1590 u8 reserved_at_40[0x8];
1592 u8 reserved_at_60[0x20];
1595 struct mlx5_ifc_create_tis_in_bits {
1598 u8 reserved_at_20[0x10];
1600 u8 reserved_at_40[0xc0];
1601 struct mlx5_ifc_tisc_bits ctx;
1605 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
1606 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
1607 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
1608 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
1611 struct mlx5_ifc_modify_rq_in_bits {
1614 u8 reserved_at_20[0x10];
1617 u8 reserved_at_44[0x4];
1619 u8 reserved_at_60[0x20];
1620 u8 modify_bitmask[0x40];
1621 u8 reserved_at_c0[0x40];
1622 struct mlx5_ifc_rqc_bits ctx;
1626 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1627 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1628 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1629 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1630 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1633 struct mlx5_ifc_rx_hash_field_select_bits {
1634 u8 l3_prot_type[0x1];
1635 u8 l4_prot_type[0x1];
1636 u8 selected_fields[0x1e];
1640 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
1641 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
1645 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
1646 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
1650 MLX5_RX_HASH_FN_NONE = 0x0,
1651 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
1652 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
1656 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
1657 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
1661 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 = 0x0,
1662 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2 = 0x1,
1665 struct mlx5_ifc_tirc_bits {
1666 u8 reserved_at_0[0x20];
1668 u8 reserved_at_24[0x1c];
1669 u8 reserved_at_40[0x40];
1670 u8 reserved_at_80[0x4];
1671 u8 lro_timeout_period_usecs[0x10];
1672 u8 lro_enable_mask[0x4];
1673 u8 lro_max_msg_sz[0x8];
1674 u8 reserved_at_a0[0x40];
1675 u8 reserved_at_e0[0x8];
1676 u8 inline_rqn[0x18];
1677 u8 rx_hash_symmetric[0x1];
1678 u8 reserved_at_101[0x1];
1679 u8 tunneled_offload_en[0x1];
1680 u8 reserved_at_103[0x5];
1681 u8 indirect_table[0x18];
1683 u8 reserved_at_124[0x2];
1684 u8 self_lb_block[0x2];
1685 u8 transport_domain[0x18];
1686 u8 rx_hash_toeplitz_key[10][0x20];
1687 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1688 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1689 u8 reserved_at_2c0[0x4c0];
1692 struct mlx5_ifc_create_tir_out_bits {
1694 u8 reserved_at_8[0x18];
1696 u8 reserved_at_40[0x8];
1698 u8 reserved_at_60[0x20];
1701 struct mlx5_ifc_create_tir_in_bits {
1704 u8 reserved_at_20[0x10];
1706 u8 reserved_at_40[0xc0];
1707 struct mlx5_ifc_tirc_bits ctx;
1711 MLX5_INLINE_Q_TYPE_RQ = 0x0,
1712 MLX5_INLINE_Q_TYPE_VIRTQ = 0x1,
1715 struct mlx5_ifc_rq_num_bits {
1716 u8 reserved_at_0[0x8];
1720 struct mlx5_ifc_rqtc_bits {
1721 u8 reserved_at_0[0xa0];
1722 u8 reserved_at_a0[0x10];
1723 u8 rqt_max_size[0x10];
1724 u8 reserved_at_c0[0x10];
1725 u8 rqt_actual_size[0x10];
1726 u8 reserved_at_e0[0x6a0];
1727 struct mlx5_ifc_rq_num_bits rq_num[];
1730 struct mlx5_ifc_create_rqt_out_bits {
1732 u8 reserved_at_8[0x18];
1734 u8 reserved_at_40[0x8];
1736 u8 reserved_at_60[0x20];
1740 #pragma GCC diagnostic ignored "-Wpedantic"
1742 struct mlx5_ifc_create_rqt_in_bits {
1745 u8 reserved_at_20[0x10];
1747 u8 reserved_at_40[0xc0];
1748 struct mlx5_ifc_rqtc_bits rqt_context;
1751 #pragma GCC diagnostic error "-Wpedantic"
1755 MLX5_SQC_STATE_RST = 0x0,
1756 MLX5_SQC_STATE_RDY = 0x1,
1757 MLX5_SQC_STATE_ERR = 0x3,
1760 struct mlx5_ifc_sqc_bits {
1764 u8 flush_in_error_en[0x1];
1765 u8 allow_multi_pkt_send_wqe[0x1];
1766 u8 min_wqe_inline_mode[0x3];
1771 u8 reserved_at_f[0x11];
1772 u8 reserved_at_20[0x8];
1773 u8 user_index[0x18];
1774 u8 reserved_at_40[0x8];
1776 u8 reserved_at_60[0x8];
1777 u8 hairpin_peer_rq[0x18];
1778 u8 reserved_at_80[0x10];
1779 u8 hairpin_peer_vhca[0x10];
1780 u8 reserved_at_a0[0x50];
1781 u8 packet_pacing_rate_limit_index[0x10];
1782 u8 tis_lst_sz[0x10];
1783 u8 reserved_at_110[0x10];
1784 u8 reserved_at_120[0x40];
1785 u8 reserved_at_160[0x8];
1787 struct mlx5_ifc_wq_bits wq;
1790 struct mlx5_ifc_query_sq_in_bits {
1792 u8 reserved_at_10[0x10];
1793 u8 reserved_at_20[0x10];
1795 u8 reserved_at_40[0x8];
1797 u8 reserved_at_60[0x20];
1800 struct mlx5_ifc_modify_sq_out_bits {
1802 u8 reserved_at_8[0x18];
1804 u8 reserved_at_40[0x40];
1807 struct mlx5_ifc_modify_sq_in_bits {
1810 u8 reserved_at_20[0x10];
1813 u8 reserved_at_44[0x4];
1815 u8 reserved_at_60[0x20];
1816 u8 modify_bitmask[0x40];
1817 u8 reserved_at_c0[0x40];
1818 struct mlx5_ifc_sqc_bits ctx;
1821 struct mlx5_ifc_create_sq_out_bits {
1823 u8 reserved_at_8[0x18];
1825 u8 reserved_at_40[0x8];
1827 u8 reserved_at_60[0x20];
1830 struct mlx5_ifc_create_sq_in_bits {
1833 u8 reserved_at_20[0x10];
1835 u8 reserved_at_40[0xc0];
1836 struct mlx5_ifc_sqc_bits ctx;
1840 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
1841 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
1842 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
1843 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
1844 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
1847 struct mlx5_ifc_flow_meter_parameters_bits {
1848 u8 valid[0x1]; // 00h
1849 u8 bucket_overflow[0x1];
1850 u8 start_color[0x2];
1851 u8 both_buckets_on_green[0x1];
1853 u8 reserved_at_1[0x19];
1854 u8 reserved_at_2[0x20]; //04h
1855 u8 reserved_at_3[0x3];
1856 u8 cbs_exponent[0x5]; // 08h
1857 u8 cbs_mantissa[0x8];
1858 u8 reserved_at_4[0x3];
1859 u8 cir_exponent[0x5];
1860 u8 cir_mantissa[0x8];
1861 u8 reserved_at_5[0x20]; // 0Ch
1862 u8 reserved_at_6[0x3];
1863 u8 ebs_exponent[0x5]; // 10h
1864 u8 ebs_mantissa[0x8];
1865 u8 reserved_at_7[0x3];
1866 u8 eir_exponent[0x5];
1867 u8 eir_mantissa[0x8];
1868 u8 reserved_at_8[0x60]; // 14h-1Ch
1871 struct mlx5_ifc_cqc_bits {
1874 u8 initiator_src_dct[0x1];
1875 u8 dbr_umem_valid[0x1];
1876 u8 reserved_at_7[0x1];
1879 u8 reserved_at_c[0x1];
1880 u8 scqe_break_moderation_en[0x1];
1882 u8 cq_period_mode[0x2];
1883 u8 cqe_comp_en[0x1];
1884 u8 mini_cqe_res_format[0x2];
1886 u8 reserved_at_18[0x8];
1887 u8 dbr_umem_id[0x20];
1888 u8 reserved_at_40[0x14];
1889 u8 page_offset[0x6];
1890 u8 reserved_at_5a[0x6];
1891 u8 reserved_at_60[0x3];
1892 u8 log_cq_size[0x5];
1894 u8 reserved_at_80[0x4];
1896 u8 cq_max_count[0x10];
1897 u8 reserved_at_a0[0x18];
1899 u8 reserved_at_c0[0x3];
1900 u8 log_page_size[0x5];
1901 u8 reserved_at_c8[0x18];
1902 u8 reserved_at_e0[0x20];
1903 u8 reserved_at_100[0x8];
1904 u8 last_notified_index[0x18];
1905 u8 reserved_at_120[0x8];
1906 u8 last_solicit_index[0x18];
1907 u8 reserved_at_140[0x8];
1908 u8 consumer_counter[0x18];
1909 u8 reserved_at_160[0x8];
1910 u8 producer_counter[0x18];
1911 u8 local_partition_id[0xc];
1912 u8 process_id[0x14];
1913 u8 reserved_at_1A0[0x20];
1917 struct mlx5_ifc_create_cq_out_bits {
1919 u8 reserved_at_8[0x18];
1921 u8 reserved_at_40[0x8];
1923 u8 reserved_at_60[0x20];
1926 struct mlx5_ifc_create_cq_in_bits {
1929 u8 reserved_at_20[0x10];
1931 u8 reserved_at_40[0x40];
1932 struct mlx5_ifc_cqc_bits cq_context;
1933 u8 cq_umem_offset[0x40];
1934 u8 cq_umem_id[0x20];
1935 u8 cq_umem_valid[0x1];
1936 u8 reserved_at_2e1[0x1f];
1937 u8 reserved_at_300[0x580];
1942 MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
1945 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
1947 u8 reserved_at_10[0x20];
1950 u8 reserved_at_60[0x20];
1953 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
1955 u8 reserved_at_8[0x18];
1958 u8 reserved_at_60[0x20];
1962 MLX5_VIRTQ_STATE_INIT = 0,
1963 MLX5_VIRTQ_STATE_RDY = 1,
1964 MLX5_VIRTQ_STATE_SUSPEND = 2,
1965 MLX5_VIRTQ_STATE_ERROR = 3,
1969 MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),
1970 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),
1971 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),
1974 struct mlx5_ifc_virtio_q_bits {
1975 u8 virtio_q_type[0x8];
1976 u8 reserved_at_8[0x5];
1978 u8 queue_index[0x10];
1979 u8 full_emulation[0x1];
1980 u8 virtio_version_1_0[0x1];
1981 u8 reserved_at_22[0x2];
1982 u8 offload_type[0x4];
1983 u8 event_qpn_or_msix[0x18];
1984 u8 doorbell_stride_idx[0x10];
1985 u8 queue_size[0x10];
1986 u8 device_emulation_id[0x20];
1989 u8 available_addr[0x40];
1990 u8 virtio_q_mkey[0x20];
1991 u8 reserved_at_160[0x20];
1993 u8 umem_1_size[0x20];
1994 u8 umem_1_offset[0x40];
1996 u8 umem_2_size[0x20];
1997 u8 umem_2_offset[0x40];
1999 u8 umem_3_size[0x20];
2000 u8 umem_3_offset[0x40];
2001 u8 reserved_at_300[0x100];
2004 struct mlx5_ifc_virtio_net_q_bits {
2005 u8 modify_field_select[0x40];
2006 u8 reserved_at_40[0x40];
2011 u8 reserved_at_84[0x6];
2012 u8 dirty_bitmap_dump_enable[0x1];
2013 u8 vhost_log_page[0x5];
2014 u8 reserved_at_90[0xc];
2017 u8 tisn_or_qpn[0x18];
2018 u8 dirty_bitmap_mkey[0x20];
2019 u8 dirty_bitmap_size[0x20];
2020 u8 dirty_bitmap_addr[0x40];
2021 u8 hw_available_index[0x10];
2022 u8 hw_used_index[0x10];
2023 u8 reserved_at_160[0xa0];
2024 struct mlx5_ifc_virtio_q_bits virtio_q_context;
2027 struct mlx5_ifc_create_virtq_in_bits {
2028 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2029 struct mlx5_ifc_virtio_net_q_bits virtq;
2032 struct mlx5_ifc_query_virtq_out_bits {
2033 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2034 struct mlx5_ifc_virtio_net_q_bits virtq;
2037 /* CQE format mask. */
2038 #define MLX5E_CQE_FORMAT_MASK 0xc
2041 #define MLX5_OPC_MOD_MPW 0x01
2043 /* Compressed Rx CQE structure. */
2044 struct mlx5_mini_cqe8 {
2046 uint32_t rx_hash_result;
2049 uint16_t stride_idx;
2052 uint16_t wqe_counter;
2053 uint8_t s_wqe_opcode;
2060 /* srTCM PRM flow meter parameters. */
2062 MLX5_FLOW_COLOR_RED = 0,
2063 MLX5_FLOW_COLOR_YELLOW,
2064 MLX5_FLOW_COLOR_GREEN,
2065 MLX5_FLOW_COLOR_UNDEFINED,
2068 /* Maximum value of srTCM metering parameters. */
2069 #define MLX5_SRTCM_CBS_MAX (0xFF * (1ULL << 0x1F))
2070 #define MLX5_SRTCM_CIR_MAX (8 * (1ULL << 30) * 0xFF)
2071 #define MLX5_SRTCM_EBS_MAX 0
2073 /* The bits meter color use. */
2074 #define MLX5_MTR_COLOR_BITS 8
2077 * Convert a user mark to flow mark.
2080 * Mark value to convert.
2083 * Converted mark value.
2085 static inline uint32_t
2086 mlx5_flow_mark_set(uint32_t val)
2091 * Add one to the user value to differentiate un-marked flows from
2092 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
2093 * remains untouched.
2095 if (val != MLX5_FLOW_MARK_DEFAULT)
2097 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
2099 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
2100 * word, byte-swapped by the kernel on little-endian systems. In this
2101 * case, left-shifting the resulting big-endian value ensures the
2102 * least significant 24 bits are retained when converting it back.
2104 ret = rte_cpu_to_be_32(val) >> 8;
2112 * Convert a mark to user mark.
2115 * Mark value to convert.
2118 * Converted mark value.
2120 static inline uint32_t
2121 mlx5_flow_mark_get(uint32_t val)
2124 * Subtract one from the retrieved value. It was added by
2125 * mlx5_flow_mark_set() to distinguish unmarked flows.
2127 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
2128 return (val >> 8) - 1;
2134 #endif /* RTE_PMD_MLX5_PRM_H_ */