1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef __OTX2_NIX_HW_H__
6 #define __OTX2_NIX_HW_H__
10 #define NIX_AF_CFG (0x0ull)
11 #define NIX_AF_STATUS (0x10ull)
12 #define NIX_AF_NDC_CFG (0x18ull)
13 #define NIX_AF_CONST (0x20ull)
14 #define NIX_AF_CONST1 (0x28ull)
15 #define NIX_AF_CONST2 (0x30ull)
16 #define NIX_AF_CONST3 (0x38ull)
17 #define NIX_AF_SQ_CONST (0x40ull)
18 #define NIX_AF_CQ_CONST (0x48ull)
19 #define NIX_AF_RQ_CONST (0x50ull)
20 #define NIX_AF_PSE_CONST (0x60ull)
21 #define NIX_AF_TL1_CONST (0x70ull)
22 #define NIX_AF_TL2_CONST (0x78ull)
23 #define NIX_AF_TL3_CONST (0x80ull)
24 #define NIX_AF_TL4_CONST (0x88ull)
25 #define NIX_AF_MDQ_CONST (0x90ull)
26 #define NIX_AF_MC_MIRROR_CONST (0x98ull)
27 #define NIX_AF_LSO_CFG (0xa8ull)
28 #define NIX_AF_BLK_RST (0xb0ull)
29 #define NIX_AF_TX_TSTMP_CFG (0xc0ull)
30 #define NIX_AF_RX_CFG (0xd0ull)
31 #define NIX_AF_AVG_DELAY (0xe0ull)
32 #define NIX_AF_CINT_DELAY (0xf0ull)
33 #define NIX_AF_RX_MCAST_BASE (0x100ull)
34 #define NIX_AF_RX_MCAST_CFG (0x110ull)
35 #define NIX_AF_RX_MCAST_BUF_BASE (0x120ull)
36 #define NIX_AF_RX_MCAST_BUF_CFG (0x130ull)
37 #define NIX_AF_RX_MIRROR_BUF_BASE (0x140ull)
38 #define NIX_AF_RX_MIRROR_BUF_CFG (0x148ull)
39 #define NIX_AF_LF_RST (0x150ull)
40 #define NIX_AF_GEN_INT (0x160ull)
41 #define NIX_AF_GEN_INT_W1S (0x168ull)
42 #define NIX_AF_GEN_INT_ENA_W1S (0x170ull)
43 #define NIX_AF_GEN_INT_ENA_W1C (0x178ull)
44 #define NIX_AF_ERR_INT (0x180ull)
45 #define NIX_AF_ERR_INT_W1S (0x188ull)
46 #define NIX_AF_ERR_INT_ENA_W1S (0x190ull)
47 #define NIX_AF_ERR_INT_ENA_W1C (0x198ull)
48 #define NIX_AF_RAS (0x1a0ull)
49 #define NIX_AF_RAS_W1S (0x1a8ull)
50 #define NIX_AF_RAS_ENA_W1S (0x1b0ull)
51 #define NIX_AF_RAS_ENA_W1C (0x1b8ull)
52 #define NIX_AF_RVU_INT (0x1c0ull)
53 #define NIX_AF_RVU_INT_W1S (0x1c8ull)
54 #define NIX_AF_RVU_INT_ENA_W1S (0x1d0ull)
55 #define NIX_AF_RVU_INT_ENA_W1C (0x1d8ull)
56 #define NIX_AF_TCP_TIMER (0x1e0ull)
57 #define NIX_AF_RX_DEF_OL2 (0x200ull)
58 #define NIX_AF_RX_DEF_OIP4 (0x210ull)
59 #define NIX_AF_RX_DEF_IIP4 (0x220ull)
60 #define NIX_AF_RX_DEF_OIP6 (0x230ull)
61 #define NIX_AF_RX_DEF_IIP6 (0x240ull)
62 #define NIX_AF_RX_DEF_OTCP (0x250ull)
63 #define NIX_AF_RX_DEF_ITCP (0x260ull)
64 #define NIX_AF_RX_DEF_OUDP (0x270ull)
65 #define NIX_AF_RX_DEF_IUDP (0x280ull)
66 #define NIX_AF_RX_DEF_OSCTP (0x290ull)
67 #define NIX_AF_RX_DEF_ISCTP (0x2a0ull)
68 #define NIX_AF_RX_DEF_IPSECX(a) (0x2b0ull | (uint64_t)(a) << 3)
69 #define NIX_AF_RX_IPSEC_GEN_CFG (0x300ull)
70 #define NIX_AF_RX_CPTX_INST_QSEL(a) (0x320ull | (uint64_t)(a) << 3)
71 #define NIX_AF_RX_CPTX_CREDIT(a) (0x360ull | (uint64_t)(a) << 3)
72 #define NIX_AF_NDC_RX_SYNC (0x3e0ull)
73 #define NIX_AF_NDC_TX_SYNC (0x3f0ull)
74 #define NIX_AF_AQ_CFG (0x400ull)
75 #define NIX_AF_AQ_BASE (0x410ull)
76 #define NIX_AF_AQ_STATUS (0x420ull)
77 #define NIX_AF_AQ_DOOR (0x430ull)
78 #define NIX_AF_AQ_DONE_WAIT (0x440ull)
79 #define NIX_AF_AQ_DONE (0x450ull)
80 #define NIX_AF_AQ_DONE_ACK (0x460ull)
81 #define NIX_AF_AQ_DONE_TIMER (0x470ull)
82 #define NIX_AF_AQ_DONE_ENA_W1S (0x490ull)
83 #define NIX_AF_AQ_DONE_ENA_W1C (0x498ull)
84 #define NIX_AF_RX_LINKX_CFG(a) (0x540ull | (uint64_t)(a) << 16)
85 #define NIX_AF_RX_SW_SYNC (0x550ull)
86 #define NIX_AF_RX_LINKX_WRR_CFG(a) (0x560ull | (uint64_t)(a) << 16)
87 #define NIX_AF_EXPR_TX_FIFO_STATUS (0x640ull)
88 #define NIX_AF_NORM_TX_FIFO_STATUS (0x648ull)
89 #define NIX_AF_SDP_TX_FIFO_STATUS (0x650ull)
90 #define NIX_AF_TX_NPC_CAPTURE_CONFIG (0x660ull)
91 #define NIX_AF_TX_NPC_CAPTURE_INFO (0x668ull)
92 #define NIX_AF_TX_NPC_CAPTURE_RESPX(a) (0x680ull | (uint64_t)(a) << 3)
93 #define NIX_AF_SEB_ACTIVE_CYCLES_PCX(a) (0x6c0ull | (uint64_t)(a) << 3)
94 #define NIX_AF_SMQX_CFG(a) (0x700ull | (uint64_t)(a) << 16)
95 #define NIX_AF_SMQX_HEAD(a) (0x710ull | (uint64_t)(a) << 16)
96 #define NIX_AF_SMQX_TAIL(a) (0x720ull | (uint64_t)(a) << 16)
97 #define NIX_AF_SMQX_STATUS(a) (0x730ull | (uint64_t)(a) << 16)
98 #define NIX_AF_SMQX_NXT_HEAD(a) (0x740ull | (uint64_t)(a) << 16)
99 #define NIX_AF_SQM_ACTIVE_CYCLES_PC (0x770ull)
100 #define NIX_AF_PSE_CHANNEL_LEVEL (0x800ull)
101 #define NIX_AF_PSE_SHAPER_CFG (0x810ull)
102 #define NIX_AF_PSE_ACTIVE_CYCLES_PC (0x8c0ull)
103 #define NIX_AF_MARK_FORMATX_CTL(a) (0x900ull | (uint64_t)(a) << 18)
104 #define NIX_AF_TX_LINKX_NORM_CREDIT(a) (0xa00ull | (uint64_t)(a) << 16)
105 #define NIX_AF_TX_LINKX_EXPR_CREDIT(a) (0xa10ull | (uint64_t)(a) << 16)
106 #define NIX_AF_TX_LINKX_SW_XOFF(a) (0xa20ull | (uint64_t)(a) << 16)
107 #define NIX_AF_TX_LINKX_HW_XOFF(a) (0xa30ull | (uint64_t)(a) << 16)
108 #define NIX_AF_SDP_LINK_CREDIT (0xa40ull)
109 #define NIX_AF_SDP_SW_XOFFX(a) (0xa60ull | (uint64_t)(a) << 3)
110 #define NIX_AF_SDP_HW_XOFFX(a) (0xac0ull | (uint64_t)(a) << 3)
111 #define NIX_AF_TL4X_BP_STATUS(a) (0xb00ull | (uint64_t)(a) << 16)
112 #define NIX_AF_TL4X_SDP_LINK_CFG(a) (0xb10ull | (uint64_t)(a) << 16)
113 #define NIX_AF_TL1X_SCHEDULE(a) (0xc00ull | (uint64_t)(a) << 16)
114 #define NIX_AF_TL1X_SHAPE(a) (0xc10ull | (uint64_t)(a) << 16)
115 #define NIX_AF_TL1X_CIR(a) (0xc20ull | (uint64_t)(a) << 16)
116 #define NIX_AF_TL1X_SHAPE_STATE(a) (0xc50ull | (uint64_t)(a) << 16)
117 #define NIX_AF_TL1X_SW_XOFF(a) (0xc70ull | (uint64_t)(a) << 16)
118 #define NIX_AF_TL1X_TOPOLOGY(a) (0xc80ull | (uint64_t)(a) << 16)
119 #define NIX_AF_TL1X_MD_DEBUG0(a) (0xcc0ull | (uint64_t)(a) << 16)
120 #define NIX_AF_TL1X_MD_DEBUG1(a) (0xcc8ull | (uint64_t)(a) << 16)
121 #define NIX_AF_TL1X_MD_DEBUG2(a) (0xcd0ull | (uint64_t)(a) << 16)
122 #define NIX_AF_TL1X_MD_DEBUG3(a) (0xcd8ull | (uint64_t)(a) << 16)
123 #define NIX_AF_TL1X_DROPPED_PACKETS(a) (0xd20ull | (uint64_t)(a) << 16)
124 #define NIX_AF_TL1X_DROPPED_BYTES(a) (0xd30ull | (uint64_t)(a) << 16)
125 #define NIX_AF_TL1X_RED_PACKETS(a) (0xd40ull | (uint64_t)(a) << 16)
126 #define NIX_AF_TL1X_RED_BYTES(a) (0xd50ull | (uint64_t)(a) << 16)
127 #define NIX_AF_TL1X_YELLOW_PACKETS(a) (0xd60ull | (uint64_t)(a) << 16)
128 #define NIX_AF_TL1X_YELLOW_BYTES(a) (0xd70ull | (uint64_t)(a) << 16)
129 #define NIX_AF_TL1X_GREEN_PACKETS(a) (0xd80ull | (uint64_t)(a) << 16)
130 #define NIX_AF_TL1X_GREEN_BYTES(a) (0xd90ull | (uint64_t)(a) << 16)
131 #define NIX_AF_TL2X_SCHEDULE(a) (0xe00ull | (uint64_t)(a) << 16)
132 #define NIX_AF_TL2X_SHAPE(a) (0xe10ull | (uint64_t)(a) << 16)
133 #define NIX_AF_TL2X_CIR(a) (0xe20ull | (uint64_t)(a) << 16)
134 #define NIX_AF_TL2X_PIR(a) (0xe30ull | (uint64_t)(a) << 16)
135 #define NIX_AF_TL2X_SCHED_STATE(a) (0xe40ull | (uint64_t)(a) << 16)
136 #define NIX_AF_TL2X_SHAPE_STATE(a) (0xe50ull | (uint64_t)(a) << 16)
137 #define NIX_AF_TL2X_SW_XOFF(a) (0xe70ull | (uint64_t)(a) << 16)
138 #define NIX_AF_TL2X_TOPOLOGY(a) (0xe80ull | (uint64_t)(a) << 16)
139 #define NIX_AF_TL2X_PARENT(a) (0xe88ull | (uint64_t)(a) << 16)
140 #define NIX_AF_TL2X_MD_DEBUG0(a) (0xec0ull | (uint64_t)(a) << 16)
141 #define NIX_AF_TL2X_MD_DEBUG1(a) (0xec8ull | (uint64_t)(a) << 16)
142 #define NIX_AF_TL2X_MD_DEBUG2(a) (0xed0ull | (uint64_t)(a) << 16)
143 #define NIX_AF_TL2X_MD_DEBUG3(a) (0xed8ull | (uint64_t)(a) << 16)
144 #define NIX_AF_TL3X_SCHEDULE(a) \
145 (0x1000ull | (uint64_t)(a) << 16)
146 #define NIX_AF_TL3X_SHAPE(a) \
147 (0x1010ull | (uint64_t)(a) << 16)
148 #define NIX_AF_TL3X_CIR(a) \
149 (0x1020ull | (uint64_t)(a) << 16)
150 #define NIX_AF_TL3X_PIR(a) \
151 (0x1030ull | (uint64_t)(a) << 16)
152 #define NIX_AF_TL3X_SCHED_STATE(a) \
153 (0x1040ull | (uint64_t)(a) << 16)
154 #define NIX_AF_TL3X_SHAPE_STATE(a) \
155 (0x1050ull | (uint64_t)(a) << 16)
156 #define NIX_AF_TL3X_SW_XOFF(a) \
157 (0x1070ull | (uint64_t)(a) << 16)
158 #define NIX_AF_TL3X_TOPOLOGY(a) \
159 (0x1080ull | (uint64_t)(a) << 16)
160 #define NIX_AF_TL3X_PARENT(a) \
161 (0x1088ull | (uint64_t)(a) << 16)
162 #define NIX_AF_TL3X_MD_DEBUG0(a) \
163 (0x10c0ull | (uint64_t)(a) << 16)
164 #define NIX_AF_TL3X_MD_DEBUG1(a) \
165 (0x10c8ull | (uint64_t)(a) << 16)
166 #define NIX_AF_TL3X_MD_DEBUG2(a) \
167 (0x10d0ull | (uint64_t)(a) << 16)
168 #define NIX_AF_TL3X_MD_DEBUG3(a) \
169 (0x10d8ull | (uint64_t)(a) << 16)
170 #define NIX_AF_TL4X_SCHEDULE(a) \
171 (0x1200ull | (uint64_t)(a) << 16)
172 #define NIX_AF_TL4X_SHAPE(a) \
173 (0x1210ull | (uint64_t)(a) << 16)
174 #define NIX_AF_TL4X_CIR(a) \
175 (0x1220ull | (uint64_t)(a) << 16)
176 #define NIX_AF_TL4X_PIR(a) \
177 (0x1230ull | (uint64_t)(a) << 16)
178 #define NIX_AF_TL4X_SCHED_STATE(a) \
179 (0x1240ull | (uint64_t)(a) << 16)
180 #define NIX_AF_TL4X_SHAPE_STATE(a) \
181 (0x1250ull | (uint64_t)(a) << 16)
182 #define NIX_AF_TL4X_SW_XOFF(a) \
183 (0x1270ull | (uint64_t)(a) << 16)
184 #define NIX_AF_TL4X_TOPOLOGY(a) \
185 (0x1280ull | (uint64_t)(a) << 16)
186 #define NIX_AF_TL4X_PARENT(a) \
187 (0x1288ull | (uint64_t)(a) << 16)
188 #define NIX_AF_TL4X_MD_DEBUG0(a) \
189 (0x12c0ull | (uint64_t)(a) << 16)
190 #define NIX_AF_TL4X_MD_DEBUG1(a) \
191 (0x12c8ull | (uint64_t)(a) << 16)
192 #define NIX_AF_TL4X_MD_DEBUG2(a) \
193 (0x12d0ull | (uint64_t)(a) << 16)
194 #define NIX_AF_TL4X_MD_DEBUG3(a) \
195 (0x12d8ull | (uint64_t)(a) << 16)
196 #define NIX_AF_MDQX_SCHEDULE(a) \
197 (0x1400ull | (uint64_t)(a) << 16)
198 #define NIX_AF_MDQX_SHAPE(a) \
199 (0x1410ull | (uint64_t)(a) << 16)
200 #define NIX_AF_MDQX_CIR(a) \
201 (0x1420ull | (uint64_t)(a) << 16)
202 #define NIX_AF_MDQX_PIR(a) \
203 (0x1430ull | (uint64_t)(a) << 16)
204 #define NIX_AF_MDQX_SCHED_STATE(a) \
205 (0x1440ull | (uint64_t)(a) << 16)
206 #define NIX_AF_MDQX_SHAPE_STATE(a) \
207 (0x1450ull | (uint64_t)(a) << 16)
208 #define NIX_AF_MDQX_SW_XOFF(a) \
209 (0x1470ull | (uint64_t)(a) << 16)
210 #define NIX_AF_MDQX_PARENT(a) \
211 (0x1480ull | (uint64_t)(a) << 16)
212 #define NIX_AF_MDQX_MD_DEBUG(a) \
213 (0x14c0ull | (uint64_t)(a) << 16)
214 #define NIX_AF_TL3_TL2X_CFG(a) \
215 (0x1600ull | (uint64_t)(a) << 16)
216 #define NIX_AF_TL3_TL2X_BP_STATUS(a) \
217 (0x1610ull | (uint64_t)(a) << 16)
218 #define NIX_AF_TL3_TL2X_LINKX_CFG(a, b) \
219 (0x1700ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3)
220 #define NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(a, b) \
221 (0x1800ull | (uint64_t)(a) << 18 | (uint64_t)(b) << 3)
222 #define NIX_AF_TX_MCASTX(a) \
223 (0x1900ull | (uint64_t)(a) << 15)
224 #define NIX_AF_TX_VTAG_DEFX_CTL(a) \
225 (0x1a00ull | (uint64_t)(a) << 16)
226 #define NIX_AF_TX_VTAG_DEFX_DATA(a) \
227 (0x1a10ull | (uint64_t)(a) << 16)
228 #define NIX_AF_RX_BPIDX_STATUS(a) \
229 (0x1a20ull | (uint64_t)(a) << 17)
230 #define NIX_AF_RX_CHANX_CFG(a) \
231 (0x1a30ull | (uint64_t)(a) << 15)
232 #define NIX_AF_CINT_TIMERX(a) \
233 (0x1a40ull | (uint64_t)(a) << 18)
234 #define NIX_AF_LSO_FORMATX_FIELDX(a, b) \
235 (0x1b00ull | (uint64_t)(a) << 16 | (uint64_t)(b) << 3)
236 #define NIX_AF_LFX_CFG(a) \
237 (0x4000ull | (uint64_t)(a) << 17)
238 #define NIX_AF_LFX_SQS_CFG(a) \
239 (0x4020ull | (uint64_t)(a) << 17)
240 #define NIX_AF_LFX_TX_CFG2(a) \
241 (0x4028ull | (uint64_t)(a) << 17)
242 #define NIX_AF_LFX_SQS_BASE(a) \
243 (0x4030ull | (uint64_t)(a) << 17)
244 #define NIX_AF_LFX_RQS_CFG(a) \
245 (0x4040ull | (uint64_t)(a) << 17)
246 #define NIX_AF_LFX_RQS_BASE(a) \
247 (0x4050ull | (uint64_t)(a) << 17)
248 #define NIX_AF_LFX_CQS_CFG(a) \
249 (0x4060ull | (uint64_t)(a) << 17)
250 #define NIX_AF_LFX_CQS_BASE(a) \
251 (0x4070ull | (uint64_t)(a) << 17)
252 #define NIX_AF_LFX_TX_CFG(a) \
253 (0x4080ull | (uint64_t)(a) << 17)
254 #define NIX_AF_LFX_TX_PARSE_CFG(a) \
255 (0x4090ull | (uint64_t)(a) << 17)
256 #define NIX_AF_LFX_RX_CFG(a) \
257 (0x40a0ull | (uint64_t)(a) << 17)
258 #define NIX_AF_LFX_RSS_CFG(a) \
259 (0x40c0ull | (uint64_t)(a) << 17)
260 #define NIX_AF_LFX_RSS_BASE(a) \
261 (0x40d0ull | (uint64_t)(a) << 17)
262 #define NIX_AF_LFX_QINTS_CFG(a) \
263 (0x4100ull | (uint64_t)(a) << 17)
264 #define NIX_AF_LFX_QINTS_BASE(a) \
265 (0x4110ull | (uint64_t)(a) << 17)
266 #define NIX_AF_LFX_CINTS_CFG(a) \
267 (0x4120ull | (uint64_t)(a) << 17)
268 #define NIX_AF_LFX_CINTS_BASE(a) \
269 (0x4130ull | (uint64_t)(a) << 17)
270 #define NIX_AF_LFX_RX_IPSEC_CFG0(a) \
271 (0x4140ull | (uint64_t)(a) << 17)
272 #define NIX_AF_LFX_RX_IPSEC_CFG1(a) \
273 (0x4148ull | (uint64_t)(a) << 17)
274 #define NIX_AF_LFX_RX_IPSEC_DYNO_CFG(a) \
275 (0x4150ull | (uint64_t)(a) << 17)
276 #define NIX_AF_LFX_RX_IPSEC_DYNO_BASE(a) \
277 (0x4158ull | (uint64_t)(a) << 17)
278 #define NIX_AF_LFX_RX_IPSEC_SA_BASE(a) \
279 (0x4170ull | (uint64_t)(a) << 17)
280 #define NIX_AF_LFX_TX_STATUS(a) \
281 (0x4180ull | (uint64_t)(a) << 17)
282 #define NIX_AF_LFX_RX_VTAG_TYPEX(a, b) \
283 (0x4200ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3)
284 #define NIX_AF_LFX_LOCKX(a, b) \
285 (0x4300ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3)
286 #define NIX_AF_LFX_TX_STATX(a, b) \
287 (0x4400ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3)
288 #define NIX_AF_LFX_RX_STATX(a, b) \
289 (0x4500ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3)
290 #define NIX_AF_LFX_RSS_GRPX(a, b) \
291 (0x4600ull | (uint64_t)(a) << 17 | (uint64_t)(b) << 3)
292 #define NIX_AF_RX_NPC_MC_RCV (0x4700ull)
293 #define NIX_AF_RX_NPC_MC_DROP (0x4710ull)
294 #define NIX_AF_RX_NPC_MIRROR_RCV (0x4720ull)
295 #define NIX_AF_RX_NPC_MIRROR_DROP (0x4730ull)
296 #define NIX_AF_RX_ACTIVE_CYCLES_PCX(a) \
297 (0x4800ull | (uint64_t)(a) << 16)
298 #define NIX_PRIV_AF_INT_CFG (0x8000000ull)
299 #define NIX_PRIV_LFX_CFG(a) \
300 (0x8000010ull | (uint64_t)(a) << 8)
301 #define NIX_PRIV_LFX_INT_CFG(a) \
302 (0x8000020ull | (uint64_t)(a) << 8)
303 #define NIX_AF_RVU_LF_CFG_DEBUG (0x8000030ull)
305 #define NIX_LF_RX_SECRETX(a) (0x0ull | (uint64_t)(a) << 3)
306 #define NIX_LF_CFG (0x100ull)
307 #define NIX_LF_GINT (0x200ull)
308 #define NIX_LF_GINT_W1S (0x208ull)
309 #define NIX_LF_GINT_ENA_W1C (0x210ull)
310 #define NIX_LF_GINT_ENA_W1S (0x218ull)
311 #define NIX_LF_ERR_INT (0x220ull)
312 #define NIX_LF_ERR_INT_W1S (0x228ull)
313 #define NIX_LF_ERR_INT_ENA_W1C (0x230ull)
314 #define NIX_LF_ERR_INT_ENA_W1S (0x238ull)
315 #define NIX_LF_RAS (0x240ull)
316 #define NIX_LF_RAS_W1S (0x248ull)
317 #define NIX_LF_RAS_ENA_W1C (0x250ull)
318 #define NIX_LF_RAS_ENA_W1S (0x258ull)
319 #define NIX_LF_SQ_OP_ERR_DBG (0x260ull)
320 #define NIX_LF_MNQ_ERR_DBG (0x270ull)
321 #define NIX_LF_SEND_ERR_DBG (0x280ull)
322 #define NIX_LF_TX_STATX(a) (0x300ull | (uint64_t)(a) << 3)
323 #define NIX_LF_RX_STATX(a) (0x400ull | (uint64_t)(a) << 3)
324 #define NIX_LF_OP_SENDX(a) (0x800ull | (uint64_t)(a) << 3)
325 #define NIX_LF_RQ_OP_INT (0x900ull)
326 #define NIX_LF_RQ_OP_OCTS (0x910ull)
327 #define NIX_LF_RQ_OP_PKTS (0x920ull)
328 #define NIX_LF_RQ_OP_DROP_OCTS (0x930ull)
329 #define NIX_LF_RQ_OP_DROP_PKTS (0x940ull)
330 #define NIX_LF_RQ_OP_RE_PKTS (0x950ull)
331 #define NIX_LF_OP_IPSEC_DYNO_CNT (0x980ull)
332 #define NIX_LF_SQ_OP_INT (0xa00ull)
333 #define NIX_LF_SQ_OP_OCTS (0xa10ull)
334 #define NIX_LF_SQ_OP_PKTS (0xa20ull)
335 #define NIX_LF_SQ_OP_STATUS (0xa30ull)
336 #define NIX_LF_SQ_OP_DROP_OCTS (0xa40ull)
337 #define NIX_LF_SQ_OP_DROP_PKTS (0xa50ull)
338 #define NIX_LF_CQ_OP_INT (0xb00ull)
339 #define NIX_LF_CQ_OP_DOOR (0xb30ull)
340 #define NIX_LF_CQ_OP_STATUS (0xb40ull)
341 #define NIX_LF_QINTX_CNT(a) (0xc00ull | (uint64_t)(a) << 12)
342 #define NIX_LF_QINTX_INT(a) (0xc10ull | (uint64_t)(a) << 12)
343 #define NIX_LF_QINTX_ENA_W1S(a) (0xc20ull | (uint64_t)(a) << 12)
344 #define NIX_LF_QINTX_ENA_W1C(a) (0xc30ull | (uint64_t)(a) << 12)
345 #define NIX_LF_CINTX_CNT(a) (0xd00ull | (uint64_t)(a) << 12)
346 #define NIX_LF_CINTX_WAIT(a) (0xd10ull | (uint64_t)(a) << 12)
347 #define NIX_LF_CINTX_INT(a) (0xd20ull | (uint64_t)(a) << 12)
348 #define NIX_LF_CINTX_INT_W1S(a) (0xd30ull | (uint64_t)(a) << 12)
349 #define NIX_LF_CINTX_ENA_W1S(a) (0xd40ull | (uint64_t)(a) << 12)
350 #define NIX_LF_CINTX_ENA_W1C(a) (0xd50ull | (uint64_t)(a) << 12)
355 #define NIX_TX_VTAGOP_NOP (0x0ull)
356 #define NIX_TX_VTAGOP_INSERT (0x1ull)
357 #define NIX_TX_VTAGOP_REPLACE (0x2ull)
359 #define NIX_TX_ACTIONOP_DROP (0x0ull)
360 #define NIX_TX_ACTIONOP_UCAST_DEFAULT (0x1ull)
361 #define NIX_TX_ACTIONOP_UCAST_CHAN (0x2ull)
362 #define NIX_TX_ACTIONOP_MCAST (0x3ull)
363 #define NIX_TX_ACTIONOP_DROP_VIOL (0x5ull)
365 #define NIX_INTF_RX (0x0ull)
366 #define NIX_INTF_TX (0x1ull)
368 #define NIX_TXLAYER_OL3 (0x0ull)
369 #define NIX_TXLAYER_OL4 (0x1ull)
370 #define NIX_TXLAYER_IL3 (0x2ull)
371 #define NIX_TXLAYER_IL4 (0x3ull)
373 #define NIX_SUBDC_NOP (0x0ull)
374 #define NIX_SUBDC_EXT (0x1ull)
375 #define NIX_SUBDC_CRC (0x2ull)
376 #define NIX_SUBDC_IMM (0x3ull)
377 #define NIX_SUBDC_SG (0x4ull)
378 #define NIX_SUBDC_MEM (0x5ull)
379 #define NIX_SUBDC_JUMP (0x6ull)
380 #define NIX_SUBDC_WORK (0x7ull)
381 #define NIX_SUBDC_SOD (0xfull)
383 #define NIX_STYPE_STF (0x0ull)
384 #define NIX_STYPE_STT (0x1ull)
385 #define NIX_STYPE_STP (0x2ull)
387 #define NIX_STAT_LF_TX_TX_UCAST (0x0ull)
388 #define NIX_STAT_LF_TX_TX_BCAST (0x1ull)
389 #define NIX_STAT_LF_TX_TX_MCAST (0x2ull)
390 #define NIX_STAT_LF_TX_TX_DROP (0x3ull)
391 #define NIX_STAT_LF_TX_TX_OCTS (0x4ull)
393 #define NIX_STAT_LF_RX_RX_OCTS (0x0ull)
394 #define NIX_STAT_LF_RX_RX_UCAST (0x1ull)
395 #define NIX_STAT_LF_RX_RX_BCAST (0x2ull)
396 #define NIX_STAT_LF_RX_RX_MCAST (0x3ull)
397 #define NIX_STAT_LF_RX_RX_DROP (0x4ull)
398 #define NIX_STAT_LF_RX_RX_DROP_OCTS (0x5ull)
399 #define NIX_STAT_LF_RX_RX_FCS (0x6ull)
400 #define NIX_STAT_LF_RX_RX_ERR (0x7ull)
401 #define NIX_STAT_LF_RX_RX_DRP_BCAST (0x8ull)
402 #define NIX_STAT_LF_RX_RX_DRP_MCAST (0x9ull)
403 #define NIX_STAT_LF_RX_RX_DRP_L3BCAST (0xaull)
404 #define NIX_STAT_LF_RX_RX_DRP_L3MCAST (0xbull)
406 #define NIX_SQOPERR_SQ_OOR (0x0ull)
407 #define NIX_SQOPERR_SQ_CTX_FAULT (0x1ull)
408 #define NIX_SQOPERR_SQ_CTX_POISON (0x2ull)
409 #define NIX_SQOPERR_SQ_DISABLED (0x3ull)
410 #define NIX_SQOPERR_MAX_SQE_SIZE_ERR (0x4ull)
411 #define NIX_SQOPERR_SQE_OFLOW (0x5ull)
412 #define NIX_SQOPERR_SQB_NULL (0x6ull)
413 #define NIX_SQOPERR_SQB_FAULT (0x7ull)
415 #define NIX_XQESZ_W64 (0x0ull)
416 #define NIX_XQESZ_W16 (0x1ull)
418 #define NIX_VTAGSIZE_T4 (0x0ull)
419 #define NIX_VTAGSIZE_T8 (0x1ull)
421 #define NIX_RX_ACTIONOP_DROP (0x0ull)
422 #define NIX_RX_ACTIONOP_UCAST (0x1ull)
423 #define NIX_RX_ACTIONOP_UCAST_IPSEC (0x2ull)
424 #define NIX_RX_ACTIONOP_MCAST (0x3ull)
425 #define NIX_RX_ACTIONOP_RSS (0x4ull)
426 #define NIX_RX_ACTIONOP_PF_FUNC_DROP (0x5ull)
427 #define NIX_RX_ACTIONOP_MIRROR (0x6ull)
429 #define NIX_RX_VTAGACTION_VTAG0_RELPTR (0x0ull)
430 #define NIX_RX_VTAGACTION_VTAG1_RELPTR (0x4ull)
431 #define NIX_RX_VTAGACTION_VTAG_VALID (0x1ull)
432 #define NIX_TX_VTAGACTION_VTAG0_RELPTR \
433 (sizeof(struct nix_inst_hdr_s) + 2 * 6)
434 #define NIX_TX_VTAGACTION_VTAG1_RELPTR \
435 (sizeof(struct nix_inst_hdr_s) + 2 * 6 + 4)
436 #define NIX_RQINT_DROP (0x0ull)
437 #define NIX_RQINT_RED (0x1ull)
438 #define NIX_RQINT_R2 (0x2ull)
439 #define NIX_RQINT_R3 (0x3ull)
440 #define NIX_RQINT_R4 (0x4ull)
441 #define NIX_RQINT_R5 (0x5ull)
442 #define NIX_RQINT_R6 (0x6ull)
443 #define NIX_RQINT_R7 (0x7ull)
445 #define NIX_MAXSQESZ_W16 (0x0ull)
446 #define NIX_MAXSQESZ_W8 (0x1ull)
448 #define NIX_LSOALG_NOP (0x0ull)
449 #define NIX_LSOALG_ADD_SEGNUM (0x1ull)
450 #define NIX_LSOALG_ADD_PAYLEN (0x2ull)
451 #define NIX_LSOALG_ADD_OFFSET (0x3ull)
452 #define NIX_LSOALG_TCP_FLAGS (0x4ull)
454 #define NIX_MNQERR_SQ_CTX_FAULT (0x0ull)
455 #define NIX_MNQERR_SQ_CTX_POISON (0x1ull)
456 #define NIX_MNQERR_SQB_FAULT (0x2ull)
457 #define NIX_MNQERR_SQB_POISON (0x3ull)
458 #define NIX_MNQERR_TOTAL_ERR (0x4ull)
459 #define NIX_MNQERR_LSO_ERR (0x5ull)
460 #define NIX_MNQERR_CQ_QUERY_ERR (0x6ull)
461 #define NIX_MNQERR_MAX_SQE_SIZE_ERR (0x7ull)
462 #define NIX_MNQERR_MAXLEN_ERR (0x8ull)
463 #define NIX_MNQERR_SQE_SIZEM1_ZERO (0x9ull)
465 #define NIX_MDTYPE_RSVD (0x0ull)
466 #define NIX_MDTYPE_FLUSH (0x1ull)
467 #define NIX_MDTYPE_PMD (0x2ull)
469 #define NIX_NDC_TX_PORT_LMT (0x0ull)
470 #define NIX_NDC_TX_PORT_ENQ (0x1ull)
471 #define NIX_NDC_TX_PORT_MNQ (0x2ull)
472 #define NIX_NDC_TX_PORT_DEQ (0x3ull)
473 #define NIX_NDC_TX_PORT_DMA (0x4ull)
474 #define NIX_NDC_TX_PORT_XQE (0x5ull)
476 #define NIX_NDC_RX_PORT_AQ (0x0ull)
477 #define NIX_NDC_RX_PORT_CQ (0x1ull)
478 #define NIX_NDC_RX_PORT_CINT (0x2ull)
479 #define NIX_NDC_RX_PORT_MC (0x3ull)
480 #define NIX_NDC_RX_PORT_PKT (0x4ull)
481 #define NIX_NDC_RX_PORT_RQ (0x5ull)
483 #define NIX_RE_OPCODE_RE_NONE (0x0ull)
484 #define NIX_RE_OPCODE_RE_PARTIAL (0x1ull)
485 #define NIX_RE_OPCODE_RE_JABBER (0x2ull)
486 #define NIX_RE_OPCODE_RE_FCS (0x7ull)
487 #define NIX_RE_OPCODE_RE_FCS_RCV (0x8ull)
488 #define NIX_RE_OPCODE_RE_TERMINATE (0x9ull)
489 #define NIX_RE_OPCODE_RE_RX_CTL (0xbull)
490 #define NIX_RE_OPCODE_RE_SKIP (0xcull)
491 #define NIX_RE_OPCODE_RE_DMAPKT (0xfull)
492 #define NIX_RE_OPCODE_UNDERSIZE (0x10ull)
493 #define NIX_RE_OPCODE_OVERSIZE (0x11ull)
494 #define NIX_RE_OPCODE_OL2_LENMISM (0x12ull)
496 #define NIX_REDALG_STD (0x0ull)
497 #define NIX_REDALG_SEND (0x1ull)
498 #define NIX_REDALG_STALL (0x2ull)
499 #define NIX_REDALG_DISCARD (0x3ull)
501 #define NIX_RX_MCOP_RQ (0x0ull)
502 #define NIX_RX_MCOP_RSS (0x1ull)
504 #define NIX_RX_PERRCODE_NPC_RESULT_ERR (0x2ull)
505 #define NIX_RX_PERRCODE_MCAST_FAULT (0x4ull)
506 #define NIX_RX_PERRCODE_MIRROR_FAULT (0x5ull)
507 #define NIX_RX_PERRCODE_MCAST_POISON (0x6ull)
508 #define NIX_RX_PERRCODE_MIRROR_POISON (0x7ull)
509 #define NIX_RX_PERRCODE_DATA_FAULT (0x8ull)
510 #define NIX_RX_PERRCODE_MEMOUT (0x9ull)
511 #define NIX_RX_PERRCODE_BUFS_OFLOW (0xaull)
512 #define NIX_RX_PERRCODE_OL3_LEN (0x10ull)
513 #define NIX_RX_PERRCODE_OL4_LEN (0x11ull)
514 #define NIX_RX_PERRCODE_OL4_CHK (0x12ull)
515 #define NIX_RX_PERRCODE_OL4_PORT (0x13ull)
516 #define NIX_RX_PERRCODE_IL3_LEN (0x20ull)
517 #define NIX_RX_PERRCODE_IL4_LEN (0x21ull)
518 #define NIX_RX_PERRCODE_IL4_CHK (0x22ull)
519 #define NIX_RX_PERRCODE_IL4_PORT (0x23ull)
521 #define NIX_SENDCRCALG_CRC32 (0x0ull)
522 #define NIX_SENDCRCALG_CRC32C (0x1ull)
523 #define NIX_SENDCRCALG_ONES16 (0x2ull)
525 #define NIX_SENDL3TYPE_NONE (0x0ull)
526 #define NIX_SENDL3TYPE_IP4 (0x2ull)
527 #define NIX_SENDL3TYPE_IP4_CKSUM (0x3ull)
528 #define NIX_SENDL3TYPE_IP6 (0x4ull)
530 #define NIX_SENDL4TYPE_NONE (0x0ull)
531 #define NIX_SENDL4TYPE_TCP_CKSUM (0x1ull)
532 #define NIX_SENDL4TYPE_SCTP_CKSUM (0x2ull)
533 #define NIX_SENDL4TYPE_UDP_CKSUM (0x3ull)
535 #define NIX_SENDLDTYPE_LDD (0x0ull)
536 #define NIX_SENDLDTYPE_LDT (0x1ull)
537 #define NIX_SENDLDTYPE_LDWB (0x2ull)
539 #define NIX_SENDMEMALG_SET (0x0ull)
540 #define NIX_SENDMEMALG_SETTSTMP (0x1ull)
541 #define NIX_SENDMEMALG_SETRSLT (0x2ull)
542 #define NIX_SENDMEMALG_ADD (0x8ull)
543 #define NIX_SENDMEMALG_SUB (0x9ull)
544 #define NIX_SENDMEMALG_ADDLEN (0xaull)
545 #define NIX_SENDMEMALG_SUBLEN (0xbull)
546 #define NIX_SENDMEMALG_ADDMBUF (0xcull)
547 #define NIX_SENDMEMALG_SUBMBUF (0xdull)
549 #define NIX_SENDMEMDSZ_B64 (0x0ull)
550 #define NIX_SENDMEMDSZ_B32 (0x1ull)
551 #define NIX_SENDMEMDSZ_B16 (0x2ull)
552 #define NIX_SENDMEMDSZ_B8 (0x3ull)
554 #define NIX_SEND_STATUS_GOOD (0x0ull)
555 #define NIX_SEND_STATUS_SQ_CTX_FAULT (0x1ull)
556 #define NIX_SEND_STATUS_SQ_CTX_POISON (0x2ull)
557 #define NIX_SEND_STATUS_SQB_FAULT (0x3ull)
558 #define NIX_SEND_STATUS_SQB_POISON (0x4ull)
559 #define NIX_SEND_STATUS_SEND_HDR_ERR (0x5ull)
560 #define NIX_SEND_STATUS_SEND_EXT_ERR (0x6ull)
561 #define NIX_SEND_STATUS_JUMP_FAULT (0x7ull)
562 #define NIX_SEND_STATUS_JUMP_POISON (0x8ull)
563 #define NIX_SEND_STATUS_SEND_CRC_ERR (0x10ull)
564 #define NIX_SEND_STATUS_SEND_IMM_ERR (0x11ull)
565 #define NIX_SEND_STATUS_SEND_SG_ERR (0x12ull)
566 #define NIX_SEND_STATUS_SEND_MEM_ERR (0x13ull)
567 #define NIX_SEND_STATUS_INVALID_SUBDC (0x14ull)
568 #define NIX_SEND_STATUS_SUBDC_ORDER_ERR (0x15ull)
569 #define NIX_SEND_STATUS_DATA_FAULT (0x16ull)
570 #define NIX_SEND_STATUS_DATA_POISON (0x17ull)
571 #define NIX_SEND_STATUS_NPC_DROP_ACTION (0x20ull)
572 #define NIX_SEND_STATUS_LOCK_VIOL (0x21ull)
573 #define NIX_SEND_STATUS_NPC_UCAST_CHAN_ERR (0x22ull)
574 #define NIX_SEND_STATUS_NPC_MCAST_CHAN_ERR (0x23ull)
575 #define NIX_SEND_STATUS_NPC_MCAST_ABORT (0x24ull)
576 #define NIX_SEND_STATUS_NPC_VTAG_PTR_ERR (0x25ull)
577 #define NIX_SEND_STATUS_NPC_VTAG_SIZE_ERR (0x26ull)
578 #define NIX_SEND_STATUS_SEND_MEM_FAULT (0x27ull)
580 #define NIX_SQINT_LMT_ERR (0x0ull)
581 #define NIX_SQINT_MNQ_ERR (0x1ull)
582 #define NIX_SQINT_SEND_ERR (0x2ull)
583 #define NIX_SQINT_SQB_ALLOC_FAIL (0x3ull)
585 #define NIX_XQE_TYPE_INVALID (0x0ull)
586 #define NIX_XQE_TYPE_RX (0x1ull)
587 #define NIX_XQE_TYPE_RX_IPSECS (0x2ull)
588 #define NIX_XQE_TYPE_RX_IPSECH (0x3ull)
589 #define NIX_XQE_TYPE_RX_IPSECD (0x4ull)
590 #define NIX_XQE_TYPE_SEND (0x8ull)
592 #define NIX_AQ_COMP_NOTDONE (0x0ull)
593 #define NIX_AQ_COMP_GOOD (0x1ull)
594 #define NIX_AQ_COMP_SWERR (0x2ull)
595 #define NIX_AQ_COMP_CTX_POISON (0x3ull)
596 #define NIX_AQ_COMP_CTX_FAULT (0x4ull)
597 #define NIX_AQ_COMP_LOCKERR (0x5ull)
598 #define NIX_AQ_COMP_SQB_ALLOC_FAIL (0x6ull)
600 #define NIX_AF_INT_VEC_RVU (0x0ull)
601 #define NIX_AF_INT_VEC_GEN (0x1ull)
602 #define NIX_AF_INT_VEC_AQ_DONE (0x2ull)
603 #define NIX_AF_INT_VEC_AF_ERR (0x3ull)
604 #define NIX_AF_INT_VEC_POISON (0x4ull)
606 #define NIX_AQINT_GEN_RX_MCAST_DROP (0x0ull)
607 #define NIX_AQINT_GEN_RX_MIRROR_DROP (0x1ull)
608 #define NIX_AQINT_GEN_TL1_DRAIN (0x3ull)
609 #define NIX_AQINT_GEN_SMQ_FLUSH_DONE (0x4ull)
611 #define NIX_AQ_INSTOP_NOP (0x0ull)
612 #define NIX_AQ_INSTOP_INIT (0x1ull)
613 #define NIX_AQ_INSTOP_WRITE (0x2ull)
614 #define NIX_AQ_INSTOP_READ (0x3ull)
615 #define NIX_AQ_INSTOP_LOCK (0x4ull)
616 #define NIX_AQ_INSTOP_UNLOCK (0x5ull)
618 #define NIX_AQ_CTYPE_RQ (0x0ull)
619 #define NIX_AQ_CTYPE_SQ (0x1ull)
620 #define NIX_AQ_CTYPE_CQ (0x2ull)
621 #define NIX_AQ_CTYPE_MCE (0x3ull)
622 #define NIX_AQ_CTYPE_RSS (0x4ull)
623 #define NIX_AQ_CTYPE_DYNO (0x5ull)
625 #define NIX_COLORRESULT_GREEN (0x0ull)
626 #define NIX_COLORRESULT_YELLOW (0x1ull)
627 #define NIX_COLORRESULT_RED_SEND (0x2ull)
628 #define NIX_COLORRESULT_RED_DROP (0x3ull)
630 #define NIX_CHAN_LBKX_CHX(a, b) \
631 (0x000ull | ((uint64_t)(a) << 8) | (uint64_t)(b))
632 #define NIX_CHAN_R4 (0x400ull)
633 #define NIX_CHAN_R5 (0x500ull)
634 #define NIX_CHAN_R6 (0x600ull)
635 #define NIX_CHAN_SDP_CH_END (0x7ffull)
636 #define NIX_CHAN_SDP_CH_START (0x700ull)
637 #define NIX_CHAN_CGXX_LMACX_CHX(a, b, c) \
638 (0x800ull | ((uint64_t)(a) << 8) | ((uint64_t)(b) << 4) | \
641 #define NIX_INTF_SDP (0x4ull)
642 #define NIX_INTF_CGX0 (0x0ull)
643 #define NIX_INTF_CGX1 (0x1ull)
644 #define NIX_INTF_CGX2 (0x2ull)
645 #define NIX_INTF_LBK0 (0x3ull)
647 #define NIX_CQERRINT_DOOR_ERR (0x0ull)
648 #define NIX_CQERRINT_WR_FULL (0x1ull)
649 #define NIX_CQERRINT_CQE_FAULT (0x2ull)
651 #define NIX_LF_INT_VEC_GINT (0x80ull)
652 #define NIX_LF_INT_VEC_ERR_INT (0x81ull)
653 #define NIX_LF_INT_VEC_POISON (0x82ull)
654 #define NIX_LF_INT_VEC_QINT_END (0x3full)
655 #define NIX_LF_INT_VEC_QINT_START (0x0ull)
656 #define NIX_LF_INT_VEC_CINT_END (0x7full)
657 #define NIX_LF_INT_VEC_CINT_START (0x40ull)
659 /* Enums definitions */
661 /* Structures definitions */
663 /* NIX admin queue instruction structure */
664 struct nix_aq_inst_s {
668 uint64_t rsvd_23_15 : 9;
669 uint64_t cindex : 20;
670 uint64_t rsvd_62_44 : 19;
671 uint64_t doneint : 1;
672 uint64_t res_addr : 64; /* W1 */
675 /* NIX admin queue result structure */
676 struct nix_aq_res_s {
679 uint64_t compcode : 8;
680 uint64_t doneint : 1;
681 uint64_t rsvd_63_17 : 47;
682 uint64_t rsvd_127_64 : 64; /* W1 */
685 /* NIX completion interrupt context hardware structure */
686 struct nix_cint_hw_s {
687 uint64_t ecount : 32;
688 uint64_t qcount : 16;
691 uint64_t timer_idx : 8;
692 uint64_t rsvd_63_58 : 6;
693 uint64_t ecount_wait : 32;
694 uint64_t qcount_wait : 16;
695 uint64_t time_wait : 8;
696 uint64_t rsvd_127_120 : 8;
699 /* NIX completion queue entry header structure */
700 struct nix_cqe_hdr_s {
703 uint64_t rsvd_57_52 : 6;
705 uint64_t cqe_type : 4;
708 /* NIX completion queue context structure */
709 struct nix_cq_ctx_s {
710 uint64_t base : 64;/* W0 */
711 uint64_t rsvd_67_64 : 4;
713 uint64_t rsvd_71_69 : 3;
715 uint64_t rsvd_83_81 : 3;
716 uint64_t qint_idx : 7;
718 uint64_t cint_idx : 7;
719 uint64_t avg_con : 9;
723 uint64_t avg_level : 8;
724 uint64_t update_time : 16;
727 uint64_t drop_ena : 1;
729 uint64_t rsvd_211_210 : 2;
730 uint64_t substream : 20;
731 uint64_t caching : 1;
732 uint64_t rsvd_235_233 : 3;
734 uint64_t cq_err_int : 8;
735 uint64_t cq_err_int_ena : 8;
738 /* NIX instruction header structure */
739 struct nix_inst_hdr_s {
740 uint64_t pf_func : 16;
742 uint64_t rsvd_63_36 : 28;
745 /* NIX i/o virtual address structure */
747 uint64_t addr : 64; /* W0 */
750 /* NIX IPsec dynamic ordering counter structure */
751 struct nix_ipsec_dyno_s {
752 uint32_t count : 32; /* W0 */
755 /* NIX memory value structure */
756 struct nix_mem_result_s {
759 uint64_t rsvd_63_3 : 61;
762 /* NIX statistics operation write data structure */
763 struct nix_op_q_wdata_s {
764 uint64_t rsvd_31_0 : 32;
766 uint64_t rsvd_63_52 : 12;
769 /* NIX queue interrupt context hardware structure */
770 struct nix_qint_hw_s {
772 uint32_t rsvd_30_22 : 9;
776 /* NIX receive queue context structure */
777 struct nix_rq_ctx_hw_s {
779 uint64_t sso_ena : 1;
780 uint64_t ipsech_ena : 1;
781 uint64_t ena_wqwd : 1;
783 uint64_t substream : 20;
784 uint64_t wqe_aura : 20;
785 uint64_t spb_aura : 20;
786 uint64_t lpb_aura : 20;
787 uint64_t sso_grp : 10;
789 uint64_t pb_caching : 2;
790 uint64_t wqe_caching : 1;
791 uint64_t xqe_drop_ena : 1;
792 uint64_t spb_drop_ena : 1;
793 uint64_t lpb_drop_ena : 1;
794 uint64_t wqe_skip : 2;
795 uint64_t rsvd_127_124 : 4;
796 uint64_t rsvd_139_128 : 12;
797 uint64_t spb_sizem1 : 6;
798 uint64_t rsvd_150_146 : 5;
799 uint64_t spb_ena : 1;
800 uint64_t lpb_sizem1 : 12;
801 uint64_t first_skip : 7;
802 uint64_t rsvd_171 : 1;
803 uint64_t later_skip : 6;
804 uint64_t xqe_imm_size : 6;
805 uint64_t rsvd_189_184 : 6;
806 uint64_t xqe_imm_copy : 1;
807 uint64_t xqe_hdr_split : 1;
808 uint64_t xqe_drop : 8;
809 uint64_t xqe_pass : 8;
810 uint64_t wqe_pool_drop : 8;
811 uint64_t wqe_pool_pass : 8;
812 uint64_t spb_aura_drop : 8;
813 uint64_t spb_aura_pass : 8;
814 uint64_t spb_pool_drop : 8;
815 uint64_t spb_pool_pass : 8;
816 uint64_t lpb_aura_drop : 8;
817 uint64_t lpb_aura_pass : 8;
818 uint64_t lpb_pool_drop : 8;
819 uint64_t lpb_pool_pass : 8;
820 uint64_t rsvd_319_288 : 32;
822 uint64_t good_utag : 8;
823 uint64_t bad_utag : 8;
824 uint64_t flow_tagw : 6;
825 uint64_t rsvd_383_366 : 18;
827 uint64_t rsvd_447_432 : 16;
829 uint64_t rsvd_511_496 : 16;
830 uint64_t drop_octs : 48;
831 uint64_t rsvd_575_560 : 16;
832 uint64_t drop_pkts : 48;
833 uint64_t rsvd_639_624 : 16;
834 uint64_t re_pkts : 48;
835 uint64_t rsvd_702_688 : 15;
836 uint64_t ena_copy : 1;
837 uint64_t rsvd_739_704 : 36;
839 uint64_t rq_int_ena : 8;
840 uint64_t qint_idx : 7;
841 uint64_t rsvd_767_763 : 5;
842 uint64_t rsvd_831_768 : 64;/* W12 */
843 uint64_t rsvd_895_832 : 64;/* W13 */
844 uint64_t rsvd_959_896 : 64;/* W14 */
845 uint64_t rsvd_1023_960 : 64;/* W15 */
848 /* NIX receive queue context structure */
849 struct nix_rq_ctx_s {
851 uint64_t sso_ena : 1;
852 uint64_t ipsech_ena : 1;
853 uint64_t ena_wqwd : 1;
855 uint64_t substream : 20;
856 uint64_t wqe_aura : 20;
857 uint64_t spb_aura : 20;
858 uint64_t lpb_aura : 20;
859 uint64_t sso_grp : 10;
861 uint64_t pb_caching : 2;
862 uint64_t wqe_caching : 1;
863 uint64_t xqe_drop_ena : 1;
864 uint64_t spb_drop_ena : 1;
865 uint64_t lpb_drop_ena : 1;
866 uint64_t rsvd_127_122 : 6;
867 uint64_t rsvd_139_128 : 12;
868 uint64_t spb_sizem1 : 6;
869 uint64_t wqe_skip : 2;
870 uint64_t rsvd_150_148 : 3;
871 uint64_t spb_ena : 1;
872 uint64_t lpb_sizem1 : 12;
873 uint64_t first_skip : 7;
874 uint64_t rsvd_171 : 1;
875 uint64_t later_skip : 6;
876 uint64_t xqe_imm_size : 6;
877 uint64_t rsvd_189_184 : 6;
878 uint64_t xqe_imm_copy : 1;
879 uint64_t xqe_hdr_split : 1;
880 uint64_t xqe_drop : 8;
881 uint64_t xqe_pass : 8;
882 uint64_t wqe_pool_drop : 8;
883 uint64_t wqe_pool_pass : 8;
884 uint64_t spb_aura_drop : 8;
885 uint64_t spb_aura_pass : 8;
886 uint64_t spb_pool_drop : 8;
887 uint64_t spb_pool_pass : 8;
888 uint64_t lpb_aura_drop : 8;
889 uint64_t lpb_aura_pass : 8;
890 uint64_t lpb_pool_drop : 8;
891 uint64_t lpb_pool_pass : 8;
892 uint64_t rsvd_291_288 : 4;
894 uint64_t rq_int_ena : 8;
895 uint64_t qint_idx : 7;
896 uint64_t rsvd_319_315 : 5;
898 uint64_t good_utag : 8;
899 uint64_t bad_utag : 8;
900 uint64_t flow_tagw : 6;
901 uint64_t rsvd_383_366 : 18;
903 uint64_t rsvd_447_432 : 16;
905 uint64_t rsvd_511_496 : 16;
906 uint64_t drop_octs : 48;
907 uint64_t rsvd_575_560 : 16;
908 uint64_t drop_pkts : 48;
909 uint64_t rsvd_639_624 : 16;
910 uint64_t re_pkts : 48;
911 uint64_t rsvd_703_688 : 16;
912 uint64_t rsvd_767_704 : 64;/* W11 */
913 uint64_t rsvd_831_768 : 64;/* W12 */
914 uint64_t rsvd_895_832 : 64;/* W13 */
915 uint64_t rsvd_959_896 : 64;/* W14 */
916 uint64_t rsvd_1023_960 : 64;/* W15 */
919 /* NIX receive side scaling entry structure */
922 uint32_t rsvd_31_20 : 12;
925 /* NIX receive action structure */
926 struct nix_rx_action_s {
928 uint64_t pf_func : 16;
930 uint64_t match_id : 16;
931 uint64_t flow_key_alg : 5;
932 uint64_t rsvd_63_61 : 3;
935 /* NIX receive immediate sub descriptor structure */
936 struct nix_rx_imm_s {
939 uint64_t rsvd_59_19 : 41;
943 /* NIX receive multicast/mirror entry structure */
944 struct nix_rx_mce_s {
949 uint64_t rsvd_31_24 : 8;
950 uint64_t pf_func : 16;
954 /* NIX receive parse structure */
955 struct nix_rx_parse_s {
957 uint64_t desc_sizem1 : 5;
958 uint64_t imm_copy : 1;
959 uint64_t express : 1;
962 uint64_t errcode : 8;
971 uint64_t pkt_lenm1 : 16;
976 uint64_t vtag0_valid : 1;
977 uint64_t vtag0_gone : 1;
978 uint64_t vtag1_valid : 1;
979 uint64_t vtag1_gone : 1;
981 uint64_t rsvd_95_94 : 2;
982 uint64_t vtag0_tci : 16;
983 uint64_t vtag1_tci : 16;
984 uint64_t laflags : 8;
985 uint64_t lbflags : 8;
986 uint64_t lcflags : 8;
987 uint64_t ldflags : 8;
988 uint64_t leflags : 8;
989 uint64_t lfflags : 8;
990 uint64_t lgflags : 8;
991 uint64_t lhflags : 8;
992 uint64_t eoh_ptr : 8;
993 uint64_t wqe_aura : 20;
994 uint64_t pb_aura : 20;
995 uint64_t match_id : 16;
1004 uint64_t vtag0_ptr : 8;
1005 uint64_t vtag1_ptr : 8;
1006 uint64_t flow_key_alg : 5;
1007 uint64_t rsvd_383_341 : 43;
1008 uint64_t rsvd_447_384 : 64; /* W6 */
1011 /* NIX receive scatter/gather sub descriptor structure */
1012 struct nix_rx_sg_s {
1013 uint64_t seg1_size : 16;
1014 uint64_t seg2_size : 16;
1015 uint64_t seg3_size : 16;
1017 uint64_t rsvd_59_50 : 10;
1021 /* NIX receive vtag action structure */
1022 struct nix_rx_vtag_action_s {
1023 uint64_t vtag0_relptr : 8;
1024 uint64_t vtag0_lid : 3;
1025 uint64_t rsvd_11 : 1;
1026 uint64_t vtag0_type : 3;
1027 uint64_t vtag0_valid : 1;
1028 uint64_t rsvd_31_16 : 16;
1029 uint64_t vtag1_relptr : 8;
1030 uint64_t vtag1_lid : 3;
1031 uint64_t rsvd_43 : 1;
1032 uint64_t vtag1_type : 3;
1033 uint64_t vtag1_valid : 1;
1034 uint64_t rsvd_63_48 : 16;
1037 /* NIX send completion structure */
1038 struct nix_send_comp_s {
1039 uint64_t status : 8;
1040 uint64_t sqe_id : 16;
1041 uint64_t rsvd_63_24 : 40;
1044 /* NIX send CRC sub descriptor structure */
1045 struct nix_send_crc_s {
1047 uint64_t start : 16;
1048 uint64_t insert : 16;
1049 uint64_t rsvd_57_48 : 10;
1053 uint64_t rsvd_127_96 : 32;
1056 /* NIX send extended header sub descriptor structure */
1058 union nix_send_ext_w0_u {
1061 uint64_t lso_mps : 14;
1064 uint64_t lso_sb : 8;
1065 uint64_t lso_format : 5;
1066 uint64_t rsvd_31_29 : 3;
1067 uint64_t shp_chg : 9;
1068 uint64_t shp_dis : 1;
1069 uint64_t shp_ra : 2;
1070 uint64_t markptr : 8;
1071 uint64_t markform : 7;
1072 uint64_t mark_en : 1;
1078 union nix_send_ext_w1_u {
1081 uint64_t vlan0_ins_ptr : 8;
1082 uint64_t vlan0_ins_tci : 16;
1083 uint64_t vlan1_ins_ptr : 8;
1084 uint64_t vlan1_ins_tci : 16;
1085 uint64_t vlan0_ins_ena : 1;
1086 uint64_t vlan1_ins_ena : 1;
1087 uint64_t rsvd_127_114 : 14;
1091 struct nix_send_ext_s {
1092 union nix_send_ext_w0_u w0;
1093 union nix_send_ext_w1_u w1;
1096 /* NIX send header sub descriptor structure */
1098 union nix_send_hdr_w0_u {
1101 uint64_t total : 18;
1102 uint64_t rsvd_18 : 1;
1105 uint64_t sizem1 : 3;
1112 union nix_send_hdr_w1_u {
1115 uint64_t ol3ptr : 8;
1116 uint64_t ol4ptr : 8;
1117 uint64_t il3ptr : 8;
1118 uint64_t il4ptr : 8;
1119 uint64_t ol3type : 4;
1120 uint64_t ol4type : 4;
1121 uint64_t il3type : 4;
1122 uint64_t il4type : 4;
1123 uint64_t sqe_id : 16;
1127 struct nix_send_hdr_s {
1128 union nix_send_hdr_w0_u w0;
1129 union nix_send_hdr_w1_u w1;
1132 /* NIX send immediate sub descriptor structure */
1133 struct nix_send_imm_s {
1136 uint64_t rsvd_59_19 : 41;
1140 /* NIX send jump sub descriptor structure */
1141 struct nix_send_jump_s {
1142 uint64_t sizem1 : 7;
1143 uint64_t rsvd_13_7 : 7;
1144 uint64_t ld_type : 2;
1146 uint64_t rsvd_58_36 : 23;
1149 uint64_t addr : 64; /* W1 */
1152 /* NIX send memory sub descriptor structure */
1153 struct nix_send_mem_s {
1154 uint64_t offset : 16;
1155 uint64_t rsvd_52_16 : 37;
1160 uint64_t addr : 64; /* W1 */
1163 /* NIX send scatter/gather sub descriptor structure */
1165 union nix_send_sg_s {
1168 uint64_t seg1_size : 16;
1169 uint64_t seg2_size : 16;
1170 uint64_t seg3_size : 16;
1172 uint64_t rsvd_54_50 : 5;
1176 uint64_t ld_type : 2;
1181 /* NIX send work sub descriptor structure */
1182 struct nix_send_work_s {
1186 uint64_t rsvd_59_44 : 16;
1188 uint64_t addr : 64; /* W1 */
1191 /* NIX sq context hardware structure */
1192 struct nix_sq_ctx_hw_s {
1194 uint64_t substream : 20;
1195 uint64_t max_sqe_size : 2;
1196 uint64_t sqe_way_mask : 16;
1197 uint64_t sqb_aura : 20;
1198 uint64_t gbl_rsvd1 : 5;
1199 uint64_t cq_id : 20;
1200 uint64_t cq_ena : 1;
1201 uint64_t qint_idx : 6;
1202 uint64_t gbl_rsvd2 : 1;
1203 uint64_t sq_int : 8;
1204 uint64_t sq_int_ena : 8;
1206 uint64_t sqe_stype : 2;
1207 uint64_t gbl_rsvd : 17;
1208 uint64_t head_sqb : 64;/* W2 */
1209 uint64_t head_offset : 6;
1210 uint64_t sqb_dequeue_count : 16;
1211 uint64_t default_chan : 12;
1212 uint64_t sdp_mcast : 1;
1213 uint64_t sso_ena : 1;
1214 uint64_t dse_rsvd1 : 28;
1215 uint64_t sqb_enqueue_count : 16;
1216 uint64_t tail_offset : 6;
1217 uint64_t lmt_dis : 1;
1218 uint64_t smq_rr_quantum : 24;
1219 uint64_t dnq_rsvd1 : 17;
1220 uint64_t tail_sqb : 64;/* W5 */
1221 uint64_t next_sqb : 64;/* W6 */
1222 uint64_t mnq_dis : 1;
1224 uint64_t smq_pend : 1;
1225 uint64_t smq_next_sq : 20;
1226 uint64_t smq_next_sq_vld : 1;
1227 uint64_t scm1_rsvd2 : 32;
1228 uint64_t smenq_sqb : 64;/* W8 */
1229 uint64_t smenq_offset : 6;
1230 uint64_t cq_limit : 8;
1231 uint64_t smq_rr_count : 25;
1232 uint64_t scm_lso_rem : 18;
1233 uint64_t scm_dq_rsvd0 : 7;
1234 uint64_t smq_lso_segnum : 8;
1235 uint64_t vfi_lso_total : 18;
1236 uint64_t vfi_lso_sizem1 : 3;
1237 uint64_t vfi_lso_sb : 8;
1238 uint64_t vfi_lso_mps : 14;
1239 uint64_t vfi_lso_vlan0_ins_ena : 1;
1240 uint64_t vfi_lso_vlan1_ins_ena : 1;
1241 uint64_t vfi_lso_vld : 1;
1242 uint64_t smenq_next_sqb_vld : 1;
1243 uint64_t scm_dq_rsvd1 : 9;
1244 uint64_t smenq_next_sqb : 64;/* W11 */
1245 uint64_t seb_rsvd1 : 64;/* W12 */
1246 uint64_t drop_pkts : 48;
1247 uint64_t drop_octs_lsw : 16;
1248 uint64_t drop_octs_msw : 32;
1249 uint64_t pkts_lsw : 32;
1250 uint64_t pkts_msw : 16;
1254 /* NIX send queue context structure */
1255 struct nix_sq_ctx_s {
1257 uint64_t qint_idx : 6;
1258 uint64_t substream : 20;
1259 uint64_t sdp_mcast : 1;
1261 uint64_t sqe_way_mask : 16;
1263 uint64_t cq_ena : 1;
1265 uint64_t sso_ena : 1;
1266 uint64_t smq_rr_quantum : 24;
1267 uint64_t default_chan : 12;
1268 uint64_t sqb_count : 16;
1269 uint64_t smq_rr_count : 25;
1270 uint64_t sqb_aura : 20;
1271 uint64_t sq_int : 8;
1272 uint64_t sq_int_ena : 8;
1273 uint64_t sqe_stype : 2;
1274 uint64_t rsvd_191 : 1;
1275 uint64_t max_sqe_size : 2;
1276 uint64_t cq_limit : 8;
1277 uint64_t lmt_dis : 1;
1278 uint64_t mnq_dis : 1;
1279 uint64_t smq_next_sq : 20;
1280 uint64_t smq_lso_segnum : 8;
1281 uint64_t tail_offset : 6;
1282 uint64_t smenq_offset : 6;
1283 uint64_t head_offset : 6;
1284 uint64_t smenq_next_sqb_vld : 1;
1285 uint64_t smq_pend : 1;
1286 uint64_t smq_next_sq_vld : 1;
1287 uint64_t rsvd_255_253 : 3;
1288 uint64_t next_sqb : 64;/* W4 */
1289 uint64_t tail_sqb : 64;/* W5 */
1290 uint64_t smenq_sqb : 64;/* W6 */
1291 uint64_t smenq_next_sqb : 64;/* W7 */
1292 uint64_t head_sqb : 64;/* W8 */
1293 uint64_t rsvd_583_576 : 8;
1294 uint64_t vfi_lso_total : 18;
1295 uint64_t vfi_lso_sizem1 : 3;
1296 uint64_t vfi_lso_sb : 8;
1297 uint64_t vfi_lso_mps : 14;
1298 uint64_t vfi_lso_vlan0_ins_ena : 1;
1299 uint64_t vfi_lso_vlan1_ins_ena : 1;
1300 uint64_t vfi_lso_vld : 1;
1301 uint64_t rsvd_639_630 : 10;
1302 uint64_t scm_lso_rem : 18;
1303 uint64_t rsvd_703_658 : 46;
1305 uint64_t rsvd_767_752 : 16;
1307 uint64_t rsvd_831_816 : 16;
1308 uint64_t rsvd_895_832 : 64;/* W13 */
1309 uint64_t drop_octs : 48;
1310 uint64_t rsvd_959_944 : 16;
1311 uint64_t drop_pkts : 48;
1312 uint64_t rsvd_1023_1008 : 16;
1315 /* NIX transmit action structure */
1316 struct nix_tx_action_s {
1318 uint64_t rsvd_11_4 : 8;
1319 uint64_t index : 20;
1320 uint64_t match_id : 16;
1321 uint64_t rsvd_63_48 : 16;
1324 /* NIX transmit vtag action structure */
1325 struct nix_tx_vtag_action_s {
1326 uint64_t vtag0_relptr : 8;
1327 uint64_t vtag0_lid : 3;
1328 uint64_t rsvd_11 : 1;
1329 uint64_t vtag0_op : 2;
1330 uint64_t rsvd_15_14 : 2;
1331 uint64_t vtag0_def : 10;
1332 uint64_t rsvd_31_26 : 6;
1333 uint64_t vtag1_relptr : 8;
1334 uint64_t vtag1_lid : 3;
1335 uint64_t rsvd_43 : 1;
1336 uint64_t vtag1_op : 2;
1337 uint64_t rsvd_47_46 : 2;
1338 uint64_t vtag1_def : 10;
1339 uint64_t rsvd_63_58 : 6;
1342 /* NIX work queue entry header structure */
1343 struct nix_wqe_hdr_s {
1349 uint64_t wqe_type : 4;
1352 /* NIX Rx flow key algorithm field structure */
1353 struct nix_rx_flowkey_alg {
1354 uint64_t key_offset :6;
1355 uint64_t ln_mask :1;
1356 uint64_t fn_mask :1;
1357 uint64_t hdr_offset :8;
1358 uint64_t bytesm1 :5;
1360 uint64_t reserved_24_24 :1;
1362 uint64_t sel_chan :1;
1363 uint64_t ltype_mask :4;
1364 uint64_t ltype_match :4;
1365 uint64_t reserved_35_63 :29;
1368 /* NIX LSO format field structure */
1369 struct nix_lso_format {
1370 uint64_t offset : 8;
1372 uint64_t rsvd_10_11 : 2;
1373 uint64_t sizem1 : 2;
1374 uint64_t rsvd_14_15 : 2;
1376 uint64_t rsvd_19_63 : 45;
1379 #define NIX_LSO_FIELD_MAX (8)
1380 #define NIX_LSO_FIELD_ALG_MASK GENMASK(18, 16)
1381 #define NIX_LSO_FIELD_SZ_MASK GENMASK(13, 12)
1382 #define NIX_LSO_FIELD_LY_MASK GENMASK(9, 8)
1383 #define NIX_LSO_FIELD_OFF_MASK GENMASK(7, 0)
1385 #define NIX_LSO_FIELD_MASK \
1386 (NIX_LSO_FIELD_OFF_MASK | \
1387 NIX_LSO_FIELD_LY_MASK | \
1388 NIX_LSO_FIELD_SZ_MASK | \
1389 NIX_LSO_FIELD_ALG_MASK)
1391 #endif /* __OTX2_NIX_HW_H__ */