raw/octeontx2_ep: add device configuration
[dpdk.git] / drivers / common / octeontx2 / hw / otx2_ssow.h
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(C) 2019 Marvell International Ltd.
3  */
4
5 #ifndef __OTX2_SSOW_HW_H__
6 #define __OTX2_SSOW_HW_H__
7
8 /* Register offsets */
9
10 #define SSOW_AF_RVU_LF_HWS_CFG_DEBUG    (0x10ull)
11 #define SSOW_AF_LF_HWS_RST              (0x30ull)
12 #define SSOW_PRIV_LFX_HWS_CFG(a)        (0x1000ull | (uint64_t)(a) << 3)
13 #define SSOW_PRIV_LFX_HWS_INT_CFG(a)    (0x2000ull | (uint64_t)(a) << 3)
14 #define SSOW_AF_SCRATCH_WS              (0x100000ull)
15 #define SSOW_AF_SCRATCH_GW              (0x200000ull)
16 #define SSOW_AF_SCRATCH_AW              (0x300000ull)
17
18 #define SSOW_LF_GWS_LINKS               (0x10ull)
19 #define SSOW_LF_GWS_PENDWQP             (0x40ull)
20 #define SSOW_LF_GWS_PENDSTATE           (0x50ull)
21 #define SSOW_LF_GWS_NW_TIM              (0x70ull)
22 #define SSOW_LF_GWS_GRPMSK_CHG          (0x80ull)
23 #define SSOW_LF_GWS_INT                 (0x100ull)
24 #define SSOW_LF_GWS_INT_W1S             (0x108ull)
25 #define SSOW_LF_GWS_INT_ENA_W1S         (0x110ull)
26 #define SSOW_LF_GWS_INT_ENA_W1C         (0x118ull)
27 #define SSOW_LF_GWS_TAG                 (0x200ull)
28 #define SSOW_LF_GWS_WQP                 (0x210ull)
29 #define SSOW_LF_GWS_SWTP                (0x220ull)
30 #define SSOW_LF_GWS_PENDTAG             (0x230ull)
31 #define SSOW_LF_GWS_OP_ALLOC_WE         (0x400ull)
32 #define SSOW_LF_GWS_OP_GET_WORK         (0x600ull)
33 #define SSOW_LF_GWS_OP_SWTAG_FLUSH      (0x800ull)
34 #define SSOW_LF_GWS_OP_SWTAG_UNTAG      (0x810ull)
35 #define SSOW_LF_GWS_OP_SWTP_CLR         (0x820ull)
36 #define SSOW_LF_GWS_OP_UPD_WQP_GRP0     (0x830ull)
37 #define SSOW_LF_GWS_OP_UPD_WQP_GRP1     (0x838ull)
38 #define SSOW_LF_GWS_OP_DESCHED          (0x880ull)
39 #define SSOW_LF_GWS_OP_DESCHED_NOSCH    (0x8c0ull)
40 #define SSOW_LF_GWS_OP_SWTAG_DESCHED    (0x980ull)
41 #define SSOW_LF_GWS_OP_SWTAG_NOSCHED    (0x9c0ull)
42 #define SSOW_LF_GWS_OP_CLR_NSCHED0      (0xa00ull)
43 #define SSOW_LF_GWS_OP_CLR_NSCHED1      (0xa08ull)
44 #define SSOW_LF_GWS_OP_SWTP_SET         (0xc00ull)
45 #define SSOW_LF_GWS_OP_SWTAG_NORM       (0xc10ull)
46 #define SSOW_LF_GWS_OP_SWTAG_FULL0      (0xc20ull)
47 #define SSOW_LF_GWS_OP_SWTAG_FULL1      (0xc28ull)
48 #define SSOW_LF_GWS_OP_GWC_INVAL        (0xe00ull)
49
50
51 /* Enum offsets */
52
53 #define SSOW_LF_INT_VEC_IOP    (0x0ull)
54
55
56 #endif /* __OTX2_SSOW_HW_H__ */