1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #include <rte_atomic.h>
6 #include <rte_malloc.h>
9 #include "otx2_common.h"
11 #include "otx2_mbox.h"
15 * Set default NPA configuration.
18 otx2_npa_set_defaults(struct otx2_idev_cfg *idev)
20 idev->npa_pf_func = 0;
21 rte_atomic16_set(&idev->npa_refcnt, 0);
26 * Get intra device config structure.
28 struct otx2_idev_cfg *
29 otx2_intra_dev_get_cfg(void)
31 const char name[] = "octeontx2_intra_device_conf";
32 const struct rte_memzone *mz;
33 struct otx2_idev_cfg *idev;
35 mz = rte_memzone_lookup(name);
39 /* Request for the first time */
40 mz = rte_memzone_reserve_aligned(name, sizeof(struct otx2_idev_cfg),
41 SOCKET_ID_ANY, 0, OTX2_ALIGN);
44 idev->sso_pf_func = 0;
46 otx2_npa_set_defaults(idev);
57 otx2_sso_pf_func_get(void)
59 struct otx2_idev_cfg *idev;
63 idev = otx2_intra_dev_get_cfg();
66 sso_pf_func = idev->sso_pf_func;
76 otx2_sso_pf_func_set(uint16_t sso_pf_func)
78 struct otx2_idev_cfg *idev;
80 idev = otx2_intra_dev_get_cfg();
83 idev->sso_pf_func = sso_pf_func;
93 otx2_npa_pf_func_get(void)
95 struct otx2_idev_cfg *idev;
99 idev = otx2_intra_dev_get_cfg();
102 npa_pf_func = idev->npa_pf_func;
112 otx2_npa_lf_obj_get(void)
114 struct otx2_idev_cfg *idev;
116 idev = otx2_intra_dev_get_cfg();
118 if (idev != NULL && rte_atomic16_read(&idev->npa_refcnt))
126 * Is NPA lf active for the given device?.
129 otx2_npa_lf_active(void *otx2_dev)
131 struct otx2_dev *dev = otx2_dev;
132 struct otx2_idev_cfg *idev;
134 /* Check if npalf is actively used on this dev */
135 idev = otx2_intra_dev_get_cfg();
136 if (!idev || !idev->npa_lf || idev->npa_lf->mbox != dev->mbox)
139 return rte_atomic16_read(&idev->npa_refcnt);
144 * Gets reference only to existing NPA LF object.
146 int otx2_npa_lf_obj_ref(void)
148 struct otx2_idev_cfg *idev;
152 idev = otx2_intra_dev_get_cfg();
154 /* Check if ref not possible */
159 /* Get ref only if > 0 */
160 cnt = rte_atomic16_read(&idev->npa_refcnt);
162 rc = rte_atomic16_cmpset(&idev->npa_refcnt_u16, cnt, cnt + 1);
166 cnt = rte_atomic16_read(&idev->npa_refcnt);
169 return cnt ? 0 : -EINVAL;
173 parse_npa_lock_mask(const char *key, const char *value, void *extra_args)
178 val = strtoull(value, NULL, 16);
180 *(uint64_t *)extra_args = val;
187 * Parse common device arguments
189 void otx2_parse_common_devargs(struct rte_kvargs *kvlist)
192 struct otx2_idev_cfg *idev;
193 uint64_t npa_lock_mask = 0;
195 idev = otx2_intra_dev_get_cfg();
200 rte_kvargs_process(kvlist, OTX2_NPA_LOCK_MASK,
201 &parse_npa_lock_mask, &npa_lock_mask);
203 idev->npa_lock_mask = npa_lock_mask;
206 RTE_LOG_REGISTER(otx2_logtype_base, pmd.octeontx2.base, NOTICE);
207 RTE_LOG_REGISTER(otx2_logtype_mbox, pmd.octeontx2.mbox, NOTICE);
208 RTE_LOG_REGISTER(otx2_logtype_npa, pmd.mempool.octeontx2, NOTICE);
209 RTE_LOG_REGISTER(otx2_logtype_nix, pmd.net.octeontx2, NOTICE);
210 RTE_LOG_REGISTER(otx2_logtype_npc, pmd.net.octeontx2.flow, NOTICE);
211 RTE_LOG_REGISTER(otx2_logtype_tm, pmd.net.octeontx2.tm, NOTICE);
212 RTE_LOG_REGISTER(otx2_logtype_sso, pmd.event.octeontx2, NOTICE);
213 RTE_LOG_REGISTER(otx2_logtype_tim, pmd.event.octeontx2.timer, NOTICE);
214 RTE_LOG_REGISTER(otx2_logtype_dpi, pmd.raw.octeontx2.dpi, NOTICE);
215 RTE_LOG_REGISTER(otx2_logtype_ep, pmd.raw.octeontx2.ep, NOTICE);
216 RTE_LOG_REGISTER(otx2_logtype_ree, pmd.regex.octeontx2, NOTICE);