1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef _OTX2_COMMON_H_
6 #define _OTX2_COMMON_H_
8 #include <rte_atomic.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_kvargs.h>
12 #include <rte_memory.h>
13 #include <rte_memzone.h>
16 #include "hw/otx2_rvu.h"
17 #include "hw/otx2_nix.h"
18 #include "hw/otx2_npc.h"
19 #include "hw/otx2_npa.h"
20 #include "hw/otx2_sdp.h"
21 #include "hw/otx2_sso.h"
22 #include "hw/otx2_ssow.h"
23 #include "hw/otx2_tim.h"
26 #define OTX2_ALIGN 128
28 /* Bits manipulation */
30 #define BIT_ULL(nr) (1ULL << (nr))
33 #define BIT(nr) (1UL << (nr))
37 #define BITS_PER_LONG (__SIZEOF_LONG__ * 8)
39 #ifndef BITS_PER_LONG_LONG
40 #define BITS_PER_LONG_LONG (__SIZEOF_LONG_LONG__ * 8)
44 #define GENMASK(h, l) \
45 (((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
48 #define GENMASK_ULL(h, l) \
49 (((~0ULL) - (1ULL << (l)) + 1) & \
50 (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))
53 #define OTX2_NPA_LOCK_MASK "npa_lock_mask"
55 /* Intra device related functions */
57 struct otx2_idev_cfg {
60 struct otx2_npa_lf *npa_lf;
63 rte_atomic16_t npa_refcnt;
64 uint16_t npa_refcnt_u16;
66 uint64_t npa_lock_mask;
70 struct otx2_idev_cfg *otx2_intra_dev_get_cfg(void);
72 void otx2_sso_pf_func_set(uint16_t sso_pf_func);
74 uint16_t otx2_sso_pf_func_get(void);
76 uint16_t otx2_npa_pf_func_get(void);
78 struct otx2_npa_lf *otx2_npa_lf_obj_get(void);
80 void otx2_npa_set_defaults(struct otx2_idev_cfg *idev);
82 int otx2_npa_lf_active(void *dev);
84 int otx2_npa_lf_obj_ref(void);
86 void otx2_parse_common_devargs(struct rte_kvargs *kvlist);
89 extern int otx2_logtype_base;
90 extern int otx2_logtype_mbox;
91 extern int otx2_logtype_npa;
92 extern int otx2_logtype_nix;
93 extern int otx2_logtype_sso;
94 extern int otx2_logtype_npc;
95 extern int otx2_logtype_tm;
96 extern int otx2_logtype_tim;
97 extern int otx2_logtype_dpi;
98 extern int otx2_logtype_ep;
100 #define otx2_err(fmt, args...) \
101 RTE_LOG(ERR, PMD, "%s():%u " fmt "\n", \
102 __func__, __LINE__, ## args)
104 #define otx2_info(fmt, args...) \
105 RTE_LOG(INFO, PMD, fmt"\n", ## args)
107 #define otx2_dbg(subsystem, fmt, args...) \
108 rte_log(RTE_LOG_DEBUG, otx2_logtype_ ## subsystem, \
109 "[%s] %s():%u " fmt "\n", \
110 #subsystem, __func__, __LINE__, ##args)
112 #define otx2_base_dbg(fmt, ...) otx2_dbg(base, fmt, ##__VA_ARGS__)
113 #define otx2_mbox_dbg(fmt, ...) otx2_dbg(mbox, fmt, ##__VA_ARGS__)
114 #define otx2_npa_dbg(fmt, ...) otx2_dbg(npa, fmt, ##__VA_ARGS__)
115 #define otx2_nix_dbg(fmt, ...) otx2_dbg(nix, fmt, ##__VA_ARGS__)
116 #define otx2_sso_dbg(fmt, ...) otx2_dbg(sso, fmt, ##__VA_ARGS__)
117 #define otx2_npc_dbg(fmt, ...) otx2_dbg(npc, fmt, ##__VA_ARGS__)
118 #define otx2_tm_dbg(fmt, ...) otx2_dbg(tm, fmt, ##__VA_ARGS__)
119 #define otx2_tim_dbg(fmt, ...) otx2_dbg(tim, fmt, ##__VA_ARGS__)
120 #define otx2_dpi_dbg(fmt, ...) otx2_dbg(dpi, fmt, ##__VA_ARGS__)
121 #define otx2_sdp_dbg(fmt, ...) otx2_dbg(ep, fmt, ##__VA_ARGS__)
124 #define PCI_VENDOR_ID_CAVIUM 0x177D
125 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063
126 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064
127 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
128 #define PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF 0xA0F9
129 #define PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_VF 0xA0FA
130 #define PCI_DEVID_OCTEONTX2_RVU_NPA_PF 0xA0FB
131 #define PCI_DEVID_OCTEONTX2_RVU_NPA_VF 0xA0FC
132 #define PCI_DEVID_OCTEONTX2_RVU_CPT_PF 0xA0FD
133 #define PCI_DEVID_OCTEONTX2_RVU_CPT_VF 0xA0FE
134 #define PCI_DEVID_OCTEONTX2_RVU_AF_VF 0xA0f8
135 #define PCI_DEVID_OCTEONTX2_DPI_VF 0xA081
136 #define PCI_DEVID_OCTEONTX2_EP_VF 0xB203 /* OCTEON TX2 EP mode */
137 #define PCI_DEVID_OCTEONTX2_RVU_SDP_PF 0xA0f6
138 #define PCI_DEVID_OCTEONTX2_RVU_SDP_VF 0xA0f7
141 * REVID for RVU PCIe devices.
142 * Bits 0..1: minor pass
143 * Bits 3..2: major pass
144 * Bits 7..4: midr id, 0:96, 1:95, 2:loki, f:unknown
147 #define RVU_PCI_REV_MIDR_ID(rev_id) (rev_id >> 4)
148 #define RVU_PCI_REV_MAJOR(rev_id) ((rev_id >> 2) & 0x3)
149 #define RVU_PCI_REV_MINOR(rev_id) (rev_id & 0x3)
151 #define RVU_PCI_CN96XX_MIDR_ID 0x0
152 #define RVU_PCI_CNF95XX_MIDR_ID 0x1
154 /* PCI Config offsets */
155 #define RVU_PCI_REVISION_ID 0x08
158 #define otx2_read64(addr) rte_read64_relaxed((void *)(addr))
159 #define otx2_write64(val, addr) rte_write64_relaxed((val), (void *)(addr))
161 #if defined(RTE_ARCH_ARM64)
162 #include "otx2_io_arm64.h"
164 #include "otx2_io_generic.h"
167 /* Fastpath lookup */
168 #define OTX2_NIX_FASTPATH_LOOKUP_MEM "otx2_nix_fastpath_lookup_mem"
169 #define OTX2_NIX_SA_TBL_START (4096*4 + 69632*2)
171 #endif /* _OTX2_COMMON_H_ */