1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef _OTX2_COMMON_H_
6 #define _OTX2_COMMON_H_
8 #include <rte_common.h>
10 #include <rte_memory.h>
12 #include "hw/otx2_rvu.h"
13 #include "hw/otx2_nix.h"
14 #include "hw/otx2_npc.h"
15 #include "hw/otx2_npa.h"
16 #include "hw/otx2_sso.h"
17 #include "hw/otx2_ssow.h"
18 #include "hw/otx2_tim.h"
21 #define OTX2_ALIGN 128
23 /* Bits manipulation */
25 #define BIT_ULL(nr) (1ULL << (nr))
28 #define BIT(nr) (1UL << (nr))
31 /* Compiler attributes */
33 #define __hot __attribute__((hot))
37 extern int otx2_logtype_base;
38 extern int otx2_logtype_mbox;
39 extern int otx2_logtype_npa;
40 extern int otx2_logtype_nix;
41 extern int otx2_logtype_sso;
42 extern int otx2_logtype_npc;
43 extern int otx2_logtype_tm;
44 extern int otx2_logtype_tim;
45 extern int otx2_logtype_dpi;
47 #define OTX2_CLNRM "\x1b[0m"
48 #define OTX2_CLRED "\x1b[31m"
50 #define otx2_err(fmt, args...) \
51 RTE_LOG(ERR, PMD, ""OTX2_CLRED"%s():%u " fmt OTX2_CLNRM"\n", \
52 __func__, __LINE__, ## args)
54 #define otx2_info(fmt, args...) \
55 RTE_LOG(INFO, PMD, fmt"\n", ## args)
57 #define otx2_dbg(subsystem, fmt, args...) \
58 rte_log(RTE_LOG_DEBUG, otx2_logtype_ ## subsystem, \
59 "[%s] %s():%u " fmt "\n", \
60 #subsystem, __func__, __LINE__, ##args)
62 #define otx2_base_dbg(fmt, ...) otx2_dbg(base, fmt, ##__VA_ARGS__)
63 #define otx2_mbox_dbg(fmt, ...) otx2_dbg(mbox, fmt, ##__VA_ARGS__)
64 #define otx2_npa_dbg(fmt, ...) otx2_dbg(npa, fmt, ##__VA_ARGS__)
65 #define otx2_nix_dbg(fmt, ...) otx2_dbg(nix, fmt, ##__VA_ARGS__)
66 #define otx2_sso_dbg(fmt, ...) otx2_dbg(sso, fmt, ##__VA_ARGS__)
67 #define otx2_npc_dbg(fmt, ...) otx2_dbg(npc, fmt, ##__VA_ARGS__)
68 #define otx2_tm_dbg(fmt, ...) otx2_dbg(tm, fmt, ##__VA_ARGS__)
69 #define otx2_tim_dbg(fmt, ...) otx2_dbg(tim, fmt, ##__VA_ARGS__)
70 #define otx2_dpi_dbg(fmt, ...) otx2_dbg(dpi, fmt, ##__VA_ARGS__)
73 #define PCI_VENDOR_ID_CAVIUM 0x177D
74 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063
75 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064
76 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
77 #define PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF 0xA0F9
78 #define PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_VF 0xA0FA
79 #define PCI_DEVID_OCTEONTX2_RVU_NPA_PF 0xA0FB
80 #define PCI_DEVID_OCTEONTX2_RVU_NPA_VF 0xA0FC
81 #define PCI_DEVID_OCTEONTX2_RVU_CPT_PF 0xA0FD
82 #define PCI_DEVID_OCTEONTX2_RVU_CPT_VF 0xA0FE
83 #define PCI_DEVID_OCTEONTX2_RVU_AF_VF 0xA0f8
84 #define PCI_DEVID_OCTEONTX2_DPI_VF 0xA081
87 #define otx2_read64(addr) rte_read64_relaxed((void *)(addr))
88 #define otx2_write64(val, addr) rte_write64_relaxed((val), (void *)(addr))
90 #if defined(RTE_ARCH_ARM64)
91 #include "otx2_io_arm64.h"
93 #include "otx2_io_generic.h"
96 #endif /* _OTX2_COMMON_H_ */