1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef _OTX2_COMMON_H_
6 #define _OTX2_COMMON_H_
8 #include <rte_atomic.h>
9 #include <rte_common.h>
10 #include <rte_cycles.h>
11 #include <rte_memory.h>
12 #include <rte_memzone.h>
15 #include "hw/otx2_rvu.h"
16 #include "hw/otx2_nix.h"
17 #include "hw/otx2_npc.h"
18 #include "hw/otx2_npa.h"
19 #include "hw/otx2_sso.h"
20 #include "hw/otx2_ssow.h"
21 #include "hw/otx2_tim.h"
24 #define OTX2_ALIGN 128
26 /* Bits manipulation */
28 #define BIT_ULL(nr) (1ULL << (nr))
31 #define BIT(nr) (1UL << (nr))
34 /* Compiler attributes */
36 #define __hot __attribute__((hot))
39 /* Intra device related functions */
41 struct otx2_idev_cfg {
44 struct otx2_npa_lf *npa_lf;
47 rte_atomic16_t npa_refcnt;
48 uint16_t npa_refcnt_u16;
52 struct otx2_idev_cfg *otx2_intra_dev_get_cfg(void);
53 void otx2_sso_pf_func_set(uint16_t sso_pf_func);
54 uint16_t otx2_sso_pf_func_get(void);
55 uint16_t otx2_npa_pf_func_get(void);
56 struct otx2_npa_lf *otx2_npa_lf_obj_get(void);
57 void otx2_npa_set_defaults(struct otx2_idev_cfg *idev);
58 int otx2_npa_lf_active(void *dev);
59 int otx2_npa_lf_obj_ref(void);
62 extern int otx2_logtype_base;
63 extern int otx2_logtype_mbox;
64 extern int otx2_logtype_npa;
65 extern int otx2_logtype_nix;
66 extern int otx2_logtype_sso;
67 extern int otx2_logtype_npc;
68 extern int otx2_logtype_tm;
69 extern int otx2_logtype_tim;
70 extern int otx2_logtype_dpi;
72 #define OTX2_CLNRM "\x1b[0m"
73 #define OTX2_CLRED "\x1b[31m"
75 #define otx2_err(fmt, args...) \
76 RTE_LOG(ERR, PMD, ""OTX2_CLRED"%s():%u " fmt OTX2_CLNRM"\n", \
77 __func__, __LINE__, ## args)
79 #define otx2_info(fmt, args...) \
80 RTE_LOG(INFO, PMD, fmt"\n", ## args)
82 #define otx2_dbg(subsystem, fmt, args...) \
83 rte_log(RTE_LOG_DEBUG, otx2_logtype_ ## subsystem, \
84 "[%s] %s():%u " fmt "\n", \
85 #subsystem, __func__, __LINE__, ##args)
87 #define otx2_base_dbg(fmt, ...) otx2_dbg(base, fmt, ##__VA_ARGS__)
88 #define otx2_mbox_dbg(fmt, ...) otx2_dbg(mbox, fmt, ##__VA_ARGS__)
89 #define otx2_npa_dbg(fmt, ...) otx2_dbg(npa, fmt, ##__VA_ARGS__)
90 #define otx2_nix_dbg(fmt, ...) otx2_dbg(nix, fmt, ##__VA_ARGS__)
91 #define otx2_sso_dbg(fmt, ...) otx2_dbg(sso, fmt, ##__VA_ARGS__)
92 #define otx2_npc_dbg(fmt, ...) otx2_dbg(npc, fmt, ##__VA_ARGS__)
93 #define otx2_tm_dbg(fmt, ...) otx2_dbg(tm, fmt, ##__VA_ARGS__)
94 #define otx2_tim_dbg(fmt, ...) otx2_dbg(tim, fmt, ##__VA_ARGS__)
95 #define otx2_dpi_dbg(fmt, ...) otx2_dbg(dpi, fmt, ##__VA_ARGS__)
98 #define PCI_VENDOR_ID_CAVIUM 0x177D
99 #define PCI_DEVID_OCTEONTX2_RVU_PF 0xA063
100 #define PCI_DEVID_OCTEONTX2_RVU_VF 0xA064
101 #define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
102 #define PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_PF 0xA0F9
103 #define PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_VF 0xA0FA
104 #define PCI_DEVID_OCTEONTX2_RVU_NPA_PF 0xA0FB
105 #define PCI_DEVID_OCTEONTX2_RVU_NPA_VF 0xA0FC
106 #define PCI_DEVID_OCTEONTX2_RVU_CPT_PF 0xA0FD
107 #define PCI_DEVID_OCTEONTX2_RVU_CPT_VF 0xA0FE
108 #define PCI_DEVID_OCTEONTX2_RVU_AF_VF 0xA0f8
109 #define PCI_DEVID_OCTEONTX2_DPI_VF 0xA081
112 #define otx2_read64(addr) rte_read64_relaxed((void *)(addr))
113 #define otx2_write64(val, addr) rte_write64_relaxed((val), (void *)(addr))
115 #if defined(RTE_ARCH_ARM64)
116 #include "otx2_io_arm64.h"
118 #include "otx2_io_generic.h"
121 #endif /* _OTX2_COMMON_H_ */