1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
10 #include <rte_alarm.h>
11 #include <rte_common.h>
13 #include <rte_memcpy.h>
16 #include "otx2_mbox.h"
18 #define RVU_MAX_VF 64 /* RVU_PF_VFPF_MBOX_INT(0..1) */
19 #define RVU_MAX_INT_RETRY 3
21 /* PF/VF message handling timer */
22 #define VF_PF_MBOX_TIMER_MS (20 * 1000)
25 mbox_mem_map(off_t off, size_t size)
27 void *va = MAP_FAILED;
33 mem_fd = open("/dev/mem", O_RDWR);
37 va = mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, mem_fd, off);
41 otx2_err("Failed to mmap sz=0x%zx, fd=%d, off=%jd",
42 size, mem_fd, (intmax_t)off);
48 mbox_mem_unmap(void *va, size_t size)
55 pf_af_sync_msg(struct otx2_dev *dev, struct mbox_msghdr **rsp)
57 uint32_t timeout = 0, sleep = 1; struct otx2_mbox *mbox = dev->mbox;
58 struct otx2_mbox_dev *mdev = &mbox->dev[0];
59 volatile uint64_t int_status;
60 struct mbox_msghdr *msghdr;
64 /* We need to disable PF interrupts. We are in timer interrupt */
65 otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
68 otx2_mbox_msg_send(mbox, 0);
73 if (timeout >= MBOX_RSP_TIMEOUT) {
74 otx2_err("Message timeout: %dms", MBOX_RSP_TIMEOUT);
78 int_status = otx2_read64(dev->bar2 + RVU_PF_INT);
79 } while ((int_status & 0x1) != 0x1);
82 otx2_write64(int_status, dev->bar2 + RVU_PF_INT);
84 /* Enable interrupts */
85 otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);
89 off = mbox->rx_start +
90 RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
91 msghdr = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + off);
101 af_pf_wait_msg(struct otx2_dev *dev, uint16_t vf, int num_msg)
103 uint32_t timeout = 0, sleep = 1; struct otx2_mbox *mbox = dev->mbox;
104 struct otx2_mbox_dev *mdev = &mbox->dev[0];
105 volatile uint64_t int_status;
106 struct mbox_hdr *req_hdr;
107 struct mbox_msghdr *msg;
108 struct mbox_msghdr *rsp;
113 /* We need to disable PF interrupts. We are in timer interrupt */
114 otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
117 otx2_mbox_msg_send(mbox, 0);
122 if (timeout >= MBOX_RSP_TIMEOUT) {
123 otx2_err("Routed messages %d timeout: %dms",
124 num_msg, MBOX_RSP_TIMEOUT);
127 int_status = otx2_read64(dev->bar2 + RVU_PF_INT);
128 } while ((int_status & 0x1) != 0x1);
131 otx2_write64(~0ull, dev->bar2 + RVU_PF_INT);
133 /* Enable interrupts */
134 otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);
136 rte_spinlock_lock(&mdev->mbox_lock);
138 req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
139 if (req_hdr->num_msgs != num_msg)
140 otx2_err("Routed messages: %d received: %d", num_msg,
143 /* Get messages from mbox */
144 offset = mbox->rx_start +
145 RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
146 for (i = 0; i < req_hdr->num_msgs; i++) {
147 msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
148 size = mbox->rx_start + msg->next_msgoff - offset;
150 /* Reserve PF/VF mbox message */
151 size = RTE_ALIGN(size, MBOX_MSG_ALIGN);
152 rsp = otx2_mbox_alloc_msg(&dev->mbox_vfpf, vf, size);
153 otx2_mbox_rsp_init(msg->id, rsp);
155 /* Copy message from AF<->PF mbox to PF<->VF mbox */
156 otx2_mbox_memcpy((uint8_t *)rsp + sizeof(struct mbox_msghdr),
157 (uint8_t *)msg + sizeof(struct mbox_msghdr),
158 size - sizeof(struct mbox_msghdr));
160 /* Set status and sender pf_func data */
162 rsp->pcifunc = msg->pcifunc;
164 offset = mbox->rx_start + msg->next_msgoff;
166 rte_spinlock_unlock(&mdev->mbox_lock);
168 return req_hdr->num_msgs;
172 vf_pf_process_msgs(struct otx2_dev *dev, uint16_t vf)
174 int offset, routed = 0; struct otx2_mbox *mbox = &dev->mbox_vfpf;
175 struct otx2_mbox_dev *mdev = &mbox->dev[vf];
176 struct mbox_hdr *req_hdr;
177 struct mbox_msghdr *msg;
181 req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
182 if (!req_hdr->num_msgs)
185 offset = mbox->rx_start + RTE_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
187 for (i = 0; i < req_hdr->num_msgs; i++) {
189 msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
190 size = mbox->rx_start + msg->next_msgoff - offset;
193 msg->pcifunc = otx2_pfvf_func(dev->pf, vf);
195 if (msg->id == MBOX_MSG_READY) {
196 struct ready_msg_rsp *rsp;
197 uint16_t max_bits = sizeof(dev->active_vfs[0]) * 8;
199 /* Handle READY message in PF */
200 dev->active_vfs[vf / max_bits] |=
201 BIT_ULL(vf % max_bits);
202 rsp = (struct ready_msg_rsp *)
203 otx2_mbox_alloc_msg(mbox, vf, sizeof(*rsp));
204 otx2_mbox_rsp_init(msg->id, rsp);
206 /* PF/VF function ID */
207 rsp->hdr.pcifunc = msg->pcifunc;
210 struct mbox_msghdr *af_req;
211 /* Reserve AF/PF mbox message */
212 size = RTE_ALIGN(size, MBOX_MSG_ALIGN);
213 af_req = otx2_mbox_alloc_msg(dev->mbox, 0, size);
214 otx2_mbox_req_init(msg->id, af_req);
216 /* Copy message from VF<->PF mbox to PF<->AF mbox */
217 otx2_mbox_memcpy((uint8_t *)af_req +
218 sizeof(struct mbox_msghdr),
219 (uint8_t *)msg + sizeof(struct mbox_msghdr),
220 size - sizeof(struct mbox_msghdr));
221 af_req->pcifunc = msg->pcifunc;
224 offset = mbox->rx_start + msg->next_msgoff;
228 otx2_base_dbg("pf:%d routed %d messages from vf:%d to AF",
229 dev->pf, routed, vf);
230 af_pf_wait_msg(dev, vf, routed);
231 otx2_mbox_reset(dev->mbox, 0);
234 /* Send mbox responses to VF */
235 if (mdev->num_msgs) {
236 otx2_base_dbg("pf:%d reply %d messages to vf:%d",
237 dev->pf, mdev->num_msgs, vf);
238 otx2_mbox_msg_send(mbox, vf);
245 vf_pf_process_up_msgs(struct otx2_dev *dev, uint16_t vf)
247 struct otx2_mbox *mbox = &dev->mbox_vfpf_up;
248 struct otx2_mbox_dev *mdev = &mbox->dev[vf];
249 struct mbox_hdr *req_hdr;
250 struct mbox_msghdr *msg;
255 req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
256 if (req_hdr->num_msgs == 0)
259 offset = mbox->rx_start + RTE_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
261 for (i = 0; i < req_hdr->num_msgs; i++) {
262 msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
266 msg->pcifunc = otx2_pfvf_func(dev->pf, vf);
269 case MBOX_MSG_CGX_LINK_EVENT:
270 otx2_base_dbg("PF: Msg 0x%x (%s) fn:0x%x (pf:%d,vf:%d)",
271 msg->id, otx2_mbox_id2name(msg->id),
272 msg->pcifunc, otx2_get_pf(msg->pcifunc),
273 otx2_get_vf(msg->pcifunc));
275 case MBOX_MSG_CGX_PTP_RX_INFO:
276 otx2_base_dbg("PF: Msg 0x%x (%s) fn:0x%x (pf:%d,vf:%d)",
277 msg->id, otx2_mbox_id2name(msg->id),
278 msg->pcifunc, otx2_get_pf(msg->pcifunc),
279 otx2_get_vf(msg->pcifunc));
282 otx2_err("Not handled UP msg 0x%x (%s) func:0x%x",
283 msg->id, otx2_mbox_id2name(msg->id),
286 offset = mbox->rx_start + msg->next_msgoff;
288 otx2_mbox_reset(mbox, vf);
289 mdev->msgs_acked = msgs_acked;
296 otx2_vf_pf_mbox_handle_msg(void *param)
298 uint16_t vf, max_vf, max_bits;
299 struct otx2_dev *dev = param;
301 max_bits = sizeof(dev->intr.bits[0]) * sizeof(uint64_t);
302 max_vf = max_bits * MAX_VFPF_DWORD_BITS;
304 for (vf = 0; vf < max_vf; vf++) {
305 if (dev->intr.bits[vf/max_bits] & BIT_ULL(vf%max_bits)) {
306 otx2_base_dbg("Process vf:%d request (pf:%d, vf:%d)",
307 vf, dev->pf, dev->vf);
308 vf_pf_process_msgs(dev, vf);
310 vf_pf_process_up_msgs(dev, vf);
311 dev->intr.bits[vf/max_bits] &= ~(BIT_ULL(vf%max_bits));
318 otx2_vf_pf_mbox_irq(void *param)
320 struct otx2_dev *dev = param;
321 bool alarm_set = false;
325 for (vfpf = 0; vfpf < MAX_VFPF_DWORD_BITS; ++vfpf) {
326 intr = otx2_read64(dev->bar2 + RVU_PF_VFPF_MBOX_INTX(vfpf));
330 otx2_base_dbg("vfpf: %d intr: 0x%" PRIx64 " (pf:%d, vf:%d)",
331 vfpf, intr, dev->pf, dev->vf);
333 /* Save and clear intr bits */
334 dev->intr.bits[vfpf] |= intr;
335 otx2_write64(intr, dev->bar2 + RVU_PF_VFPF_MBOX_INTX(vfpf));
339 if (!dev->timer_set && alarm_set) {
341 /* Start timer to handle messages */
342 rte_eal_alarm_set(VF_PF_MBOX_TIMER_MS,
343 otx2_vf_pf_mbox_handle_msg, dev);
348 otx2_process_msgs(struct otx2_dev *dev, struct otx2_mbox *mbox)
350 struct otx2_mbox_dev *mdev = &mbox->dev[0];
351 struct mbox_hdr *req_hdr;
352 struct mbox_msghdr *msg;
357 req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
358 if (req_hdr->num_msgs == 0)
361 offset = mbox->rx_start + RTE_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
362 for (i = 0; i < req_hdr->num_msgs; i++) {
363 msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
366 otx2_base_dbg("Message 0x%x (%s) pf:%d/vf:%d",
367 msg->id, otx2_mbox_id2name(msg->id),
368 otx2_get_pf(msg->pcifunc),
369 otx2_get_vf(msg->pcifunc));
372 /* Add message id's that are handled here */
374 /* Get our identity */
375 dev->pf_func = msg->pcifunc;
380 otx2_err("Message (%s) response has err=%d",
381 otx2_mbox_id2name(msg->id), msg->rc);
384 offset = mbox->rx_start + msg->next_msgoff;
387 otx2_mbox_reset(mbox, 0);
388 /* Update acked if someone is waiting a message */
389 mdev->msgs_acked = msgs_acked;
393 /* Copies the message received from AF and sends it to VF */
395 pf_vf_mbox_send_up_msg(struct otx2_dev *dev, void *rec_msg)
397 uint16_t max_bits = sizeof(dev->active_vfs[0]) * sizeof(uint64_t);
398 struct otx2_mbox *vf_mbox = &dev->mbox_vfpf_up;
399 struct msg_req *msg = rec_msg;
400 struct mbox_msghdr *vf_msg;
404 size = RTE_ALIGN(otx2_mbox_id2size(msg->hdr.id), MBOX_MSG_ALIGN);
405 /* Send UP message to all VF's */
406 for (vf = 0; vf < vf_mbox->ndevs; vf++) {
408 if (!(dev->active_vfs[vf / max_bits] & (BIT_ULL(vf))))
411 otx2_base_dbg("(%s) size: %zx to VF: %d",
412 otx2_mbox_id2name(msg->hdr.id), size, vf);
414 /* Reserve PF/VF mbox message */
415 vf_msg = otx2_mbox_alloc_msg(vf_mbox, vf, size);
417 otx2_err("Failed to alloc VF%d UP message", vf);
420 otx2_mbox_req_init(msg->hdr.id, vf_msg);
423 * Copy message from AF<->PF UP mbox
426 otx2_mbox_memcpy((uint8_t *)vf_msg +
427 sizeof(struct mbox_msghdr), (uint8_t *)msg
428 + sizeof(struct mbox_msghdr), size -
429 sizeof(struct mbox_msghdr));
431 vf_msg->rc = msg->hdr.rc;
432 /* Set PF to be a sender */
433 vf_msg->pcifunc = dev->pf_func;
436 otx2_mbox_msg_send(vf_mbox, vf);
441 otx2_mbox_up_handler_cgx_link_event(struct otx2_dev *dev,
442 struct cgx_link_info_msg *msg,
445 struct cgx_link_user_info *linfo = &msg->link_info;
447 otx2_base_dbg("pf:%d/vf:%d NIC Link %s --> 0x%x (%s) from: pf:%d/vf:%d",
448 otx2_get_pf(dev->pf_func), otx2_get_vf(dev->pf_func),
449 linfo->link_up ? "UP" : "DOWN", msg->hdr.id,
450 otx2_mbox_id2name(msg->hdr.id),
451 otx2_get_pf(msg->hdr.pcifunc),
452 otx2_get_vf(msg->hdr.pcifunc));
454 /* PF gets link notification from AF */
455 if (otx2_get_pf(msg->hdr.pcifunc) == 0) {
456 if (dev->ops && dev->ops->link_status_update)
457 dev->ops->link_status_update(dev, linfo);
459 /* Forward the same message as received from AF to VF */
460 pf_vf_mbox_send_up_msg(dev, msg);
462 /* VF gets link up notification */
463 if (dev->ops && dev->ops->link_status_update)
464 dev->ops->link_status_update(dev, linfo);
472 otx2_mbox_up_handler_cgx_ptp_rx_info(struct otx2_dev *dev,
473 struct cgx_ptp_rx_info_msg *msg,
476 otx2_nix_dbg("pf:%d/vf:%d PTP mode %s --> 0x%x (%s) from: pf:%d/vf:%d",
477 otx2_get_pf(dev->pf_func),
478 otx2_get_vf(dev->pf_func),
479 msg->ptp_en ? "ENABLED" : "DISABLED",
480 msg->hdr.id, otx2_mbox_id2name(msg->hdr.id),
481 otx2_get_pf(msg->hdr.pcifunc),
482 otx2_get_vf(msg->hdr.pcifunc));
484 /* PF gets PTP notification from AF */
485 if (otx2_get_pf(msg->hdr.pcifunc) == 0) {
486 if (dev->ops && dev->ops->ptp_info_update)
487 dev->ops->ptp_info_update(dev, msg->ptp_en);
489 /* Forward the same message as received from AF to VF */
490 pf_vf_mbox_send_up_msg(dev, msg);
492 /* VF gets PTP notification */
493 if (dev->ops && dev->ops->ptp_info_update)
494 dev->ops->ptp_info_update(dev, msg->ptp_en);
502 mbox_process_msgs_up(struct otx2_dev *dev, struct mbox_msghdr *req)
504 /* Check if valid, if not reply with a invalid msg */
505 if (req->sig != OTX2_MBOX_REQ_SIG)
509 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
511 struct _rsp_type *rsp; \
514 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \
516 sizeof(struct _rsp_type)); \
521 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \
522 rsp->hdr.pcifunc = dev->pf_func; \
525 err = otx2_mbox_up_handler_ ## _fn_name( \
526 dev, (struct _req_type *)req, rsp); \
533 otx2_reply_invalid_msg(&dev->mbox_up, 0, 0, req->id);
540 otx2_process_msgs_up(struct otx2_dev *dev, struct otx2_mbox *mbox)
542 struct otx2_mbox_dev *mdev = &mbox->dev[0];
543 struct mbox_hdr *req_hdr;
544 struct mbox_msghdr *msg;
547 req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
548 if (req_hdr->num_msgs == 0)
551 offset = mbox->rx_start + RTE_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
552 for (i = 0; i < req_hdr->num_msgs; i++) {
553 msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
555 otx2_base_dbg("Message 0x%x (%s) pf:%d/vf:%d",
556 msg->id, otx2_mbox_id2name(msg->id),
557 otx2_get_pf(msg->pcifunc),
558 otx2_get_vf(msg->pcifunc));
559 err = mbox_process_msgs_up(dev, msg);
561 otx2_err("Error %d handling 0x%x (%s)",
562 err, msg->id, otx2_mbox_id2name(msg->id));
563 offset = mbox->rx_start + msg->next_msgoff;
565 /* Send mbox responses */
566 if (mdev->num_msgs) {
567 otx2_base_dbg("Reply num_msgs:%d", mdev->num_msgs);
568 otx2_mbox_msg_send(mbox, 0);
573 otx2_pf_vf_mbox_irq(void *param)
575 struct otx2_dev *dev = param;
578 intr = otx2_read64(dev->bar2 + RVU_VF_INT);
582 otx2_write64(intr, dev->bar2 + RVU_VF_INT);
583 otx2_base_dbg("Irq 0x%" PRIx64 "(pf:%d,vf:%d)", intr, dev->pf, dev->vf);
585 /* First process all configuration messages */
586 otx2_process_msgs(dev, dev->mbox);
588 /* Process Uplink messages */
589 otx2_process_msgs_up(dev, &dev->mbox_up);
594 otx2_af_pf_mbox_irq(void *param)
596 struct otx2_dev *dev = param;
599 intr = otx2_read64(dev->bar2 + RVU_PF_INT);
603 otx2_write64(intr, dev->bar2 + RVU_PF_INT);
605 otx2_base_dbg("Irq 0x%" PRIx64 "(pf:%d,vf:%d)", intr, dev->pf, dev->vf);
607 /* First process all configuration messages */
608 otx2_process_msgs(dev, dev->mbox);
610 /* Process Uplink messages */
611 otx2_process_msgs_up(dev, &dev->mbox_up);
616 mbox_register_pf_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
618 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
622 for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i)
623 otx2_write64(~0ull, dev->bar2 +
624 RVU_PF_VFPF_MBOX_INT_ENA_W1CX(i));
626 otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
630 /* MBOX interrupt for VF(0...63) <-> PF */
631 rc = otx2_register_irq(intr_handle, otx2_vf_pf_mbox_irq, dev,
632 RVU_PF_INT_VEC_VFPF_MBOX0);
635 otx2_err("Fail to register PF(VF0-63) mbox irq");
638 /* MBOX interrupt for VF(64...128) <-> PF */
639 rc = otx2_register_irq(intr_handle, otx2_vf_pf_mbox_irq, dev,
640 RVU_PF_INT_VEC_VFPF_MBOX1);
643 otx2_err("Fail to register PF(VF64-128) mbox irq");
646 /* MBOX interrupt AF <-> PF */
647 rc = otx2_register_irq(intr_handle, otx2_af_pf_mbox_irq,
648 dev, RVU_PF_INT_VEC_AFPF_MBOX);
650 otx2_err("Fail to register AF<->PF mbox irq");
655 for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i)
656 otx2_write64(~0ull, dev->bar2 +
657 RVU_PF_VFPF_MBOX_INT_ENA_W1SX(i));
659 otx2_write64(~0ull, dev->bar2 + RVU_PF_INT);
660 otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);
666 mbox_register_vf_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
668 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
672 otx2_write64(~0ull, dev->bar2 + RVU_VF_INT_ENA_W1C);
674 /* MBOX interrupt PF <-> VF */
675 rc = otx2_register_irq(intr_handle, otx2_pf_vf_mbox_irq,
676 dev, RVU_VF_INT_VEC_MBOX);
678 otx2_err("Fail to register PF<->VF mbox irq");
683 otx2_write64(~0ull, dev->bar2 + RVU_VF_INT);
684 otx2_write64(~0ull, dev->bar2 + RVU_VF_INT_ENA_W1S);
690 mbox_register_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
692 if (otx2_dev_is_vf(dev))
693 return mbox_register_vf_irq(pci_dev, dev);
695 return mbox_register_pf_irq(pci_dev, dev);
699 mbox_unregister_pf_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
701 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
705 for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i)
706 otx2_write64(~0ull, dev->bar2 +
707 RVU_PF_VFPF_MBOX_INT_ENA_W1CX(i));
709 otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
713 rte_eal_alarm_cancel(otx2_vf_pf_mbox_handle_msg, dev);
715 /* Unregister the interrupt handler for each vectors */
716 /* MBOX interrupt for VF(0...63) <-> PF */
717 otx2_unregister_irq(intr_handle, otx2_vf_pf_mbox_irq, dev,
718 RVU_PF_INT_VEC_VFPF_MBOX0);
720 /* MBOX interrupt for VF(64...128) <-> PF */
721 otx2_unregister_irq(intr_handle, otx2_vf_pf_mbox_irq, dev,
722 RVU_PF_INT_VEC_VFPF_MBOX1);
724 /* MBOX interrupt AF <-> PF */
725 otx2_unregister_irq(intr_handle, otx2_af_pf_mbox_irq, dev,
726 RVU_PF_INT_VEC_AFPF_MBOX);
731 mbox_unregister_vf_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
733 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
736 otx2_write64(~0ull, dev->bar2 + RVU_VF_INT_ENA_W1C);
738 /* Unregister the interrupt handler */
739 otx2_unregister_irq(intr_handle, otx2_pf_vf_mbox_irq, dev,
740 RVU_VF_INT_VEC_MBOX);
744 mbox_unregister_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
746 if (otx2_dev_is_vf(dev))
747 return mbox_unregister_vf_irq(pci_dev, dev);
749 return mbox_unregister_pf_irq(pci_dev, dev);
753 vf_flr_send_msg(struct otx2_dev *dev, uint16_t vf)
755 struct otx2_mbox *mbox = dev->mbox;
759 req = otx2_mbox_alloc_msg_vf_flr(mbox);
760 /* Overwrite pcifunc to indicate VF */
761 req->hdr.pcifunc = otx2_pfvf_func(dev->pf, vf);
763 /* Sync message in interrupt context */
764 rc = pf_af_sync_msg(dev, NULL);
766 otx2_err("Failed to send VF FLR mbox msg, rc=%d", rc);
772 otx2_pf_vf_flr_irq(void *param)
774 struct otx2_dev *dev = (struct otx2_dev *)param;
775 uint16_t max_vf = 64, vf;
780 max_vf = (dev->maxvf > 0) ? dev->maxvf : 64;
783 otx2_base_dbg("FLR VF interrupt: max_vf: %d", max_vf);
785 for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i) {
786 intr = otx2_read64(bar2 + RVU_PF_VFFLR_INTX(i));
790 for (vf = 0; vf < max_vf; vf++) {
791 if (!(intr & (1ULL << vf)))
795 otx2_base_dbg("FLR: i :%d intr: 0x%" PRIx64 ", vf-%d",
797 /* Clear interrupt */
798 otx2_write64(BIT_ULL(vf), bar2 + RVU_PF_VFFLR_INTX(i));
799 /* Disable the interrupt */
800 otx2_write64(BIT_ULL(vf),
801 bar2 + RVU_PF_VFFLR_INT_ENA_W1CX(i));
802 /* Inform AF about VF reset */
803 vf_flr_send_msg(dev, vf);
805 /* Signal FLR finish */
806 otx2_write64(BIT_ULL(vf), bar2 + RVU_PF_VFTRPENDX(i));
807 /* Enable interrupt */
809 bar2 + RVU_PF_VFFLR_INT_ENA_W1SX(i));
815 vf_flr_unregister_irqs(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
817 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
820 otx2_base_dbg("Unregister VF FLR interrupts for %s", pci_dev->name);
823 for (i = 0; i < MAX_VFPF_DWORD_BITS; i++)
824 otx2_write64(~0ull, dev->bar2 + RVU_PF_VFFLR_INT_ENA_W1CX(i));
826 otx2_unregister_irq(intr_handle, otx2_pf_vf_flr_irq, dev,
827 RVU_PF_INT_VEC_VFFLR0);
829 otx2_unregister_irq(intr_handle, otx2_pf_vf_flr_irq, dev,
830 RVU_PF_INT_VEC_VFFLR1);
836 vf_flr_register_irqs(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
838 struct rte_intr_handle *handle = &pci_dev->intr_handle;
841 otx2_base_dbg("Register VF FLR interrupts for %s", pci_dev->name);
843 rc = otx2_register_irq(handle, otx2_pf_vf_flr_irq, dev,
844 RVU_PF_INT_VEC_VFFLR0);
846 otx2_err("Failed to init RVU_PF_INT_VEC_VFFLR0 rc=%d", rc);
848 rc = otx2_register_irq(handle, otx2_pf_vf_flr_irq, dev,
849 RVU_PF_INT_VEC_VFFLR1);
851 otx2_err("Failed to init RVU_PF_INT_VEC_VFFLR1 rc=%d", rc);
853 /* Enable HW interrupt */
854 for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i) {
855 otx2_write64(~0ull, dev->bar2 + RVU_PF_VFFLR_INTX(i));
856 otx2_write64(~0ull, dev->bar2 + RVU_PF_VFTRPENDX(i));
857 otx2_write64(~0ull, dev->bar2 + RVU_PF_VFFLR_INT_ENA_W1SX(i));
864 * Get number of active VFs for the given PF device.
867 otx2_dev_active_vfs(void *otx2_dev)
869 struct otx2_dev *dev = otx2_dev;
872 for (i = 0; i < MAX_VFPF_DWORD_BITS; i++)
873 count += __builtin_popcount(dev->active_vfs[i]);
879 otx2_update_pass_hwcap(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
881 RTE_SET_USED(pci_dev);
883 /* Update this logic when we have A1 */
884 dev->hwcap |= OTX2_HWCAP_F_A0;
888 otx2_update_vf_hwcap(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
892 switch (pci_dev->id.device_id) {
893 case PCI_DEVID_OCTEONTX2_RVU_PF:
895 case PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_VF:
896 case PCI_DEVID_OCTEONTX2_RVU_NPA_VF:
897 case PCI_DEVID_OCTEONTX2_RVU_CPT_VF:
898 case PCI_DEVID_OCTEONTX2_RVU_AF_VF:
899 case PCI_DEVID_OCTEONTX2_RVU_VF:
900 dev->hwcap |= OTX2_HWCAP_F_VF;
907 * Initialize the otx2 device
910 otx2_dev_init(struct rte_pci_device *pci_dev, void *otx2_dev)
912 int up_direction = MBOX_DIR_PFAF_UP;
913 int rc, direction = MBOX_DIR_PFAF;
914 struct otx2_dev *dev = otx2_dev;
915 uintptr_t bar2, bar4;
919 bar2 = (uintptr_t)pci_dev->mem_resource[2].addr;
920 bar4 = (uintptr_t)pci_dev->mem_resource[4].addr;
922 if (bar2 == 0 || bar4 == 0) {
923 otx2_err("Failed to get pci bars");
928 dev->node = pci_dev->device.numa_node;
929 dev->maxvf = pci_dev->max_vfs;
933 otx2_update_vf_hwcap(pci_dev, dev);
934 otx2_update_pass_hwcap(pci_dev, dev);
936 if (otx2_dev_is_vf(dev)) {
937 direction = MBOX_DIR_VFPF;
938 up_direction = MBOX_DIR_VFPF_UP;
941 /* Initialize the local mbox */
942 rc = otx2_mbox_init(&dev->mbox_local, bar4, bar2, direction, 1);
945 dev->mbox = &dev->mbox_local;
947 rc = otx2_mbox_init(&dev->mbox_up, bar4, bar2, up_direction, 1);
951 /* Register mbox interrupts */
952 rc = mbox_register_irq(pci_dev, dev);
956 /* Check the readiness of PF/VF */
957 rc = otx2_send_ready_msg(dev->mbox, &dev->pf_func);
959 goto mbox_unregister;
961 dev->pf = otx2_get_pf(dev->pf_func);
962 dev->vf = otx2_get_vf(dev->pf_func);
963 memset(&dev->active_vfs, 0, sizeof(dev->active_vfs));
965 /* Found VF devices in a PF device */
966 if (pci_dev->max_vfs > 0) {
968 /* Remap mbox area for all vf's */
969 bar4_addr = otx2_read64(bar2 + RVU_PF_VF_BAR4_ADDR);
970 if (bar4_addr == 0) {
975 hwbase = mbox_mem_map(bar4_addr, MBOX_SIZE * pci_dev->max_vfs);
976 if (hwbase == MAP_FAILED) {
980 /* Init mbox object */
981 rc = otx2_mbox_init(&dev->mbox_vfpf, (uintptr_t)hwbase,
982 bar2, MBOX_DIR_PFVF, pci_dev->max_vfs);
986 /* PF -> VF UP messages */
987 rc = otx2_mbox_init(&dev->mbox_vfpf_up, (uintptr_t)hwbase,
988 bar2, MBOX_DIR_PFVF_UP, pci_dev->max_vfs);
993 /* Register VF-FLR irq handlers */
994 if (otx2_dev_is_pf(dev)) {
995 rc = vf_flr_register_irqs(pci_dev, dev);
999 dev->mbox_active = 1;
1003 mbox_mem_unmap(hwbase, MBOX_SIZE * pci_dev->max_vfs);
1005 mbox_unregister_irq(pci_dev, dev);
1007 otx2_mbox_fini(dev->mbox);
1008 otx2_mbox_fini(&dev->mbox_up);
1015 * Finalize the otx2 device
1018 otx2_dev_fini(struct rte_pci_device *pci_dev, void *otx2_dev)
1020 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1021 struct otx2_dev *dev = otx2_dev;
1022 struct otx2_idev_cfg *idev;
1023 struct otx2_mbox *mbox;
1025 /* Clear references to this pci dev */
1026 idev = otx2_intra_dev_get_cfg();
1027 if (idev->npa_lf && idev->npa_lf->pci_dev == pci_dev)
1028 idev->npa_lf = NULL;
1030 mbox_unregister_irq(pci_dev, dev);
1032 if (otx2_dev_is_pf(dev))
1033 vf_flr_unregister_irqs(pci_dev, dev);
1034 /* Release PF - VF */
1035 mbox = &dev->mbox_vfpf;
1036 if (mbox->hwbase && mbox->dev)
1037 mbox_mem_unmap((void *)mbox->hwbase,
1038 MBOX_SIZE * pci_dev->max_vfs);
1039 otx2_mbox_fini(mbox);
1040 mbox = &dev->mbox_vfpf_up;
1041 otx2_mbox_fini(mbox);
1043 /* Release PF - AF */
1045 otx2_mbox_fini(mbox);
1046 mbox = &dev->mbox_up;
1047 otx2_mbox_fini(mbox);
1048 dev->mbox_active = 0;
1050 /* Disable MSIX vectors */
1051 otx2_disable_irqs(intr_handle);