1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
10 #include <rte_alarm.h>
11 #include <rte_common.h>
13 #include <rte_memcpy.h>
16 #include "otx2_mbox.h"
18 #define RVU_MAX_VF 64 /* RVU_PF_VFPF_MBOX_INT(0..1) */
19 #define RVU_MAX_INT_RETRY 3
21 /* PF/VF message handling timer */
22 #define VF_PF_MBOX_TIMER_MS (20 * 1000)
25 mbox_mem_map(off_t off, size_t size)
27 void *va = MAP_FAILED;
33 mem_fd = open("/dev/mem", O_RDWR);
37 va = mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, mem_fd, off);
41 otx2_err("Failed to mmap sz=0x%zx, fd=%d, off=%jd",
42 size, mem_fd, (intmax_t)off);
48 mbox_mem_unmap(void *va, size_t size)
55 af_pf_wait_msg(struct otx2_dev *dev, uint16_t vf, int num_msg)
57 uint32_t timeout = 0, sleep = 1; struct otx2_mbox *mbox = dev->mbox;
58 struct otx2_mbox_dev *mdev = &mbox->dev[0];
59 volatile uint64_t int_status;
60 struct mbox_hdr *req_hdr;
61 struct mbox_msghdr *msg;
62 struct mbox_msghdr *rsp;
67 /* We need to disable PF interrupts. We are in timer interrupt */
68 otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
71 otx2_mbox_msg_send(mbox, 0);
76 if (timeout >= MBOX_RSP_TIMEOUT) {
77 otx2_err("Routed messages %d timeout: %dms",
78 num_msg, MBOX_RSP_TIMEOUT);
81 int_status = otx2_read64(dev->bar2 + RVU_PF_INT);
82 } while ((int_status & 0x1) != 0x1);
85 otx2_write64(~0ull, dev->bar2 + RVU_PF_INT);
87 /* Enable interrupts */
88 otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);
90 rte_spinlock_lock(&mdev->mbox_lock);
92 req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
93 if (req_hdr->num_msgs != num_msg)
94 otx2_err("Routed messages: %d received: %d", num_msg,
97 /* Get messages from mbox */
98 offset = mbox->rx_start +
99 RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
100 for (i = 0; i < req_hdr->num_msgs; i++) {
101 msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
102 size = mbox->rx_start + msg->next_msgoff - offset;
104 /* Reserve PF/VF mbox message */
105 size = RTE_ALIGN(size, MBOX_MSG_ALIGN);
106 rsp = otx2_mbox_alloc_msg(&dev->mbox_vfpf, vf, size);
107 otx2_mbox_rsp_init(msg->id, rsp);
109 /* Copy message from AF<->PF mbox to PF<->VF mbox */
110 otx2_mbox_memcpy((uint8_t *)rsp + sizeof(struct mbox_msghdr),
111 (uint8_t *)msg + sizeof(struct mbox_msghdr),
112 size - sizeof(struct mbox_msghdr));
114 /* Set status and sender pf_func data */
116 rsp->pcifunc = msg->pcifunc;
118 offset = mbox->rx_start + msg->next_msgoff;
120 rte_spinlock_unlock(&mdev->mbox_lock);
122 return req_hdr->num_msgs;
126 vf_pf_process_msgs(struct otx2_dev *dev, uint16_t vf)
128 int offset, routed = 0; struct otx2_mbox *mbox = &dev->mbox_vfpf;
129 struct otx2_mbox_dev *mdev = &mbox->dev[vf];
130 struct mbox_hdr *req_hdr;
131 struct mbox_msghdr *msg;
135 req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
136 if (!req_hdr->num_msgs)
139 offset = mbox->rx_start + RTE_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
141 for (i = 0; i < req_hdr->num_msgs; i++) {
143 msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
144 size = mbox->rx_start + msg->next_msgoff - offset;
147 msg->pcifunc = otx2_pfvf_func(dev->pf, vf);
149 if (msg->id == MBOX_MSG_READY) {
150 struct ready_msg_rsp *rsp;
151 uint16_t max_bits = sizeof(dev->active_vfs[0]) * 8;
153 /* Handle READY message in PF */
154 dev->active_vfs[vf / max_bits] |=
155 BIT_ULL(vf % max_bits);
156 rsp = (struct ready_msg_rsp *)
157 otx2_mbox_alloc_msg(mbox, vf, sizeof(*rsp));
158 otx2_mbox_rsp_init(msg->id, rsp);
160 /* PF/VF function ID */
161 rsp->hdr.pcifunc = msg->pcifunc;
164 struct mbox_msghdr *af_req;
165 /* Reserve AF/PF mbox message */
166 size = RTE_ALIGN(size, MBOX_MSG_ALIGN);
167 af_req = otx2_mbox_alloc_msg(dev->mbox, 0, size);
168 otx2_mbox_req_init(msg->id, af_req);
170 /* Copy message from VF<->PF mbox to PF<->AF mbox */
171 otx2_mbox_memcpy((uint8_t *)af_req +
172 sizeof(struct mbox_msghdr),
173 (uint8_t *)msg + sizeof(struct mbox_msghdr),
174 size - sizeof(struct mbox_msghdr));
175 af_req->pcifunc = msg->pcifunc;
178 offset = mbox->rx_start + msg->next_msgoff;
182 otx2_base_dbg("pf:%d routed %d messages from vf:%d to AF",
183 dev->pf, routed, vf);
184 af_pf_wait_msg(dev, vf, routed);
185 otx2_mbox_reset(dev->mbox, 0);
188 /* Send mbox responses to VF */
189 if (mdev->num_msgs) {
190 otx2_base_dbg("pf:%d reply %d messages to vf:%d",
191 dev->pf, mdev->num_msgs, vf);
192 otx2_mbox_msg_send(mbox, vf);
199 otx2_vf_pf_mbox_handle_msg(void *param)
201 uint16_t vf, max_vf, max_bits;
202 struct otx2_dev *dev = param;
204 max_bits = sizeof(dev->intr.bits[0]) * sizeof(uint64_t);
205 max_vf = max_bits * MAX_VFPF_DWORD_BITS;
207 for (vf = 0; vf < max_vf; vf++) {
208 if (dev->intr.bits[vf/max_bits] & BIT_ULL(vf%max_bits)) {
209 otx2_base_dbg("Process vf:%d request (pf:%d, vf:%d)",
210 vf, dev->pf, dev->vf);
211 vf_pf_process_msgs(dev, vf);
212 dev->intr.bits[vf/max_bits] &= ~(BIT_ULL(vf%max_bits));
219 otx2_vf_pf_mbox_irq(void *param)
221 struct otx2_dev *dev = param;
222 bool alarm_set = false;
226 for (vfpf = 0; vfpf < MAX_VFPF_DWORD_BITS; ++vfpf) {
227 intr = otx2_read64(dev->bar2 + RVU_PF_VFPF_MBOX_INTX(vfpf));
231 otx2_base_dbg("vfpf: %d intr: 0x%" PRIx64 " (pf:%d, vf:%d)",
232 vfpf, intr, dev->pf, dev->vf);
234 /* Save and clear intr bits */
235 dev->intr.bits[vfpf] |= intr;
236 otx2_write64(intr, dev->bar2 + RVU_PF_VFPF_MBOX_INTX(vfpf));
240 if (!dev->timer_set && alarm_set) {
242 /* Start timer to handle messages */
243 rte_eal_alarm_set(VF_PF_MBOX_TIMER_MS,
244 otx2_vf_pf_mbox_handle_msg, dev);
249 otx2_process_msgs(struct otx2_dev *dev, struct otx2_mbox *mbox)
251 struct otx2_mbox_dev *mdev = &mbox->dev[0];
252 struct mbox_hdr *req_hdr;
253 struct mbox_msghdr *msg;
258 req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
259 if (req_hdr->num_msgs == 0)
262 offset = mbox->rx_start + RTE_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
263 for (i = 0; i < req_hdr->num_msgs; i++) {
264 msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
267 otx2_base_dbg("Message 0x%x (%s) pf:%d/vf:%d",
268 msg->id, otx2_mbox_id2name(msg->id),
269 otx2_get_pf(msg->pcifunc),
270 otx2_get_vf(msg->pcifunc));
273 /* Add message id's that are handled here */
275 /* Get our identity */
276 dev->pf_func = msg->pcifunc;
281 otx2_err("Message (%s) response has err=%d",
282 otx2_mbox_id2name(msg->id), msg->rc);
285 offset = mbox->rx_start + msg->next_msgoff;
288 otx2_mbox_reset(mbox, 0);
289 /* Update acked if someone is waiting a message */
290 mdev->msgs_acked = msgs_acked;
295 otx2_af_pf_mbox_irq(void *param)
297 struct otx2_dev *dev = param;
300 intr = otx2_read64(dev->bar2 + RVU_PF_INT);
304 otx2_write64(intr, dev->bar2 + RVU_PF_INT);
306 otx2_base_dbg("Irq 0x%" PRIx64 "(pf:%d,vf:%d)", intr, dev->pf, dev->vf);
308 /* First process all configuration messages */
309 otx2_process_msgs(dev, dev->mbox);
313 mbox_register_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
315 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
319 for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i)
320 otx2_write64(~0ull, dev->bar2 +
321 RVU_PF_VFPF_MBOX_INT_ENA_W1CX(i));
323 otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
327 /* MBOX interrupt for VF(0...63) <-> PF */
328 rc = otx2_register_irq(intr_handle, otx2_vf_pf_mbox_irq, dev,
329 RVU_PF_INT_VEC_VFPF_MBOX0);
332 otx2_err("Fail to register PF(VF0-63) mbox irq");
335 /* MBOX interrupt for VF(64...128) <-> PF */
336 rc = otx2_register_irq(intr_handle, otx2_vf_pf_mbox_irq, dev,
337 RVU_PF_INT_VEC_VFPF_MBOX1);
340 otx2_err("Fail to register PF(VF64-128) mbox irq");
343 /* MBOX interrupt AF <-> PF */
344 rc = otx2_register_irq(intr_handle, otx2_af_pf_mbox_irq,
345 dev, RVU_PF_INT_VEC_AFPF_MBOX);
347 otx2_err("Fail to register AF<->PF mbox irq");
352 for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i)
353 otx2_write64(~0ull, dev->bar2 +
354 RVU_PF_VFPF_MBOX_INT_ENA_W1SX(i));
356 otx2_write64(~0ull, dev->bar2 + RVU_PF_INT);
357 otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);
363 mbox_unregister_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
365 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
369 for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i)
370 otx2_write64(~0ull, dev->bar2 +
371 RVU_PF_VFPF_MBOX_INT_ENA_W1CX(i));
373 otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
377 rte_eal_alarm_cancel(otx2_vf_pf_mbox_handle_msg, dev);
379 /* Unregister the interrupt handler for each vectors */
380 /* MBOX interrupt for VF(0...63) <-> PF */
381 otx2_unregister_irq(intr_handle, otx2_vf_pf_mbox_irq, dev,
382 RVU_PF_INT_VEC_VFPF_MBOX0);
384 /* MBOX interrupt for VF(64...128) <-> PF */
385 otx2_unregister_irq(intr_handle, otx2_vf_pf_mbox_irq, dev,
386 RVU_PF_INT_VEC_VFPF_MBOX1);
388 /* MBOX interrupt AF <-> PF */
389 otx2_unregister_irq(intr_handle, otx2_af_pf_mbox_irq, dev,
390 RVU_PF_INT_VEC_AFPF_MBOX);
394 otx2_update_pass_hwcap(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
396 RTE_SET_USED(pci_dev);
398 /* Update this logic when we have A1 */
399 dev->hwcap |= OTX2_HWCAP_F_A0;
403 otx2_update_vf_hwcap(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
407 switch (pci_dev->id.device_id) {
408 case PCI_DEVID_OCTEONTX2_RVU_PF:
410 case PCI_DEVID_OCTEONTX2_RVU_SSO_TIM_VF:
411 case PCI_DEVID_OCTEONTX2_RVU_NPA_VF:
412 case PCI_DEVID_OCTEONTX2_RVU_CPT_VF:
413 case PCI_DEVID_OCTEONTX2_RVU_AF_VF:
414 case PCI_DEVID_OCTEONTX2_RVU_VF:
415 dev->hwcap |= OTX2_HWCAP_F_VF;
422 * Initialize the otx2 device
425 otx2_dev_init(struct rte_pci_device *pci_dev, void *otx2_dev)
427 int up_direction = MBOX_DIR_PFAF_UP;
428 int rc, direction = MBOX_DIR_PFAF;
429 struct otx2_dev *dev = otx2_dev;
430 uintptr_t bar2, bar4;
434 bar2 = (uintptr_t)pci_dev->mem_resource[2].addr;
435 bar4 = (uintptr_t)pci_dev->mem_resource[4].addr;
437 if (bar2 == 0 || bar4 == 0) {
438 otx2_err("Failed to get pci bars");
443 dev->node = pci_dev->device.numa_node;
444 dev->maxvf = pci_dev->max_vfs;
448 otx2_update_vf_hwcap(pci_dev, dev);
449 otx2_update_pass_hwcap(pci_dev, dev);
451 if (otx2_dev_is_vf(dev)) {
452 direction = MBOX_DIR_VFPF;
453 up_direction = MBOX_DIR_VFPF_UP;
456 /* Initialize the local mbox */
457 rc = otx2_mbox_init(&dev->mbox_local, bar4, bar2, direction, 1);
460 dev->mbox = &dev->mbox_local;
462 rc = otx2_mbox_init(&dev->mbox_up, bar4, bar2, up_direction, 1);
466 /* Register mbox interrupts */
467 rc = mbox_register_irq(pci_dev, dev);
471 /* Check the readiness of PF/VF */
472 rc = otx2_send_ready_msg(dev->mbox, &dev->pf_func);
474 goto mbox_unregister;
476 dev->pf = otx2_get_pf(dev->pf_func);
477 dev->vf = otx2_get_vf(dev->pf_func);
478 memset(&dev->active_vfs, 0, sizeof(dev->active_vfs));
480 /* Found VF devices in a PF device */
481 if (pci_dev->max_vfs > 0) {
483 /* Remap mbox area for all vf's */
484 bar4_addr = otx2_read64(bar2 + RVU_PF_VF_BAR4_ADDR);
485 if (bar4_addr == 0) {
490 hwbase = mbox_mem_map(bar4_addr, MBOX_SIZE * pci_dev->max_vfs);
491 if (hwbase == MAP_FAILED) {
495 /* Init mbox object */
496 rc = otx2_mbox_init(&dev->mbox_vfpf, (uintptr_t)hwbase,
497 bar2, MBOX_DIR_PFVF, pci_dev->max_vfs);
501 /* PF -> VF UP messages */
502 rc = otx2_mbox_init(&dev->mbox_vfpf_up, (uintptr_t)hwbase,
503 bar2, MBOX_DIR_PFVF_UP, pci_dev->max_vfs);
508 dev->mbox_active = 1;
512 mbox_mem_unmap(hwbase, MBOX_SIZE * pci_dev->max_vfs);
514 mbox_unregister_irq(pci_dev, dev);
516 otx2_mbox_fini(dev->mbox);
517 otx2_mbox_fini(&dev->mbox_up);
524 * Finalize the otx2 device
527 otx2_dev_fini(struct rte_pci_device *pci_dev, void *otx2_dev)
529 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
530 struct otx2_dev *dev = otx2_dev;
531 struct otx2_idev_cfg *idev;
532 struct otx2_mbox *mbox;
534 /* Clear references to this pci dev */
535 idev = otx2_intra_dev_get_cfg();
536 if (idev->npa_lf && idev->npa_lf->pci_dev == pci_dev)
539 mbox_unregister_irq(pci_dev, dev);
541 /* Release PF - VF */
542 mbox = &dev->mbox_vfpf;
543 if (mbox->hwbase && mbox->dev)
544 mbox_mem_unmap((void *)mbox->hwbase,
545 MBOX_SIZE * pci_dev->max_vfs);
546 otx2_mbox_fini(mbox);
547 mbox = &dev->mbox_vfpf_up;
548 otx2_mbox_fini(mbox);
550 /* Release PF - AF */
552 otx2_mbox_fini(mbox);
553 mbox = &dev->mbox_up;
554 otx2_mbox_fini(mbox);
555 dev->mbox_active = 0;
557 /* Disable MSIX vectors */
558 otx2_disable_irqs(intr_handle);