1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef __OTX2_MBOX_H__
6 #define __OTX2_MBOX_H__
11 #include <rte_ether.h>
12 #include <rte_spinlock.h>
14 #include <otx2_common.h>
16 #define SZ_64K (64ULL * 1024ULL)
17 #define SZ_1K (1ULL * 1024ULL)
18 #define MBOX_SIZE SZ_64K
20 /* AF/PF: PF initiated, PF/VF VF initiated */
21 #define MBOX_DOWN_RX_START 0
22 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
23 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
24 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
25 /* AF/PF: AF initiated, PF/VF PF initiated */
26 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
27 #define MBOX_UP_RX_SIZE SZ_1K
28 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
29 #define MBOX_UP_TX_SIZE SZ_1K
31 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
32 # error "Incorrect mailbox area sizes"
35 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
37 #define MBOX_RSP_TIMEOUT 3000 /* Time to wait for mbox response in ms */
39 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
41 /* Mailbox directions */
42 #define MBOX_DIR_AFPF 0 /* AF replies to PF */
43 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */
44 #define MBOX_DIR_PFVF 2 /* PF replies to VF */
45 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */
46 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */
47 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */
48 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */
49 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */
51 /* Device memory does not support unaligned access, instruct compiler to
52 * not optimize the memory access when working with mailbox memory.
54 #define __otx2_io volatile
56 struct otx2_mbox_dev {
57 void *mbase; /* This dev's mbox region */
58 rte_spinlock_t mbox_lock;
59 uint16_t msg_size; /* Total msg size to be sent */
60 uint16_t rsp_size; /* Total rsp size to be sure the reply is ok */
61 uint16_t num_msgs; /* No of msgs sent or waiting for response */
62 uint16_t msgs_acked; /* No of msgs for which response is received */
66 uintptr_t hwbase; /* Mbox region advertised by HW */
67 uintptr_t reg_base;/* CSR base for this dev */
68 uint64_t trigger; /* Trigger mbox notification */
69 uint16_t tr_shift; /* Mbox trigger shift */
70 uint64_t rx_start; /* Offset of Rx region in mbox memory */
71 uint64_t tx_start; /* Offset of Tx region in mbox memory */
72 uint16_t rx_size; /* Size of Rx region */
73 uint16_t tx_size; /* Size of Tx region */
74 uint16_t ndevs; /* The number of peers */
75 struct otx2_mbox_dev *dev;
76 uint64_t intr_offset; /* Offset to interrupt register */
79 /* Header which precedes all mbox messages */
81 uint64_t __otx2_io msg_size; /* Total msgs size embedded */
82 uint16_t __otx2_io num_msgs; /* No of msgs embedded */
85 /* Header which precedes every msg and is also part of it */
87 uint16_t __otx2_io pcifunc; /* Who's sending this msg */
88 uint16_t __otx2_io id; /* Mbox message ID */
89 #define OTX2_MBOX_REQ_SIG (0xdead)
90 #define OTX2_MBOX_RSP_SIG (0xbeef)
91 /* Signature, for validating corrupted msgs */
92 uint16_t __otx2_io sig;
93 #define OTX2_MBOX_VERSION (0x0007)
94 /* Version of msg's structure for this ID */
95 uint16_t __otx2_io ver;
96 /* Offset of next msg within mailbox region */
97 uint16_t __otx2_io next_msgoff;
98 int __otx2_io rc; /* Msg processed response code */
101 /* Mailbox message types */
102 #define MBOX_MSG_MASK 0xFFFF
103 #define MBOX_MSG_INVALID 0xFFFE
104 #define MBOX_MSG_MAX 0xFFFF
106 #define MBOX_MESSAGES \
107 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
108 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
109 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach_req, msg_rsp)\
110 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach_req, msg_rsp)\
111 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
112 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
113 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
114 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
115 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
116 M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \
117 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
118 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
119 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
120 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
121 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get,\
122 cgx_mac_addr_set_or_get) \
123 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get,\
124 cgx_mac_addr_set_or_get) \
125 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
126 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
127 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
128 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
129 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg)\
130 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
131 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
132 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
133 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
134 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
136 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
137 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
138 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
139 cgx_mac_addr_add_rsp) \
140 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
142 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
143 cgx_max_dmac_entries_get_rsp) \
144 M(CGX_SET_LINK_STATE, 0x214, cgx_set_link_state, \
145 cgx_set_link_state_msg, msg_rsp) \
146 M(CGX_GET_PHY_MOD_TYPE, 0x215, cgx_get_phy_mod_type, msg_req, \
148 M(CGX_SET_PHY_MOD_TYPE, 0x216, cgx_set_phy_mod_type, cgx_phy_mod_type, \
150 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
151 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\
152 cgx_set_link_mode_rsp) \
153 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
154 M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \
155 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
156 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, npa_lf_alloc_req, \
158 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
159 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp)\
160 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
161 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
162 M(SSO_LF_ALLOC, 0x600, sso_lf_alloc, sso_lf_alloc_req, \
164 M(SSO_LF_FREE, 0x601, sso_lf_free, sso_lf_free_req, msg_rsp) \
165 M(SSOW_LF_ALLOC, 0x602, ssow_lf_alloc, ssow_lf_alloc_req, msg_rsp)\
166 M(SSOW_LF_FREE, 0x603, ssow_lf_free, ssow_lf_free_req, msg_rsp) \
167 M(SSO_HW_SETCONFIG, 0x604, sso_hw_setconfig, sso_hw_setconfig, \
169 M(SSO_GRP_SET_PRIORITY, 0x605, sso_grp_set_priority, sso_grp_priority, \
171 M(SSO_GRP_GET_PRIORITY, 0x606, sso_grp_get_priority, sso_info_req, \
173 M(SSO_WS_CACHE_INV, 0x607, sso_ws_cache_inv, msg_req, msg_rsp) \
174 M(SSO_GRP_QOS_CONFIG, 0x608, sso_grp_qos_config, sso_grp_qos_cfg, \
176 M(SSO_GRP_GET_STATS, 0x609, sso_grp_get_stats, sso_info_req, \
178 M(SSO_HWS_GET_STATS, 0x610, sso_hws_get_stats, sso_info_req, \
180 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
181 M(TIM_LF_ALLOC, 0x800, tim_lf_alloc, tim_lf_alloc_req, \
183 M(TIM_LF_FREE, 0x801, tim_lf_free, tim_ring_req, msg_rsp) \
184 M(TIM_CONFIG_RING, 0x802, tim_config_ring, tim_config_req, msg_rsp)\
185 M(TIM_ENABLE_RING, 0x803, tim_enable_ring, tim_ring_req, \
187 M(TIM_DISABLE_RING, 0x804, tim_disable_ring, tim_ring_req, msg_rsp) \
188 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
189 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \
190 cpt_lf_alloc_rsp_msg) \
191 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
192 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
194 M(CPT_SET_CRYPTO_GRP, 0xA03, cpt_set_crypto_grp, \
195 cpt_set_crypto_grp_req_msg, \
197 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
198 cpt_inline_ipsec_cfg_msg, msg_rsp) \
199 M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg, \
200 cpt_rx_inline_lf_cfg_msg, msg_rsp) \
201 M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg) \
202 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
203 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, \
204 npc_mcam_alloc_entry_req, \
205 npc_mcam_alloc_entry_rsp) \
206 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
207 npc_mcam_free_entry_req, msg_rsp) \
208 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
209 npc_mcam_write_entry_req, msg_rsp) \
210 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
211 npc_mcam_ena_dis_entry_req, msg_rsp) \
212 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
213 npc_mcam_ena_dis_entry_req, msg_rsp) \
214 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, \
215 npc_mcam_shift_entry_req, \
216 npc_mcam_shift_entry_rsp) \
217 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
218 npc_mcam_alloc_counter_req, \
219 npc_mcam_alloc_counter_rsp) \
220 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
221 npc_mcam_oper_counter_req, \
223 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
224 npc_mcam_unmap_counter_req, \
226 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
227 npc_mcam_oper_counter_req, \
229 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
230 npc_mcam_oper_counter_req, \
231 npc_mcam_oper_counter_rsp) \
232 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry,\
233 npc_mcam_alloc_and_write_entry_req, \
234 npc_mcam_alloc_and_write_entry_rsp) \
235 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, msg_req, \
236 npc_get_kex_cfg_rsp) \
237 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \
238 npc_install_flow_req, \
239 npc_install_flow_rsp) \
240 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \
241 npc_delete_flow_req, msg_rsp) \
242 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
243 npc_mcam_read_entry_req, \
244 npc_mcam_read_entry_rsp) \
245 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \
248 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
249 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, nix_lf_alloc_req, \
251 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
252 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, \
254 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, hwctx_disable_req, \
256 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, nix_txsch_alloc_req, \
257 nix_txsch_alloc_rsp) \
258 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, \
260 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
262 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
263 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \
264 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
265 nix_rss_flowkey_cfg, \
266 nix_rss_flowkey_cfg_rsp) \
267 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, \
269 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
270 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
271 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
272 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
273 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
274 nix_mark_format_cfg, \
275 nix_mark_format_cfg_rsp) \
276 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
277 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, nix_lso_format_cfg, \
278 nix_lso_format_cfg_rsp) \
279 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, \
281 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, \
283 M(NIX_SET_VLAN_TPID, 0x8015, nix_set_vlan_tpid, nix_set_vlan_tpid, \
285 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
287 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp)\
288 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, \
289 nix_get_mac_addr_rsp) \
290 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \
291 nix_inline_ipsec_cfg, msg_rsp) \
292 M(NIX_INLINE_IPSEC_LF_CFG, \
293 0x801a, nix_inline_ipsec_lf_cfg, \
294 nix_inline_ipsec_lf_cfg, msg_rsp)
296 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
297 #define MBOX_UP_CGX_MESSAGES \
298 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, \
300 M(CGX_PTP_RX_INFO, 0xC01, cgx_ptp_rx_info, cgx_ptp_rx_info_msg, \
304 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
310 /* Mailbox message formats */
312 #define RVU_DEFAULT_PF_FUNC 0xFFFF
314 /* Generic request msg used for those mbox messages which
315 * don't send any data in the request.
318 struct mbox_msghdr hdr;
321 /* Generic response msg used a ack or response for those mbox
322 * messages which doesn't have a specific rsp msg format.
325 struct mbox_msghdr hdr;
328 /* RVU mailbox error codes
332 RVU_INVALID_VF_ID = -256,
335 struct ready_msg_rsp {
336 struct mbox_msghdr hdr;
337 uint16_t __otx2_io sclk_feq; /* SCLK frequency */
338 uint16_t __otx2_io rclk_freq; /* RCLK frequency */
341 /* Struct to set pkind */
342 struct npc_set_pkind {
343 struct mbox_msghdr hdr;
344 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0)
345 #define OTX2_PRIV_FLAGS_EDSA BIT_ULL(1)
346 #define OTX2_PRIV_FLAGS_HIGIG BIT_ULL(2)
347 #define OTX2_PRIV_FLAGS_LEN_90B BIT_ULL(3)
348 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63)
349 uint64_t __otx2_io mode;
350 #define PKIND_TX BIT_ULL(0)
351 #define PKIND_RX BIT_ULL(1)
352 uint8_t __otx2_io dir;
353 uint8_t __otx2_io pkind; /* valid only in case custom flag */
356 /* Structure for requesting resource provisioning.
357 * 'modify' flag to be used when either requesting more
358 * or to detach partial of a certain resource type.
359 * Rest of the fields specify how many of what type to
361 * To request LFs from two blocks of same type this mailbox
362 * can be sent twice as below:
363 * struct rsrc_attach *attach;
364 * .. Allocate memory for message ..
365 * attach->cptlfs = 3; <3 LFs from CPT0>
367 * .. Allocate memory for message ..
368 * attach->modify = 1;
369 * attach->cpt_blkaddr = BLKADDR_CPT1;
370 * attach->cptlfs = 2; <2 LFs from CPT1>
373 struct rsrc_attach_req {
374 struct mbox_msghdr hdr;
375 uint8_t __otx2_io modify:1;
376 uint8_t __otx2_io npalf:1;
377 uint8_t __otx2_io nixlf:1;
378 uint16_t __otx2_io sso;
379 uint16_t __otx2_io ssow;
380 uint16_t __otx2_io timlfs;
381 uint16_t __otx2_io cptlfs;
382 uint16_t __otx2_io reelfs;
383 /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
384 int __otx2_io cpt_blkaddr;
385 /* BLKADDR_REE0/BLKADDR_REE1 or 0 for BLKADDR_REE0 */
386 int __otx2_io ree_blkaddr;
389 /* Structure for relinquishing resources.
390 * 'partial' flag to be used when relinquishing all resources
391 * but only of a certain type. If not set, all resources of all
392 * types provisioned to the RVU function will be detached.
394 struct rsrc_detach_req {
395 struct mbox_msghdr hdr;
396 uint8_t __otx2_io partial:1;
397 uint8_t __otx2_io npalf:1;
398 uint8_t __otx2_io nixlf:1;
399 uint8_t __otx2_io sso:1;
400 uint8_t __otx2_io ssow:1;
401 uint8_t __otx2_io timlfs:1;
402 uint8_t __otx2_io cptlfs:1;
403 uint8_t __otx2_io reelfs:1;
406 /* NIX Transmit schedulers */
407 #define NIX_TXSCH_LVL_SMQ 0x0
408 #define NIX_TXSCH_LVL_MDQ 0x0
409 #define NIX_TXSCH_LVL_TL4 0x1
410 #define NIX_TXSCH_LVL_TL3 0x2
411 #define NIX_TXSCH_LVL_TL2 0x3
412 #define NIX_TXSCH_LVL_TL1 0x4
413 #define NIX_TXSCH_LVL_CNT 0x5
416 * Number of resources available to the caller.
417 * In reply to MBOX_MSG_FREE_RSRC_CNT.
419 struct free_rsrcs_rsp {
420 struct mbox_msghdr hdr;
421 uint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT];
422 uint16_t __otx2_io sso;
423 uint16_t __otx2_io tim;
424 uint16_t __otx2_io ssow;
425 uint16_t __otx2_io cpt;
426 uint8_t __otx2_io npa;
427 uint8_t __otx2_io nix;
428 uint16_t __otx2_io schq_nix1[NIX_TXSCH_LVL_CNT];
429 uint8_t __otx2_io nix1;
430 uint8_t __otx2_io cpt1;
431 uint8_t __otx2_io ree0;
432 uint8_t __otx2_io ree1;
435 #define MSIX_VECTOR_INVALID 0xFFFF
436 #define MAX_RVU_BLKLF_CNT 256
438 struct msix_offset_rsp {
439 struct mbox_msghdr hdr;
440 uint16_t __otx2_io npa_msixoff;
441 uint16_t __otx2_io nix_msixoff;
442 uint8_t __otx2_io sso;
443 uint8_t __otx2_io ssow;
444 uint8_t __otx2_io timlfs;
445 uint8_t __otx2_io cptlfs;
446 uint16_t __otx2_io sso_msixoff[MAX_RVU_BLKLF_CNT];
447 uint16_t __otx2_io ssow_msixoff[MAX_RVU_BLKLF_CNT];
448 uint16_t __otx2_io timlf_msixoff[MAX_RVU_BLKLF_CNT];
449 uint16_t __otx2_io cptlf_msixoff[MAX_RVU_BLKLF_CNT];
450 uint8_t __otx2_io cpt1_lfs;
451 uint8_t __otx2_io ree0_lfs;
452 uint8_t __otx2_io ree1_lfs;
453 uint16_t __otx2_io cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
454 uint16_t __otx2_io ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
455 uint16_t __otx2_io ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
459 /* CGX mbox message formats */
461 struct cgx_stats_rsp {
462 struct mbox_msghdr hdr;
463 #define CGX_RX_STATS_COUNT 13
464 #define CGX_TX_STATS_COUNT 18
465 uint64_t __otx2_io rx_stats[CGX_RX_STATS_COUNT];
466 uint64_t __otx2_io tx_stats[CGX_TX_STATS_COUNT];
469 struct cgx_fec_stats_rsp {
470 struct mbox_msghdr hdr;
471 uint64_t __otx2_io fec_corr_blks;
472 uint64_t __otx2_io fec_uncorr_blks;
474 /* Structure for requesting the operation for
475 * setting/getting mac address in the CGX interface
477 struct cgx_mac_addr_set_or_get {
478 struct mbox_msghdr hdr;
479 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
482 /* Structure for requesting the operation to
483 * add DMAC filter entry into CGX interface
485 struct cgx_mac_addr_add_req {
486 struct mbox_msghdr hdr;
487 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
490 /* Structure for response against the operation to
491 * add DMAC filter entry into CGX interface
493 struct cgx_mac_addr_add_rsp {
494 struct mbox_msghdr hdr;
495 uint8_t __otx2_io index;
498 /* Structure for requesting the operation to
499 * delete DMAC filter entry from CGX interface
501 struct cgx_mac_addr_del_req {
502 struct mbox_msghdr hdr;
503 uint8_t __otx2_io index;
506 /* Structure for response against the operation to
507 * get maximum supported DMAC filter entries
509 struct cgx_max_dmac_entries_get_rsp {
510 struct mbox_msghdr hdr;
511 uint8_t __otx2_io max_dmac_filters;
514 struct cgx_link_user_info {
515 uint64_t __otx2_io link_up:1;
516 uint64_t __otx2_io full_duplex:1;
517 uint64_t __otx2_io lmac_type_id:4;
518 uint64_t __otx2_io speed:20; /* speed in Mbps */
519 uint64_t __otx2_io an:1; /* AN supported or not */
520 uint64_t __otx2_io fec:2; /* FEC type if enabled else 0 */
521 uint64_t __otx2_io port:8;
522 #define LMACTYPE_STR_LEN 16
523 char lmac_type[LMACTYPE_STR_LEN];
526 struct cgx_link_info_msg {
527 struct mbox_msghdr hdr;
528 struct cgx_link_user_info link_info;
531 struct cgx_ptp_rx_info_msg {
532 struct mbox_msghdr hdr;
533 uint8_t __otx2_io ptp_en;
536 struct cgx_pause_frm_cfg {
537 struct mbox_msghdr hdr;
538 uint8_t __otx2_io set;
539 /* set = 1 if the request is to config pause frames */
540 /* set = 0 if the request is to fetch pause frames config */
541 uint8_t __otx2_io rx_pause;
542 uint8_t __otx2_io tx_pause;
545 struct sfp_eeprom_s {
546 #define SFP_EEPROM_SIZE 256
547 uint16_t __otx2_io sff_id;
548 uint8_t __otx2_io buf[SFP_EEPROM_SIZE];
549 uint64_t __otx2_io reserved;
559 uint64_t __otx2_io can_change_mod_type : 1;
560 uint64_t __otx2_io mod_type : 1;
563 struct cgx_lmac_fwdata_s {
564 uint16_t __otx2_io rw_valid;
565 uint64_t __otx2_io supported_fec;
566 uint64_t __otx2_io supported_an;
567 uint64_t __otx2_io supported_link_modes;
568 /* Only applicable if AN is supported */
569 uint64_t __otx2_io advertised_fec;
570 uint64_t __otx2_io advertised_link_modes;
571 /* Only applicable if SFP/QSFP slot is present */
572 struct sfp_eeprom_s sfp_eeprom;
574 #define LMAC_FWDATA_RESERVED_MEM 1023
575 uint64_t __otx2_io reserved[LMAC_FWDATA_RESERVED_MEM];
579 struct mbox_msghdr hdr;
580 struct cgx_lmac_fwdata_s fwdata;
584 struct mbox_msghdr hdr;
588 struct cgx_set_link_state_msg {
589 struct mbox_msghdr hdr;
590 uint8_t __otx2_io enable;
593 struct cgx_phy_mod_type {
594 struct mbox_msghdr hdr;
598 struct cgx_set_link_mode_args {
599 uint32_t __otx2_io speed;
600 uint8_t __otx2_io duplex;
601 uint8_t __otx2_io an;
602 uint8_t __otx2_io ports;
603 uint64_t __otx2_io mode;
606 struct cgx_set_link_mode_req {
607 struct mbox_msghdr hdr;
608 struct cgx_set_link_mode_args args;
611 struct cgx_set_link_mode_rsp {
612 struct mbox_msghdr hdr;
613 int __otx2_io status;
615 /* NPA mbox message formats */
617 /* NPA mailbox error codes
621 NPA_AF_ERR_PARAM = -301,
622 NPA_AF_ERR_AQ_FULL = -302,
623 NPA_AF_ERR_AQ_ENQUEUE = -303,
624 NPA_AF_ERR_AF_LF_INVALID = -304,
625 NPA_AF_ERR_AF_LF_ALLOC = -305,
626 NPA_AF_ERR_LF_RESET = -306,
629 #define NPA_AURA_SZ_0 0
630 #define NPA_AURA_SZ_128 1
631 #define NPA_AURA_SZ_256 2
632 #define NPA_AURA_SZ_512 3
633 #define NPA_AURA_SZ_1K 4
634 #define NPA_AURA_SZ_2K 5
635 #define NPA_AURA_SZ_4K 6
636 #define NPA_AURA_SZ_8K 7
637 #define NPA_AURA_SZ_16K 8
638 #define NPA_AURA_SZ_32K 9
639 #define NPA_AURA_SZ_64K 10
640 #define NPA_AURA_SZ_128K 11
641 #define NPA_AURA_SZ_256K 12
642 #define NPA_AURA_SZ_512K 13
643 #define NPA_AURA_SZ_1M 14
644 #define NPA_AURA_SZ_MAX 15
646 /* For NPA LF context alloc and init */
647 struct npa_lf_alloc_req {
648 struct mbox_msghdr hdr;
650 int __otx2_io aura_sz; /* No of auras. See NPA_AURA_SZ_* */
651 uint32_t __otx2_io nr_pools; /* No of pools */
652 uint64_t __otx2_io way_mask;
655 struct npa_lf_alloc_rsp {
656 struct mbox_msghdr hdr;
657 uint32_t __otx2_io stack_pg_ptrs; /* No of ptrs per stack page */
658 uint32_t __otx2_io stack_pg_bytes; /* Size of stack page */
659 uint16_t __otx2_io qints; /* NPA_AF_CONST::QINTS */
662 /* NPA AQ enqueue msg */
663 struct npa_aq_enq_req {
664 struct mbox_msghdr hdr;
665 uint32_t __otx2_io aura_id;
666 uint8_t __otx2_io ctype;
667 uint8_t __otx2_io op;
669 /* Valid when op == WRITE/INIT and ctype == AURA.
670 * LF fills the pool_id in aura.pool_addr. AF will translate
671 * the pool_id to pool context pointer.
673 __otx2_io struct npa_aura_s aura;
674 /* Valid when op == WRITE/INIT and ctype == POOL */
675 __otx2_io struct npa_pool_s pool;
677 /* Mask data when op == WRITE (1=write, 0=don't write) */
679 /* Valid when op == WRITE and ctype == AURA */
680 __otx2_io struct npa_aura_s aura_mask;
681 /* Valid when op == WRITE and ctype == POOL */
682 __otx2_io struct npa_pool_s pool_mask;
686 struct npa_aq_enq_rsp {
687 struct mbox_msghdr hdr;
689 /* Valid when op == READ and ctype == AURA */
690 __otx2_io struct npa_aura_s aura;
691 /* Valid when op == READ and ctype == POOL */
692 __otx2_io struct npa_pool_s pool;
696 /* Disable all contexts of type 'ctype' */
697 struct hwctx_disable_req {
698 struct mbox_msghdr hdr;
699 uint8_t __otx2_io ctype;
702 /* NIX mbox message formats */
704 /* NIX mailbox error codes
708 NIX_AF_ERR_PARAM = -401,
709 NIX_AF_ERR_AQ_FULL = -402,
710 NIX_AF_ERR_AQ_ENQUEUE = -403,
711 NIX_AF_ERR_AF_LF_INVALID = -404,
712 NIX_AF_ERR_AF_LF_ALLOC = -405,
713 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
714 NIX_AF_ERR_TLX_INVALID = -407,
715 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
716 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
717 NIX_AF_ERR_FRS_INVALID = -410,
718 NIX_AF_ERR_RX_LINK_INVALID = -411,
719 NIX_AF_INVAL_TXSCHQ_CFG = -412,
720 NIX_AF_SMQ_FLUSH_FAILED = -413,
721 NIX_AF_ERR_LF_RESET = -414,
722 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
723 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
724 NIX_AF_ERR_MARK_CFG_FAIL = -417,
725 NIX_AF_ERR_LSO_CFG_FAIL = -418,
726 NIX_AF_INVAL_NPA_PF_FUNC = -419,
727 NIX_AF_INVAL_SSO_PF_FUNC = -420,
728 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
729 NIX_AF_ERR_RX_VTAG_INUSE = -422,
730 NIX_AF_ERR_PTP_CONFIG_FAIL = -423,
733 /* For NIX LF context alloc and init */
734 struct nix_lf_alloc_req {
735 struct mbox_msghdr hdr;
737 uint32_t __otx2_io rq_cnt; /* No of receive queues */
738 uint32_t __otx2_io sq_cnt; /* No of send queues */
739 uint32_t __otx2_io cq_cnt; /* No of completion queues */
740 uint8_t __otx2_io xqe_sz;
741 uint16_t __otx2_io rss_sz;
742 uint8_t __otx2_io rss_grps;
743 uint16_t __otx2_io npa_func;
744 /* RVU_DEFAULT_PF_FUNC == default pf_func associated with lf */
745 uint16_t __otx2_io sso_func;
746 uint64_t __otx2_io rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
747 uint64_t __otx2_io way_mask;
748 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
752 struct nix_lf_alloc_rsp {
753 struct mbox_msghdr hdr;
754 uint16_t __otx2_io sqb_size;
755 uint16_t __otx2_io rx_chan_base;
756 uint16_t __otx2_io tx_chan_base;
757 uint8_t __otx2_io rx_chan_cnt; /* Total number of RX channels */
758 uint8_t __otx2_io tx_chan_cnt; /* Total number of TX channels */
759 uint8_t __otx2_io lso_tsov4_idx;
760 uint8_t __otx2_io lso_tsov6_idx;
761 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
762 uint8_t __otx2_io lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
763 uint8_t __otx2_io lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
764 uint16_t __otx2_io cints; /* NIX_AF_CONST2::CINTS */
765 uint16_t __otx2_io qints; /* NIX_AF_CONST2::QINTS */
766 uint8_t __otx2_io hw_rx_tstamp_en; /*set if rx timestamping enabled */
767 uint8_t __otx2_io cgx_links; /* No. of CGX links present in HW */
768 uint8_t __otx2_io lbk_links; /* No. of LBK links present in HW */
769 uint8_t __otx2_io sdp_links; /* No. of SDP links present in HW */
772 struct nix_lf_free_req {
773 struct mbox_msghdr hdr;
774 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
775 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
776 uint64_t __otx2_io flags;
779 /* NIX AQ enqueue msg */
780 struct nix_aq_enq_req {
781 struct mbox_msghdr hdr;
782 uint32_t __otx2_io qidx;
783 uint8_t __otx2_io ctype;
784 uint8_t __otx2_io op;
786 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */
787 __otx2_io struct nix_rq_ctx_s rq;
788 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */
789 __otx2_io struct nix_sq_ctx_s sq;
790 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */
791 __otx2_io struct nix_cq_ctx_s cq;
792 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */
793 __otx2_io struct nix_rsse_s rss;
794 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */
795 __otx2_io struct nix_rx_mce_s mce;
797 /* Mask data when op == WRITE (1=write, 0=don't write) */
799 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */
800 __otx2_io struct nix_rq_ctx_s rq_mask;
801 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */
802 __otx2_io struct nix_sq_ctx_s sq_mask;
803 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */
804 __otx2_io struct nix_cq_ctx_s cq_mask;
805 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */
806 __otx2_io struct nix_rsse_s rss_mask;
807 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */
808 __otx2_io struct nix_rx_mce_s mce_mask;
812 struct nix_aq_enq_rsp {
813 struct mbox_msghdr hdr;
815 __otx2_io struct nix_rq_ctx_s rq;
816 __otx2_io struct nix_sq_ctx_s sq;
817 __otx2_io struct nix_cq_ctx_s cq;
818 __otx2_io struct nix_rsse_s rss;
819 __otx2_io struct nix_rx_mce_s mce;
823 /* Tx scheduler/shaper mailbox messages */
825 #define MAX_TXSCHQ_PER_FUNC 128
827 struct nix_txsch_alloc_req {
828 struct mbox_msghdr hdr;
829 /* Scheduler queue count request at each level */
830 uint16_t __otx2_io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
831 uint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
834 struct nix_txsch_alloc_rsp {
835 struct mbox_msghdr hdr;
836 /* Scheduler queue count allocated at each level */
837 uint16_t __otx2_io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
838 uint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
839 /* Scheduler queue list allocated at each level */
841 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
842 uint16_t __otx2_io schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
843 /* Traffic aggregation scheduler level */
844 uint8_t __otx2_io aggr_level;
845 /* Aggregation lvl's RR_PRIO config */
846 uint8_t __otx2_io aggr_lvl_rr_prio;
847 /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
848 uint8_t __otx2_io link_cfg_lvl;
851 struct nix_txsch_free_req {
852 struct mbox_msghdr hdr;
853 #define TXSCHQ_FREE_ALL BIT_ULL(0)
854 uint16_t __otx2_io flags;
855 /* Scheduler queue level to be freed */
856 uint16_t __otx2_io schq_lvl;
857 /* List of scheduler queues to be freed */
858 uint16_t __otx2_io schq;
861 struct nix_txschq_config {
862 struct mbox_msghdr hdr;
863 uint8_t __otx2_io lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
864 uint8_t __otx2_io read;
865 #define TXSCHQ_IDX_SHIFT 16
866 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
867 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
868 uint8_t __otx2_io num_regs;
869 #define MAX_REGS_PER_MBOX_MSG 20
870 uint64_t __otx2_io reg[MAX_REGS_PER_MBOX_MSG];
871 uint64_t __otx2_io regval[MAX_REGS_PER_MBOX_MSG];
872 /* All 0's => overwrite with new value */
873 uint64_t __otx2_io regval_mask[MAX_REGS_PER_MBOX_MSG];
876 struct nix_vtag_config {
877 struct mbox_msghdr hdr;
878 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
879 uint8_t __otx2_io vtag_size;
880 /* cfg_type is '0' for tx vlan cfg
881 * cfg_type is '1' for rx vlan cfg
883 uint8_t __otx2_io cfg_type;
885 /* Valid when cfg_type is '0' */
887 uint64_t __otx2_io vtag0;
888 uint64_t __otx2_io vtag1;
890 /* cfg_vtag0 & cfg_vtag1 fields are valid
891 * when free_vtag0 & free_vtag1 are '0's.
893 /* cfg_vtag0 = 1 to configure vtag0 */
894 uint8_t __otx2_io cfg_vtag0 :1;
895 /* cfg_vtag1 = 1 to configure vtag1 */
896 uint8_t __otx2_io cfg_vtag1 :1;
898 /* vtag0_idx & vtag1_idx are only valid when
899 * both cfg_vtag0 & cfg_vtag1 are '0's,
900 * these fields are used along with free_vtag0
901 * & free_vtag1 to free the nix lf's tx_vlan
904 * Denotes the indices of tx_vtag def registers
905 * that needs to be cleared and freed.
907 int __otx2_io vtag0_idx;
908 int __otx2_io vtag1_idx;
910 /* Free_vtag0 & free_vtag1 fields are valid
911 * when cfg_vtag0 & cfg_vtag1 are '0's.
913 /* Free_vtag0 = 1 clears vtag0 configuration
914 * vtag0_idx denotes the index to be cleared.
916 uint8_t __otx2_io free_vtag0 :1;
917 /* Free_vtag1 = 1 clears vtag1 configuration
918 * vtag1_idx denotes the index to be cleared.
920 uint8_t __otx2_io free_vtag1 :1;
923 /* Valid when cfg_type is '1' */
925 /* Rx vtag type index, valid values are in 0..7 range */
926 uint8_t __otx2_io vtag_type;
928 uint8_t __otx2_io strip_vtag :1;
929 /* Rx vtag capture */
930 uint8_t __otx2_io capture_vtag :1;
935 struct nix_vtag_config_rsp {
936 struct mbox_msghdr hdr;
937 /* Indices of tx_vtag def registers used to configure
938 * tx vtag0 & vtag1 headers, these indices are valid
939 * when nix_vtag_config mbox requested for vtag0 and/
940 * or vtag1 configuration.
942 int __otx2_io vtag0_idx;
943 int __otx2_io vtag1_idx;
946 struct nix_rss_flowkey_cfg {
947 struct mbox_msghdr hdr;
948 int __otx2_io mcam_index; /* MCAM entry index to modify */
949 uint32_t __otx2_io flowkey_cfg; /* Flowkey types selected */
950 #define FLOW_KEY_TYPE_PORT BIT(0)
951 #define FLOW_KEY_TYPE_IPV4 BIT(1)
952 #define FLOW_KEY_TYPE_IPV6 BIT(2)
953 #define FLOW_KEY_TYPE_TCP BIT(3)
954 #define FLOW_KEY_TYPE_UDP BIT(4)
955 #define FLOW_KEY_TYPE_SCTP BIT(5)
956 #define FLOW_KEY_TYPE_NVGRE BIT(6)
957 #define FLOW_KEY_TYPE_VXLAN BIT(7)
958 #define FLOW_KEY_TYPE_GENEVE BIT(8)
959 #define FLOW_KEY_TYPE_ETH_DMAC BIT(9)
960 #define FLOW_KEY_TYPE_IPV6_EXT BIT(10)
961 #define FLOW_KEY_TYPE_GTPU BIT(11)
962 #define FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
963 #define FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
964 #define FLOW_KEY_TYPE_INNR_TCP BIT(14)
965 #define FLOW_KEY_TYPE_INNR_UDP BIT(15)
966 #define FLOW_KEY_TYPE_INNR_SCTP BIT(16)
967 #define FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
968 #define FLOW_KEY_TYPE_CH_LEN_90B BIT(18)
969 #define FLOW_KEY_TYPE_L4_DST BIT(28)
970 #define FLOW_KEY_TYPE_L4_SRC BIT(29)
971 #define FLOW_KEY_TYPE_L3_DST BIT(30)
972 #define FLOW_KEY_TYPE_L3_SRC BIT(31)
973 uint8_t __otx2_io group; /* RSS context or group */
976 struct nix_rss_flowkey_cfg_rsp {
977 struct mbox_msghdr hdr;
978 uint8_t __otx2_io alg_idx; /* Selected algo index */
981 struct nix_set_mac_addr {
982 struct mbox_msghdr hdr;
983 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
986 struct nix_get_mac_addr_rsp {
987 struct mbox_msghdr hdr;
988 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
991 struct nix_mark_format_cfg {
992 struct mbox_msghdr hdr;
993 uint8_t __otx2_io offset;
994 uint8_t __otx2_io y_mask;
995 uint8_t __otx2_io y_val;
996 uint8_t __otx2_io r_mask;
997 uint8_t __otx2_io r_val;
1000 struct nix_mark_format_cfg_rsp {
1001 struct mbox_msghdr hdr;
1002 uint8_t __otx2_io mark_format_idx;
1005 struct nix_lso_format_cfg {
1006 struct mbox_msghdr hdr;
1007 uint64_t __otx2_io field_mask;
1008 uint64_t __otx2_io fields[NIX_LSO_FIELD_MAX];
1011 struct nix_lso_format_cfg_rsp {
1012 struct mbox_msghdr hdr;
1013 uint8_t __otx2_io lso_format_idx;
1016 struct nix_rx_mode {
1017 struct mbox_msghdr hdr;
1018 #define NIX_RX_MODE_UCAST BIT(0)
1019 #define NIX_RX_MODE_PROMISC BIT(1)
1020 #define NIX_RX_MODE_ALLMULTI BIT(2)
1021 uint16_t __otx2_io mode;
1025 struct mbox_msghdr hdr;
1026 #define NIX_RX_OL3_VERIFY BIT(0)
1027 #define NIX_RX_OL4_VERIFY BIT(1)
1028 uint8_t __otx2_io len_verify; /* Outer L3/L4 len check */
1029 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
1030 uint8_t __otx2_io csum_verify; /* Outer L4 checksum verification */
1033 struct nix_frs_cfg {
1034 struct mbox_msghdr hdr;
1035 uint8_t __otx2_io update_smq; /* Update SMQ's min/max lens */
1036 uint8_t __otx2_io update_minlen; /* Set minlen also */
1037 uint8_t __otx2_io sdp_link; /* Set SDP RX link */
1038 uint16_t __otx2_io maxlen;
1039 uint16_t __otx2_io minlen;
1042 struct nix_set_vlan_tpid {
1043 struct mbox_msghdr hdr;
1044 #define NIX_VLAN_TYPE_INNER 0
1045 #define NIX_VLAN_TYPE_OUTER 1
1046 uint8_t __otx2_io vlan_type;
1047 uint16_t __otx2_io tpid;
1050 struct nix_bp_cfg_req {
1051 struct mbox_msghdr hdr;
1052 uint16_t __otx2_io chan_base; /* Starting channel number */
1053 uint8_t __otx2_io chan_cnt; /* Number of channels */
1054 uint8_t __otx2_io bpid_per_chan;
1055 /* bpid_per_chan = 0 assigns single bp id for range of channels */
1056 /* bpid_per_chan = 1 assigns separate bp id for each channel */
1059 /* PF can be mapped to either CGX or LBK interface,
1060 * so maximum 64 channels are possible.
1062 #define NIX_MAX_CHAN 64
1063 struct nix_bp_cfg_rsp {
1064 struct mbox_msghdr hdr;
1065 /* Channel and bpid mapping */
1066 uint16_t __otx2_io chan_bpid[NIX_MAX_CHAN];
1067 /* Number of channel for which bpids are assigned */
1068 uint8_t __otx2_io chan_cnt;
1071 /* Global NIX inline IPSec configuration */
1072 struct nix_inline_ipsec_cfg {
1073 struct mbox_msghdr hdr;
1074 uint32_t __otx2_io cpt_credit;
1076 uint8_t __otx2_io egrp;
1077 uint8_t __otx2_io opcode;
1080 uint16_t __otx2_io cpt_pf_func;
1081 uint8_t __otx2_io cpt_slot;
1083 uint8_t __otx2_io enable;
1086 /* Per NIX LF inline IPSec configuration */
1087 struct nix_inline_ipsec_lf_cfg {
1088 struct mbox_msghdr hdr;
1089 uint64_t __otx2_io sa_base_addr;
1091 uint32_t __otx2_io tag_const;
1092 uint16_t __otx2_io lenm1_max;
1093 uint8_t __otx2_io sa_pow2_size;
1094 uint8_t __otx2_io tt;
1097 uint32_t __otx2_io sa_idx_max;
1098 uint8_t __otx2_io sa_idx_w;
1100 uint8_t __otx2_io enable;
1103 /* SSO mailbox error codes
1106 enum sso_af_status {
1107 SSO_AF_ERR_PARAM = -501,
1108 SSO_AF_ERR_LF_INVALID = -502,
1109 SSO_AF_ERR_AF_LF_ALLOC = -503,
1110 SSO_AF_ERR_GRP_EBUSY = -504,
1111 SSO_AF_INVAL_NPA_PF_FUNC = -505,
1114 struct sso_lf_alloc_req {
1115 struct mbox_msghdr hdr;
1117 uint16_t __otx2_io hwgrps;
1120 struct sso_lf_alloc_rsp {
1121 struct mbox_msghdr hdr;
1122 uint32_t __otx2_io xaq_buf_size;
1123 uint32_t __otx2_io xaq_wq_entries;
1124 uint32_t __otx2_io in_unit_entries;
1125 uint16_t __otx2_io hwgrps;
1128 struct sso_lf_free_req {
1129 struct mbox_msghdr hdr;
1131 uint16_t __otx2_io hwgrps;
1134 /* SSOW mailbox error codes
1137 enum ssow_af_status {
1138 SSOW_AF_ERR_PARAM = -601,
1139 SSOW_AF_ERR_LF_INVALID = -602,
1140 SSOW_AF_ERR_AF_LF_ALLOC = -603,
1143 struct ssow_lf_alloc_req {
1144 struct mbox_msghdr hdr;
1146 uint16_t __otx2_io hws;
1149 struct ssow_lf_free_req {
1150 struct mbox_msghdr hdr;
1152 uint16_t __otx2_io hws;
1155 struct sso_hw_setconfig {
1156 struct mbox_msghdr hdr;
1157 uint32_t __otx2_io npa_aura_id;
1158 uint16_t __otx2_io npa_pf_func;
1159 uint16_t __otx2_io hwgrps;
1162 struct sso_info_req {
1163 struct mbox_msghdr hdr;
1165 uint16_t __otx2_io grp;
1166 uint16_t __otx2_io hws;
1170 struct sso_grp_priority {
1171 struct mbox_msghdr hdr;
1172 uint16_t __otx2_io grp;
1173 uint8_t __otx2_io priority;
1174 uint8_t __otx2_io affinity;
1175 uint8_t __otx2_io weight;
1178 struct sso_grp_qos_cfg {
1179 struct mbox_msghdr hdr;
1180 uint16_t __otx2_io grp;
1181 uint32_t __otx2_io xaq_limit;
1182 uint16_t __otx2_io taq_thr;
1183 uint16_t __otx2_io iaq_thr;
1186 struct sso_grp_stats {
1187 struct mbox_msghdr hdr;
1188 uint16_t __otx2_io grp;
1189 uint64_t __otx2_io ws_pc;
1190 uint64_t __otx2_io ext_pc;
1191 uint64_t __otx2_io wa_pc;
1192 uint64_t __otx2_io ts_pc;
1193 uint64_t __otx2_io ds_pc;
1194 uint64_t __otx2_io dq_pc;
1195 uint64_t __otx2_io aw_status;
1196 uint64_t __otx2_io page_cnt;
1199 struct sso_hws_stats {
1200 struct mbox_msghdr hdr;
1201 uint16_t __otx2_io hws;
1202 uint64_t __otx2_io arbitration;
1205 /* CPT mailbox error codes
1208 enum cpt_af_status {
1209 CPT_AF_ERR_PARAM = -901,
1210 CPT_AF_ERR_GRP_INVALID = -902,
1211 CPT_AF_ERR_LF_INVALID = -903,
1212 CPT_AF_ERR_ACCESS_DENIED = -904,
1213 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
1214 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906,
1215 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907,
1216 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908
1219 /* CPT mbox message formats */
1221 struct cpt_rd_wr_reg_msg {
1222 struct mbox_msghdr hdr;
1223 uint64_t __otx2_io reg_offset;
1224 uint64_t __otx2_io *ret_val;
1225 uint64_t __otx2_io val;
1226 uint8_t __otx2_io is_write;
1229 struct cpt_set_crypto_grp_req_msg {
1230 struct mbox_msghdr hdr;
1231 uint8_t __otx2_io crypto_eng_grp;
1234 struct cpt_lf_alloc_req_msg {
1235 struct mbox_msghdr hdr;
1236 uint16_t __otx2_io nix_pf_func;
1237 uint16_t __otx2_io sso_pf_func;
1240 struct cpt_lf_alloc_rsp_msg {
1241 struct mbox_msghdr hdr;
1242 uint8_t __otx2_io crypto_eng_grp;
1245 #define CPT_INLINE_INBOUND 0
1246 #define CPT_INLINE_OUTBOUND 1
1248 struct cpt_inline_ipsec_cfg_msg {
1249 struct mbox_msghdr hdr;
1250 uint8_t __otx2_io enable;
1251 uint8_t __otx2_io slot;
1252 uint8_t __otx2_io dir;
1253 uint16_t __otx2_io sso_pf_func; /* Inbound path SSO_PF_FUNC */
1254 uint16_t __otx2_io nix_pf_func; /* Outbound path NIX_PF_FUNC */
1257 struct cpt_rx_inline_lf_cfg_msg {
1258 struct mbox_msghdr hdr;
1259 uint16_t __otx2_io sso_pf_func;
1263 CPT_ENG_TYPE_AE = 1,
1264 CPT_ENG_TYPE_SE = 2,
1265 CPT_ENG_TYPE_IE = 3,
1269 /* CPT HW capabilities */
1270 union cpt_eng_caps {
1271 uint64_t __otx2_io u;
1273 uint64_t __otx2_io reserved_0_4:5;
1274 uint64_t __otx2_io mul:1;
1275 uint64_t __otx2_io sha1_sha2:1;
1276 uint64_t __otx2_io chacha20:1;
1277 uint64_t __otx2_io zuc_snow3g:1;
1278 uint64_t __otx2_io sha3:1;
1279 uint64_t __otx2_io aes:1;
1280 uint64_t __otx2_io kasumi:1;
1281 uint64_t __otx2_io des:1;
1282 uint64_t __otx2_io crc:1;
1283 uint64_t __otx2_io reserved_14_63:50;
1287 struct cpt_caps_rsp_msg {
1288 struct mbox_msghdr hdr;
1289 uint16_t __otx2_io cpt_pf_drv_version;
1290 uint8_t __otx2_io cpt_revision;
1291 union cpt_eng_caps eng_caps[CPT_MAX_ENG_TYPES];
1294 /* NPC mbox message structs */
1296 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
1297 #define NPC_MCAM_INVALID_MAP 0xFFFF
1299 /* NPC mailbox error codes
1302 enum npc_af_status {
1303 NPC_MCAM_INVALID_REQ = -701,
1304 NPC_MCAM_ALLOC_DENIED = -702,
1305 NPC_MCAM_ALLOC_FAILED = -703,
1306 NPC_MCAM_PERM_DENIED = -704,
1307 NPC_AF_ERR_HIGIG_CONFIG_FAIL = -705,
1310 struct npc_mcam_alloc_entry_req {
1311 struct mbox_msghdr hdr;
1312 #define NPC_MAX_NONCONTIG_ENTRIES 256
1313 uint8_t __otx2_io contig; /* Contiguous entries ? */
1314 #define NPC_MCAM_ANY_PRIO 0
1315 #define NPC_MCAM_LOWER_PRIO 1
1316 #define NPC_MCAM_HIGHER_PRIO 2
1317 uint8_t __otx2_io priority; /* Lower or higher w.r.t ref_entry */
1318 uint16_t __otx2_io ref_entry;
1319 uint16_t __otx2_io count; /* Number of entries requested */
1322 struct npc_mcam_alloc_entry_rsp {
1323 struct mbox_msghdr hdr;
1324 /* Entry alloc'ed or start index if contiguous.
1325 * Invalid in case of non-contiguous.
1327 uint16_t __otx2_io entry;
1328 uint16_t __otx2_io count; /* Number of entries allocated */
1329 uint16_t __otx2_io free_count; /* Number of entries available */
1330 uint16_t __otx2_io entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1333 struct npc_mcam_free_entry_req {
1334 struct mbox_msghdr hdr;
1335 uint16_t __otx2_io entry; /* Entry index to be freed */
1336 uint8_t __otx2_io all; /* Free all entries alloc'ed to this PFVF */
1340 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max key width */
1341 uint64_t __otx2_io kw[NPC_MAX_KWS_IN_KEY];
1342 uint64_t __otx2_io kw_mask[NPC_MAX_KWS_IN_KEY];
1343 uint64_t __otx2_io action;
1344 uint64_t __otx2_io vtag_action;
1347 struct npc_mcam_write_entry_req {
1348 struct mbox_msghdr hdr;
1349 struct mcam_entry entry_data;
1350 uint16_t __otx2_io entry; /* MCAM entry to write this match key */
1351 uint16_t __otx2_io cntr; /* Counter for this MCAM entry */
1352 uint8_t __otx2_io intf; /* Rx or Tx interface */
1353 uint8_t __otx2_io enable_entry;/* Enable this MCAM entry ? */
1354 uint8_t __otx2_io set_cntr; /* Set counter for this entry ? */
1357 /* Enable/Disable a given entry */
1358 struct npc_mcam_ena_dis_entry_req {
1359 struct mbox_msghdr hdr;
1360 uint16_t __otx2_io entry;
1363 struct npc_mcam_shift_entry_req {
1364 struct mbox_msghdr hdr;
1365 #define NPC_MCAM_MAX_SHIFTS 64
1366 uint16_t __otx2_io curr_entry[NPC_MCAM_MAX_SHIFTS];
1367 uint16_t __otx2_io new_entry[NPC_MCAM_MAX_SHIFTS];
1368 uint16_t __otx2_io shift_count; /* Number of entries to shift */
1371 struct npc_mcam_shift_entry_rsp {
1372 struct mbox_msghdr hdr;
1373 /* Index in 'curr_entry', not entry itself */
1374 uint16_t __otx2_io failed_entry_idx;
1377 struct npc_mcam_alloc_counter_req {
1378 struct mbox_msghdr hdr;
1379 uint8_t __otx2_io contig; /* Contiguous counters ? */
1380 #define NPC_MAX_NONCONTIG_COUNTERS 64
1381 uint16_t __otx2_io count; /* Number of counters requested */
1384 struct npc_mcam_alloc_counter_rsp {
1385 struct mbox_msghdr hdr;
1386 /* Counter alloc'ed or start idx if contiguous.
1387 * Invalid incase of non-contiguous.
1389 uint16_t __otx2_io cntr;
1390 uint16_t __otx2_io count; /* Number of counters allocated */
1391 uint16_t __otx2_io cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1394 struct npc_mcam_oper_counter_req {
1395 struct mbox_msghdr hdr;
1396 uint16_t __otx2_io cntr; /* Free a counter or clear/fetch it's stats */
1399 struct npc_mcam_oper_counter_rsp {
1400 struct mbox_msghdr hdr;
1401 /* valid only while fetching counter's stats */
1402 uint64_t __otx2_io stat;
1405 struct npc_mcam_unmap_counter_req {
1406 struct mbox_msghdr hdr;
1407 uint16_t __otx2_io cntr;
1408 uint16_t __otx2_io entry; /* Entry and counter to be unmapped */
1409 uint8_t __otx2_io all; /* Unmap all entries using this counter ? */
1412 struct npc_mcam_alloc_and_write_entry_req {
1413 struct mbox_msghdr hdr;
1414 struct mcam_entry entry_data;
1415 uint16_t __otx2_io ref_entry;
1416 uint8_t __otx2_io priority; /* Lower or higher w.r.t ref_entry */
1417 uint8_t __otx2_io intf; /* Rx or Tx interface */
1418 uint8_t __otx2_io enable_entry;/* Enable this MCAM entry ? */
1419 uint8_t __otx2_io alloc_cntr; /* Allocate counter and map ? */
1422 struct npc_mcam_alloc_and_write_entry_rsp {
1423 struct mbox_msghdr hdr;
1424 uint16_t __otx2_io entry;
1425 uint16_t __otx2_io cntr;
1428 struct npc_get_kex_cfg_rsp {
1429 struct mbox_msghdr hdr;
1430 uint64_t __otx2_io rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1431 uint64_t __otx2_io tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1432 #define NPC_MAX_INTF 2
1433 #define NPC_MAX_LID 8
1434 #define NPC_MAX_LT 16
1435 #define NPC_MAX_LD 2
1436 #define NPC_MAX_LFL 16
1437 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1438 uint64_t __otx2_io kex_ld_flags[NPC_MAX_LD];
1439 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1441 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
1442 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1444 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1445 #define MKEX_NAME_LEN 128
1446 uint8_t __otx2_io mkex_pfl_name[MKEX_NAME_LEN];
1449 enum header_fields {
1464 NPC_HEADER_FIELDS_MAX,
1468 unsigned char __otx2_io dmac[6];
1469 unsigned char __otx2_io smac[6];
1470 uint16_t __otx2_io etype;
1471 uint16_t __otx2_io vlan_etype;
1472 uint16_t __otx2_io vlan_tci;
1474 uint32_t __otx2_io ip4src;
1475 uint32_t __otx2_io ip6src[4];
1478 uint32_t __otx2_io ip4dst;
1479 uint32_t __otx2_io ip6dst[4];
1481 uint8_t __otx2_io tos;
1482 uint8_t __otx2_io ip_ver;
1483 uint8_t __otx2_io ip_proto;
1484 uint8_t __otx2_io tc;
1485 uint16_t __otx2_io sport;
1486 uint16_t __otx2_io dport;
1489 struct npc_install_flow_req {
1490 struct mbox_msghdr hdr;
1491 struct flow_msg packet;
1492 struct flow_msg mask;
1493 uint64_t __otx2_io features;
1494 uint16_t __otx2_io entry;
1495 uint16_t __otx2_io channel;
1496 uint8_t __otx2_io intf;
1497 uint8_t __otx2_io set_cntr;
1498 uint8_t __otx2_io default_rule;
1499 /* Overwrite(0) or append(1) flow to default rule? */
1500 uint8_t __otx2_io append;
1501 uint16_t __otx2_io vf;
1503 uint32_t __otx2_io index;
1504 uint16_t __otx2_io match_id;
1505 uint8_t __otx2_io flow_key_alg;
1506 uint8_t __otx2_io op;
1508 uint8_t __otx2_io vtag0_type;
1509 uint8_t __otx2_io vtag0_valid;
1510 uint8_t __otx2_io vtag1_type;
1511 uint8_t __otx2_io vtag1_valid;
1513 /* vtag tx action */
1514 uint16_t __otx2_io vtag0_def;
1515 uint8_t __otx2_io vtag0_op;
1516 uint16_t __otx2_io vtag1_def;
1517 uint8_t __otx2_io vtag1_op;
1520 struct npc_install_flow_rsp {
1521 struct mbox_msghdr hdr;
1522 /* Negative if no counter else counter number */
1523 int __otx2_io counter;
1526 struct npc_delete_flow_req {
1527 struct mbox_msghdr hdr;
1528 uint16_t __otx2_io entry;
1529 uint16_t __otx2_io start;/*Disable range of entries */
1530 uint16_t __otx2_io end;
1531 uint8_t __otx2_io all; /* PF + VFs */
1534 struct npc_mcam_read_entry_req {
1535 struct mbox_msghdr hdr;
1536 /* MCAM entry to read */
1537 uint16_t __otx2_io entry;
1540 struct npc_mcam_read_entry_rsp {
1541 struct mbox_msghdr hdr;
1542 struct mcam_entry entry_data;
1543 uint8_t __otx2_io intf;
1544 uint8_t __otx2_io enable;
1547 /* TIM mailbox error codes
1550 enum tim_af_status {
1551 TIM_AF_NO_RINGS_LEFT = -801,
1552 TIM_AF_INVALID_NPA_PF_FUNC = -802,
1553 TIM_AF_INVALID_SSO_PF_FUNC = -803,
1554 TIM_AF_RING_STILL_RUNNING = -804,
1555 TIM_AF_LF_INVALID = -805,
1556 TIM_AF_CSIZE_NOT_ALIGNED = -806,
1557 TIM_AF_CSIZE_TOO_SMALL = -807,
1558 TIM_AF_CSIZE_TOO_BIG = -808,
1559 TIM_AF_INTERVAL_TOO_SMALL = -809,
1560 TIM_AF_INVALID_BIG_ENDIAN_VALUE = -810,
1561 TIM_AF_INVALID_CLOCK_SOURCE = -811,
1562 TIM_AF_GPIO_CLK_SRC_NOT_ENABLED = -812,
1563 TIM_AF_INVALID_BSIZE = -813,
1564 TIM_AF_INVALID_ENABLE_PERIODIC = -814,
1565 TIM_AF_INVALID_ENABLE_DONTFREE = -815,
1566 TIM_AF_ENA_DONTFRE_NSET_PERIODIC = -816,
1567 TIM_AF_RING_ALREADY_DISABLED = -817,
1571 TIM_CLK_SRCS_TENNS = 0,
1572 TIM_CLK_SRCS_GPIO = 1,
1573 TIM_CLK_SRCS_GTI = 2,
1574 TIM_CLK_SRCS_PTP = 3,
1575 TIM_CLK_SRSC_INVALID,
1578 enum tim_gpio_edge {
1579 TIM_GPIO_NO_EDGE = 0,
1580 TIM_GPIO_LTOH_TRANS = 1,
1581 TIM_GPIO_HTOL_TRANS = 2,
1582 TIM_GPIO_BOTH_TRANS = 3,
1587 PTP_OP_ADJFINE = 0, /* adjfine(req.scaled_ppm); */
1588 PTP_OP_GET_CLOCK = 1, /* rsp.clk = get_clock() */
1592 struct mbox_msghdr hdr;
1593 uint8_t __otx2_io op;
1594 int64_t __otx2_io scaled_ppm;
1595 uint8_t __otx2_io is_pmu;
1599 struct mbox_msghdr hdr;
1600 uint64_t __otx2_io clk;
1601 uint64_t __otx2_io tsc;
1604 struct get_hw_cap_rsp {
1605 struct mbox_msghdr hdr;
1606 /* Schq mapping fixed or flexible */
1607 uint8_t __otx2_io nix_fixed_txschq_mapping;
1608 uint8_t __otx2_io nix_shaping; /* Is shaping and coloring supported */
1611 struct ndc_sync_op {
1612 struct mbox_msghdr hdr;
1613 uint8_t __otx2_io nix_lf_tx_sync;
1614 uint8_t __otx2_io nix_lf_rx_sync;
1615 uint8_t __otx2_io npa_lf_sync;
1618 struct tim_lf_alloc_req {
1619 struct mbox_msghdr hdr;
1620 uint16_t __otx2_io ring;
1621 uint16_t __otx2_io npa_pf_func;
1622 uint16_t __otx2_io sso_pf_func;
1625 struct tim_ring_req {
1626 struct mbox_msghdr hdr;
1627 uint16_t __otx2_io ring;
1630 struct tim_config_req {
1631 struct mbox_msghdr hdr;
1632 uint16_t __otx2_io ring;
1633 uint8_t __otx2_io bigendian;
1634 uint8_t __otx2_io clocksource;
1635 uint8_t __otx2_io enableperiodic;
1636 uint8_t __otx2_io enabledontfreebuffer;
1637 uint32_t __otx2_io bucketsize;
1638 uint32_t __otx2_io chunksize;
1639 uint32_t __otx2_io interval;
1642 struct tim_lf_alloc_rsp {
1643 struct mbox_msghdr hdr;
1644 uint64_t __otx2_io tenns_clk;
1647 struct tim_enable_rsp {
1648 struct mbox_msghdr hdr;
1649 uint64_t __otx2_io timestarted;
1650 uint32_t __otx2_io currentbucket;
1654 const char *otx2_mbox_id2name(uint16_t id);
1655 int otx2_mbox_id2size(uint16_t id);
1656 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
1657 int otx2_mbox_init(struct otx2_mbox *mbox, uintptr_t hwbase, uintptr_t reg_base,
1658 int direction, int ndevsi, uint64_t intr_offset);
1659 void otx2_mbox_fini(struct otx2_mbox *mbox);
1661 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
1663 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
1664 int otx2_mbox_wait_for_rsp_tmo(struct otx2_mbox *mbox, int devid, uint32_t tmo);
1666 int otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, void **msg);
1668 int otx2_mbox_get_rsp_tmo(struct otx2_mbox *mbox, int devid, void **msg,
1670 int otx2_mbox_get_availmem(struct otx2_mbox *mbox, int devid);
1672 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
1673 int size, int size_rsp);
1675 static inline struct mbox_msghdr *
1676 otx2_mbox_alloc_msg(struct otx2_mbox *mbox, int devid, int size)
1678 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
1682 otx2_mbox_req_init(uint16_t mbox_id, void *msghdr)
1684 struct mbox_msghdr *hdr = msghdr;
1686 hdr->sig = OTX2_MBOX_REQ_SIG;
1687 hdr->ver = OTX2_MBOX_VERSION;
1693 otx2_mbox_rsp_init(uint16_t mbox_id, void *msghdr)
1695 struct mbox_msghdr *hdr = msghdr;
1697 hdr->sig = OTX2_MBOX_RSP_SIG;
1698 hdr->rc = -ETIMEDOUT;
1703 otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid)
1705 struct otx2_mbox_dev *mdev = &mbox->dev[devid];
1708 rte_spinlock_lock(&mdev->mbox_lock);
1709 ret = mdev->num_msgs != 0;
1710 rte_spinlock_unlock(&mdev->mbox_lock);
1716 otx2_mbox_process(struct otx2_mbox *mbox)
1718 otx2_mbox_msg_send(mbox, 0);
1719 return otx2_mbox_get_rsp(mbox, 0, NULL);
1723 otx2_mbox_process_msg(struct otx2_mbox *mbox, void **msg)
1725 otx2_mbox_msg_send(mbox, 0);
1726 return otx2_mbox_get_rsp(mbox, 0, msg);
1730 otx2_mbox_process_tmo(struct otx2_mbox *mbox, uint32_t tmo)
1732 otx2_mbox_msg_send(mbox, 0);
1733 return otx2_mbox_get_rsp_tmo(mbox, 0, NULL, tmo);
1737 otx2_mbox_process_msg_tmo(struct otx2_mbox *mbox, void **msg, uint32_t tmo)
1739 otx2_mbox_msg_send(mbox, 0);
1740 return otx2_mbox_get_rsp_tmo(mbox, 0, msg, tmo);
1743 int otx2_send_ready_msg(struct otx2_mbox *mbox, uint16_t *pf_func /* out */);
1744 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, uint16_t pf_func,
1747 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
1748 static inline struct _req_type \
1749 *otx2_mbox_alloc_msg_ ## _fn_name(struct otx2_mbox *mbox) \
1751 struct _req_type *req; \
1753 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \
1754 mbox, 0, sizeof(struct _req_type), \
1755 sizeof(struct _rsp_type)); \
1759 req->hdr.sig = OTX2_MBOX_REQ_SIG; \
1760 req->hdr.id = _id; \
1761 otx2_mbox_dbg("id=0x%x (%s)", \
1762 req->hdr.id, otx2_mbox_id2name(req->hdr.id)); \
1769 /* This is required for copy operations from device memory which do not work on
1770 * addresses which are unaligned to 16B. This is because of specific
1771 * optimizations to libc memcpy.
1773 static inline volatile void *
1774 otx2_mbox_memcpy(volatile void *d, const volatile void *s, size_t l)
1776 const volatile uint8_t *sb;
1777 volatile uint8_t *db;
1782 db = (volatile uint8_t *)d;
1783 sb = (const volatile uint8_t *)s;
1784 for (i = 0; i < l; i++)
1789 /* This is required for memory operations from device memory which do not
1790 * work on addresses which are unaligned to 16B. This is because of specific
1791 * optimizations to libc memset.
1794 otx2_mbox_memset(volatile void *d, uint8_t val, size_t l)
1796 volatile uint8_t *db;
1801 db = (volatile uint8_t *)d;
1802 for (i = 0; i < l; i++)
1806 #endif /* __OTX2_MBOX_H__ */