1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef __OTX2_MBOX_H__
6 #define __OTX2_MBOX_H__
11 #include <rte_ether.h>
12 #include <rte_spinlock.h>
14 #include <otx2_common.h>
16 #define SZ_64K (64ULL * 1024ULL)
17 #define SZ_1K (1ULL * 1024ULL)
18 #define MBOX_SIZE SZ_64K
20 /* AF/PF: PF initiated, PF/VF VF initiated */
21 #define MBOX_DOWN_RX_START 0
22 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
23 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
24 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
25 /* AF/PF: AF initiated, PF/VF PF initiated */
26 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
27 #define MBOX_UP_RX_SIZE SZ_1K
28 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
29 #define MBOX_UP_TX_SIZE SZ_1K
31 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
32 # error "Incorrect mailbox area sizes"
35 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
37 #define MBOX_RSP_TIMEOUT 3000 /* Time to wait for mbox response in ms */
39 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
41 /* Mailbox directions */
42 #define MBOX_DIR_AFPF 0 /* AF replies to PF */
43 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */
44 #define MBOX_DIR_PFVF 2 /* PF replies to VF */
45 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */
46 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */
47 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */
48 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */
49 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */
51 /* Device memory does not support unaligned access, instruct compiler to
52 * not optimize the memory access when working with mailbox memory.
54 #define __otx2_io volatile
56 struct otx2_mbox_dev {
57 void *mbase; /* This dev's mbox region */
58 rte_spinlock_t mbox_lock;
59 uint16_t msg_size; /* Total msg size to be sent */
60 uint16_t rsp_size; /* Total rsp size to be sure the reply is ok */
61 uint16_t num_msgs; /* No of msgs sent or waiting for response */
62 uint16_t msgs_acked; /* No of msgs for which response is received */
66 uintptr_t hwbase; /* Mbox region advertised by HW */
67 uintptr_t reg_base;/* CSR base for this dev */
68 uint64_t trigger; /* Trigger mbox notification */
69 uint16_t tr_shift; /* Mbox trigger shift */
70 uint64_t rx_start; /* Offset of Rx region in mbox memory */
71 uint64_t tx_start; /* Offset of Tx region in mbox memory */
72 uint16_t rx_size; /* Size of Rx region */
73 uint16_t tx_size; /* Size of Tx region */
74 uint16_t ndevs; /* The number of peers */
75 struct otx2_mbox_dev *dev;
76 uint64_t intr_offset; /* Offset to interrupt register */
79 /* Header which precedes all mbox messages */
81 uint64_t __otx2_io msg_size; /* Total msgs size embedded */
82 uint16_t __otx2_io num_msgs; /* No of msgs embedded */
85 /* Header which precedes every msg and is also part of it */
87 uint16_t __otx2_io pcifunc; /* Who's sending this msg */
88 uint16_t __otx2_io id; /* Mbox message ID */
89 #define OTX2_MBOX_REQ_SIG (0xdead)
90 #define OTX2_MBOX_RSP_SIG (0xbeef)
91 /* Signature, for validating corrupted msgs */
92 uint16_t __otx2_io sig;
93 #define OTX2_MBOX_VERSION (0x0009)
94 /* Version of msg's structure for this ID */
95 uint16_t __otx2_io ver;
96 /* Offset of next msg within mailbox region */
97 uint16_t __otx2_io next_msgoff;
98 int __otx2_io rc; /* Msg processed response code */
101 /* Mailbox message types */
102 #define MBOX_MSG_MASK 0xFFFF
103 #define MBOX_MSG_INVALID 0xFFFE
104 #define MBOX_MSG_MAX 0xFFFF
106 #define MBOX_MESSAGES \
107 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
108 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
109 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach_req, msg_rsp)\
110 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach_req, msg_rsp)\
111 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
112 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
113 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
114 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
115 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
116 M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \
117 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
118 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
119 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
120 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
121 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get,\
122 cgx_mac_addr_set_or_get) \
123 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get,\
124 cgx_mac_addr_set_or_get) \
125 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
126 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
127 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
128 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
129 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg)\
130 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
131 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
132 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
133 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
134 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
136 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
137 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
138 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
139 cgx_mac_addr_add_rsp) \
140 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
142 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
143 cgx_max_dmac_entries_get_rsp) \
144 M(CGX_SET_LINK_STATE, 0x214, cgx_set_link_state, \
145 cgx_set_link_state_msg, msg_rsp) \
146 M(CGX_GET_PHY_MOD_TYPE, 0x215, cgx_get_phy_mod_type, msg_req, \
148 M(CGX_SET_PHY_MOD_TYPE, 0x216, cgx_set_phy_mod_type, cgx_phy_mod_type, \
150 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
151 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\
152 cgx_set_link_mode_rsp) \
153 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
154 M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \
155 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
156 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, npa_lf_alloc_req, \
158 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
159 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp)\
160 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
161 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
162 M(SSO_LF_ALLOC, 0x600, sso_lf_alloc, sso_lf_alloc_req, \
164 M(SSO_LF_FREE, 0x601, sso_lf_free, sso_lf_free_req, msg_rsp) \
165 M(SSOW_LF_ALLOC, 0x602, ssow_lf_alloc, ssow_lf_alloc_req, msg_rsp)\
166 M(SSOW_LF_FREE, 0x603, ssow_lf_free, ssow_lf_free_req, msg_rsp) \
167 M(SSO_HW_SETCONFIG, 0x604, sso_hw_setconfig, sso_hw_setconfig, \
169 M(SSO_GRP_SET_PRIORITY, 0x605, sso_grp_set_priority, sso_grp_priority, \
171 M(SSO_GRP_GET_PRIORITY, 0x606, sso_grp_get_priority, sso_info_req, \
173 M(SSO_WS_CACHE_INV, 0x607, sso_ws_cache_inv, msg_req, msg_rsp) \
174 M(SSO_GRP_QOS_CONFIG, 0x608, sso_grp_qos_config, sso_grp_qos_cfg, \
176 M(SSO_GRP_GET_STATS, 0x609, sso_grp_get_stats, sso_info_req, \
178 M(SSO_HWS_GET_STATS, 0x610, sso_hws_get_stats, sso_info_req, \
180 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
181 M(TIM_LF_ALLOC, 0x800, tim_lf_alloc, tim_lf_alloc_req, \
183 M(TIM_LF_FREE, 0x801, tim_lf_free, tim_ring_req, msg_rsp) \
184 M(TIM_CONFIG_RING, 0x802, tim_config_ring, tim_config_req, msg_rsp)\
185 M(TIM_ENABLE_RING, 0x803, tim_enable_ring, tim_ring_req, \
187 M(TIM_DISABLE_RING, 0x804, tim_disable_ring, tim_ring_req, msg_rsp) \
188 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
189 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \
190 cpt_lf_alloc_rsp_msg) \
191 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
192 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
194 M(CPT_SET_CRYPTO_GRP, 0xA03, cpt_set_crypto_grp, \
195 cpt_set_crypto_grp_req_msg, \
197 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
198 cpt_inline_ipsec_cfg_msg, msg_rsp) \
199 M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg, \
200 cpt_rx_inline_lf_cfg_msg, msg_rsp) \
201 M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg) \
202 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
203 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, \
204 npc_mcam_alloc_entry_req, \
205 npc_mcam_alloc_entry_rsp) \
206 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
207 npc_mcam_free_entry_req, msg_rsp) \
208 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
209 npc_mcam_write_entry_req, msg_rsp) \
210 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
211 npc_mcam_ena_dis_entry_req, msg_rsp) \
212 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
213 npc_mcam_ena_dis_entry_req, msg_rsp) \
214 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, \
215 npc_mcam_shift_entry_req, \
216 npc_mcam_shift_entry_rsp) \
217 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
218 npc_mcam_alloc_counter_req, \
219 npc_mcam_alloc_counter_rsp) \
220 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
221 npc_mcam_oper_counter_req, \
223 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
224 npc_mcam_unmap_counter_req, \
226 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
227 npc_mcam_oper_counter_req, \
229 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
230 npc_mcam_oper_counter_req, \
231 npc_mcam_oper_counter_rsp) \
232 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry,\
233 npc_mcam_alloc_and_write_entry_req, \
234 npc_mcam_alloc_and_write_entry_rsp) \
235 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, msg_req, \
236 npc_get_kex_cfg_rsp) \
237 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \
238 npc_install_flow_req, \
239 npc_install_flow_rsp) \
240 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \
241 npc_delete_flow_req, msg_rsp) \
242 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
243 npc_mcam_read_entry_req, \
244 npc_mcam_read_entry_rsp) \
245 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \
248 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, msg_req, \
249 npc_mcam_read_base_rule_rsp) \
250 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
251 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, nix_lf_alloc_req, \
253 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
254 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, \
256 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, hwctx_disable_req, \
258 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, nix_txsch_alloc_req, \
259 nix_txsch_alloc_rsp) \
260 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, \
262 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
264 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
265 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \
266 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
267 nix_rss_flowkey_cfg, \
268 nix_rss_flowkey_cfg_rsp) \
269 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, \
271 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
272 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
273 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
274 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
275 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
276 nix_mark_format_cfg, \
277 nix_mark_format_cfg_rsp) \
278 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
279 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, nix_lso_format_cfg, \
280 nix_lso_format_cfg_rsp) \
281 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, \
283 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, \
285 M(NIX_SET_VLAN_TPID, 0x8015, nix_set_vlan_tpid, nix_set_vlan_tpid, \
287 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
289 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp)\
290 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, \
291 nix_get_mac_addr_rsp) \
292 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \
293 nix_inline_ipsec_cfg, msg_rsp) \
294 M(NIX_INLINE_IPSEC_LF_CFG, \
295 0x801a, nix_inline_ipsec_lf_cfg, \
296 nix_inline_ipsec_lf_cfg, msg_rsp)
298 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
299 #define MBOX_UP_CGX_MESSAGES \
300 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, \
302 M(CGX_PTP_RX_INFO, 0xC01, cgx_ptp_rx_info, cgx_ptp_rx_info_msg, \
306 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
312 /* Mailbox message formats */
314 #define RVU_DEFAULT_PF_FUNC 0xFFFF
316 /* Generic request msg used for those mbox messages which
317 * don't send any data in the request.
320 struct mbox_msghdr hdr;
323 /* Generic response msg used a ack or response for those mbox
324 * messages which doesn't have a specific rsp msg format.
327 struct mbox_msghdr hdr;
330 /* RVU mailbox error codes
334 RVU_INVALID_VF_ID = -256,
337 struct ready_msg_rsp {
338 struct mbox_msghdr hdr;
339 uint16_t __otx2_io sclk_feq; /* SCLK frequency */
340 uint16_t __otx2_io rclk_freq; /* RCLK frequency */
343 /* Struct to set pkind */
344 struct npc_set_pkind {
345 struct mbox_msghdr hdr;
346 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0)
347 #define OTX2_PRIV_FLAGS_EDSA BIT_ULL(1)
348 #define OTX2_PRIV_FLAGS_HIGIG BIT_ULL(2)
349 #define OTX2_PRIV_FLAGS_LEN_90B BIT_ULL(3)
350 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63)
351 uint64_t __otx2_io mode;
352 #define PKIND_TX BIT_ULL(0)
353 #define PKIND_RX BIT_ULL(1)
354 uint8_t __otx2_io dir;
355 uint8_t __otx2_io pkind; /* valid only in case custom flag */
358 /* Structure for requesting resource provisioning.
359 * 'modify' flag to be used when either requesting more
360 * or to detach partial of a certain resource type.
361 * Rest of the fields specify how many of what type to
363 * To request LFs from two blocks of same type this mailbox
364 * can be sent twice as below:
365 * struct rsrc_attach *attach;
366 * .. Allocate memory for message ..
367 * attach->cptlfs = 3; <3 LFs from CPT0>
369 * .. Allocate memory for message ..
370 * attach->modify = 1;
371 * attach->cpt_blkaddr = BLKADDR_CPT1;
372 * attach->cptlfs = 2; <2 LFs from CPT1>
375 struct rsrc_attach_req {
376 struct mbox_msghdr hdr;
377 uint8_t __otx2_io modify:1;
378 uint8_t __otx2_io npalf:1;
379 uint8_t __otx2_io nixlf:1;
380 uint16_t __otx2_io sso;
381 uint16_t __otx2_io ssow;
382 uint16_t __otx2_io timlfs;
383 uint16_t __otx2_io cptlfs;
384 uint16_t __otx2_io reelfs;
385 /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
386 int __otx2_io cpt_blkaddr;
387 /* BLKADDR_REE0/BLKADDR_REE1 or 0 for BLKADDR_REE0 */
388 int __otx2_io ree_blkaddr;
391 /* Structure for relinquishing resources.
392 * 'partial' flag to be used when relinquishing all resources
393 * but only of a certain type. If not set, all resources of all
394 * types provisioned to the RVU function will be detached.
396 struct rsrc_detach_req {
397 struct mbox_msghdr hdr;
398 uint8_t __otx2_io partial:1;
399 uint8_t __otx2_io npalf:1;
400 uint8_t __otx2_io nixlf:1;
401 uint8_t __otx2_io sso:1;
402 uint8_t __otx2_io ssow:1;
403 uint8_t __otx2_io timlfs:1;
404 uint8_t __otx2_io cptlfs:1;
405 uint8_t __otx2_io reelfs:1;
408 /* NIX Transmit schedulers */
409 #define NIX_TXSCH_LVL_SMQ 0x0
410 #define NIX_TXSCH_LVL_MDQ 0x0
411 #define NIX_TXSCH_LVL_TL4 0x1
412 #define NIX_TXSCH_LVL_TL3 0x2
413 #define NIX_TXSCH_LVL_TL2 0x3
414 #define NIX_TXSCH_LVL_TL1 0x4
415 #define NIX_TXSCH_LVL_CNT 0x5
418 * Number of resources available to the caller.
419 * In reply to MBOX_MSG_FREE_RSRC_CNT.
421 struct free_rsrcs_rsp {
422 struct mbox_msghdr hdr;
423 uint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT];
424 uint16_t __otx2_io sso;
425 uint16_t __otx2_io tim;
426 uint16_t __otx2_io ssow;
427 uint16_t __otx2_io cpt;
428 uint8_t __otx2_io npa;
429 uint8_t __otx2_io nix;
430 uint16_t __otx2_io schq_nix1[NIX_TXSCH_LVL_CNT];
431 uint8_t __otx2_io nix1;
432 uint8_t __otx2_io cpt1;
433 uint8_t __otx2_io ree0;
434 uint8_t __otx2_io ree1;
437 #define MSIX_VECTOR_INVALID 0xFFFF
438 #define MAX_RVU_BLKLF_CNT 256
440 struct msix_offset_rsp {
441 struct mbox_msghdr hdr;
442 uint16_t __otx2_io npa_msixoff;
443 uint16_t __otx2_io nix_msixoff;
444 uint8_t __otx2_io sso;
445 uint8_t __otx2_io ssow;
446 uint8_t __otx2_io timlfs;
447 uint8_t __otx2_io cptlfs;
448 uint16_t __otx2_io sso_msixoff[MAX_RVU_BLKLF_CNT];
449 uint16_t __otx2_io ssow_msixoff[MAX_RVU_BLKLF_CNT];
450 uint16_t __otx2_io timlf_msixoff[MAX_RVU_BLKLF_CNT];
451 uint16_t __otx2_io cptlf_msixoff[MAX_RVU_BLKLF_CNT];
452 uint8_t __otx2_io cpt1_lfs;
453 uint8_t __otx2_io ree0_lfs;
454 uint8_t __otx2_io ree1_lfs;
455 uint16_t __otx2_io cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
456 uint16_t __otx2_io ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
457 uint16_t __otx2_io ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
461 /* CGX mbox message formats */
463 struct cgx_stats_rsp {
464 struct mbox_msghdr hdr;
465 #define CGX_RX_STATS_COUNT 13
466 #define CGX_TX_STATS_COUNT 18
467 uint64_t __otx2_io rx_stats[CGX_RX_STATS_COUNT];
468 uint64_t __otx2_io tx_stats[CGX_TX_STATS_COUNT];
471 struct cgx_fec_stats_rsp {
472 struct mbox_msghdr hdr;
473 uint64_t __otx2_io fec_corr_blks;
474 uint64_t __otx2_io fec_uncorr_blks;
476 /* Structure for requesting the operation for
477 * setting/getting mac address in the CGX interface
479 struct cgx_mac_addr_set_or_get {
480 struct mbox_msghdr hdr;
481 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
484 /* Structure for requesting the operation to
485 * add DMAC filter entry into CGX interface
487 struct cgx_mac_addr_add_req {
488 struct mbox_msghdr hdr;
489 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
492 /* Structure for response against the operation to
493 * add DMAC filter entry into CGX interface
495 struct cgx_mac_addr_add_rsp {
496 struct mbox_msghdr hdr;
497 uint8_t __otx2_io index;
500 /* Structure for requesting the operation to
501 * delete DMAC filter entry from CGX interface
503 struct cgx_mac_addr_del_req {
504 struct mbox_msghdr hdr;
505 uint8_t __otx2_io index;
508 /* Structure for response against the operation to
509 * get maximum supported DMAC filter entries
511 struct cgx_max_dmac_entries_get_rsp {
512 struct mbox_msghdr hdr;
513 uint8_t __otx2_io max_dmac_filters;
516 struct cgx_link_user_info {
517 uint64_t __otx2_io link_up:1;
518 uint64_t __otx2_io full_duplex:1;
519 uint64_t __otx2_io lmac_type_id:4;
520 uint64_t __otx2_io speed:20; /* speed in Mbps */
521 uint64_t __otx2_io an:1; /* AN supported or not */
522 uint64_t __otx2_io fec:2; /* FEC type if enabled else 0 */
523 uint64_t __otx2_io port:8;
524 #define LMACTYPE_STR_LEN 16
525 char lmac_type[LMACTYPE_STR_LEN];
528 struct cgx_link_info_msg {
529 struct mbox_msghdr hdr;
530 struct cgx_link_user_info link_info;
533 struct cgx_ptp_rx_info_msg {
534 struct mbox_msghdr hdr;
535 uint8_t __otx2_io ptp_en;
538 struct cgx_pause_frm_cfg {
539 struct mbox_msghdr hdr;
540 uint8_t __otx2_io set;
541 /* set = 1 if the request is to config pause frames */
542 /* set = 0 if the request is to fetch pause frames config */
543 uint8_t __otx2_io rx_pause;
544 uint8_t __otx2_io tx_pause;
547 struct sfp_eeprom_s {
548 #define SFP_EEPROM_SIZE 256
549 uint16_t __otx2_io sff_id;
550 uint8_t __otx2_io buf[SFP_EEPROM_SIZE];
551 uint64_t __otx2_io reserved;
561 uint64_t __otx2_io can_change_mod_type : 1;
562 uint64_t __otx2_io mod_type : 1;
565 struct cgx_lmac_fwdata_s {
566 uint16_t __otx2_io rw_valid;
567 uint64_t __otx2_io supported_fec;
568 uint64_t __otx2_io supported_an;
569 uint64_t __otx2_io supported_link_modes;
570 /* Only applicable if AN is supported */
571 uint64_t __otx2_io advertised_fec;
572 uint64_t __otx2_io advertised_link_modes;
573 /* Only applicable if SFP/QSFP slot is present */
574 struct sfp_eeprom_s sfp_eeprom;
576 #define LMAC_FWDATA_RESERVED_MEM 1023
577 uint64_t __otx2_io reserved[LMAC_FWDATA_RESERVED_MEM];
581 struct mbox_msghdr hdr;
582 struct cgx_lmac_fwdata_s fwdata;
586 struct mbox_msghdr hdr;
590 struct cgx_set_link_state_msg {
591 struct mbox_msghdr hdr;
592 uint8_t __otx2_io enable;
595 struct cgx_phy_mod_type {
596 struct mbox_msghdr hdr;
600 struct cgx_set_link_mode_args {
601 uint32_t __otx2_io speed;
602 uint8_t __otx2_io duplex;
603 uint8_t __otx2_io an;
604 uint8_t __otx2_io ports;
605 uint64_t __otx2_io mode;
608 struct cgx_set_link_mode_req {
609 struct mbox_msghdr hdr;
610 struct cgx_set_link_mode_args args;
613 struct cgx_set_link_mode_rsp {
614 struct mbox_msghdr hdr;
615 int __otx2_io status;
617 /* NPA mbox message formats */
619 /* NPA mailbox error codes
623 NPA_AF_ERR_PARAM = -301,
624 NPA_AF_ERR_AQ_FULL = -302,
625 NPA_AF_ERR_AQ_ENQUEUE = -303,
626 NPA_AF_ERR_AF_LF_INVALID = -304,
627 NPA_AF_ERR_AF_LF_ALLOC = -305,
628 NPA_AF_ERR_LF_RESET = -306,
631 #define NPA_AURA_SZ_0 0
632 #define NPA_AURA_SZ_128 1
633 #define NPA_AURA_SZ_256 2
634 #define NPA_AURA_SZ_512 3
635 #define NPA_AURA_SZ_1K 4
636 #define NPA_AURA_SZ_2K 5
637 #define NPA_AURA_SZ_4K 6
638 #define NPA_AURA_SZ_8K 7
639 #define NPA_AURA_SZ_16K 8
640 #define NPA_AURA_SZ_32K 9
641 #define NPA_AURA_SZ_64K 10
642 #define NPA_AURA_SZ_128K 11
643 #define NPA_AURA_SZ_256K 12
644 #define NPA_AURA_SZ_512K 13
645 #define NPA_AURA_SZ_1M 14
646 #define NPA_AURA_SZ_MAX 15
648 /* For NPA LF context alloc and init */
649 struct npa_lf_alloc_req {
650 struct mbox_msghdr hdr;
652 int __otx2_io aura_sz; /* No of auras. See NPA_AURA_SZ_* */
653 uint32_t __otx2_io nr_pools; /* No of pools */
654 uint64_t __otx2_io way_mask;
657 struct npa_lf_alloc_rsp {
658 struct mbox_msghdr hdr;
659 uint32_t __otx2_io stack_pg_ptrs; /* No of ptrs per stack page */
660 uint32_t __otx2_io stack_pg_bytes; /* Size of stack page */
661 uint16_t __otx2_io qints; /* NPA_AF_CONST::QINTS */
664 /* NPA AQ enqueue msg */
665 struct npa_aq_enq_req {
666 struct mbox_msghdr hdr;
667 uint32_t __otx2_io aura_id;
668 uint8_t __otx2_io ctype;
669 uint8_t __otx2_io op;
671 /* Valid when op == WRITE/INIT and ctype == AURA.
672 * LF fills the pool_id in aura.pool_addr. AF will translate
673 * the pool_id to pool context pointer.
675 __otx2_io struct npa_aura_s aura;
676 /* Valid when op == WRITE/INIT and ctype == POOL */
677 __otx2_io struct npa_pool_s pool;
679 /* Mask data when op == WRITE (1=write, 0=don't write) */
681 /* Valid when op == WRITE and ctype == AURA */
682 __otx2_io struct npa_aura_s aura_mask;
683 /* Valid when op == WRITE and ctype == POOL */
684 __otx2_io struct npa_pool_s pool_mask;
688 struct npa_aq_enq_rsp {
689 struct mbox_msghdr hdr;
691 /* Valid when op == READ and ctype == AURA */
692 __otx2_io struct npa_aura_s aura;
693 /* Valid when op == READ and ctype == POOL */
694 __otx2_io struct npa_pool_s pool;
698 /* Disable all contexts of type 'ctype' */
699 struct hwctx_disable_req {
700 struct mbox_msghdr hdr;
701 uint8_t __otx2_io ctype;
704 /* NIX mbox message formats */
706 /* NIX mailbox error codes
710 NIX_AF_ERR_PARAM = -401,
711 NIX_AF_ERR_AQ_FULL = -402,
712 NIX_AF_ERR_AQ_ENQUEUE = -403,
713 NIX_AF_ERR_AF_LF_INVALID = -404,
714 NIX_AF_ERR_AF_LF_ALLOC = -405,
715 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
716 NIX_AF_ERR_TLX_INVALID = -407,
717 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
718 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
719 NIX_AF_ERR_FRS_INVALID = -410,
720 NIX_AF_ERR_RX_LINK_INVALID = -411,
721 NIX_AF_INVAL_TXSCHQ_CFG = -412,
722 NIX_AF_SMQ_FLUSH_FAILED = -413,
723 NIX_AF_ERR_LF_RESET = -414,
724 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
725 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
726 NIX_AF_ERR_MARK_CFG_FAIL = -417,
727 NIX_AF_ERR_LSO_CFG_FAIL = -418,
728 NIX_AF_INVAL_NPA_PF_FUNC = -419,
729 NIX_AF_INVAL_SSO_PF_FUNC = -420,
730 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
731 NIX_AF_ERR_RX_VTAG_INUSE = -422,
732 NIX_AF_ERR_PTP_CONFIG_FAIL = -423,
735 /* For NIX LF context alloc and init */
736 struct nix_lf_alloc_req {
737 struct mbox_msghdr hdr;
739 uint32_t __otx2_io rq_cnt; /* No of receive queues */
740 uint32_t __otx2_io sq_cnt; /* No of send queues */
741 uint32_t __otx2_io cq_cnt; /* No of completion queues */
742 uint8_t __otx2_io xqe_sz;
743 uint16_t __otx2_io rss_sz;
744 uint8_t __otx2_io rss_grps;
745 uint16_t __otx2_io npa_func;
746 /* RVU_DEFAULT_PF_FUNC == default pf_func associated with lf */
747 uint16_t __otx2_io sso_func;
748 uint64_t __otx2_io rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
749 uint64_t __otx2_io way_mask;
750 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
754 struct nix_lf_alloc_rsp {
755 struct mbox_msghdr hdr;
756 uint16_t __otx2_io sqb_size;
757 uint16_t __otx2_io rx_chan_base;
758 uint16_t __otx2_io tx_chan_base;
759 uint8_t __otx2_io rx_chan_cnt; /* Total number of RX channels */
760 uint8_t __otx2_io tx_chan_cnt; /* Total number of TX channels */
761 uint8_t __otx2_io lso_tsov4_idx;
762 uint8_t __otx2_io lso_tsov6_idx;
763 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
764 uint8_t __otx2_io lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
765 uint8_t __otx2_io lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
766 uint16_t __otx2_io cints; /* NIX_AF_CONST2::CINTS */
767 uint16_t __otx2_io qints; /* NIX_AF_CONST2::QINTS */
768 uint8_t __otx2_io hw_rx_tstamp_en; /*set if rx timestamping enabled */
769 uint8_t __otx2_io cgx_links; /* No. of CGX links present in HW */
770 uint8_t __otx2_io lbk_links; /* No. of LBK links present in HW */
771 uint8_t __otx2_io sdp_links; /* No. of SDP links present in HW */
772 uint8_t __otx2_io tx_link; /* Transmit channel link number */
775 struct nix_lf_free_req {
776 struct mbox_msghdr hdr;
777 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
778 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
779 uint64_t __otx2_io flags;
782 /* NIX AQ enqueue msg */
783 struct nix_aq_enq_req {
784 struct mbox_msghdr hdr;
785 uint32_t __otx2_io qidx;
786 uint8_t __otx2_io ctype;
787 uint8_t __otx2_io op;
789 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */
790 __otx2_io struct nix_rq_ctx_s rq;
791 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */
792 __otx2_io struct nix_sq_ctx_s sq;
793 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */
794 __otx2_io struct nix_cq_ctx_s cq;
795 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */
796 __otx2_io struct nix_rsse_s rss;
797 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */
798 __otx2_io struct nix_rx_mce_s mce;
800 /* Mask data when op == WRITE (1=write, 0=don't write) */
802 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */
803 __otx2_io struct nix_rq_ctx_s rq_mask;
804 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */
805 __otx2_io struct nix_sq_ctx_s sq_mask;
806 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */
807 __otx2_io struct nix_cq_ctx_s cq_mask;
808 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */
809 __otx2_io struct nix_rsse_s rss_mask;
810 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */
811 __otx2_io struct nix_rx_mce_s mce_mask;
815 struct nix_aq_enq_rsp {
816 struct mbox_msghdr hdr;
818 __otx2_io struct nix_rq_ctx_s rq;
819 __otx2_io struct nix_sq_ctx_s sq;
820 __otx2_io struct nix_cq_ctx_s cq;
821 __otx2_io struct nix_rsse_s rss;
822 __otx2_io struct nix_rx_mce_s mce;
826 /* Tx scheduler/shaper mailbox messages */
828 #define MAX_TXSCHQ_PER_FUNC 128
830 struct nix_txsch_alloc_req {
831 struct mbox_msghdr hdr;
832 /* Scheduler queue count request at each level */
833 uint16_t __otx2_io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
834 uint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
837 struct nix_txsch_alloc_rsp {
838 struct mbox_msghdr hdr;
839 /* Scheduler queue count allocated at each level */
840 uint16_t __otx2_io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
841 uint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
842 /* Scheduler queue list allocated at each level */
844 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
845 uint16_t __otx2_io schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
846 /* Traffic aggregation scheduler level */
847 uint8_t __otx2_io aggr_level;
848 /* Aggregation lvl's RR_PRIO config */
849 uint8_t __otx2_io aggr_lvl_rr_prio;
850 /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
851 uint8_t __otx2_io link_cfg_lvl;
854 struct nix_txsch_free_req {
855 struct mbox_msghdr hdr;
856 #define TXSCHQ_FREE_ALL BIT_ULL(0)
857 uint16_t __otx2_io flags;
858 /* Scheduler queue level to be freed */
859 uint16_t __otx2_io schq_lvl;
860 /* List of scheduler queues to be freed */
861 uint16_t __otx2_io schq;
864 struct nix_txschq_config {
865 struct mbox_msghdr hdr;
866 uint8_t __otx2_io lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
867 uint8_t __otx2_io read;
868 #define TXSCHQ_IDX_SHIFT 16
869 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
870 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
871 uint8_t __otx2_io num_regs;
872 #define MAX_REGS_PER_MBOX_MSG 20
873 uint64_t __otx2_io reg[MAX_REGS_PER_MBOX_MSG];
874 uint64_t __otx2_io regval[MAX_REGS_PER_MBOX_MSG];
875 /* All 0's => overwrite with new value */
876 uint64_t __otx2_io regval_mask[MAX_REGS_PER_MBOX_MSG];
879 struct nix_vtag_config {
880 struct mbox_msghdr hdr;
881 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
882 uint8_t __otx2_io vtag_size;
883 /* cfg_type is '0' for tx vlan cfg
884 * cfg_type is '1' for rx vlan cfg
886 uint8_t __otx2_io cfg_type;
888 /* Valid when cfg_type is '0' */
890 uint64_t __otx2_io vtag0;
891 uint64_t __otx2_io vtag1;
893 /* cfg_vtag0 & cfg_vtag1 fields are valid
894 * when free_vtag0 & free_vtag1 are '0's.
896 /* cfg_vtag0 = 1 to configure vtag0 */
897 uint8_t __otx2_io cfg_vtag0 :1;
898 /* cfg_vtag1 = 1 to configure vtag1 */
899 uint8_t __otx2_io cfg_vtag1 :1;
901 /* vtag0_idx & vtag1_idx are only valid when
902 * both cfg_vtag0 & cfg_vtag1 are '0's,
903 * these fields are used along with free_vtag0
904 * & free_vtag1 to free the nix lf's tx_vlan
907 * Denotes the indices of tx_vtag def registers
908 * that needs to be cleared and freed.
910 int __otx2_io vtag0_idx;
911 int __otx2_io vtag1_idx;
913 /* Free_vtag0 & free_vtag1 fields are valid
914 * when cfg_vtag0 & cfg_vtag1 are '0's.
916 /* Free_vtag0 = 1 clears vtag0 configuration
917 * vtag0_idx denotes the index to be cleared.
919 uint8_t __otx2_io free_vtag0 :1;
920 /* Free_vtag1 = 1 clears vtag1 configuration
921 * vtag1_idx denotes the index to be cleared.
923 uint8_t __otx2_io free_vtag1 :1;
926 /* Valid when cfg_type is '1' */
928 /* Rx vtag type index, valid values are in 0..7 range */
929 uint8_t __otx2_io vtag_type;
931 uint8_t __otx2_io strip_vtag :1;
932 /* Rx vtag capture */
933 uint8_t __otx2_io capture_vtag :1;
938 struct nix_vtag_config_rsp {
939 struct mbox_msghdr hdr;
940 /* Indices of tx_vtag def registers used to configure
941 * tx vtag0 & vtag1 headers, these indices are valid
942 * when nix_vtag_config mbox requested for vtag0 and/
943 * or vtag1 configuration.
945 int __otx2_io vtag0_idx;
946 int __otx2_io vtag1_idx;
949 struct nix_rss_flowkey_cfg {
950 struct mbox_msghdr hdr;
951 int __otx2_io mcam_index; /* MCAM entry index to modify */
952 uint32_t __otx2_io flowkey_cfg; /* Flowkey types selected */
953 #define FLOW_KEY_TYPE_PORT BIT(0)
954 #define FLOW_KEY_TYPE_IPV4 BIT(1)
955 #define FLOW_KEY_TYPE_IPV6 BIT(2)
956 #define FLOW_KEY_TYPE_TCP BIT(3)
957 #define FLOW_KEY_TYPE_UDP BIT(4)
958 #define FLOW_KEY_TYPE_SCTP BIT(5)
959 #define FLOW_KEY_TYPE_NVGRE BIT(6)
960 #define FLOW_KEY_TYPE_VXLAN BIT(7)
961 #define FLOW_KEY_TYPE_GENEVE BIT(8)
962 #define FLOW_KEY_TYPE_ETH_DMAC BIT(9)
963 #define FLOW_KEY_TYPE_IPV6_EXT BIT(10)
964 #define FLOW_KEY_TYPE_GTPU BIT(11)
965 #define FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
966 #define FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
967 #define FLOW_KEY_TYPE_INNR_TCP BIT(14)
968 #define FLOW_KEY_TYPE_INNR_UDP BIT(15)
969 #define FLOW_KEY_TYPE_INNR_SCTP BIT(16)
970 #define FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
971 #define FLOW_KEY_TYPE_CH_LEN_90B BIT(18)
972 #define FLOW_KEY_TYPE_CUSTOM0 BIT(19)
973 #define FLOW_KEY_TYPE_VLAN BIT(20)
974 #define FLOW_KEY_TYPE_L4_DST BIT(28)
975 #define FLOW_KEY_TYPE_L4_SRC BIT(29)
976 #define FLOW_KEY_TYPE_L3_DST BIT(30)
977 #define FLOW_KEY_TYPE_L3_SRC BIT(31)
978 uint8_t __otx2_io group; /* RSS context or group */
981 struct nix_rss_flowkey_cfg_rsp {
982 struct mbox_msghdr hdr;
983 uint8_t __otx2_io alg_idx; /* Selected algo index */
986 struct nix_set_mac_addr {
987 struct mbox_msghdr hdr;
988 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
991 struct nix_get_mac_addr_rsp {
992 struct mbox_msghdr hdr;
993 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
996 struct nix_mark_format_cfg {
997 struct mbox_msghdr hdr;
998 uint8_t __otx2_io offset;
999 uint8_t __otx2_io y_mask;
1000 uint8_t __otx2_io y_val;
1001 uint8_t __otx2_io r_mask;
1002 uint8_t __otx2_io r_val;
1005 struct nix_mark_format_cfg_rsp {
1006 struct mbox_msghdr hdr;
1007 uint8_t __otx2_io mark_format_idx;
1010 struct nix_lso_format_cfg {
1011 struct mbox_msghdr hdr;
1012 uint64_t __otx2_io field_mask;
1013 uint64_t __otx2_io fields[NIX_LSO_FIELD_MAX];
1016 struct nix_lso_format_cfg_rsp {
1017 struct mbox_msghdr hdr;
1018 uint8_t __otx2_io lso_format_idx;
1021 struct nix_rx_mode {
1022 struct mbox_msghdr hdr;
1023 #define NIX_RX_MODE_UCAST BIT(0)
1024 #define NIX_RX_MODE_PROMISC BIT(1)
1025 #define NIX_RX_MODE_ALLMULTI BIT(2)
1026 uint16_t __otx2_io mode;
1030 struct mbox_msghdr hdr;
1031 #define NIX_RX_OL3_VERIFY BIT(0)
1032 #define NIX_RX_OL4_VERIFY BIT(1)
1033 uint8_t __otx2_io len_verify; /* Outer L3/L4 len check */
1034 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
1035 uint8_t __otx2_io csum_verify; /* Outer L4 checksum verification */
1038 struct nix_frs_cfg {
1039 struct mbox_msghdr hdr;
1040 uint8_t __otx2_io update_smq; /* Update SMQ's min/max lens */
1041 uint8_t __otx2_io update_minlen; /* Set minlen also */
1042 uint8_t __otx2_io sdp_link; /* Set SDP RX link */
1043 uint16_t __otx2_io maxlen;
1044 uint16_t __otx2_io minlen;
1047 struct nix_set_vlan_tpid {
1048 struct mbox_msghdr hdr;
1049 #define NIX_VLAN_TYPE_INNER 0
1050 #define NIX_VLAN_TYPE_OUTER 1
1051 uint8_t __otx2_io vlan_type;
1052 uint16_t __otx2_io tpid;
1055 struct nix_bp_cfg_req {
1056 struct mbox_msghdr hdr;
1057 uint16_t __otx2_io chan_base; /* Starting channel number */
1058 uint8_t __otx2_io chan_cnt; /* Number of channels */
1059 uint8_t __otx2_io bpid_per_chan;
1060 /* bpid_per_chan = 0 assigns single bp id for range of channels */
1061 /* bpid_per_chan = 1 assigns separate bp id for each channel */
1064 /* PF can be mapped to either CGX or LBK interface,
1065 * so maximum 64 channels are possible.
1067 #define NIX_MAX_CHAN 64
1068 struct nix_bp_cfg_rsp {
1069 struct mbox_msghdr hdr;
1070 /* Channel and bpid mapping */
1071 uint16_t __otx2_io chan_bpid[NIX_MAX_CHAN];
1072 /* Number of channel for which bpids are assigned */
1073 uint8_t __otx2_io chan_cnt;
1076 /* Global NIX inline IPSec configuration */
1077 struct nix_inline_ipsec_cfg {
1078 struct mbox_msghdr hdr;
1079 uint32_t __otx2_io cpt_credit;
1081 uint8_t __otx2_io egrp;
1082 uint8_t __otx2_io opcode;
1085 uint16_t __otx2_io cpt_pf_func;
1086 uint8_t __otx2_io cpt_slot;
1088 uint8_t __otx2_io enable;
1091 /* Per NIX LF inline IPSec configuration */
1092 struct nix_inline_ipsec_lf_cfg {
1093 struct mbox_msghdr hdr;
1094 uint64_t __otx2_io sa_base_addr;
1096 uint32_t __otx2_io tag_const;
1097 uint16_t __otx2_io lenm1_max;
1098 uint8_t __otx2_io sa_pow2_size;
1099 uint8_t __otx2_io tt;
1102 uint32_t __otx2_io sa_idx_max;
1103 uint8_t __otx2_io sa_idx_w;
1105 uint8_t __otx2_io enable;
1108 /* SSO mailbox error codes
1111 enum sso_af_status {
1112 SSO_AF_ERR_PARAM = -501,
1113 SSO_AF_ERR_LF_INVALID = -502,
1114 SSO_AF_ERR_AF_LF_ALLOC = -503,
1115 SSO_AF_ERR_GRP_EBUSY = -504,
1116 SSO_AF_INVAL_NPA_PF_FUNC = -505,
1119 struct sso_lf_alloc_req {
1120 struct mbox_msghdr hdr;
1122 uint16_t __otx2_io hwgrps;
1125 struct sso_lf_alloc_rsp {
1126 struct mbox_msghdr hdr;
1127 uint32_t __otx2_io xaq_buf_size;
1128 uint32_t __otx2_io xaq_wq_entries;
1129 uint32_t __otx2_io in_unit_entries;
1130 uint16_t __otx2_io hwgrps;
1133 struct sso_lf_free_req {
1134 struct mbox_msghdr hdr;
1136 uint16_t __otx2_io hwgrps;
1139 /* SSOW mailbox error codes
1142 enum ssow_af_status {
1143 SSOW_AF_ERR_PARAM = -601,
1144 SSOW_AF_ERR_LF_INVALID = -602,
1145 SSOW_AF_ERR_AF_LF_ALLOC = -603,
1148 struct ssow_lf_alloc_req {
1149 struct mbox_msghdr hdr;
1151 uint16_t __otx2_io hws;
1154 struct ssow_lf_free_req {
1155 struct mbox_msghdr hdr;
1157 uint16_t __otx2_io hws;
1160 struct sso_hw_setconfig {
1161 struct mbox_msghdr hdr;
1162 uint32_t __otx2_io npa_aura_id;
1163 uint16_t __otx2_io npa_pf_func;
1164 uint16_t __otx2_io hwgrps;
1167 struct sso_info_req {
1168 struct mbox_msghdr hdr;
1170 uint16_t __otx2_io grp;
1171 uint16_t __otx2_io hws;
1175 struct sso_grp_priority {
1176 struct mbox_msghdr hdr;
1177 uint16_t __otx2_io grp;
1178 uint8_t __otx2_io priority;
1179 uint8_t __otx2_io affinity;
1180 uint8_t __otx2_io weight;
1183 struct sso_grp_qos_cfg {
1184 struct mbox_msghdr hdr;
1185 uint16_t __otx2_io grp;
1186 uint32_t __otx2_io xaq_limit;
1187 uint16_t __otx2_io taq_thr;
1188 uint16_t __otx2_io iaq_thr;
1191 struct sso_grp_stats {
1192 struct mbox_msghdr hdr;
1193 uint16_t __otx2_io grp;
1194 uint64_t __otx2_io ws_pc;
1195 uint64_t __otx2_io ext_pc;
1196 uint64_t __otx2_io wa_pc;
1197 uint64_t __otx2_io ts_pc;
1198 uint64_t __otx2_io ds_pc;
1199 uint64_t __otx2_io dq_pc;
1200 uint64_t __otx2_io aw_status;
1201 uint64_t __otx2_io page_cnt;
1204 struct sso_hws_stats {
1205 struct mbox_msghdr hdr;
1206 uint16_t __otx2_io hws;
1207 uint64_t __otx2_io arbitration;
1210 /* CPT mailbox error codes
1213 enum cpt_af_status {
1214 CPT_AF_ERR_PARAM = -901,
1215 CPT_AF_ERR_GRP_INVALID = -902,
1216 CPT_AF_ERR_LF_INVALID = -903,
1217 CPT_AF_ERR_ACCESS_DENIED = -904,
1218 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
1219 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906,
1220 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907,
1221 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908
1224 /* CPT mbox message formats */
1226 struct cpt_rd_wr_reg_msg {
1227 struct mbox_msghdr hdr;
1228 uint64_t __otx2_io reg_offset;
1229 uint64_t __otx2_io *ret_val;
1230 uint64_t __otx2_io val;
1231 uint8_t __otx2_io is_write;
1234 struct cpt_set_crypto_grp_req_msg {
1235 struct mbox_msghdr hdr;
1236 uint8_t __otx2_io crypto_eng_grp;
1239 struct cpt_lf_alloc_req_msg {
1240 struct mbox_msghdr hdr;
1241 uint16_t __otx2_io nix_pf_func;
1242 uint16_t __otx2_io sso_pf_func;
1245 struct cpt_lf_alloc_rsp_msg {
1246 struct mbox_msghdr hdr;
1247 uint8_t __otx2_io crypto_eng_grp;
1250 #define CPT_INLINE_INBOUND 0
1251 #define CPT_INLINE_OUTBOUND 1
1253 struct cpt_inline_ipsec_cfg_msg {
1254 struct mbox_msghdr hdr;
1255 uint8_t __otx2_io enable;
1256 uint8_t __otx2_io slot;
1257 uint8_t __otx2_io dir;
1258 uint16_t __otx2_io sso_pf_func; /* Inbound path SSO_PF_FUNC */
1259 uint16_t __otx2_io nix_pf_func; /* Outbound path NIX_PF_FUNC */
1262 struct cpt_rx_inline_lf_cfg_msg {
1263 struct mbox_msghdr hdr;
1264 uint16_t __otx2_io sso_pf_func;
1268 CPT_ENG_TYPE_AE = 1,
1269 CPT_ENG_TYPE_SE = 2,
1270 CPT_ENG_TYPE_IE = 3,
1274 /* CPT HW capabilities */
1275 union cpt_eng_caps {
1276 uint64_t __otx2_io u;
1278 uint64_t __otx2_io reserved_0_4:5;
1279 uint64_t __otx2_io mul:1;
1280 uint64_t __otx2_io sha1_sha2:1;
1281 uint64_t __otx2_io chacha20:1;
1282 uint64_t __otx2_io zuc_snow3g:1;
1283 uint64_t __otx2_io sha3:1;
1284 uint64_t __otx2_io aes:1;
1285 uint64_t __otx2_io kasumi:1;
1286 uint64_t __otx2_io des:1;
1287 uint64_t __otx2_io crc:1;
1288 uint64_t __otx2_io reserved_14_63:50;
1292 struct cpt_caps_rsp_msg {
1293 struct mbox_msghdr hdr;
1294 uint16_t __otx2_io cpt_pf_drv_version;
1295 uint8_t __otx2_io cpt_revision;
1296 union cpt_eng_caps eng_caps[CPT_MAX_ENG_TYPES];
1299 /* NPC mbox message structs */
1301 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
1302 #define NPC_MCAM_INVALID_MAP 0xFFFF
1304 /* NPC mailbox error codes
1307 enum npc_af_status {
1308 NPC_MCAM_INVALID_REQ = -701,
1309 NPC_MCAM_ALLOC_DENIED = -702,
1310 NPC_MCAM_ALLOC_FAILED = -703,
1311 NPC_MCAM_PERM_DENIED = -704,
1312 NPC_AF_ERR_HIGIG_CONFIG_FAIL = -705,
1315 struct npc_mcam_alloc_entry_req {
1316 struct mbox_msghdr hdr;
1317 #define NPC_MAX_NONCONTIG_ENTRIES 256
1318 uint8_t __otx2_io contig; /* Contiguous entries ? */
1319 #define NPC_MCAM_ANY_PRIO 0
1320 #define NPC_MCAM_LOWER_PRIO 1
1321 #define NPC_MCAM_HIGHER_PRIO 2
1322 uint8_t __otx2_io priority; /* Lower or higher w.r.t ref_entry */
1323 uint16_t __otx2_io ref_entry;
1324 uint16_t __otx2_io count; /* Number of entries requested */
1327 struct npc_mcam_alloc_entry_rsp {
1328 struct mbox_msghdr hdr;
1329 /* Entry alloc'ed or start index if contiguous.
1330 * Invalid in case of non-contiguous.
1332 uint16_t __otx2_io entry;
1333 uint16_t __otx2_io count; /* Number of entries allocated */
1334 uint16_t __otx2_io free_count; /* Number of entries available */
1335 uint16_t __otx2_io entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1338 struct npc_mcam_free_entry_req {
1339 struct mbox_msghdr hdr;
1340 uint16_t __otx2_io entry; /* Entry index to be freed */
1341 uint8_t __otx2_io all; /* Free all entries alloc'ed to this PFVF */
1345 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max key width */
1346 uint64_t __otx2_io kw[NPC_MAX_KWS_IN_KEY];
1347 uint64_t __otx2_io kw_mask[NPC_MAX_KWS_IN_KEY];
1348 uint64_t __otx2_io action;
1349 uint64_t __otx2_io vtag_action;
1352 struct npc_mcam_write_entry_req {
1353 struct mbox_msghdr hdr;
1354 struct mcam_entry entry_data;
1355 uint16_t __otx2_io entry; /* MCAM entry to write this match key */
1356 uint16_t __otx2_io cntr; /* Counter for this MCAM entry */
1357 uint8_t __otx2_io intf; /* Rx or Tx interface */
1358 uint8_t __otx2_io enable_entry;/* Enable this MCAM entry ? */
1359 uint8_t __otx2_io set_cntr; /* Set counter for this entry ? */
1362 /* Enable/Disable a given entry */
1363 struct npc_mcam_ena_dis_entry_req {
1364 struct mbox_msghdr hdr;
1365 uint16_t __otx2_io entry;
1368 struct npc_mcam_shift_entry_req {
1369 struct mbox_msghdr hdr;
1370 #define NPC_MCAM_MAX_SHIFTS 64
1371 uint16_t __otx2_io curr_entry[NPC_MCAM_MAX_SHIFTS];
1372 uint16_t __otx2_io new_entry[NPC_MCAM_MAX_SHIFTS];
1373 uint16_t __otx2_io shift_count; /* Number of entries to shift */
1376 struct npc_mcam_shift_entry_rsp {
1377 struct mbox_msghdr hdr;
1378 /* Index in 'curr_entry', not entry itself */
1379 uint16_t __otx2_io failed_entry_idx;
1382 struct npc_mcam_alloc_counter_req {
1383 struct mbox_msghdr hdr;
1384 uint8_t __otx2_io contig; /* Contiguous counters ? */
1385 #define NPC_MAX_NONCONTIG_COUNTERS 64
1386 uint16_t __otx2_io count; /* Number of counters requested */
1389 struct npc_mcam_alloc_counter_rsp {
1390 struct mbox_msghdr hdr;
1391 /* Counter alloc'ed or start idx if contiguous.
1392 * Invalid incase of non-contiguous.
1394 uint16_t __otx2_io cntr;
1395 uint16_t __otx2_io count; /* Number of counters allocated */
1396 uint16_t __otx2_io cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1399 struct npc_mcam_oper_counter_req {
1400 struct mbox_msghdr hdr;
1401 uint16_t __otx2_io cntr; /* Free a counter or clear/fetch it's stats */
1404 struct npc_mcam_oper_counter_rsp {
1405 struct mbox_msghdr hdr;
1406 /* valid only while fetching counter's stats */
1407 uint64_t __otx2_io stat;
1410 struct npc_mcam_unmap_counter_req {
1411 struct mbox_msghdr hdr;
1412 uint16_t __otx2_io cntr;
1413 uint16_t __otx2_io entry; /* Entry and counter to be unmapped */
1414 uint8_t __otx2_io all; /* Unmap all entries using this counter ? */
1417 struct npc_mcam_alloc_and_write_entry_req {
1418 struct mbox_msghdr hdr;
1419 struct mcam_entry entry_data;
1420 uint16_t __otx2_io ref_entry;
1421 uint8_t __otx2_io priority; /* Lower or higher w.r.t ref_entry */
1422 uint8_t __otx2_io intf; /* Rx or Tx interface */
1423 uint8_t __otx2_io enable_entry;/* Enable this MCAM entry ? */
1424 uint8_t __otx2_io alloc_cntr; /* Allocate counter and map ? */
1427 struct npc_mcam_alloc_and_write_entry_rsp {
1428 struct mbox_msghdr hdr;
1429 uint16_t __otx2_io entry;
1430 uint16_t __otx2_io cntr;
1433 struct npc_get_kex_cfg_rsp {
1434 struct mbox_msghdr hdr;
1435 uint64_t __otx2_io rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1436 uint64_t __otx2_io tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1437 #define NPC_MAX_INTF 2
1438 #define NPC_MAX_LID 8
1439 #define NPC_MAX_LT 16
1440 #define NPC_MAX_LD 2
1441 #define NPC_MAX_LFL 16
1442 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1443 uint64_t __otx2_io kex_ld_flags[NPC_MAX_LD];
1444 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1446 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
1447 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1449 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1450 #define MKEX_NAME_LEN 128
1451 uint8_t __otx2_io mkex_pfl_name[MKEX_NAME_LEN];
1454 enum header_fields {
1469 NPC_HEADER_FIELDS_MAX,
1473 unsigned char __otx2_io dmac[6];
1474 unsigned char __otx2_io smac[6];
1475 uint16_t __otx2_io etype;
1476 uint16_t __otx2_io vlan_etype;
1477 uint16_t __otx2_io vlan_tci;
1479 uint32_t __otx2_io ip4src;
1480 uint32_t __otx2_io ip6src[4];
1483 uint32_t __otx2_io ip4dst;
1484 uint32_t __otx2_io ip6dst[4];
1486 uint8_t __otx2_io tos;
1487 uint8_t __otx2_io ip_ver;
1488 uint8_t __otx2_io ip_proto;
1489 uint8_t __otx2_io tc;
1490 uint16_t __otx2_io sport;
1491 uint16_t __otx2_io dport;
1494 struct npc_install_flow_req {
1495 struct mbox_msghdr hdr;
1496 struct flow_msg packet;
1497 struct flow_msg mask;
1498 uint64_t __otx2_io features;
1499 uint16_t __otx2_io entry;
1500 uint16_t __otx2_io channel;
1501 uint8_t __otx2_io intf;
1502 uint8_t __otx2_io set_cntr;
1503 uint8_t __otx2_io default_rule;
1504 /* Overwrite(0) or append(1) flow to default rule? */
1505 uint8_t __otx2_io append;
1506 uint16_t __otx2_io vf;
1508 uint32_t __otx2_io index;
1509 uint16_t __otx2_io match_id;
1510 uint8_t __otx2_io flow_key_alg;
1511 uint8_t __otx2_io op;
1513 uint8_t __otx2_io vtag0_type;
1514 uint8_t __otx2_io vtag0_valid;
1515 uint8_t __otx2_io vtag1_type;
1516 uint8_t __otx2_io vtag1_valid;
1518 /* vtag tx action */
1519 uint16_t __otx2_io vtag0_def;
1520 uint8_t __otx2_io vtag0_op;
1521 uint16_t __otx2_io vtag1_def;
1522 uint8_t __otx2_io vtag1_op;
1525 struct npc_install_flow_rsp {
1526 struct mbox_msghdr hdr;
1527 /* Negative if no counter else counter number */
1528 int __otx2_io counter;
1531 struct npc_delete_flow_req {
1532 struct mbox_msghdr hdr;
1533 uint16_t __otx2_io entry;
1534 uint16_t __otx2_io start;/*Disable range of entries */
1535 uint16_t __otx2_io end;
1536 uint8_t __otx2_io all; /* PF + VFs */
1539 struct npc_mcam_read_entry_req {
1540 struct mbox_msghdr hdr;
1541 /* MCAM entry to read */
1542 uint16_t __otx2_io entry;
1545 struct npc_mcam_read_entry_rsp {
1546 struct mbox_msghdr hdr;
1547 struct mcam_entry entry_data;
1548 uint8_t __otx2_io intf;
1549 uint8_t __otx2_io enable;
1552 struct npc_mcam_read_base_rule_rsp {
1553 struct mbox_msghdr hdr;
1554 struct mcam_entry entry_data;
1557 /* TIM mailbox error codes
1560 enum tim_af_status {
1561 TIM_AF_NO_RINGS_LEFT = -801,
1562 TIM_AF_INVALID_NPA_PF_FUNC = -802,
1563 TIM_AF_INVALID_SSO_PF_FUNC = -803,
1564 TIM_AF_RING_STILL_RUNNING = -804,
1565 TIM_AF_LF_INVALID = -805,
1566 TIM_AF_CSIZE_NOT_ALIGNED = -806,
1567 TIM_AF_CSIZE_TOO_SMALL = -807,
1568 TIM_AF_CSIZE_TOO_BIG = -808,
1569 TIM_AF_INTERVAL_TOO_SMALL = -809,
1570 TIM_AF_INVALID_BIG_ENDIAN_VALUE = -810,
1571 TIM_AF_INVALID_CLOCK_SOURCE = -811,
1572 TIM_AF_GPIO_CLK_SRC_NOT_ENABLED = -812,
1573 TIM_AF_INVALID_BSIZE = -813,
1574 TIM_AF_INVALID_ENABLE_PERIODIC = -814,
1575 TIM_AF_INVALID_ENABLE_DONTFREE = -815,
1576 TIM_AF_ENA_DONTFRE_NSET_PERIODIC = -816,
1577 TIM_AF_RING_ALREADY_DISABLED = -817,
1581 TIM_CLK_SRCS_TENNS = 0,
1582 TIM_CLK_SRCS_GPIO = 1,
1583 TIM_CLK_SRCS_GTI = 2,
1584 TIM_CLK_SRCS_PTP = 3,
1585 TIM_CLK_SRSC_INVALID,
1588 enum tim_gpio_edge {
1589 TIM_GPIO_NO_EDGE = 0,
1590 TIM_GPIO_LTOH_TRANS = 1,
1591 TIM_GPIO_HTOL_TRANS = 2,
1592 TIM_GPIO_BOTH_TRANS = 3,
1597 PTP_OP_ADJFINE = 0, /* adjfine(req.scaled_ppm); */
1598 PTP_OP_GET_CLOCK = 1, /* rsp.clk = get_clock() */
1602 struct mbox_msghdr hdr;
1603 uint8_t __otx2_io op;
1604 int64_t __otx2_io scaled_ppm;
1605 uint8_t __otx2_io is_pmu;
1609 struct mbox_msghdr hdr;
1610 uint64_t __otx2_io clk;
1611 uint64_t __otx2_io tsc;
1614 struct get_hw_cap_rsp {
1615 struct mbox_msghdr hdr;
1616 /* Schq mapping fixed or flexible */
1617 uint8_t __otx2_io nix_fixed_txschq_mapping;
1618 uint8_t __otx2_io nix_shaping; /* Is shaping and coloring supported */
1621 struct ndc_sync_op {
1622 struct mbox_msghdr hdr;
1623 uint8_t __otx2_io nix_lf_tx_sync;
1624 uint8_t __otx2_io nix_lf_rx_sync;
1625 uint8_t __otx2_io npa_lf_sync;
1628 struct tim_lf_alloc_req {
1629 struct mbox_msghdr hdr;
1630 uint16_t __otx2_io ring;
1631 uint16_t __otx2_io npa_pf_func;
1632 uint16_t __otx2_io sso_pf_func;
1635 struct tim_ring_req {
1636 struct mbox_msghdr hdr;
1637 uint16_t __otx2_io ring;
1640 struct tim_config_req {
1641 struct mbox_msghdr hdr;
1642 uint16_t __otx2_io ring;
1643 uint8_t __otx2_io bigendian;
1644 uint8_t __otx2_io clocksource;
1645 uint8_t __otx2_io enableperiodic;
1646 uint8_t __otx2_io enabledontfreebuffer;
1647 uint32_t __otx2_io bucketsize;
1648 uint32_t __otx2_io chunksize;
1649 uint32_t __otx2_io interval;
1652 struct tim_lf_alloc_rsp {
1653 struct mbox_msghdr hdr;
1654 uint64_t __otx2_io tenns_clk;
1657 struct tim_enable_rsp {
1658 struct mbox_msghdr hdr;
1659 uint64_t __otx2_io timestarted;
1660 uint32_t __otx2_io currentbucket;
1664 const char *otx2_mbox_id2name(uint16_t id);
1665 int otx2_mbox_id2size(uint16_t id);
1666 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
1667 int otx2_mbox_init(struct otx2_mbox *mbox, uintptr_t hwbase, uintptr_t reg_base,
1668 int direction, int ndevsi, uint64_t intr_offset);
1669 void otx2_mbox_fini(struct otx2_mbox *mbox);
1671 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
1673 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
1674 int otx2_mbox_wait_for_rsp_tmo(struct otx2_mbox *mbox, int devid, uint32_t tmo);
1676 int otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, void **msg);
1678 int otx2_mbox_get_rsp_tmo(struct otx2_mbox *mbox, int devid, void **msg,
1680 int otx2_mbox_get_availmem(struct otx2_mbox *mbox, int devid);
1682 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
1683 int size, int size_rsp);
1685 static inline struct mbox_msghdr *
1686 otx2_mbox_alloc_msg(struct otx2_mbox *mbox, int devid, int size)
1688 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
1692 otx2_mbox_req_init(uint16_t mbox_id, void *msghdr)
1694 struct mbox_msghdr *hdr = msghdr;
1696 hdr->sig = OTX2_MBOX_REQ_SIG;
1697 hdr->ver = OTX2_MBOX_VERSION;
1703 otx2_mbox_rsp_init(uint16_t mbox_id, void *msghdr)
1705 struct mbox_msghdr *hdr = msghdr;
1707 hdr->sig = OTX2_MBOX_RSP_SIG;
1708 hdr->rc = -ETIMEDOUT;
1713 otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid)
1715 struct otx2_mbox_dev *mdev = &mbox->dev[devid];
1718 rte_spinlock_lock(&mdev->mbox_lock);
1719 ret = mdev->num_msgs != 0;
1720 rte_spinlock_unlock(&mdev->mbox_lock);
1726 otx2_mbox_process(struct otx2_mbox *mbox)
1728 otx2_mbox_msg_send(mbox, 0);
1729 return otx2_mbox_get_rsp(mbox, 0, NULL);
1733 otx2_mbox_process_msg(struct otx2_mbox *mbox, void **msg)
1735 otx2_mbox_msg_send(mbox, 0);
1736 return otx2_mbox_get_rsp(mbox, 0, msg);
1740 otx2_mbox_process_tmo(struct otx2_mbox *mbox, uint32_t tmo)
1742 otx2_mbox_msg_send(mbox, 0);
1743 return otx2_mbox_get_rsp_tmo(mbox, 0, NULL, tmo);
1747 otx2_mbox_process_msg_tmo(struct otx2_mbox *mbox, void **msg, uint32_t tmo)
1749 otx2_mbox_msg_send(mbox, 0);
1750 return otx2_mbox_get_rsp_tmo(mbox, 0, msg, tmo);
1753 int otx2_send_ready_msg(struct otx2_mbox *mbox, uint16_t *pf_func /* out */);
1754 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, uint16_t pf_func,
1757 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
1758 static inline struct _req_type \
1759 *otx2_mbox_alloc_msg_ ## _fn_name(struct otx2_mbox *mbox) \
1761 struct _req_type *req; \
1763 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \
1764 mbox, 0, sizeof(struct _req_type), \
1765 sizeof(struct _rsp_type)); \
1769 req->hdr.sig = OTX2_MBOX_REQ_SIG; \
1770 req->hdr.id = _id; \
1771 otx2_mbox_dbg("id=0x%x (%s)", \
1772 req->hdr.id, otx2_mbox_id2name(req->hdr.id)); \
1779 /* This is required for copy operations from device memory which do not work on
1780 * addresses which are unaligned to 16B. This is because of specific
1781 * optimizations to libc memcpy.
1783 static inline volatile void *
1784 otx2_mbox_memcpy(volatile void *d, const volatile void *s, size_t l)
1786 const volatile uint8_t *sb;
1787 volatile uint8_t *db;
1792 db = (volatile uint8_t *)d;
1793 sb = (const volatile uint8_t *)s;
1794 for (i = 0; i < l; i++)
1799 /* This is required for memory operations from device memory which do not
1800 * work on addresses which are unaligned to 16B. This is because of specific
1801 * optimizations to libc memset.
1804 otx2_mbox_memset(volatile void *d, uint8_t val, size_t l)
1806 volatile uint8_t *db;
1811 db = (volatile uint8_t *)d;
1812 for (i = 0; i < l; i++)
1816 #endif /* __OTX2_MBOX_H__ */