1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef __OTX2_MBOX_H__
6 #define __OTX2_MBOX_H__
11 #include <rte_ether.h>
12 #include <rte_spinlock.h>
14 #include <otx2_common.h>
16 #define SZ_64K (64ULL * 1024ULL)
17 #define SZ_1K (1ULL * 1024ULL)
18 #define MBOX_SIZE SZ_64K
20 /* AF/PF: PF initiated, PF/VF VF initiated */
21 #define MBOX_DOWN_RX_START 0
22 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
23 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
24 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
25 /* AF/PF: AF initiated, PF/VF PF initiated */
26 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
27 #define MBOX_UP_RX_SIZE SZ_1K
28 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
29 #define MBOX_UP_TX_SIZE SZ_1K
31 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
32 # error "Incorrect mailbox area sizes"
35 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
37 #define MBOX_RSP_TIMEOUT 3000 /* Time to wait for mbox response in ms */
39 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
41 /* Mailbox directions */
42 #define MBOX_DIR_AFPF 0 /* AF replies to PF */
43 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */
44 #define MBOX_DIR_PFVF 2 /* PF replies to VF */
45 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */
46 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */
47 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */
48 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */
49 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */
51 /* Device memory does not support unaligned access, instruct compiler to
52 * not optimize the memory access when working with mailbox memory.
54 #define __otx2_io volatile
56 struct otx2_mbox_dev {
57 void *mbase; /* This dev's mbox region */
58 rte_spinlock_t mbox_lock;
59 uint16_t msg_size; /* Total msg size to be sent */
60 uint16_t rsp_size; /* Total rsp size to be sure the reply is ok */
61 uint16_t num_msgs; /* No of msgs sent or waiting for response */
62 uint16_t msgs_acked; /* No of msgs for which response is received */
66 uintptr_t hwbase; /* Mbox region advertised by HW */
67 uintptr_t reg_base;/* CSR base for this dev */
68 uint64_t trigger; /* Trigger mbox notification */
69 uint16_t tr_shift; /* Mbox trigger shift */
70 uint64_t rx_start; /* Offset of Rx region in mbox memory */
71 uint64_t tx_start; /* Offset of Tx region in mbox memory */
72 uint16_t rx_size; /* Size of Rx region */
73 uint16_t tx_size; /* Size of Tx region */
74 uint16_t ndevs; /* The number of peers */
75 struct otx2_mbox_dev *dev;
76 uint64_t intr_offset; /* Offset to interrupt register */
79 /* Header which precedes all mbox messages */
81 uint64_t __otx2_io msg_size; /* Total msgs size embedded */
82 uint16_t __otx2_io num_msgs; /* No of msgs embedded */
85 /* Header which precedes every msg and is also part of it */
87 uint16_t __otx2_io pcifunc; /* Who's sending this msg */
88 uint16_t __otx2_io id; /* Mbox message ID */
89 #define OTX2_MBOX_REQ_SIG (0xdead)
90 #define OTX2_MBOX_RSP_SIG (0xbeef)
91 /* Signature, for validating corrupted msgs */
92 uint16_t __otx2_io sig;
93 #define OTX2_MBOX_VERSION (0x000a)
94 /* Version of msg's structure for this ID */
95 uint16_t __otx2_io ver;
96 /* Offset of next msg within mailbox region */
97 uint16_t __otx2_io next_msgoff;
98 int __otx2_io rc; /* Msg processed response code */
101 /* Mailbox message types */
102 #define MBOX_MSG_MASK 0xFFFF
103 #define MBOX_MSG_INVALID 0xFFFE
104 #define MBOX_MSG_MAX 0xFFFF
106 #define MBOX_MESSAGES \
107 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
108 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
109 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach_req, msg_rsp)\
110 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach_req, msg_rsp)\
111 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
112 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
113 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
114 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
115 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
116 M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \
117 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
118 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
119 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
120 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
121 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get,\
122 cgx_mac_addr_set_or_get) \
123 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get,\
124 cgx_mac_addr_set_or_get) \
125 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
126 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
127 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
128 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
129 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg)\
130 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
131 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
132 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
133 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
134 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
136 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
137 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
138 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
139 cgx_mac_addr_add_rsp) \
140 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
142 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
143 cgx_max_dmac_entries_get_rsp) \
144 M(CGX_SET_LINK_STATE, 0x214, cgx_set_link_state, \
145 cgx_set_link_state_msg, msg_rsp) \
146 M(CGX_GET_PHY_MOD_TYPE, 0x215, cgx_get_phy_mod_type, msg_req, \
148 M(CGX_SET_PHY_MOD_TYPE, 0x216, cgx_set_phy_mod_type, cgx_phy_mod_type, \
150 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
151 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\
152 cgx_set_link_mode_rsp) \
153 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
154 M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \
155 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
156 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, npa_lf_alloc_req, \
158 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
159 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp)\
160 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
161 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
162 M(SSO_LF_ALLOC, 0x600, sso_lf_alloc, sso_lf_alloc_req, \
164 M(SSO_LF_FREE, 0x601, sso_lf_free, sso_lf_free_req, msg_rsp) \
165 M(SSOW_LF_ALLOC, 0x602, ssow_lf_alloc, ssow_lf_alloc_req, msg_rsp)\
166 M(SSOW_LF_FREE, 0x603, ssow_lf_free, ssow_lf_free_req, msg_rsp) \
167 M(SSO_HW_SETCONFIG, 0x604, sso_hw_setconfig, sso_hw_setconfig, \
169 M(SSO_GRP_SET_PRIORITY, 0x605, sso_grp_set_priority, sso_grp_priority, \
171 M(SSO_GRP_GET_PRIORITY, 0x606, sso_grp_get_priority, sso_info_req, \
173 M(SSO_WS_CACHE_INV, 0x607, sso_ws_cache_inv, msg_req, msg_rsp) \
174 M(SSO_GRP_QOS_CONFIG, 0x608, sso_grp_qos_config, sso_grp_qos_cfg, \
176 M(SSO_GRP_GET_STATS, 0x609, sso_grp_get_stats, sso_info_req, \
178 M(SSO_HWS_GET_STATS, 0x610, sso_hws_get_stats, sso_info_req, \
180 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
181 M(TIM_LF_ALLOC, 0x800, tim_lf_alloc, tim_lf_alloc_req, \
183 M(TIM_LF_FREE, 0x801, tim_lf_free, tim_ring_req, msg_rsp) \
184 M(TIM_CONFIG_RING, 0x802, tim_config_ring, tim_config_req, msg_rsp)\
185 M(TIM_ENABLE_RING, 0x803, tim_enable_ring, tim_ring_req, \
187 M(TIM_DISABLE_RING, 0x804, tim_disable_ring, tim_ring_req, msg_rsp) \
188 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
189 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \
190 cpt_lf_alloc_rsp_msg) \
191 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
192 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
194 M(CPT_SET_CRYPTO_GRP, 0xA03, cpt_set_crypto_grp, \
195 cpt_set_crypto_grp_req_msg, \
197 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
198 cpt_inline_ipsec_cfg_msg, msg_rsp) \
199 M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg, \
200 cpt_rx_inline_lf_cfg_msg, msg_rsp) \
201 M(CPT_GET_CAPS, 0xBFD, cpt_caps_get, msg_req, cpt_caps_rsp_msg) \
202 /* REE mbox IDs (range 0xE00 - 0xFFF) */ \
203 M(REE_CONFIG_LF, 0xE01, ree_config_lf, ree_lf_req_msg, \
205 M(REE_RD_WR_REGISTER, 0xE02, ree_rd_wr_register, ree_rd_wr_reg_msg, \
207 M(REE_RULE_DB_PROG, 0xE03, ree_rule_db_prog, \
208 ree_rule_db_prog_req_msg, \
210 M(REE_RULE_DB_LEN_GET, 0xE04, ree_rule_db_len_get, ree_req_msg, \
211 ree_rule_db_len_rsp_msg) \
212 M(REE_RULE_DB_GET, 0xE05, ree_rule_db_get, \
213 ree_rule_db_get_req_msg, \
214 ree_rule_db_get_rsp_msg) \
215 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
216 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, \
217 npc_mcam_alloc_entry_req, \
218 npc_mcam_alloc_entry_rsp) \
219 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
220 npc_mcam_free_entry_req, msg_rsp) \
221 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
222 npc_mcam_write_entry_req, msg_rsp) \
223 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
224 npc_mcam_ena_dis_entry_req, msg_rsp) \
225 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
226 npc_mcam_ena_dis_entry_req, msg_rsp) \
227 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, \
228 npc_mcam_shift_entry_req, \
229 npc_mcam_shift_entry_rsp) \
230 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
231 npc_mcam_alloc_counter_req, \
232 npc_mcam_alloc_counter_rsp) \
233 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
234 npc_mcam_oper_counter_req, \
236 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
237 npc_mcam_unmap_counter_req, \
239 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
240 npc_mcam_oper_counter_req, \
242 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
243 npc_mcam_oper_counter_req, \
244 npc_mcam_oper_counter_rsp) \
245 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry,\
246 npc_mcam_alloc_and_write_entry_req, \
247 npc_mcam_alloc_and_write_entry_rsp) \
248 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, msg_req, \
249 npc_get_kex_cfg_rsp) \
250 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \
251 npc_install_flow_req, \
252 npc_install_flow_rsp) \
253 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \
254 npc_delete_flow_req, msg_rsp) \
255 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
256 npc_mcam_read_entry_req, \
257 npc_mcam_read_entry_rsp) \
258 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \
261 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule, msg_req, \
262 npc_mcam_read_base_rule_rsp) \
263 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
264 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, nix_lf_alloc_req, \
266 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
267 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, \
269 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, hwctx_disable_req, \
271 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, nix_txsch_alloc_req, \
272 nix_txsch_alloc_rsp) \
273 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, \
275 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
277 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
278 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \
279 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
280 nix_rss_flowkey_cfg, \
281 nix_rss_flowkey_cfg_rsp) \
282 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, \
284 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
285 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
286 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
287 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
288 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
289 nix_mark_format_cfg, \
290 nix_mark_format_cfg_rsp) \
291 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
292 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, nix_lso_format_cfg, \
293 nix_lso_format_cfg_rsp) \
294 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, \
296 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, \
298 M(NIX_SET_VLAN_TPID, 0x8015, nix_set_vlan_tpid, nix_set_vlan_tpid, \
300 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
302 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp)\
303 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, \
304 nix_get_mac_addr_rsp) \
305 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \
306 nix_inline_ipsec_cfg, msg_rsp) \
307 M(NIX_INLINE_IPSEC_LF_CFG, \
308 0x801a, nix_inline_ipsec_lf_cfg, \
309 nix_inline_ipsec_lf_cfg, msg_rsp)
311 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
312 #define MBOX_UP_CGX_MESSAGES \
313 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, \
315 M(CGX_PTP_RX_INFO, 0xC01, cgx_ptp_rx_info, cgx_ptp_rx_info_msg, \
319 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
325 /* Mailbox message formats */
327 #define RVU_DEFAULT_PF_FUNC 0xFFFF
329 /* Generic request msg used for those mbox messages which
330 * don't send any data in the request.
333 struct mbox_msghdr hdr;
336 /* Generic response msg used a ack or response for those mbox
337 * messages which doesn't have a specific rsp msg format.
340 struct mbox_msghdr hdr;
343 /* RVU mailbox error codes
347 RVU_INVALID_VF_ID = -256,
350 struct ready_msg_rsp {
351 struct mbox_msghdr hdr;
352 uint16_t __otx2_io sclk_feq; /* SCLK frequency */
353 uint16_t __otx2_io rclk_freq; /* RCLK frequency */
356 enum npc_pkind_type {
357 NPC_RX_CHLEN24B_PKIND = 57ULL,
358 NPC_RX_CPT_HDR_PKIND,
359 NPC_RX_CHLEN90B_PKIND,
366 #define OTX2_PRIV_FLAGS_CH_LEN_90B 254
367 #define OTX2_PRIV_FLAGS_CH_LEN_24B 255
369 /* Struct to set pkind */
370 struct npc_set_pkind {
371 struct mbox_msghdr hdr;
372 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0)
373 #define OTX2_PRIV_FLAGS_EDSA BIT_ULL(1)
374 #define OTX2_PRIV_FLAGS_HIGIG BIT_ULL(2)
375 #define OTX2_PRIV_FLAGS_FDSA BIT_ULL(3)
376 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63)
377 uint64_t __otx2_io mode;
378 #define PKIND_TX BIT_ULL(0)
379 #define PKIND_RX BIT_ULL(1)
380 uint8_t __otx2_io dir;
381 uint8_t __otx2_io pkind; /* valid only in case custom flag */
384 /* Structure for requesting resource provisioning.
385 * 'modify' flag to be used when either requesting more
386 * or to detach partial of a certain resource type.
387 * Rest of the fields specify how many of what type to
389 * To request LFs from two blocks of same type this mailbox
390 * can be sent twice as below:
391 * struct rsrc_attach *attach;
392 * .. Allocate memory for message ..
393 * attach->cptlfs = 3; <3 LFs from CPT0>
395 * .. Allocate memory for message ..
396 * attach->modify = 1;
397 * attach->cpt_blkaddr = BLKADDR_CPT1;
398 * attach->cptlfs = 2; <2 LFs from CPT1>
401 struct rsrc_attach_req {
402 struct mbox_msghdr hdr;
403 uint8_t __otx2_io modify:1;
404 uint8_t __otx2_io npalf:1;
405 uint8_t __otx2_io nixlf:1;
406 uint16_t __otx2_io sso;
407 uint16_t __otx2_io ssow;
408 uint16_t __otx2_io timlfs;
409 uint16_t __otx2_io cptlfs;
410 uint16_t __otx2_io reelfs;
411 /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
412 int __otx2_io cpt_blkaddr;
413 /* BLKADDR_REE0/BLKADDR_REE1 or 0 for BLKADDR_REE0 */
414 int __otx2_io ree_blkaddr;
417 /* Structure for relinquishing resources.
418 * 'partial' flag to be used when relinquishing all resources
419 * but only of a certain type. If not set, all resources of all
420 * types provisioned to the RVU function will be detached.
422 struct rsrc_detach_req {
423 struct mbox_msghdr hdr;
424 uint8_t __otx2_io partial:1;
425 uint8_t __otx2_io npalf:1;
426 uint8_t __otx2_io nixlf:1;
427 uint8_t __otx2_io sso:1;
428 uint8_t __otx2_io ssow:1;
429 uint8_t __otx2_io timlfs:1;
430 uint8_t __otx2_io cptlfs:1;
431 uint8_t __otx2_io reelfs:1;
434 /* NIX Transmit schedulers */
435 #define NIX_TXSCH_LVL_SMQ 0x0
436 #define NIX_TXSCH_LVL_MDQ 0x0
437 #define NIX_TXSCH_LVL_TL4 0x1
438 #define NIX_TXSCH_LVL_TL3 0x2
439 #define NIX_TXSCH_LVL_TL2 0x3
440 #define NIX_TXSCH_LVL_TL1 0x4
441 #define NIX_TXSCH_LVL_CNT 0x5
444 * Number of resources available to the caller.
445 * In reply to MBOX_MSG_FREE_RSRC_CNT.
447 struct free_rsrcs_rsp {
448 struct mbox_msghdr hdr;
449 uint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT];
450 uint16_t __otx2_io sso;
451 uint16_t __otx2_io tim;
452 uint16_t __otx2_io ssow;
453 uint16_t __otx2_io cpt;
454 uint8_t __otx2_io npa;
455 uint8_t __otx2_io nix;
456 uint16_t __otx2_io schq_nix1[NIX_TXSCH_LVL_CNT];
457 uint8_t __otx2_io nix1;
458 uint8_t __otx2_io cpt1;
459 uint8_t __otx2_io ree0;
460 uint8_t __otx2_io ree1;
463 #define MSIX_VECTOR_INVALID 0xFFFF
464 #define MAX_RVU_BLKLF_CNT 256
466 struct msix_offset_rsp {
467 struct mbox_msghdr hdr;
468 uint16_t __otx2_io npa_msixoff;
469 uint16_t __otx2_io nix_msixoff;
470 uint16_t __otx2_io sso;
471 uint16_t __otx2_io ssow;
472 uint16_t __otx2_io timlfs;
473 uint16_t __otx2_io cptlfs;
474 uint16_t __otx2_io sso_msixoff[MAX_RVU_BLKLF_CNT];
475 uint16_t __otx2_io ssow_msixoff[MAX_RVU_BLKLF_CNT];
476 uint16_t __otx2_io timlf_msixoff[MAX_RVU_BLKLF_CNT];
477 uint16_t __otx2_io cptlf_msixoff[MAX_RVU_BLKLF_CNT];
478 uint16_t __otx2_io cpt1_lfs;
479 uint16_t __otx2_io ree0_lfs;
480 uint16_t __otx2_io ree1_lfs;
481 uint16_t __otx2_io cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
482 uint16_t __otx2_io ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
483 uint16_t __otx2_io ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
487 /* CGX mbox message formats */
489 struct cgx_stats_rsp {
490 struct mbox_msghdr hdr;
491 #define CGX_RX_STATS_COUNT 13
492 #define CGX_TX_STATS_COUNT 18
493 uint64_t __otx2_io rx_stats[CGX_RX_STATS_COUNT];
494 uint64_t __otx2_io tx_stats[CGX_TX_STATS_COUNT];
497 struct cgx_fec_stats_rsp {
498 struct mbox_msghdr hdr;
499 uint64_t __otx2_io fec_corr_blks;
500 uint64_t __otx2_io fec_uncorr_blks;
502 /* Structure for requesting the operation for
503 * setting/getting mac address in the CGX interface
505 struct cgx_mac_addr_set_or_get {
506 struct mbox_msghdr hdr;
507 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
510 /* Structure for requesting the operation to
511 * add DMAC filter entry into CGX interface
513 struct cgx_mac_addr_add_req {
514 struct mbox_msghdr hdr;
515 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
518 /* Structure for response against the operation to
519 * add DMAC filter entry into CGX interface
521 struct cgx_mac_addr_add_rsp {
522 struct mbox_msghdr hdr;
523 uint8_t __otx2_io index;
526 /* Structure for requesting the operation to
527 * delete DMAC filter entry from CGX interface
529 struct cgx_mac_addr_del_req {
530 struct mbox_msghdr hdr;
531 uint8_t __otx2_io index;
534 /* Structure for response against the operation to
535 * get maximum supported DMAC filter entries
537 struct cgx_max_dmac_entries_get_rsp {
538 struct mbox_msghdr hdr;
539 uint8_t __otx2_io max_dmac_filters;
542 struct cgx_link_user_info {
543 uint64_t __otx2_io link_up:1;
544 uint64_t __otx2_io full_duplex:1;
545 uint64_t __otx2_io lmac_type_id:4;
546 uint64_t __otx2_io speed:20; /* speed in Mbps */
547 uint64_t __otx2_io an:1; /* AN supported or not */
548 uint64_t __otx2_io fec:2; /* FEC type if enabled else 0 */
549 uint64_t __otx2_io port:8;
550 #define LMACTYPE_STR_LEN 16
551 char lmac_type[LMACTYPE_STR_LEN];
554 struct cgx_link_info_msg {
555 struct mbox_msghdr hdr;
556 struct cgx_link_user_info link_info;
559 struct cgx_ptp_rx_info_msg {
560 struct mbox_msghdr hdr;
561 uint8_t __otx2_io ptp_en;
564 struct cgx_pause_frm_cfg {
565 struct mbox_msghdr hdr;
566 uint8_t __otx2_io set;
567 /* set = 1 if the request is to config pause frames */
568 /* set = 0 if the request is to fetch pause frames config */
569 uint8_t __otx2_io rx_pause;
570 uint8_t __otx2_io tx_pause;
573 struct sfp_eeprom_s {
574 #define SFP_EEPROM_SIZE 256
575 uint16_t __otx2_io sff_id;
576 uint8_t __otx2_io buf[SFP_EEPROM_SIZE];
577 uint64_t __otx2_io reserved;
587 uint64_t __otx2_io can_change_mod_type : 1;
588 uint64_t __otx2_io mod_type : 1;
591 struct cgx_lmac_fwdata_s {
592 uint16_t __otx2_io rw_valid;
593 uint64_t __otx2_io supported_fec;
594 uint64_t __otx2_io supported_an;
595 uint64_t __otx2_io supported_link_modes;
596 /* Only applicable if AN is supported */
597 uint64_t __otx2_io advertised_fec;
598 uint64_t __otx2_io advertised_link_modes;
599 /* Only applicable if SFP/QSFP slot is present */
600 struct sfp_eeprom_s sfp_eeprom;
602 #define LMAC_FWDATA_RESERVED_MEM 1023
603 uint64_t __otx2_io reserved[LMAC_FWDATA_RESERVED_MEM];
607 struct mbox_msghdr hdr;
608 struct cgx_lmac_fwdata_s fwdata;
612 struct mbox_msghdr hdr;
616 struct cgx_set_link_state_msg {
617 struct mbox_msghdr hdr;
618 uint8_t __otx2_io enable;
621 struct cgx_phy_mod_type {
622 struct mbox_msghdr hdr;
626 struct cgx_set_link_mode_args {
627 uint32_t __otx2_io speed;
628 uint8_t __otx2_io duplex;
629 uint8_t __otx2_io an;
630 uint8_t __otx2_io ports;
631 uint64_t __otx2_io mode;
634 struct cgx_set_link_mode_req {
635 struct mbox_msghdr hdr;
636 struct cgx_set_link_mode_args args;
639 struct cgx_set_link_mode_rsp {
640 struct mbox_msghdr hdr;
641 int __otx2_io status;
643 /* NPA mbox message formats */
645 /* NPA mailbox error codes
649 NPA_AF_ERR_PARAM = -301,
650 NPA_AF_ERR_AQ_FULL = -302,
651 NPA_AF_ERR_AQ_ENQUEUE = -303,
652 NPA_AF_ERR_AF_LF_INVALID = -304,
653 NPA_AF_ERR_AF_LF_ALLOC = -305,
654 NPA_AF_ERR_LF_RESET = -306,
657 #define NPA_AURA_SZ_0 0
658 #define NPA_AURA_SZ_128 1
659 #define NPA_AURA_SZ_256 2
660 #define NPA_AURA_SZ_512 3
661 #define NPA_AURA_SZ_1K 4
662 #define NPA_AURA_SZ_2K 5
663 #define NPA_AURA_SZ_4K 6
664 #define NPA_AURA_SZ_8K 7
665 #define NPA_AURA_SZ_16K 8
666 #define NPA_AURA_SZ_32K 9
667 #define NPA_AURA_SZ_64K 10
668 #define NPA_AURA_SZ_128K 11
669 #define NPA_AURA_SZ_256K 12
670 #define NPA_AURA_SZ_512K 13
671 #define NPA_AURA_SZ_1M 14
672 #define NPA_AURA_SZ_MAX 15
674 /* For NPA LF context alloc and init */
675 struct npa_lf_alloc_req {
676 struct mbox_msghdr hdr;
678 int __otx2_io aura_sz; /* No of auras. See NPA_AURA_SZ_* */
679 uint32_t __otx2_io nr_pools; /* No of pools */
680 uint64_t __otx2_io way_mask;
683 struct npa_lf_alloc_rsp {
684 struct mbox_msghdr hdr;
685 uint32_t __otx2_io stack_pg_ptrs; /* No of ptrs per stack page */
686 uint32_t __otx2_io stack_pg_bytes; /* Size of stack page */
687 uint16_t __otx2_io qints; /* NPA_AF_CONST::QINTS */
690 /* NPA AQ enqueue msg */
691 struct npa_aq_enq_req {
692 struct mbox_msghdr hdr;
693 uint32_t __otx2_io aura_id;
694 uint8_t __otx2_io ctype;
695 uint8_t __otx2_io op;
697 /* Valid when op == WRITE/INIT and ctype == AURA.
698 * LF fills the pool_id in aura.pool_addr. AF will translate
699 * the pool_id to pool context pointer.
701 __otx2_io struct npa_aura_s aura;
702 /* Valid when op == WRITE/INIT and ctype == POOL */
703 __otx2_io struct npa_pool_s pool;
705 /* Mask data when op == WRITE (1=write, 0=don't write) */
707 /* Valid when op == WRITE and ctype == AURA */
708 __otx2_io struct npa_aura_s aura_mask;
709 /* Valid when op == WRITE and ctype == POOL */
710 __otx2_io struct npa_pool_s pool_mask;
714 struct npa_aq_enq_rsp {
715 struct mbox_msghdr hdr;
717 /* Valid when op == READ and ctype == AURA */
718 __otx2_io struct npa_aura_s aura;
719 /* Valid when op == READ and ctype == POOL */
720 __otx2_io struct npa_pool_s pool;
724 /* Disable all contexts of type 'ctype' */
725 struct hwctx_disable_req {
726 struct mbox_msghdr hdr;
727 uint8_t __otx2_io ctype;
730 /* NIX mbox message formats */
732 /* NIX mailbox error codes
736 NIX_AF_ERR_PARAM = -401,
737 NIX_AF_ERR_AQ_FULL = -402,
738 NIX_AF_ERR_AQ_ENQUEUE = -403,
739 NIX_AF_ERR_AF_LF_INVALID = -404,
740 NIX_AF_ERR_AF_LF_ALLOC = -405,
741 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
742 NIX_AF_ERR_TLX_INVALID = -407,
743 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
744 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
745 NIX_AF_ERR_FRS_INVALID = -410,
746 NIX_AF_ERR_RX_LINK_INVALID = -411,
747 NIX_AF_INVAL_TXSCHQ_CFG = -412,
748 NIX_AF_SMQ_FLUSH_FAILED = -413,
749 NIX_AF_ERR_LF_RESET = -414,
750 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
751 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
752 NIX_AF_ERR_MARK_CFG_FAIL = -417,
753 NIX_AF_ERR_LSO_CFG_FAIL = -418,
754 NIX_AF_INVAL_NPA_PF_FUNC = -419,
755 NIX_AF_INVAL_SSO_PF_FUNC = -420,
756 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
757 NIX_AF_ERR_RX_VTAG_INUSE = -422,
758 NIX_AF_ERR_PTP_CONFIG_FAIL = -423,
761 /* For NIX LF context alloc and init */
762 struct nix_lf_alloc_req {
763 struct mbox_msghdr hdr;
765 uint32_t __otx2_io rq_cnt; /* No of receive queues */
766 uint32_t __otx2_io sq_cnt; /* No of send queues */
767 uint32_t __otx2_io cq_cnt; /* No of completion queues */
768 uint8_t __otx2_io xqe_sz;
769 uint16_t __otx2_io rss_sz;
770 uint8_t __otx2_io rss_grps;
771 uint16_t __otx2_io npa_func;
772 /* RVU_DEFAULT_PF_FUNC == default pf_func associated with lf */
773 uint16_t __otx2_io sso_func;
774 uint64_t __otx2_io rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
775 uint64_t __otx2_io way_mask;
776 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
780 struct nix_lf_alloc_rsp {
781 struct mbox_msghdr hdr;
782 uint16_t __otx2_io sqb_size;
783 uint16_t __otx2_io rx_chan_base;
784 uint16_t __otx2_io tx_chan_base;
785 uint8_t __otx2_io rx_chan_cnt; /* Total number of RX channels */
786 uint8_t __otx2_io tx_chan_cnt; /* Total number of TX channels */
787 uint8_t __otx2_io lso_tsov4_idx;
788 uint8_t __otx2_io lso_tsov6_idx;
789 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
790 uint8_t __otx2_io lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
791 uint8_t __otx2_io lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
792 uint16_t __otx2_io cints; /* NIX_AF_CONST2::CINTS */
793 uint16_t __otx2_io qints; /* NIX_AF_CONST2::QINTS */
794 uint8_t __otx2_io hw_rx_tstamp_en; /*set if rx timestamping enabled */
795 uint8_t __otx2_io cgx_links; /* No. of CGX links present in HW */
796 uint8_t __otx2_io lbk_links; /* No. of LBK links present in HW */
797 uint8_t __otx2_io sdp_links; /* No. of SDP links present in HW */
798 uint8_t __otx2_io tx_link; /* Transmit channel link number */
801 struct nix_lf_free_req {
802 struct mbox_msghdr hdr;
803 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
804 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
805 uint64_t __otx2_io flags;
808 /* NIX AQ enqueue msg */
809 struct nix_aq_enq_req {
810 struct mbox_msghdr hdr;
811 uint32_t __otx2_io qidx;
812 uint8_t __otx2_io ctype;
813 uint8_t __otx2_io op;
815 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */
816 __otx2_io struct nix_rq_ctx_s rq;
817 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */
818 __otx2_io struct nix_sq_ctx_s sq;
819 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */
820 __otx2_io struct nix_cq_ctx_s cq;
821 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */
822 __otx2_io struct nix_rsse_s rss;
823 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */
824 __otx2_io struct nix_rx_mce_s mce;
826 /* Mask data when op == WRITE (1=write, 0=don't write) */
828 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */
829 __otx2_io struct nix_rq_ctx_s rq_mask;
830 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */
831 __otx2_io struct nix_sq_ctx_s sq_mask;
832 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */
833 __otx2_io struct nix_cq_ctx_s cq_mask;
834 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */
835 __otx2_io struct nix_rsse_s rss_mask;
836 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */
837 __otx2_io struct nix_rx_mce_s mce_mask;
841 struct nix_aq_enq_rsp {
842 struct mbox_msghdr hdr;
844 __otx2_io struct nix_rq_ctx_s rq;
845 __otx2_io struct nix_sq_ctx_s sq;
846 __otx2_io struct nix_cq_ctx_s cq;
847 __otx2_io struct nix_rsse_s rss;
848 __otx2_io struct nix_rx_mce_s mce;
852 /* Tx scheduler/shaper mailbox messages */
854 #define MAX_TXSCHQ_PER_FUNC 128
856 struct nix_txsch_alloc_req {
857 struct mbox_msghdr hdr;
858 /* Scheduler queue count request at each level */
859 uint16_t __otx2_io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
860 uint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
863 struct nix_txsch_alloc_rsp {
864 struct mbox_msghdr hdr;
865 /* Scheduler queue count allocated at each level */
866 uint16_t __otx2_io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
867 uint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
868 /* Scheduler queue list allocated at each level */
870 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
871 uint16_t __otx2_io schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
872 /* Traffic aggregation scheduler level */
873 uint8_t __otx2_io aggr_level;
874 /* Aggregation lvl's RR_PRIO config */
875 uint8_t __otx2_io aggr_lvl_rr_prio;
876 /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
877 uint8_t __otx2_io link_cfg_lvl;
880 struct nix_txsch_free_req {
881 struct mbox_msghdr hdr;
882 #define TXSCHQ_FREE_ALL BIT_ULL(0)
883 uint16_t __otx2_io flags;
884 /* Scheduler queue level to be freed */
885 uint16_t __otx2_io schq_lvl;
886 /* List of scheduler queues to be freed */
887 uint16_t __otx2_io schq;
890 struct nix_txschq_config {
891 struct mbox_msghdr hdr;
892 uint8_t __otx2_io lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
893 uint8_t __otx2_io read;
894 #define TXSCHQ_IDX_SHIFT 16
895 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
896 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
897 uint8_t __otx2_io num_regs;
898 #define MAX_REGS_PER_MBOX_MSG 20
899 uint64_t __otx2_io reg[MAX_REGS_PER_MBOX_MSG];
900 uint64_t __otx2_io regval[MAX_REGS_PER_MBOX_MSG];
901 /* All 0's => overwrite with new value */
902 uint64_t __otx2_io regval_mask[MAX_REGS_PER_MBOX_MSG];
905 struct nix_vtag_config {
906 struct mbox_msghdr hdr;
907 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
908 uint8_t __otx2_io vtag_size;
909 /* cfg_type is '0' for tx vlan cfg
910 * cfg_type is '1' for rx vlan cfg
912 uint8_t __otx2_io cfg_type;
914 /* Valid when cfg_type is '0' */
916 uint64_t __otx2_io vtag0;
917 uint64_t __otx2_io vtag1;
919 /* cfg_vtag0 & cfg_vtag1 fields are valid
920 * when free_vtag0 & free_vtag1 are '0's.
922 /* cfg_vtag0 = 1 to configure vtag0 */
923 uint8_t __otx2_io cfg_vtag0 :1;
924 /* cfg_vtag1 = 1 to configure vtag1 */
925 uint8_t __otx2_io cfg_vtag1 :1;
927 /* vtag0_idx & vtag1_idx are only valid when
928 * both cfg_vtag0 & cfg_vtag1 are '0's,
929 * these fields are used along with free_vtag0
930 * & free_vtag1 to free the nix lf's tx_vlan
933 * Denotes the indices of tx_vtag def registers
934 * that needs to be cleared and freed.
936 int __otx2_io vtag0_idx;
937 int __otx2_io vtag1_idx;
939 /* Free_vtag0 & free_vtag1 fields are valid
940 * when cfg_vtag0 & cfg_vtag1 are '0's.
942 /* Free_vtag0 = 1 clears vtag0 configuration
943 * vtag0_idx denotes the index to be cleared.
945 uint8_t __otx2_io free_vtag0 :1;
946 /* Free_vtag1 = 1 clears vtag1 configuration
947 * vtag1_idx denotes the index to be cleared.
949 uint8_t __otx2_io free_vtag1 :1;
952 /* Valid when cfg_type is '1' */
954 /* Rx vtag type index, valid values are in 0..7 range */
955 uint8_t __otx2_io vtag_type;
957 uint8_t __otx2_io strip_vtag :1;
958 /* Rx vtag capture */
959 uint8_t __otx2_io capture_vtag :1;
964 struct nix_vtag_config_rsp {
965 struct mbox_msghdr hdr;
966 /* Indices of tx_vtag def registers used to configure
967 * tx vtag0 & vtag1 headers, these indices are valid
968 * when nix_vtag_config mbox requested for vtag0 and/
969 * or vtag1 configuration.
971 int __otx2_io vtag0_idx;
972 int __otx2_io vtag1_idx;
975 struct nix_rss_flowkey_cfg {
976 struct mbox_msghdr hdr;
977 int __otx2_io mcam_index; /* MCAM entry index to modify */
978 uint32_t __otx2_io flowkey_cfg; /* Flowkey types selected */
979 #define FLOW_KEY_TYPE_PORT BIT(0)
980 #define FLOW_KEY_TYPE_IPV4 BIT(1)
981 #define FLOW_KEY_TYPE_IPV6 BIT(2)
982 #define FLOW_KEY_TYPE_TCP BIT(3)
983 #define FLOW_KEY_TYPE_UDP BIT(4)
984 #define FLOW_KEY_TYPE_SCTP BIT(5)
985 #define FLOW_KEY_TYPE_NVGRE BIT(6)
986 #define FLOW_KEY_TYPE_VXLAN BIT(7)
987 #define FLOW_KEY_TYPE_GENEVE BIT(8)
988 #define FLOW_KEY_TYPE_ETH_DMAC BIT(9)
989 #define FLOW_KEY_TYPE_IPV6_EXT BIT(10)
990 #define FLOW_KEY_TYPE_GTPU BIT(11)
991 #define FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
992 #define FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
993 #define FLOW_KEY_TYPE_INNR_TCP BIT(14)
994 #define FLOW_KEY_TYPE_INNR_UDP BIT(15)
995 #define FLOW_KEY_TYPE_INNR_SCTP BIT(16)
996 #define FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
997 #define FLOW_KEY_TYPE_CH_LEN_90B BIT(18)
998 #define FLOW_KEY_TYPE_CUSTOM0 BIT(19)
999 #define FLOW_KEY_TYPE_VLAN BIT(20)
1000 #define FLOW_KEY_TYPE_L4_DST BIT(28)
1001 #define FLOW_KEY_TYPE_L4_SRC BIT(29)
1002 #define FLOW_KEY_TYPE_L3_DST BIT(30)
1003 #define FLOW_KEY_TYPE_L3_SRC BIT(31)
1004 uint8_t __otx2_io group; /* RSS context or group */
1007 struct nix_rss_flowkey_cfg_rsp {
1008 struct mbox_msghdr hdr;
1009 uint8_t __otx2_io alg_idx; /* Selected algo index */
1012 struct nix_set_mac_addr {
1013 struct mbox_msghdr hdr;
1014 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
1017 struct nix_get_mac_addr_rsp {
1018 struct mbox_msghdr hdr;
1019 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
1022 struct nix_mark_format_cfg {
1023 struct mbox_msghdr hdr;
1024 uint8_t __otx2_io offset;
1025 uint8_t __otx2_io y_mask;
1026 uint8_t __otx2_io y_val;
1027 uint8_t __otx2_io r_mask;
1028 uint8_t __otx2_io r_val;
1031 struct nix_mark_format_cfg_rsp {
1032 struct mbox_msghdr hdr;
1033 uint8_t __otx2_io mark_format_idx;
1036 struct nix_lso_format_cfg {
1037 struct mbox_msghdr hdr;
1038 uint64_t __otx2_io field_mask;
1039 uint64_t __otx2_io fields[NIX_LSO_FIELD_MAX];
1042 struct nix_lso_format_cfg_rsp {
1043 struct mbox_msghdr hdr;
1044 uint8_t __otx2_io lso_format_idx;
1047 struct nix_rx_mode {
1048 struct mbox_msghdr hdr;
1049 #define NIX_RX_MODE_UCAST BIT(0)
1050 #define NIX_RX_MODE_PROMISC BIT(1)
1051 #define NIX_RX_MODE_ALLMULTI BIT(2)
1052 uint16_t __otx2_io mode;
1056 struct mbox_msghdr hdr;
1057 #define NIX_RX_OL3_VERIFY BIT(0)
1058 #define NIX_RX_OL4_VERIFY BIT(1)
1059 uint8_t __otx2_io len_verify; /* Outer L3/L4 len check */
1060 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
1061 uint8_t __otx2_io csum_verify; /* Outer L4 checksum verification */
1064 struct nix_frs_cfg {
1065 struct mbox_msghdr hdr;
1066 uint8_t __otx2_io update_smq; /* Update SMQ's min/max lens */
1067 uint8_t __otx2_io update_minlen; /* Set minlen also */
1068 uint8_t __otx2_io sdp_link; /* Set SDP RX link */
1069 uint16_t __otx2_io maxlen;
1070 uint16_t __otx2_io minlen;
1073 struct nix_set_vlan_tpid {
1074 struct mbox_msghdr hdr;
1075 #define NIX_VLAN_TYPE_INNER 0
1076 #define NIX_VLAN_TYPE_OUTER 1
1077 uint8_t __otx2_io vlan_type;
1078 uint16_t __otx2_io tpid;
1081 struct nix_bp_cfg_req {
1082 struct mbox_msghdr hdr;
1083 uint16_t __otx2_io chan_base; /* Starting channel number */
1084 uint8_t __otx2_io chan_cnt; /* Number of channels */
1085 uint8_t __otx2_io bpid_per_chan;
1086 /* bpid_per_chan = 0 assigns single bp id for range of channels */
1087 /* bpid_per_chan = 1 assigns separate bp id for each channel */
1090 /* PF can be mapped to either CGX or LBK interface,
1091 * so maximum 64 channels are possible.
1093 #define NIX_MAX_CHAN 64
1094 struct nix_bp_cfg_rsp {
1095 struct mbox_msghdr hdr;
1096 /* Channel and bpid mapping */
1097 uint16_t __otx2_io chan_bpid[NIX_MAX_CHAN];
1098 /* Number of channel for which bpids are assigned */
1099 uint8_t __otx2_io chan_cnt;
1102 /* Global NIX inline IPSec configuration */
1103 struct nix_inline_ipsec_cfg {
1104 struct mbox_msghdr hdr;
1105 uint32_t __otx2_io cpt_credit;
1107 uint8_t __otx2_io egrp;
1108 uint8_t __otx2_io opcode;
1111 uint16_t __otx2_io cpt_pf_func;
1112 uint8_t __otx2_io cpt_slot;
1114 uint8_t __otx2_io enable;
1117 /* Per NIX LF inline IPSec configuration */
1118 struct nix_inline_ipsec_lf_cfg {
1119 struct mbox_msghdr hdr;
1120 uint64_t __otx2_io sa_base_addr;
1122 uint32_t __otx2_io tag_const;
1123 uint16_t __otx2_io lenm1_max;
1124 uint8_t __otx2_io sa_pow2_size;
1125 uint8_t __otx2_io tt;
1128 uint32_t __otx2_io sa_idx_max;
1129 uint8_t __otx2_io sa_idx_w;
1131 uint8_t __otx2_io enable;
1134 /* SSO mailbox error codes
1137 enum sso_af_status {
1138 SSO_AF_ERR_PARAM = -501,
1139 SSO_AF_ERR_LF_INVALID = -502,
1140 SSO_AF_ERR_AF_LF_ALLOC = -503,
1141 SSO_AF_ERR_GRP_EBUSY = -504,
1142 SSO_AF_INVAL_NPA_PF_FUNC = -505,
1145 struct sso_lf_alloc_req {
1146 struct mbox_msghdr hdr;
1148 uint16_t __otx2_io hwgrps;
1151 struct sso_lf_alloc_rsp {
1152 struct mbox_msghdr hdr;
1153 uint32_t __otx2_io xaq_buf_size;
1154 uint32_t __otx2_io xaq_wq_entries;
1155 uint32_t __otx2_io in_unit_entries;
1156 uint16_t __otx2_io hwgrps;
1159 struct sso_lf_free_req {
1160 struct mbox_msghdr hdr;
1162 uint16_t __otx2_io hwgrps;
1165 /* SSOW mailbox error codes
1168 enum ssow_af_status {
1169 SSOW_AF_ERR_PARAM = -601,
1170 SSOW_AF_ERR_LF_INVALID = -602,
1171 SSOW_AF_ERR_AF_LF_ALLOC = -603,
1174 struct ssow_lf_alloc_req {
1175 struct mbox_msghdr hdr;
1177 uint16_t __otx2_io hws;
1180 struct ssow_lf_free_req {
1181 struct mbox_msghdr hdr;
1183 uint16_t __otx2_io hws;
1186 struct sso_hw_setconfig {
1187 struct mbox_msghdr hdr;
1188 uint32_t __otx2_io npa_aura_id;
1189 uint16_t __otx2_io npa_pf_func;
1190 uint16_t __otx2_io hwgrps;
1193 struct sso_info_req {
1194 struct mbox_msghdr hdr;
1196 uint16_t __otx2_io grp;
1197 uint16_t __otx2_io hws;
1201 struct sso_grp_priority {
1202 struct mbox_msghdr hdr;
1203 uint16_t __otx2_io grp;
1204 uint8_t __otx2_io priority;
1205 uint8_t __otx2_io affinity;
1206 uint8_t __otx2_io weight;
1209 struct sso_grp_qos_cfg {
1210 struct mbox_msghdr hdr;
1211 uint16_t __otx2_io grp;
1212 uint32_t __otx2_io xaq_limit;
1213 uint16_t __otx2_io taq_thr;
1214 uint16_t __otx2_io iaq_thr;
1217 struct sso_grp_stats {
1218 struct mbox_msghdr hdr;
1219 uint16_t __otx2_io grp;
1220 uint64_t __otx2_io ws_pc;
1221 uint64_t __otx2_io ext_pc;
1222 uint64_t __otx2_io wa_pc;
1223 uint64_t __otx2_io ts_pc;
1224 uint64_t __otx2_io ds_pc;
1225 uint64_t __otx2_io dq_pc;
1226 uint64_t __otx2_io aw_status;
1227 uint64_t __otx2_io page_cnt;
1230 struct sso_hws_stats {
1231 struct mbox_msghdr hdr;
1232 uint16_t __otx2_io hws;
1233 uint64_t __otx2_io arbitration;
1236 /* CPT mailbox error codes
1239 enum cpt_af_status {
1240 CPT_AF_ERR_PARAM = -901,
1241 CPT_AF_ERR_GRP_INVALID = -902,
1242 CPT_AF_ERR_LF_INVALID = -903,
1243 CPT_AF_ERR_ACCESS_DENIED = -904,
1244 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
1245 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906,
1246 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907,
1247 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908
1250 /* CPT mbox message formats */
1252 struct cpt_rd_wr_reg_msg {
1253 struct mbox_msghdr hdr;
1254 uint64_t __otx2_io reg_offset;
1255 uint64_t __otx2_io *ret_val;
1256 uint64_t __otx2_io val;
1257 uint8_t __otx2_io is_write;
1258 /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
1259 uint8_t __otx2_io blkaddr;
1262 struct cpt_set_crypto_grp_req_msg {
1263 struct mbox_msghdr hdr;
1264 uint8_t __otx2_io crypto_eng_grp;
1267 struct cpt_lf_alloc_req_msg {
1268 struct mbox_msghdr hdr;
1269 uint16_t __otx2_io nix_pf_func;
1270 uint16_t __otx2_io sso_pf_func;
1271 uint16_t __otx2_io eng_grpmask;
1272 /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
1273 uint8_t __otx2_io blkaddr;
1276 struct cpt_lf_alloc_rsp_msg {
1277 struct mbox_msghdr hdr;
1278 uint16_t __otx2_io eng_grpmsk;
1281 #define CPT_INLINE_INBOUND 0
1282 #define CPT_INLINE_OUTBOUND 1
1284 struct cpt_inline_ipsec_cfg_msg {
1285 struct mbox_msghdr hdr;
1286 uint8_t __otx2_io enable;
1287 uint8_t __otx2_io slot;
1288 uint8_t __otx2_io dir;
1289 uint16_t __otx2_io sso_pf_func; /* Inbound path SSO_PF_FUNC */
1290 uint16_t __otx2_io nix_pf_func; /* Outbound path NIX_PF_FUNC */
1293 struct cpt_rx_inline_lf_cfg_msg {
1294 struct mbox_msghdr hdr;
1295 uint16_t __otx2_io sso_pf_func;
1299 CPT_ENG_TYPE_AE = 1,
1300 CPT_ENG_TYPE_SE = 2,
1301 CPT_ENG_TYPE_IE = 3,
1305 /* CPT HW capabilities */
1306 union cpt_eng_caps {
1307 uint64_t __otx2_io u;
1309 uint64_t __otx2_io reserved_0_4:5;
1310 uint64_t __otx2_io mul:1;
1311 uint64_t __otx2_io sha1_sha2:1;
1312 uint64_t __otx2_io chacha20:1;
1313 uint64_t __otx2_io zuc_snow3g:1;
1314 uint64_t __otx2_io sha3:1;
1315 uint64_t __otx2_io aes:1;
1316 uint64_t __otx2_io kasumi:1;
1317 uint64_t __otx2_io des:1;
1318 uint64_t __otx2_io crc:1;
1319 uint64_t __otx2_io reserved_14_63:50;
1323 struct cpt_caps_rsp_msg {
1324 struct mbox_msghdr hdr;
1325 uint16_t __otx2_io cpt_pf_drv_version;
1326 uint8_t __otx2_io cpt_revision;
1327 union cpt_eng_caps eng_caps[CPT_MAX_ENG_TYPES];
1330 /* NPC mbox message structs */
1332 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
1333 #define NPC_MCAM_INVALID_MAP 0xFFFF
1335 /* NPC mailbox error codes
1338 enum npc_af_status {
1339 NPC_MCAM_INVALID_REQ = -701,
1340 NPC_MCAM_ALLOC_DENIED = -702,
1341 NPC_MCAM_ALLOC_FAILED = -703,
1342 NPC_MCAM_PERM_DENIED = -704,
1343 NPC_AF_ERR_HIGIG_CONFIG_FAIL = -705,
1346 struct npc_mcam_alloc_entry_req {
1347 struct mbox_msghdr hdr;
1348 #define NPC_MAX_NONCONTIG_ENTRIES 256
1349 uint8_t __otx2_io contig; /* Contiguous entries ? */
1350 #define NPC_MCAM_ANY_PRIO 0
1351 #define NPC_MCAM_LOWER_PRIO 1
1352 #define NPC_MCAM_HIGHER_PRIO 2
1353 uint8_t __otx2_io priority; /* Lower or higher w.r.t ref_entry */
1354 uint16_t __otx2_io ref_entry;
1355 uint16_t __otx2_io count; /* Number of entries requested */
1358 struct npc_mcam_alloc_entry_rsp {
1359 struct mbox_msghdr hdr;
1360 /* Entry alloc'ed or start index if contiguous.
1361 * Invalid in case of non-contiguous.
1363 uint16_t __otx2_io entry;
1364 uint16_t __otx2_io count; /* Number of entries allocated */
1365 uint16_t __otx2_io free_count; /* Number of entries available */
1366 uint16_t __otx2_io entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1369 struct npc_mcam_free_entry_req {
1370 struct mbox_msghdr hdr;
1371 uint16_t __otx2_io entry; /* Entry index to be freed */
1372 uint8_t __otx2_io all; /* Free all entries alloc'ed to this PFVF */
1376 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max key width */
1377 uint64_t __otx2_io kw[NPC_MAX_KWS_IN_KEY];
1378 uint64_t __otx2_io kw_mask[NPC_MAX_KWS_IN_KEY];
1379 uint64_t __otx2_io action;
1380 uint64_t __otx2_io vtag_action;
1383 struct npc_mcam_write_entry_req {
1384 struct mbox_msghdr hdr;
1385 struct mcam_entry entry_data;
1386 uint16_t __otx2_io entry; /* MCAM entry to write this match key */
1387 uint16_t __otx2_io cntr; /* Counter for this MCAM entry */
1388 uint8_t __otx2_io intf; /* Rx or Tx interface */
1389 uint8_t __otx2_io enable_entry;/* Enable this MCAM entry ? */
1390 uint8_t __otx2_io set_cntr; /* Set counter for this entry ? */
1393 /* Enable/Disable a given entry */
1394 struct npc_mcam_ena_dis_entry_req {
1395 struct mbox_msghdr hdr;
1396 uint16_t __otx2_io entry;
1399 struct npc_mcam_shift_entry_req {
1400 struct mbox_msghdr hdr;
1401 #define NPC_MCAM_MAX_SHIFTS 64
1402 uint16_t __otx2_io curr_entry[NPC_MCAM_MAX_SHIFTS];
1403 uint16_t __otx2_io new_entry[NPC_MCAM_MAX_SHIFTS];
1404 uint16_t __otx2_io shift_count; /* Number of entries to shift */
1407 struct npc_mcam_shift_entry_rsp {
1408 struct mbox_msghdr hdr;
1409 /* Index in 'curr_entry', not entry itself */
1410 uint16_t __otx2_io failed_entry_idx;
1413 struct npc_mcam_alloc_counter_req {
1414 struct mbox_msghdr hdr;
1415 uint8_t __otx2_io contig; /* Contiguous counters ? */
1416 #define NPC_MAX_NONCONTIG_COUNTERS 64
1417 uint16_t __otx2_io count; /* Number of counters requested */
1420 struct npc_mcam_alloc_counter_rsp {
1421 struct mbox_msghdr hdr;
1422 /* Counter alloc'ed or start idx if contiguous.
1423 * Invalid incase of non-contiguous.
1425 uint16_t __otx2_io cntr;
1426 uint16_t __otx2_io count; /* Number of counters allocated */
1427 uint16_t __otx2_io cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1430 struct npc_mcam_oper_counter_req {
1431 struct mbox_msghdr hdr;
1432 uint16_t __otx2_io cntr; /* Free a counter or clear/fetch it's stats */
1435 struct npc_mcam_oper_counter_rsp {
1436 struct mbox_msghdr hdr;
1437 /* valid only while fetching counter's stats */
1438 uint64_t __otx2_io stat;
1441 struct npc_mcam_unmap_counter_req {
1442 struct mbox_msghdr hdr;
1443 uint16_t __otx2_io cntr;
1444 uint16_t __otx2_io entry; /* Entry and counter to be unmapped */
1445 uint8_t __otx2_io all; /* Unmap all entries using this counter ? */
1448 struct npc_mcam_alloc_and_write_entry_req {
1449 struct mbox_msghdr hdr;
1450 struct mcam_entry entry_data;
1451 uint16_t __otx2_io ref_entry;
1452 uint8_t __otx2_io priority; /* Lower or higher w.r.t ref_entry */
1453 uint8_t __otx2_io intf; /* Rx or Tx interface */
1454 uint8_t __otx2_io enable_entry;/* Enable this MCAM entry ? */
1455 uint8_t __otx2_io alloc_cntr; /* Allocate counter and map ? */
1458 struct npc_mcam_alloc_and_write_entry_rsp {
1459 struct mbox_msghdr hdr;
1460 uint16_t __otx2_io entry;
1461 uint16_t __otx2_io cntr;
1464 struct npc_get_kex_cfg_rsp {
1465 struct mbox_msghdr hdr;
1466 uint64_t __otx2_io rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1467 uint64_t __otx2_io tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1468 #define NPC_MAX_INTF 2
1469 #define NPC_MAX_LID 8
1470 #define NPC_MAX_LT 16
1471 #define NPC_MAX_LD 2
1472 #define NPC_MAX_LFL 16
1473 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1474 uint64_t __otx2_io kex_ld_flags[NPC_MAX_LD];
1475 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1477 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
1478 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1480 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1481 #define MKEX_NAME_LEN 128
1482 uint8_t __otx2_io mkex_pfl_name[MKEX_NAME_LEN];
1485 enum header_fields {
1500 NPC_HEADER_FIELDS_MAX,
1504 unsigned char __otx2_io dmac[6];
1505 unsigned char __otx2_io smac[6];
1506 uint16_t __otx2_io etype;
1507 uint16_t __otx2_io vlan_etype;
1508 uint16_t __otx2_io vlan_tci;
1510 uint32_t __otx2_io ip4src;
1511 uint32_t __otx2_io ip6src[4];
1514 uint32_t __otx2_io ip4dst;
1515 uint32_t __otx2_io ip6dst[4];
1517 uint8_t __otx2_io tos;
1518 uint8_t __otx2_io ip_ver;
1519 uint8_t __otx2_io ip_proto;
1520 uint8_t __otx2_io tc;
1521 uint16_t __otx2_io sport;
1522 uint16_t __otx2_io dport;
1525 struct npc_install_flow_req {
1526 struct mbox_msghdr hdr;
1527 struct flow_msg packet;
1528 struct flow_msg mask;
1529 uint64_t __otx2_io features;
1530 uint16_t __otx2_io entry;
1531 uint16_t __otx2_io channel;
1532 uint8_t __otx2_io intf;
1533 uint8_t __otx2_io set_cntr;
1534 uint8_t __otx2_io default_rule;
1535 /* Overwrite(0) or append(1) flow to default rule? */
1536 uint8_t __otx2_io append;
1537 uint16_t __otx2_io vf;
1539 uint32_t __otx2_io index;
1540 uint16_t __otx2_io match_id;
1541 uint8_t __otx2_io flow_key_alg;
1542 uint8_t __otx2_io op;
1544 uint8_t __otx2_io vtag0_type;
1545 uint8_t __otx2_io vtag0_valid;
1546 uint8_t __otx2_io vtag1_type;
1547 uint8_t __otx2_io vtag1_valid;
1549 /* vtag tx action */
1550 uint16_t __otx2_io vtag0_def;
1551 uint8_t __otx2_io vtag0_op;
1552 uint16_t __otx2_io vtag1_def;
1553 uint8_t __otx2_io vtag1_op;
1556 struct npc_install_flow_rsp {
1557 struct mbox_msghdr hdr;
1558 /* Negative if no counter else counter number */
1559 int __otx2_io counter;
1562 struct npc_delete_flow_req {
1563 struct mbox_msghdr hdr;
1564 uint16_t __otx2_io entry;
1565 uint16_t __otx2_io start;/*Disable range of entries */
1566 uint16_t __otx2_io end;
1567 uint8_t __otx2_io all; /* PF + VFs */
1570 struct npc_mcam_read_entry_req {
1571 struct mbox_msghdr hdr;
1572 /* MCAM entry to read */
1573 uint16_t __otx2_io entry;
1576 struct npc_mcam_read_entry_rsp {
1577 struct mbox_msghdr hdr;
1578 struct mcam_entry entry_data;
1579 uint8_t __otx2_io intf;
1580 uint8_t __otx2_io enable;
1583 struct npc_mcam_read_base_rule_rsp {
1584 struct mbox_msghdr hdr;
1585 struct mcam_entry entry_data;
1588 /* TIM mailbox error codes
1591 enum tim_af_status {
1592 TIM_AF_NO_RINGS_LEFT = -801,
1593 TIM_AF_INVALID_NPA_PF_FUNC = -802,
1594 TIM_AF_INVALID_SSO_PF_FUNC = -803,
1595 TIM_AF_RING_STILL_RUNNING = -804,
1596 TIM_AF_LF_INVALID = -805,
1597 TIM_AF_CSIZE_NOT_ALIGNED = -806,
1598 TIM_AF_CSIZE_TOO_SMALL = -807,
1599 TIM_AF_CSIZE_TOO_BIG = -808,
1600 TIM_AF_INTERVAL_TOO_SMALL = -809,
1601 TIM_AF_INVALID_BIG_ENDIAN_VALUE = -810,
1602 TIM_AF_INVALID_CLOCK_SOURCE = -811,
1603 TIM_AF_GPIO_CLK_SRC_NOT_ENABLED = -812,
1604 TIM_AF_INVALID_BSIZE = -813,
1605 TIM_AF_INVALID_ENABLE_PERIODIC = -814,
1606 TIM_AF_INVALID_ENABLE_DONTFREE = -815,
1607 TIM_AF_ENA_DONTFRE_NSET_PERIODIC = -816,
1608 TIM_AF_RING_ALREADY_DISABLED = -817,
1612 TIM_CLK_SRCS_TENNS = 0,
1613 TIM_CLK_SRCS_GPIO = 1,
1614 TIM_CLK_SRCS_GTI = 2,
1615 TIM_CLK_SRCS_PTP = 3,
1616 TIM_CLK_SRSC_INVALID,
1619 enum tim_gpio_edge {
1620 TIM_GPIO_NO_EDGE = 0,
1621 TIM_GPIO_LTOH_TRANS = 1,
1622 TIM_GPIO_HTOL_TRANS = 2,
1623 TIM_GPIO_BOTH_TRANS = 3,
1628 PTP_OP_ADJFINE = 0, /* adjfine(req.scaled_ppm); */
1629 PTP_OP_GET_CLOCK = 1, /* rsp.clk = get_clock() */
1633 struct mbox_msghdr hdr;
1634 uint8_t __otx2_io op;
1635 int64_t __otx2_io scaled_ppm;
1636 uint8_t __otx2_io is_pmu;
1640 struct mbox_msghdr hdr;
1641 uint64_t __otx2_io clk;
1642 uint64_t __otx2_io tsc;
1645 struct get_hw_cap_rsp {
1646 struct mbox_msghdr hdr;
1647 /* Schq mapping fixed or flexible */
1648 uint8_t __otx2_io nix_fixed_txschq_mapping;
1649 uint8_t __otx2_io nix_shaping; /* Is shaping and coloring supported */
1652 struct ndc_sync_op {
1653 struct mbox_msghdr hdr;
1654 uint8_t __otx2_io nix_lf_tx_sync;
1655 uint8_t __otx2_io nix_lf_rx_sync;
1656 uint8_t __otx2_io npa_lf_sync;
1659 struct tim_lf_alloc_req {
1660 struct mbox_msghdr hdr;
1661 uint16_t __otx2_io ring;
1662 uint16_t __otx2_io npa_pf_func;
1663 uint16_t __otx2_io sso_pf_func;
1666 struct tim_ring_req {
1667 struct mbox_msghdr hdr;
1668 uint16_t __otx2_io ring;
1671 struct tim_config_req {
1672 struct mbox_msghdr hdr;
1673 uint16_t __otx2_io ring;
1674 uint8_t __otx2_io bigendian;
1675 uint8_t __otx2_io clocksource;
1676 uint8_t __otx2_io enableperiodic;
1677 uint8_t __otx2_io enabledontfreebuffer;
1678 uint32_t __otx2_io bucketsize;
1679 uint32_t __otx2_io chunksize;
1680 uint32_t __otx2_io interval;
1683 struct tim_lf_alloc_rsp {
1684 struct mbox_msghdr hdr;
1685 uint64_t __otx2_io tenns_clk;
1688 struct tim_enable_rsp {
1689 struct mbox_msghdr hdr;
1690 uint64_t __otx2_io timestarted;
1691 uint32_t __otx2_io currentbucket;
1694 /* REE mailbox error codes
1695 * Range 1001 - 1100.
1697 enum ree_af_status {
1698 REE_AF_ERR_RULE_UNKNOWN_VALUE = -1001,
1699 REE_AF_ERR_LF_NO_MORE_RESOURCES = -1002,
1700 REE_AF_ERR_LF_INVALID = -1003,
1701 REE_AF_ERR_ACCESS_DENIED = -1004,
1702 REE_AF_ERR_RULE_DB_PARTIAL = -1005,
1703 REE_AF_ERR_RULE_DB_EQ_BAD_VALUE = -1006,
1704 REE_AF_ERR_RULE_DB_BLOCK_ALLOC_FAILED = -1007,
1705 REE_AF_ERR_BLOCK_NOT_IMPLEMENTED = -1008,
1706 REE_AF_ERR_RULE_DB_INC_OFFSET_TOO_BIG = -1009,
1707 REE_AF_ERR_RULE_DB_OFFSET_TOO_BIG = -1010,
1708 REE_AF_ERR_Q_IS_GRACEFUL_DIS = -1011,
1709 REE_AF_ERR_Q_NOT_GRACEFUL_DIS = -1012,
1710 REE_AF_ERR_RULE_DB_ALLOC_FAILED = -1013,
1711 REE_AF_ERR_RULE_DB_TOO_BIG = -1014,
1712 REE_AF_ERR_RULE_DB_GEQ_BAD_VALUE = -1015,
1713 REE_AF_ERR_RULE_DB_LEQ_BAD_VALUE = -1016,
1714 REE_AF_ERR_RULE_DB_WRONG_LENGTH = -1017,
1715 REE_AF_ERR_RULE_DB_WRONG_OFFSET = -1018,
1716 REE_AF_ERR_RULE_DB_BLOCK_TOO_BIG = -1019,
1717 REE_AF_ERR_RULE_DB_SHOULD_FILL_REQUEST = -1020,
1718 REE_AF_ERR_RULE_DBI_ALLOC_FAILED = -1021,
1719 REE_AF_ERR_LF_WRONG_PRIORITY = -1022,
1720 REE_AF_ERR_LF_SIZE_TOO_BIG = -1023,
1723 /* REE mbox message formats */
1725 struct ree_req_msg {
1726 struct mbox_msghdr hdr;
1727 uint32_t __otx2_io blkaddr;
1730 struct ree_lf_req_msg {
1731 struct mbox_msghdr hdr;
1732 uint32_t __otx2_io blkaddr;
1733 uint32_t __otx2_io size;
1734 uint8_t __otx2_io lf;
1735 uint8_t __otx2_io pri;
1738 struct ree_rule_db_prog_req_msg {
1739 struct mbox_msghdr hdr;
1740 #define REE_RULE_DB_REQ_BLOCK_SIZE (MBOX_SIZE >> 1)
1741 uint8_t __otx2_io rule_db[REE_RULE_DB_REQ_BLOCK_SIZE];
1742 uint32_t __otx2_io blkaddr; /* REE0 or REE1 */
1743 uint32_t __otx2_io total_len; /* total len of rule db */
1744 uint32_t __otx2_io offset; /* offset of current rule db block */
1745 uint16_t __otx2_io len; /* length of rule db block */
1746 uint8_t __otx2_io is_last; /* is this the last block */
1747 uint8_t __otx2_io is_incremental; /* is incremental flow */
1748 uint8_t __otx2_io is_dbi; /* is rule db incremental */
1751 struct ree_rule_db_get_req_msg {
1752 struct mbox_msghdr hdr;
1753 uint32_t __otx2_io blkaddr;
1754 uint32_t __otx2_io offset; /* retrieve db from this offset */
1755 uint8_t __otx2_io is_dbi; /* is request for rule db incremental */
1758 struct ree_rd_wr_reg_msg {
1759 struct mbox_msghdr hdr;
1760 uint64_t __otx2_io reg_offset;
1761 uint64_t __otx2_io *ret_val;
1762 uint64_t __otx2_io val;
1763 uint32_t __otx2_io blkaddr;
1764 uint8_t __otx2_io is_write;
1767 struct ree_rule_db_len_rsp_msg {
1768 struct mbox_msghdr hdr;
1769 uint32_t __otx2_io blkaddr;
1770 uint32_t __otx2_io len;
1771 uint32_t __otx2_io inc_len;
1774 struct ree_rule_db_get_rsp_msg {
1775 struct mbox_msghdr hdr;
1776 #define REE_RULE_DB_RSP_BLOCK_SIZE (MBOX_DOWN_TX_SIZE - SZ_1K)
1777 uint8_t __otx2_io rule_db[REE_RULE_DB_RSP_BLOCK_SIZE];
1778 uint32_t __otx2_io total_len; /* total len of rule db */
1779 uint32_t __otx2_io offset; /* offset of current rule db block */
1780 uint16_t __otx2_io len; /* length of rule db block */
1781 uint8_t __otx2_io is_last; /* is this the last block */
1785 const char *otx2_mbox_id2name(uint16_t id);
1786 int otx2_mbox_id2size(uint16_t id);
1787 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
1788 int otx2_mbox_init(struct otx2_mbox *mbox, uintptr_t hwbase, uintptr_t reg_base,
1789 int direction, int ndevsi, uint64_t intr_offset);
1790 void otx2_mbox_fini(struct otx2_mbox *mbox);
1792 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
1794 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
1795 int otx2_mbox_wait_for_rsp_tmo(struct otx2_mbox *mbox, int devid, uint32_t tmo);
1797 int otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, void **msg);
1799 int otx2_mbox_get_rsp_tmo(struct otx2_mbox *mbox, int devid, void **msg,
1801 int otx2_mbox_get_availmem(struct otx2_mbox *mbox, int devid);
1803 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
1804 int size, int size_rsp);
1806 static inline struct mbox_msghdr *
1807 otx2_mbox_alloc_msg(struct otx2_mbox *mbox, int devid, int size)
1809 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
1813 otx2_mbox_req_init(uint16_t mbox_id, void *msghdr)
1815 struct mbox_msghdr *hdr = msghdr;
1817 hdr->sig = OTX2_MBOX_REQ_SIG;
1818 hdr->ver = OTX2_MBOX_VERSION;
1824 otx2_mbox_rsp_init(uint16_t mbox_id, void *msghdr)
1826 struct mbox_msghdr *hdr = msghdr;
1828 hdr->sig = OTX2_MBOX_RSP_SIG;
1829 hdr->rc = -ETIMEDOUT;
1834 otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid)
1836 struct otx2_mbox_dev *mdev = &mbox->dev[devid];
1839 rte_spinlock_lock(&mdev->mbox_lock);
1840 ret = mdev->num_msgs != 0;
1841 rte_spinlock_unlock(&mdev->mbox_lock);
1847 otx2_mbox_process(struct otx2_mbox *mbox)
1849 otx2_mbox_msg_send(mbox, 0);
1850 return otx2_mbox_get_rsp(mbox, 0, NULL);
1854 otx2_mbox_process_msg(struct otx2_mbox *mbox, void **msg)
1856 otx2_mbox_msg_send(mbox, 0);
1857 return otx2_mbox_get_rsp(mbox, 0, msg);
1861 otx2_mbox_process_tmo(struct otx2_mbox *mbox, uint32_t tmo)
1863 otx2_mbox_msg_send(mbox, 0);
1864 return otx2_mbox_get_rsp_tmo(mbox, 0, NULL, tmo);
1868 otx2_mbox_process_msg_tmo(struct otx2_mbox *mbox, void **msg, uint32_t tmo)
1870 otx2_mbox_msg_send(mbox, 0);
1871 return otx2_mbox_get_rsp_tmo(mbox, 0, msg, tmo);
1874 int otx2_send_ready_msg(struct otx2_mbox *mbox, uint16_t *pf_func /* out */);
1875 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, uint16_t pf_func,
1878 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
1879 static inline struct _req_type \
1880 *otx2_mbox_alloc_msg_ ## _fn_name(struct otx2_mbox *mbox) \
1882 struct _req_type *req; \
1884 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \
1885 mbox, 0, sizeof(struct _req_type), \
1886 sizeof(struct _rsp_type)); \
1890 req->hdr.sig = OTX2_MBOX_REQ_SIG; \
1891 req->hdr.id = _id; \
1892 otx2_mbox_dbg("id=0x%x (%s)", \
1893 req->hdr.id, otx2_mbox_id2name(req->hdr.id)); \
1900 /* This is required for copy operations from device memory which do not work on
1901 * addresses which are unaligned to 16B. This is because of specific
1902 * optimizations to libc memcpy.
1904 static inline volatile void *
1905 otx2_mbox_memcpy(volatile void *d, const volatile void *s, size_t l)
1907 const volatile uint8_t *sb;
1908 volatile uint8_t *db;
1913 db = (volatile uint8_t *)d;
1914 sb = (const volatile uint8_t *)s;
1915 for (i = 0; i < l; i++)
1920 /* This is required for memory operations from device memory which do not
1921 * work on addresses which are unaligned to 16B. This is because of specific
1922 * optimizations to libc memset.
1925 otx2_mbox_memset(volatile void *d, uint8_t val, size_t l)
1927 volatile uint8_t *db;
1932 db = (volatile uint8_t *)d;
1933 for (i = 0; i < l; i++)
1937 #endif /* __OTX2_MBOX_H__ */