1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef __OTX2_MBOX_H__
6 #define __OTX2_MBOX_H__
11 #include <rte_ether.h>
12 #include <rte_spinlock.h>
14 #include <otx2_common.h>
16 #define SZ_64K (64ULL * 1024ULL)
17 #define SZ_1K (1ULL * 1024ULL)
18 #define MBOX_SIZE SZ_64K
20 /* AF/PF: PF initiated, PF/VF VF initiated */
21 #define MBOX_DOWN_RX_START 0
22 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
23 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
24 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
25 /* AF/PF: AF initiated, PF/VF PF initiated */
26 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
27 #define MBOX_UP_RX_SIZE SZ_1K
28 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
29 #define MBOX_UP_TX_SIZE SZ_1K
31 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
32 # error "Incorrect mailbox area sizes"
35 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
37 #define MBOX_RSP_TIMEOUT 3000 /* Time to wait for mbox response in ms */
39 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
41 /* Mailbox directions */
42 #define MBOX_DIR_AFPF 0 /* AF replies to PF */
43 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */
44 #define MBOX_DIR_PFVF 2 /* PF replies to VF */
45 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */
46 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */
47 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */
48 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */
49 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */
51 /* Device memory does not support unaligned access, instruct compiler to
52 * not optimize the memory access when working with mailbox memory.
54 #define __otx2_io volatile
56 struct otx2_mbox_dev {
57 void *mbase; /* This dev's mbox region */
58 rte_spinlock_t mbox_lock;
59 uint16_t msg_size; /* Total msg size to be sent */
60 uint16_t rsp_size; /* Total rsp size to be sure the reply is ok */
61 uint16_t num_msgs; /* No of msgs sent or waiting for response */
62 uint16_t msgs_acked; /* No of msgs for which response is received */
66 uintptr_t hwbase; /* Mbox region advertised by HW */
67 uintptr_t reg_base;/* CSR base for this dev */
68 uint64_t trigger; /* Trigger mbox notification */
69 uint16_t tr_shift; /* Mbox trigger shift */
70 uint64_t rx_start; /* Offset of Rx region in mbox memory */
71 uint64_t tx_start; /* Offset of Tx region in mbox memory */
72 uint16_t rx_size; /* Size of Rx region */
73 uint16_t tx_size; /* Size of Tx region */
74 uint16_t ndevs; /* The number of peers */
75 struct otx2_mbox_dev *dev;
76 uint64_t intr_offset; /* Offset to interrupt register */
79 /* Header which precedes all mbox messages */
81 uint64_t __otx2_io msg_size; /* Total msgs size embedded */
82 uint16_t __otx2_io num_msgs; /* No of msgs embedded */
85 /* Header which precedes every msg and is also part of it */
87 uint16_t __otx2_io pcifunc; /* Who's sending this msg */
88 uint16_t __otx2_io id; /* Mbox message ID */
89 #define OTX2_MBOX_REQ_SIG (0xdead)
90 #define OTX2_MBOX_RSP_SIG (0xbeef)
91 /* Signature, for validating corrupted msgs */
92 uint16_t __otx2_io sig;
93 #define OTX2_MBOX_VERSION (0x0007)
94 /* Version of msg's structure for this ID */
95 uint16_t __otx2_io ver;
96 /* Offset of next msg within mailbox region */
97 uint16_t __otx2_io next_msgoff;
98 int __otx2_io rc; /* Msg processed response code */
101 /* Mailbox message types */
102 #define MBOX_MSG_MASK 0xFFFF
103 #define MBOX_MSG_INVALID 0xFFFE
104 #define MBOX_MSG_MAX 0xFFFF
106 #define MBOX_MESSAGES \
107 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
108 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
109 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach_req, msg_rsp)\
110 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach_req, msg_rsp)\
111 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
112 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
113 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
114 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
115 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
116 M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \
117 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
118 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
119 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
120 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
121 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get,\
122 cgx_mac_addr_set_or_get) \
123 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get,\
124 cgx_mac_addr_set_or_get) \
125 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
126 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
127 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
128 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
129 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg)\
130 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
131 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
132 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
133 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
134 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
136 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
137 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
138 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
139 cgx_mac_addr_add_rsp) \
140 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
142 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
143 cgx_max_dmac_entries_get_rsp) \
144 M(CGX_SET_LINK_STATE, 0x214, cgx_set_link_state, \
145 cgx_set_link_state_msg, msg_rsp) \
146 M(CGX_GET_PHY_MOD_TYPE, 0x215, cgx_get_phy_mod_type, msg_req, \
148 M(CGX_SET_PHY_MOD_TYPE, 0x216, cgx_set_phy_mod_type, cgx_phy_mod_type, \
150 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
151 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\
152 cgx_set_link_mode_rsp) \
153 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
154 M(CGX_STATS_RST, 0x21A, cgx_stats_rst, msg_req, msg_rsp) \
155 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
156 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, npa_lf_alloc_req, \
158 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
159 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp)\
160 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
161 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
162 M(SSO_LF_ALLOC, 0x600, sso_lf_alloc, sso_lf_alloc_req, \
164 M(SSO_LF_FREE, 0x601, sso_lf_free, sso_lf_free_req, msg_rsp) \
165 M(SSOW_LF_ALLOC, 0x602, ssow_lf_alloc, ssow_lf_alloc_req, msg_rsp)\
166 M(SSOW_LF_FREE, 0x603, ssow_lf_free, ssow_lf_free_req, msg_rsp) \
167 M(SSO_HW_SETCONFIG, 0x604, sso_hw_setconfig, sso_hw_setconfig, \
169 M(SSO_GRP_SET_PRIORITY, 0x605, sso_grp_set_priority, sso_grp_priority, \
171 M(SSO_GRP_GET_PRIORITY, 0x606, sso_grp_get_priority, sso_info_req, \
173 M(SSO_WS_CACHE_INV, 0x607, sso_ws_cache_inv, msg_req, msg_rsp) \
174 M(SSO_GRP_QOS_CONFIG, 0x608, sso_grp_qos_config, sso_grp_qos_cfg, \
176 M(SSO_GRP_GET_STATS, 0x609, sso_grp_get_stats, sso_info_req, \
178 M(SSO_HWS_GET_STATS, 0x610, sso_hws_get_stats, sso_info_req, \
180 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
181 M(TIM_LF_ALLOC, 0x800, tim_lf_alloc, tim_lf_alloc_req, \
183 M(TIM_LF_FREE, 0x801, tim_lf_free, tim_ring_req, msg_rsp) \
184 M(TIM_CONFIG_RING, 0x802, tim_config_ring, tim_config_req, msg_rsp)\
185 M(TIM_ENABLE_RING, 0x803, tim_enable_ring, tim_ring_req, \
187 M(TIM_DISABLE_RING, 0x804, tim_disable_ring, tim_ring_req, msg_rsp) \
188 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
189 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \
190 cpt_lf_alloc_rsp_msg) \
191 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
192 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
194 M(CPT_SET_CRYPTO_GRP, 0xA03, cpt_set_crypto_grp, \
195 cpt_set_crypto_grp_req_msg, \
197 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
198 cpt_inline_ipsec_cfg_msg, msg_rsp) \
199 M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg, \
200 cpt_rx_inline_lf_cfg_msg, msg_rsp) \
201 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
202 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, \
203 npc_mcam_alloc_entry_req, \
204 npc_mcam_alloc_entry_rsp) \
205 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
206 npc_mcam_free_entry_req, msg_rsp) \
207 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
208 npc_mcam_write_entry_req, msg_rsp) \
209 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
210 npc_mcam_ena_dis_entry_req, msg_rsp) \
211 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
212 npc_mcam_ena_dis_entry_req, msg_rsp) \
213 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, \
214 npc_mcam_shift_entry_req, \
215 npc_mcam_shift_entry_rsp) \
216 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
217 npc_mcam_alloc_counter_req, \
218 npc_mcam_alloc_counter_rsp) \
219 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
220 npc_mcam_oper_counter_req, \
222 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
223 npc_mcam_unmap_counter_req, \
225 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
226 npc_mcam_oper_counter_req, \
228 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
229 npc_mcam_oper_counter_req, \
230 npc_mcam_oper_counter_rsp) \
231 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry,\
232 npc_mcam_alloc_and_write_entry_req, \
233 npc_mcam_alloc_and_write_entry_rsp) \
234 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, msg_req, \
235 npc_get_kex_cfg_rsp) \
236 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \
237 npc_install_flow_req, \
238 npc_install_flow_rsp) \
239 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \
240 npc_delete_flow_req, msg_rsp) \
241 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
242 npc_mcam_read_entry_req, \
243 npc_mcam_read_entry_rsp) \
244 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \
247 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
248 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, nix_lf_alloc_req, \
250 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
251 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, \
253 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, hwctx_disable_req, \
255 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, nix_txsch_alloc_req, \
256 nix_txsch_alloc_rsp) \
257 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, \
259 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
261 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
262 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \
263 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
264 nix_rss_flowkey_cfg, \
265 nix_rss_flowkey_cfg_rsp) \
266 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, \
268 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
269 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
270 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
271 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
272 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
273 nix_mark_format_cfg, \
274 nix_mark_format_cfg_rsp) \
275 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
276 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, nix_lso_format_cfg, \
277 nix_lso_format_cfg_rsp) \
278 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, \
280 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, \
282 M(NIX_SET_VLAN_TPID, 0x8015, nix_set_vlan_tpid, nix_set_vlan_tpid, \
284 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
286 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp)\
287 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, \
288 nix_get_mac_addr_rsp) \
289 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \
290 nix_inline_ipsec_cfg, msg_rsp) \
291 M(NIX_INLINE_IPSEC_LF_CFG, \
292 0x801a, nix_inline_ipsec_lf_cfg, \
293 nix_inline_ipsec_lf_cfg, msg_rsp)
295 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
296 #define MBOX_UP_CGX_MESSAGES \
297 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, \
299 M(CGX_PTP_RX_INFO, 0xC01, cgx_ptp_rx_info, cgx_ptp_rx_info_msg, \
303 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
309 /* Mailbox message formats */
311 #define RVU_DEFAULT_PF_FUNC 0xFFFF
313 /* Generic request msg used for those mbox messages which
314 * don't send any data in the request.
317 struct mbox_msghdr hdr;
320 /* Generic response msg used a ack or response for those mbox
321 * messages which doesn't have a specific rsp msg format.
324 struct mbox_msghdr hdr;
327 /* RVU mailbox error codes
331 RVU_INVALID_VF_ID = -256,
334 struct ready_msg_rsp {
335 struct mbox_msghdr hdr;
336 uint16_t __otx2_io sclk_feq; /* SCLK frequency */
337 uint16_t __otx2_io rclk_freq; /* RCLK frequency */
340 /* Struct to set pkind */
341 struct npc_set_pkind {
342 struct mbox_msghdr hdr;
343 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0)
344 #define OTX2_PRIV_FLAGS_EDSA BIT_ULL(1)
345 #define OTX2_PRIV_FLAGS_HIGIG BIT_ULL(2)
346 #define OTX2_PRIV_FLAGS_LEN_90B BIT_ULL(3)
347 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63)
348 uint64_t __otx2_io mode;
349 #define PKIND_TX BIT_ULL(0)
350 #define PKIND_RX BIT_ULL(1)
351 uint8_t __otx2_io dir;
352 uint8_t __otx2_io pkind; /* valid only in case custom flag */
355 /* Structure for requesting resource provisioning.
356 * 'modify' flag to be used when either requesting more
357 * or to detach partial of a certain resource type.
358 * Rest of the fields specify how many of what type to
360 * To request LFs from two blocks of same type this mailbox
361 * can be sent twice as below:
362 * struct rsrc_attach *attach;
363 * .. Allocate memory for message ..
364 * attach->cptlfs = 3; <3 LFs from CPT0>
366 * .. Allocate memory for message ..
367 * attach->modify = 1;
368 * attach->cpt_blkaddr = BLKADDR_CPT1;
369 * attach->cptlfs = 2; <2 LFs from CPT1>
372 struct rsrc_attach_req {
373 struct mbox_msghdr hdr;
374 uint8_t __otx2_io modify:1;
375 uint8_t __otx2_io npalf:1;
376 uint8_t __otx2_io nixlf:1;
377 uint16_t __otx2_io sso;
378 uint16_t __otx2_io ssow;
379 uint16_t __otx2_io timlfs;
380 uint16_t __otx2_io cptlfs;
381 uint16_t __otx2_io reelfs;
382 /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
383 int __otx2_io cpt_blkaddr;
384 /* BLKADDR_REE0/BLKADDR_REE1 or 0 for BLKADDR_REE0 */
385 int __otx2_io ree_blkaddr;
388 /* Structure for relinquishing resources.
389 * 'partial' flag to be used when relinquishing all resources
390 * but only of a certain type. If not set, all resources of all
391 * types provisioned to the RVU function will be detached.
393 struct rsrc_detach_req {
394 struct mbox_msghdr hdr;
395 uint8_t __otx2_io partial:1;
396 uint8_t __otx2_io npalf:1;
397 uint8_t __otx2_io nixlf:1;
398 uint8_t __otx2_io sso:1;
399 uint8_t __otx2_io ssow:1;
400 uint8_t __otx2_io timlfs:1;
401 uint8_t __otx2_io cptlfs:1;
402 uint8_t __otx2_io reelfs:1;
405 /* NIX Transmit schedulers */
406 #define NIX_TXSCH_LVL_SMQ 0x0
407 #define NIX_TXSCH_LVL_MDQ 0x0
408 #define NIX_TXSCH_LVL_TL4 0x1
409 #define NIX_TXSCH_LVL_TL3 0x2
410 #define NIX_TXSCH_LVL_TL2 0x3
411 #define NIX_TXSCH_LVL_TL1 0x4
412 #define NIX_TXSCH_LVL_CNT 0x5
415 * Number of resources available to the caller.
416 * In reply to MBOX_MSG_FREE_RSRC_CNT.
418 struct free_rsrcs_rsp {
419 struct mbox_msghdr hdr;
420 uint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT];
421 uint16_t __otx2_io sso;
422 uint16_t __otx2_io tim;
423 uint16_t __otx2_io ssow;
424 uint16_t __otx2_io cpt;
425 uint8_t __otx2_io npa;
426 uint8_t __otx2_io nix;
427 uint16_t __otx2_io schq_nix1[NIX_TXSCH_LVL_CNT];
428 uint8_t __otx2_io nix1;
429 uint8_t __otx2_io cpt1;
430 uint8_t __otx2_io ree0;
431 uint8_t __otx2_io ree1;
434 #define MSIX_VECTOR_INVALID 0xFFFF
435 #define MAX_RVU_BLKLF_CNT 256
437 struct msix_offset_rsp {
438 struct mbox_msghdr hdr;
439 uint16_t __otx2_io npa_msixoff;
440 uint16_t __otx2_io nix_msixoff;
441 uint8_t __otx2_io sso;
442 uint8_t __otx2_io ssow;
443 uint8_t __otx2_io timlfs;
444 uint8_t __otx2_io cptlfs;
445 uint16_t __otx2_io sso_msixoff[MAX_RVU_BLKLF_CNT];
446 uint16_t __otx2_io ssow_msixoff[MAX_RVU_BLKLF_CNT];
447 uint16_t __otx2_io timlf_msixoff[MAX_RVU_BLKLF_CNT];
448 uint16_t __otx2_io cptlf_msixoff[MAX_RVU_BLKLF_CNT];
449 uint8_t __otx2_io cpt1_lfs;
450 uint8_t __otx2_io ree0_lfs;
451 uint8_t __otx2_io ree1_lfs;
452 uint16_t __otx2_io cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
453 uint16_t __otx2_io ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
454 uint16_t __otx2_io ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
458 /* CGX mbox message formats */
460 struct cgx_stats_rsp {
461 struct mbox_msghdr hdr;
462 #define CGX_RX_STATS_COUNT 13
463 #define CGX_TX_STATS_COUNT 18
464 uint64_t __otx2_io rx_stats[CGX_RX_STATS_COUNT];
465 uint64_t __otx2_io tx_stats[CGX_TX_STATS_COUNT];
468 struct cgx_fec_stats_rsp {
469 struct mbox_msghdr hdr;
470 uint64_t __otx2_io fec_corr_blks;
471 uint64_t __otx2_io fec_uncorr_blks;
473 /* Structure for requesting the operation for
474 * setting/getting mac address in the CGX interface
476 struct cgx_mac_addr_set_or_get {
477 struct mbox_msghdr hdr;
478 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
481 /* Structure for requesting the operation to
482 * add DMAC filter entry into CGX interface
484 struct cgx_mac_addr_add_req {
485 struct mbox_msghdr hdr;
486 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
489 /* Structure for response against the operation to
490 * add DMAC filter entry into CGX interface
492 struct cgx_mac_addr_add_rsp {
493 struct mbox_msghdr hdr;
494 uint8_t __otx2_io index;
497 /* Structure for requesting the operation to
498 * delete DMAC filter entry from CGX interface
500 struct cgx_mac_addr_del_req {
501 struct mbox_msghdr hdr;
502 uint8_t __otx2_io index;
505 /* Structure for response against the operation to
506 * get maximum supported DMAC filter entries
508 struct cgx_max_dmac_entries_get_rsp {
509 struct mbox_msghdr hdr;
510 uint8_t __otx2_io max_dmac_filters;
513 struct cgx_link_user_info {
514 uint64_t __otx2_io link_up:1;
515 uint64_t __otx2_io full_duplex:1;
516 uint64_t __otx2_io lmac_type_id:4;
517 uint64_t __otx2_io speed:20; /* speed in Mbps */
518 uint64_t __otx2_io an:1; /* AN supported or not */
519 uint64_t __otx2_io fec:2; /* FEC type if enabled else 0 */
520 uint64_t __otx2_io port:8;
521 #define LMACTYPE_STR_LEN 16
522 char lmac_type[LMACTYPE_STR_LEN];
525 struct cgx_link_info_msg {
526 struct mbox_msghdr hdr;
527 struct cgx_link_user_info link_info;
530 struct cgx_ptp_rx_info_msg {
531 struct mbox_msghdr hdr;
532 uint8_t __otx2_io ptp_en;
535 struct cgx_pause_frm_cfg {
536 struct mbox_msghdr hdr;
537 uint8_t __otx2_io set;
538 /* set = 1 if the request is to config pause frames */
539 /* set = 0 if the request is to fetch pause frames config */
540 uint8_t __otx2_io rx_pause;
541 uint8_t __otx2_io tx_pause;
544 struct sfp_eeprom_s {
545 #define SFP_EEPROM_SIZE 256
546 uint16_t __otx2_io sff_id;
547 uint8_t __otx2_io buf[SFP_EEPROM_SIZE];
548 uint64_t __otx2_io reserved;
558 uint64_t __otx2_io can_change_mod_type : 1;
559 uint64_t __otx2_io mod_type : 1;
562 struct cgx_lmac_fwdata_s {
563 uint16_t __otx2_io rw_valid;
564 uint64_t __otx2_io supported_fec;
565 uint64_t __otx2_io supported_an;
566 uint64_t __otx2_io supported_link_modes;
567 /* Only applicable if AN is supported */
568 uint64_t __otx2_io advertised_fec;
569 uint64_t __otx2_io advertised_link_modes;
570 /* Only applicable if SFP/QSFP slot is present */
571 struct sfp_eeprom_s sfp_eeprom;
573 #define LMAC_FWDATA_RESERVED_MEM 1023
574 uint64_t __otx2_io reserved[LMAC_FWDATA_RESERVED_MEM];
578 struct mbox_msghdr hdr;
579 struct cgx_lmac_fwdata_s fwdata;
583 struct mbox_msghdr hdr;
587 struct cgx_set_link_state_msg {
588 struct mbox_msghdr hdr;
589 uint8_t __otx2_io enable;
592 struct cgx_phy_mod_type {
593 struct mbox_msghdr hdr;
597 struct cgx_set_link_mode_args {
598 uint32_t __otx2_io speed;
599 uint8_t __otx2_io duplex;
600 uint8_t __otx2_io an;
601 uint8_t __otx2_io ports;
602 uint64_t __otx2_io mode;
605 struct cgx_set_link_mode_req {
606 struct mbox_msghdr hdr;
607 struct cgx_set_link_mode_args args;
610 struct cgx_set_link_mode_rsp {
611 struct mbox_msghdr hdr;
612 int __otx2_io status;
614 /* NPA mbox message formats */
616 /* NPA mailbox error codes
620 NPA_AF_ERR_PARAM = -301,
621 NPA_AF_ERR_AQ_FULL = -302,
622 NPA_AF_ERR_AQ_ENQUEUE = -303,
623 NPA_AF_ERR_AF_LF_INVALID = -304,
624 NPA_AF_ERR_AF_LF_ALLOC = -305,
625 NPA_AF_ERR_LF_RESET = -306,
628 #define NPA_AURA_SZ_0 0
629 #define NPA_AURA_SZ_128 1
630 #define NPA_AURA_SZ_256 2
631 #define NPA_AURA_SZ_512 3
632 #define NPA_AURA_SZ_1K 4
633 #define NPA_AURA_SZ_2K 5
634 #define NPA_AURA_SZ_4K 6
635 #define NPA_AURA_SZ_8K 7
636 #define NPA_AURA_SZ_16K 8
637 #define NPA_AURA_SZ_32K 9
638 #define NPA_AURA_SZ_64K 10
639 #define NPA_AURA_SZ_128K 11
640 #define NPA_AURA_SZ_256K 12
641 #define NPA_AURA_SZ_512K 13
642 #define NPA_AURA_SZ_1M 14
643 #define NPA_AURA_SZ_MAX 15
645 /* For NPA LF context alloc and init */
646 struct npa_lf_alloc_req {
647 struct mbox_msghdr hdr;
649 int __otx2_io aura_sz; /* No of auras. See NPA_AURA_SZ_* */
650 uint32_t __otx2_io nr_pools; /* No of pools */
651 uint64_t __otx2_io way_mask;
654 struct npa_lf_alloc_rsp {
655 struct mbox_msghdr hdr;
656 uint32_t __otx2_io stack_pg_ptrs; /* No of ptrs per stack page */
657 uint32_t __otx2_io stack_pg_bytes; /* Size of stack page */
658 uint16_t __otx2_io qints; /* NPA_AF_CONST::QINTS */
661 /* NPA AQ enqueue msg */
662 struct npa_aq_enq_req {
663 struct mbox_msghdr hdr;
664 uint32_t __otx2_io aura_id;
665 uint8_t __otx2_io ctype;
666 uint8_t __otx2_io op;
668 /* Valid when op == WRITE/INIT and ctype == AURA.
669 * LF fills the pool_id in aura.pool_addr. AF will translate
670 * the pool_id to pool context pointer.
672 __otx2_io struct npa_aura_s aura;
673 /* Valid when op == WRITE/INIT and ctype == POOL */
674 __otx2_io struct npa_pool_s pool;
676 /* Mask data when op == WRITE (1=write, 0=don't write) */
678 /* Valid when op == WRITE and ctype == AURA */
679 __otx2_io struct npa_aura_s aura_mask;
680 /* Valid when op == WRITE and ctype == POOL */
681 __otx2_io struct npa_pool_s pool_mask;
685 struct npa_aq_enq_rsp {
686 struct mbox_msghdr hdr;
688 /* Valid when op == READ and ctype == AURA */
689 __otx2_io struct npa_aura_s aura;
690 /* Valid when op == READ and ctype == POOL */
691 __otx2_io struct npa_pool_s pool;
695 /* Disable all contexts of type 'ctype' */
696 struct hwctx_disable_req {
697 struct mbox_msghdr hdr;
698 uint8_t __otx2_io ctype;
701 /* NIX mbox message formats */
703 /* NIX mailbox error codes
707 NIX_AF_ERR_PARAM = -401,
708 NIX_AF_ERR_AQ_FULL = -402,
709 NIX_AF_ERR_AQ_ENQUEUE = -403,
710 NIX_AF_ERR_AF_LF_INVALID = -404,
711 NIX_AF_ERR_AF_LF_ALLOC = -405,
712 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
713 NIX_AF_ERR_TLX_INVALID = -407,
714 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
715 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
716 NIX_AF_ERR_FRS_INVALID = -410,
717 NIX_AF_ERR_RX_LINK_INVALID = -411,
718 NIX_AF_INVAL_TXSCHQ_CFG = -412,
719 NIX_AF_SMQ_FLUSH_FAILED = -413,
720 NIX_AF_ERR_LF_RESET = -414,
721 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
722 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
723 NIX_AF_ERR_MARK_CFG_FAIL = -417,
724 NIX_AF_ERR_LSO_CFG_FAIL = -418,
725 NIX_AF_INVAL_NPA_PF_FUNC = -419,
726 NIX_AF_INVAL_SSO_PF_FUNC = -420,
727 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
728 NIX_AF_ERR_RX_VTAG_INUSE = -422,
729 NIX_AF_ERR_PTP_CONFIG_FAIL = -423,
732 /* For NIX LF context alloc and init */
733 struct nix_lf_alloc_req {
734 struct mbox_msghdr hdr;
736 uint32_t __otx2_io rq_cnt; /* No of receive queues */
737 uint32_t __otx2_io sq_cnt; /* No of send queues */
738 uint32_t __otx2_io cq_cnt; /* No of completion queues */
739 uint8_t __otx2_io xqe_sz;
740 uint16_t __otx2_io rss_sz;
741 uint8_t __otx2_io rss_grps;
742 uint16_t __otx2_io npa_func;
743 /* RVU_DEFAULT_PF_FUNC == default pf_func associated with lf */
744 uint16_t __otx2_io sso_func;
745 uint64_t __otx2_io rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
746 uint64_t __otx2_io way_mask;
747 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
751 struct nix_lf_alloc_rsp {
752 struct mbox_msghdr hdr;
753 uint16_t __otx2_io sqb_size;
754 uint16_t __otx2_io rx_chan_base;
755 uint16_t __otx2_io tx_chan_base;
756 uint8_t __otx2_io rx_chan_cnt; /* Total number of RX channels */
757 uint8_t __otx2_io tx_chan_cnt; /* Total number of TX channels */
758 uint8_t __otx2_io lso_tsov4_idx;
759 uint8_t __otx2_io lso_tsov6_idx;
760 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
761 uint8_t __otx2_io lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
762 uint8_t __otx2_io lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
763 uint16_t __otx2_io cints; /* NIX_AF_CONST2::CINTS */
764 uint16_t __otx2_io qints; /* NIX_AF_CONST2::QINTS */
765 uint8_t __otx2_io hw_rx_tstamp_en; /*set if rx timestamping enabled */
766 uint8_t __otx2_io cgx_links; /* No. of CGX links present in HW */
767 uint8_t __otx2_io lbk_links; /* No. of LBK links present in HW */
768 uint8_t __otx2_io sdp_links; /* No. of SDP links present in HW */
771 struct nix_lf_free_req {
772 struct mbox_msghdr hdr;
773 #define NIX_LF_DISABLE_FLOWS BIT_ULL(0)
774 #define NIX_LF_DONT_FREE_TX_VTAG BIT_ULL(1)
775 uint64_t __otx2_io flags;
778 /* NIX AQ enqueue msg */
779 struct nix_aq_enq_req {
780 struct mbox_msghdr hdr;
781 uint32_t __otx2_io qidx;
782 uint8_t __otx2_io ctype;
783 uint8_t __otx2_io op;
785 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */
786 __otx2_io struct nix_rq_ctx_s rq;
787 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */
788 __otx2_io struct nix_sq_ctx_s sq;
789 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */
790 __otx2_io struct nix_cq_ctx_s cq;
791 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */
792 __otx2_io struct nix_rsse_s rss;
793 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */
794 __otx2_io struct nix_rx_mce_s mce;
796 /* Mask data when op == WRITE (1=write, 0=don't write) */
798 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */
799 __otx2_io struct nix_rq_ctx_s rq_mask;
800 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */
801 __otx2_io struct nix_sq_ctx_s sq_mask;
802 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */
803 __otx2_io struct nix_cq_ctx_s cq_mask;
804 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */
805 __otx2_io struct nix_rsse_s rss_mask;
806 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */
807 __otx2_io struct nix_rx_mce_s mce_mask;
811 struct nix_aq_enq_rsp {
812 struct mbox_msghdr hdr;
814 __otx2_io struct nix_rq_ctx_s rq;
815 __otx2_io struct nix_sq_ctx_s sq;
816 __otx2_io struct nix_cq_ctx_s cq;
817 __otx2_io struct nix_rsse_s rss;
818 __otx2_io struct nix_rx_mce_s mce;
822 /* Tx scheduler/shaper mailbox messages */
824 #define MAX_TXSCHQ_PER_FUNC 128
826 struct nix_txsch_alloc_req {
827 struct mbox_msghdr hdr;
828 /* Scheduler queue count request at each level */
829 uint16_t __otx2_io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
830 uint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
833 struct nix_txsch_alloc_rsp {
834 struct mbox_msghdr hdr;
835 /* Scheduler queue count allocated at each level */
836 uint16_t __otx2_io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
837 uint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
838 /* Scheduler queue list allocated at each level */
840 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
841 uint16_t __otx2_io schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
842 /* Traffic aggregation scheduler level */
843 uint8_t __otx2_io aggr_level;
844 /* Aggregation lvl's RR_PRIO config */
845 uint8_t __otx2_io aggr_lvl_rr_prio;
846 /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
847 uint8_t __otx2_io link_cfg_lvl;
850 struct nix_txsch_free_req {
851 struct mbox_msghdr hdr;
852 #define TXSCHQ_FREE_ALL BIT_ULL(0)
853 uint16_t __otx2_io flags;
854 /* Scheduler queue level to be freed */
855 uint16_t __otx2_io schq_lvl;
856 /* List of scheduler queues to be freed */
857 uint16_t __otx2_io schq;
860 struct nix_txschq_config {
861 struct mbox_msghdr hdr;
862 uint8_t __otx2_io lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
863 uint8_t __otx2_io read;
864 #define TXSCHQ_IDX_SHIFT 16
865 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
866 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
867 uint8_t __otx2_io num_regs;
868 #define MAX_REGS_PER_MBOX_MSG 20
869 uint64_t __otx2_io reg[MAX_REGS_PER_MBOX_MSG];
870 uint64_t __otx2_io regval[MAX_REGS_PER_MBOX_MSG];
871 /* All 0's => overwrite with new value */
872 uint64_t __otx2_io regval_mask[MAX_REGS_PER_MBOX_MSG];
875 struct nix_vtag_config {
876 struct mbox_msghdr hdr;
877 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
878 uint8_t __otx2_io vtag_size;
879 /* cfg_type is '0' for tx vlan cfg
880 * cfg_type is '1' for rx vlan cfg
882 uint8_t __otx2_io cfg_type;
884 /* Valid when cfg_type is '0' */
886 uint64_t __otx2_io vtag0;
887 uint64_t __otx2_io vtag1;
889 /* cfg_vtag0 & cfg_vtag1 fields are valid
890 * when free_vtag0 & free_vtag1 are '0's.
892 /* cfg_vtag0 = 1 to configure vtag0 */
893 uint8_t __otx2_io cfg_vtag0 :1;
894 /* cfg_vtag1 = 1 to configure vtag1 */
895 uint8_t __otx2_io cfg_vtag1 :1;
897 /* vtag0_idx & vtag1_idx are only valid when
898 * both cfg_vtag0 & cfg_vtag1 are '0's,
899 * these fields are used along with free_vtag0
900 * & free_vtag1 to free the nix lf's tx_vlan
903 * Denotes the indices of tx_vtag def registers
904 * that needs to be cleared and freed.
906 int __otx2_io vtag0_idx;
907 int __otx2_io vtag1_idx;
909 /* Free_vtag0 & free_vtag1 fields are valid
910 * when cfg_vtag0 & cfg_vtag1 are '0's.
912 /* Free_vtag0 = 1 clears vtag0 configuration
913 * vtag0_idx denotes the index to be cleared.
915 uint8_t __otx2_io free_vtag0 :1;
916 /* Free_vtag1 = 1 clears vtag1 configuration
917 * vtag1_idx denotes the index to be cleared.
919 uint8_t __otx2_io free_vtag1 :1;
922 /* Valid when cfg_type is '1' */
924 /* Rx vtag type index, valid values are in 0..7 range */
925 uint8_t __otx2_io vtag_type;
927 uint8_t __otx2_io strip_vtag :1;
928 /* Rx vtag capture */
929 uint8_t __otx2_io capture_vtag :1;
934 struct nix_vtag_config_rsp {
935 struct mbox_msghdr hdr;
936 /* Indices of tx_vtag def registers used to configure
937 * tx vtag0 & vtag1 headers, these indices are valid
938 * when nix_vtag_config mbox requested for vtag0 and/
939 * or vtag1 configuration.
941 int __otx2_io vtag0_idx;
942 int __otx2_io vtag1_idx;
945 struct nix_rss_flowkey_cfg {
946 struct mbox_msghdr hdr;
947 int __otx2_io mcam_index; /* MCAM entry index to modify */
948 uint32_t __otx2_io flowkey_cfg; /* Flowkey types selected */
949 #define FLOW_KEY_TYPE_PORT BIT(0)
950 #define FLOW_KEY_TYPE_IPV4 BIT(1)
951 #define FLOW_KEY_TYPE_IPV6 BIT(2)
952 #define FLOW_KEY_TYPE_TCP BIT(3)
953 #define FLOW_KEY_TYPE_UDP BIT(4)
954 #define FLOW_KEY_TYPE_SCTP BIT(5)
955 #define FLOW_KEY_TYPE_NVGRE BIT(6)
956 #define FLOW_KEY_TYPE_VXLAN BIT(7)
957 #define FLOW_KEY_TYPE_GENEVE BIT(8)
958 #define FLOW_KEY_TYPE_ETH_DMAC BIT(9)
959 #define FLOW_KEY_TYPE_IPV6_EXT BIT(10)
960 #define FLOW_KEY_TYPE_GTPU BIT(11)
961 #define FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
962 #define FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
963 #define FLOW_KEY_TYPE_INNR_TCP BIT(14)
964 #define FLOW_KEY_TYPE_INNR_UDP BIT(15)
965 #define FLOW_KEY_TYPE_INNR_SCTP BIT(16)
966 #define FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
967 #define FLOW_KEY_TYPE_CH_LEN_90B BIT(18)
968 #define FLOW_KEY_TYPE_L4_DST BIT(28)
969 #define FLOW_KEY_TYPE_L4_SRC BIT(29)
970 #define FLOW_KEY_TYPE_L3_DST BIT(30)
971 #define FLOW_KEY_TYPE_L3_SRC BIT(31)
972 uint8_t __otx2_io group; /* RSS context or group */
975 struct nix_rss_flowkey_cfg_rsp {
976 struct mbox_msghdr hdr;
977 uint8_t __otx2_io alg_idx; /* Selected algo index */
980 struct nix_set_mac_addr {
981 struct mbox_msghdr hdr;
982 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
985 struct nix_get_mac_addr_rsp {
986 struct mbox_msghdr hdr;
987 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
990 struct nix_mark_format_cfg {
991 struct mbox_msghdr hdr;
992 uint8_t __otx2_io offset;
993 uint8_t __otx2_io y_mask;
994 uint8_t __otx2_io y_val;
995 uint8_t __otx2_io r_mask;
996 uint8_t __otx2_io r_val;
999 struct nix_mark_format_cfg_rsp {
1000 struct mbox_msghdr hdr;
1001 uint8_t __otx2_io mark_format_idx;
1004 struct nix_lso_format_cfg {
1005 struct mbox_msghdr hdr;
1006 uint64_t __otx2_io field_mask;
1007 uint64_t __otx2_io fields[NIX_LSO_FIELD_MAX];
1010 struct nix_lso_format_cfg_rsp {
1011 struct mbox_msghdr hdr;
1012 uint8_t __otx2_io lso_format_idx;
1015 struct nix_rx_mode {
1016 struct mbox_msghdr hdr;
1017 #define NIX_RX_MODE_UCAST BIT(0)
1018 #define NIX_RX_MODE_PROMISC BIT(1)
1019 #define NIX_RX_MODE_ALLMULTI BIT(2)
1020 uint16_t __otx2_io mode;
1024 struct mbox_msghdr hdr;
1025 #define NIX_RX_OL3_VERIFY BIT(0)
1026 #define NIX_RX_OL4_VERIFY BIT(1)
1027 uint8_t __otx2_io len_verify; /* Outer L3/L4 len check */
1028 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
1029 uint8_t __otx2_io csum_verify; /* Outer L4 checksum verification */
1032 struct nix_frs_cfg {
1033 struct mbox_msghdr hdr;
1034 uint8_t __otx2_io update_smq; /* Update SMQ's min/max lens */
1035 uint8_t __otx2_io update_minlen; /* Set minlen also */
1036 uint8_t __otx2_io sdp_link; /* Set SDP RX link */
1037 uint16_t __otx2_io maxlen;
1038 uint16_t __otx2_io minlen;
1041 struct nix_set_vlan_tpid {
1042 struct mbox_msghdr hdr;
1043 #define NIX_VLAN_TYPE_INNER 0
1044 #define NIX_VLAN_TYPE_OUTER 1
1045 uint8_t __otx2_io vlan_type;
1046 uint16_t __otx2_io tpid;
1049 struct nix_bp_cfg_req {
1050 struct mbox_msghdr hdr;
1051 uint16_t __otx2_io chan_base; /* Starting channel number */
1052 uint8_t __otx2_io chan_cnt; /* Number of channels */
1053 uint8_t __otx2_io bpid_per_chan;
1054 /* bpid_per_chan = 0 assigns single bp id for range of channels */
1055 /* bpid_per_chan = 1 assigns separate bp id for each channel */
1058 /* PF can be mapped to either CGX or LBK interface,
1059 * so maximum 64 channels are possible.
1061 #define NIX_MAX_CHAN 64
1062 struct nix_bp_cfg_rsp {
1063 struct mbox_msghdr hdr;
1064 /* Channel and bpid mapping */
1065 uint16_t __otx2_io chan_bpid[NIX_MAX_CHAN];
1066 /* Number of channel for which bpids are assigned */
1067 uint8_t __otx2_io chan_cnt;
1070 /* Global NIX inline IPSec configuration */
1071 struct nix_inline_ipsec_cfg {
1072 struct mbox_msghdr hdr;
1073 uint32_t __otx2_io cpt_credit;
1075 uint8_t __otx2_io egrp;
1076 uint8_t __otx2_io opcode;
1079 uint16_t __otx2_io cpt_pf_func;
1080 uint8_t __otx2_io cpt_slot;
1082 uint8_t __otx2_io enable;
1085 /* Per NIX LF inline IPSec configuration */
1086 struct nix_inline_ipsec_lf_cfg {
1087 struct mbox_msghdr hdr;
1088 uint64_t __otx2_io sa_base_addr;
1090 uint32_t __otx2_io tag_const;
1091 uint16_t __otx2_io lenm1_max;
1092 uint8_t __otx2_io sa_pow2_size;
1093 uint8_t __otx2_io tt;
1096 uint32_t __otx2_io sa_idx_max;
1097 uint8_t __otx2_io sa_idx_w;
1099 uint8_t __otx2_io enable;
1102 /* SSO mailbox error codes
1105 enum sso_af_status {
1106 SSO_AF_ERR_PARAM = -501,
1107 SSO_AF_ERR_LF_INVALID = -502,
1108 SSO_AF_ERR_AF_LF_ALLOC = -503,
1109 SSO_AF_ERR_GRP_EBUSY = -504,
1110 SSO_AF_INVAL_NPA_PF_FUNC = -505,
1113 struct sso_lf_alloc_req {
1114 struct mbox_msghdr hdr;
1116 uint16_t __otx2_io hwgrps;
1119 struct sso_lf_alloc_rsp {
1120 struct mbox_msghdr hdr;
1121 uint32_t __otx2_io xaq_buf_size;
1122 uint32_t __otx2_io xaq_wq_entries;
1123 uint32_t __otx2_io in_unit_entries;
1124 uint16_t __otx2_io hwgrps;
1127 struct sso_lf_free_req {
1128 struct mbox_msghdr hdr;
1130 uint16_t __otx2_io hwgrps;
1133 /* SSOW mailbox error codes
1136 enum ssow_af_status {
1137 SSOW_AF_ERR_PARAM = -601,
1138 SSOW_AF_ERR_LF_INVALID = -602,
1139 SSOW_AF_ERR_AF_LF_ALLOC = -603,
1142 struct ssow_lf_alloc_req {
1143 struct mbox_msghdr hdr;
1145 uint16_t __otx2_io hws;
1148 struct ssow_lf_free_req {
1149 struct mbox_msghdr hdr;
1151 uint16_t __otx2_io hws;
1154 struct sso_hw_setconfig {
1155 struct mbox_msghdr hdr;
1156 uint32_t __otx2_io npa_aura_id;
1157 uint16_t __otx2_io npa_pf_func;
1158 uint16_t __otx2_io hwgrps;
1161 struct sso_info_req {
1162 struct mbox_msghdr hdr;
1164 uint16_t __otx2_io grp;
1165 uint16_t __otx2_io hws;
1169 struct sso_grp_priority {
1170 struct mbox_msghdr hdr;
1171 uint16_t __otx2_io grp;
1172 uint8_t __otx2_io priority;
1173 uint8_t __otx2_io affinity;
1174 uint8_t __otx2_io weight;
1177 struct sso_grp_qos_cfg {
1178 struct mbox_msghdr hdr;
1179 uint16_t __otx2_io grp;
1180 uint32_t __otx2_io xaq_limit;
1181 uint16_t __otx2_io taq_thr;
1182 uint16_t __otx2_io iaq_thr;
1185 struct sso_grp_stats {
1186 struct mbox_msghdr hdr;
1187 uint16_t __otx2_io grp;
1188 uint64_t __otx2_io ws_pc;
1189 uint64_t __otx2_io ext_pc;
1190 uint64_t __otx2_io wa_pc;
1191 uint64_t __otx2_io ts_pc;
1192 uint64_t __otx2_io ds_pc;
1193 uint64_t __otx2_io dq_pc;
1194 uint64_t __otx2_io aw_status;
1195 uint64_t __otx2_io page_cnt;
1198 struct sso_hws_stats {
1199 struct mbox_msghdr hdr;
1200 uint16_t __otx2_io hws;
1201 uint64_t __otx2_io arbitration;
1204 /* CPT mailbox error codes
1207 enum cpt_af_status {
1208 CPT_AF_ERR_PARAM = -901,
1209 CPT_AF_ERR_GRP_INVALID = -902,
1210 CPT_AF_ERR_LF_INVALID = -903,
1211 CPT_AF_ERR_ACCESS_DENIED = -904,
1212 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
1213 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906,
1214 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907,
1215 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908
1218 /* CPT mbox message formats */
1220 struct cpt_rd_wr_reg_msg {
1221 struct mbox_msghdr hdr;
1222 uint64_t __otx2_io reg_offset;
1223 uint64_t __otx2_io *ret_val;
1224 uint64_t __otx2_io val;
1225 uint8_t __otx2_io is_write;
1228 struct cpt_set_crypto_grp_req_msg {
1229 struct mbox_msghdr hdr;
1230 uint8_t __otx2_io crypto_eng_grp;
1233 struct cpt_lf_alloc_req_msg {
1234 struct mbox_msghdr hdr;
1235 uint16_t __otx2_io nix_pf_func;
1236 uint16_t __otx2_io sso_pf_func;
1239 struct cpt_lf_alloc_rsp_msg {
1240 struct mbox_msghdr hdr;
1241 uint8_t __otx2_io crypto_eng_grp;
1244 #define CPT_INLINE_INBOUND 0
1245 #define CPT_INLINE_OUTBOUND 1
1247 struct cpt_inline_ipsec_cfg_msg {
1248 struct mbox_msghdr hdr;
1249 uint8_t __otx2_io enable;
1250 uint8_t __otx2_io slot;
1251 uint8_t __otx2_io dir;
1252 uint16_t __otx2_io sso_pf_func; /* Inbound path SSO_PF_FUNC */
1253 uint16_t __otx2_io nix_pf_func; /* Outbound path NIX_PF_FUNC */
1256 struct cpt_rx_inline_lf_cfg_msg {
1257 struct mbox_msghdr hdr;
1258 uint16_t __otx2_io sso_pf_func;
1261 /* NPC mbox message structs */
1263 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
1264 #define NPC_MCAM_INVALID_MAP 0xFFFF
1266 /* NPC mailbox error codes
1269 enum npc_af_status {
1270 NPC_MCAM_INVALID_REQ = -701,
1271 NPC_MCAM_ALLOC_DENIED = -702,
1272 NPC_MCAM_ALLOC_FAILED = -703,
1273 NPC_MCAM_PERM_DENIED = -704,
1274 NPC_AF_ERR_HIGIG_CONFIG_FAIL = -705,
1277 struct npc_mcam_alloc_entry_req {
1278 struct mbox_msghdr hdr;
1279 #define NPC_MAX_NONCONTIG_ENTRIES 256
1280 uint8_t __otx2_io contig; /* Contiguous entries ? */
1281 #define NPC_MCAM_ANY_PRIO 0
1282 #define NPC_MCAM_LOWER_PRIO 1
1283 #define NPC_MCAM_HIGHER_PRIO 2
1284 uint8_t __otx2_io priority; /* Lower or higher w.r.t ref_entry */
1285 uint16_t __otx2_io ref_entry;
1286 uint16_t __otx2_io count; /* Number of entries requested */
1289 struct npc_mcam_alloc_entry_rsp {
1290 struct mbox_msghdr hdr;
1291 /* Entry alloc'ed or start index if contiguous.
1292 * Invalid in case of non-contiguous.
1294 uint16_t __otx2_io entry;
1295 uint16_t __otx2_io count; /* Number of entries allocated */
1296 uint16_t __otx2_io free_count; /* Number of entries available */
1297 uint16_t __otx2_io entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1300 struct npc_mcam_free_entry_req {
1301 struct mbox_msghdr hdr;
1302 uint16_t __otx2_io entry; /* Entry index to be freed */
1303 uint8_t __otx2_io all; /* Free all entries alloc'ed to this PFVF */
1307 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max key width */
1308 uint64_t __otx2_io kw[NPC_MAX_KWS_IN_KEY];
1309 uint64_t __otx2_io kw_mask[NPC_MAX_KWS_IN_KEY];
1310 uint64_t __otx2_io action;
1311 uint64_t __otx2_io vtag_action;
1314 struct npc_mcam_write_entry_req {
1315 struct mbox_msghdr hdr;
1316 struct mcam_entry entry_data;
1317 uint16_t __otx2_io entry; /* MCAM entry to write this match key */
1318 uint16_t __otx2_io cntr; /* Counter for this MCAM entry */
1319 uint8_t __otx2_io intf; /* Rx or Tx interface */
1320 uint8_t __otx2_io enable_entry;/* Enable this MCAM entry ? */
1321 uint8_t __otx2_io set_cntr; /* Set counter for this entry ? */
1324 /* Enable/Disable a given entry */
1325 struct npc_mcam_ena_dis_entry_req {
1326 struct mbox_msghdr hdr;
1327 uint16_t __otx2_io entry;
1330 struct npc_mcam_shift_entry_req {
1331 struct mbox_msghdr hdr;
1332 #define NPC_MCAM_MAX_SHIFTS 64
1333 uint16_t __otx2_io curr_entry[NPC_MCAM_MAX_SHIFTS];
1334 uint16_t __otx2_io new_entry[NPC_MCAM_MAX_SHIFTS];
1335 uint16_t __otx2_io shift_count; /* Number of entries to shift */
1338 struct npc_mcam_shift_entry_rsp {
1339 struct mbox_msghdr hdr;
1340 /* Index in 'curr_entry', not entry itself */
1341 uint16_t __otx2_io failed_entry_idx;
1344 struct npc_mcam_alloc_counter_req {
1345 struct mbox_msghdr hdr;
1346 uint8_t __otx2_io contig; /* Contiguous counters ? */
1347 #define NPC_MAX_NONCONTIG_COUNTERS 64
1348 uint16_t __otx2_io count; /* Number of counters requested */
1351 struct npc_mcam_alloc_counter_rsp {
1352 struct mbox_msghdr hdr;
1353 /* Counter alloc'ed or start idx if contiguous.
1354 * Invalid incase of non-contiguous.
1356 uint16_t __otx2_io cntr;
1357 uint16_t __otx2_io count; /* Number of counters allocated */
1358 uint16_t __otx2_io cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1361 struct npc_mcam_oper_counter_req {
1362 struct mbox_msghdr hdr;
1363 uint16_t __otx2_io cntr; /* Free a counter or clear/fetch it's stats */
1366 struct npc_mcam_oper_counter_rsp {
1367 struct mbox_msghdr hdr;
1368 /* valid only while fetching counter's stats */
1369 uint64_t __otx2_io stat;
1372 struct npc_mcam_unmap_counter_req {
1373 struct mbox_msghdr hdr;
1374 uint16_t __otx2_io cntr;
1375 uint16_t __otx2_io entry; /* Entry and counter to be unmapped */
1376 uint8_t __otx2_io all; /* Unmap all entries using this counter ? */
1379 struct npc_mcam_alloc_and_write_entry_req {
1380 struct mbox_msghdr hdr;
1381 struct mcam_entry entry_data;
1382 uint16_t __otx2_io ref_entry;
1383 uint8_t __otx2_io priority; /* Lower or higher w.r.t ref_entry */
1384 uint8_t __otx2_io intf; /* Rx or Tx interface */
1385 uint8_t __otx2_io enable_entry;/* Enable this MCAM entry ? */
1386 uint8_t __otx2_io alloc_cntr; /* Allocate counter and map ? */
1389 struct npc_mcam_alloc_and_write_entry_rsp {
1390 struct mbox_msghdr hdr;
1391 uint16_t __otx2_io entry;
1392 uint16_t __otx2_io cntr;
1395 struct npc_get_kex_cfg_rsp {
1396 struct mbox_msghdr hdr;
1397 uint64_t __otx2_io rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1398 uint64_t __otx2_io tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1399 #define NPC_MAX_INTF 2
1400 #define NPC_MAX_LID 8
1401 #define NPC_MAX_LT 16
1402 #define NPC_MAX_LD 2
1403 #define NPC_MAX_LFL 16
1404 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1405 uint64_t __otx2_io kex_ld_flags[NPC_MAX_LD];
1406 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1408 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
1409 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1411 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1412 #define MKEX_NAME_LEN 128
1413 uint8_t __otx2_io mkex_pfl_name[MKEX_NAME_LEN];
1416 enum header_fields {
1431 NPC_HEADER_FIELDS_MAX,
1435 unsigned char __otx2_io dmac[6];
1436 unsigned char __otx2_io smac[6];
1437 uint16_t __otx2_io etype;
1438 uint16_t __otx2_io vlan_etype;
1439 uint16_t __otx2_io vlan_tci;
1441 uint32_t __otx2_io ip4src;
1442 uint32_t __otx2_io ip6src[4];
1445 uint32_t __otx2_io ip4dst;
1446 uint32_t __otx2_io ip6dst[4];
1448 uint8_t __otx2_io tos;
1449 uint8_t __otx2_io ip_ver;
1450 uint8_t __otx2_io ip_proto;
1451 uint8_t __otx2_io tc;
1452 uint16_t __otx2_io sport;
1453 uint16_t __otx2_io dport;
1456 struct npc_install_flow_req {
1457 struct mbox_msghdr hdr;
1458 struct flow_msg packet;
1459 struct flow_msg mask;
1460 uint64_t __otx2_io features;
1461 uint16_t __otx2_io entry;
1462 uint16_t __otx2_io channel;
1463 uint8_t __otx2_io intf;
1464 uint8_t __otx2_io set_cntr;
1465 uint8_t __otx2_io default_rule;
1466 /* Overwrite(0) or append(1) flow to default rule? */
1467 uint8_t __otx2_io append;
1468 uint16_t __otx2_io vf;
1470 uint32_t __otx2_io index;
1471 uint16_t __otx2_io match_id;
1472 uint8_t __otx2_io flow_key_alg;
1473 uint8_t __otx2_io op;
1475 uint8_t __otx2_io vtag0_type;
1476 uint8_t __otx2_io vtag0_valid;
1477 uint8_t __otx2_io vtag1_type;
1478 uint8_t __otx2_io vtag1_valid;
1480 /* vtag tx action */
1481 uint16_t __otx2_io vtag0_def;
1482 uint8_t __otx2_io vtag0_op;
1483 uint16_t __otx2_io vtag1_def;
1484 uint8_t __otx2_io vtag1_op;
1487 struct npc_install_flow_rsp {
1488 struct mbox_msghdr hdr;
1489 /* Negative if no counter else counter number */
1490 int __otx2_io counter;
1493 struct npc_delete_flow_req {
1494 struct mbox_msghdr hdr;
1495 uint16_t __otx2_io entry;
1496 uint16_t __otx2_io start;/*Disable range of entries */
1497 uint16_t __otx2_io end;
1498 uint8_t __otx2_io all; /* PF + VFs */
1501 struct npc_mcam_read_entry_req {
1502 struct mbox_msghdr hdr;
1503 /* MCAM entry to read */
1504 uint16_t __otx2_io entry;
1507 struct npc_mcam_read_entry_rsp {
1508 struct mbox_msghdr hdr;
1509 struct mcam_entry entry_data;
1510 uint8_t __otx2_io intf;
1511 uint8_t __otx2_io enable;
1514 /* TIM mailbox error codes
1517 enum tim_af_status {
1518 TIM_AF_NO_RINGS_LEFT = -801,
1519 TIM_AF_INVALID_NPA_PF_FUNC = -802,
1520 TIM_AF_INVALID_SSO_PF_FUNC = -803,
1521 TIM_AF_RING_STILL_RUNNING = -804,
1522 TIM_AF_LF_INVALID = -805,
1523 TIM_AF_CSIZE_NOT_ALIGNED = -806,
1524 TIM_AF_CSIZE_TOO_SMALL = -807,
1525 TIM_AF_CSIZE_TOO_BIG = -808,
1526 TIM_AF_INTERVAL_TOO_SMALL = -809,
1527 TIM_AF_INVALID_BIG_ENDIAN_VALUE = -810,
1528 TIM_AF_INVALID_CLOCK_SOURCE = -811,
1529 TIM_AF_GPIO_CLK_SRC_NOT_ENABLED = -812,
1530 TIM_AF_INVALID_BSIZE = -813,
1531 TIM_AF_INVALID_ENABLE_PERIODIC = -814,
1532 TIM_AF_INVALID_ENABLE_DONTFREE = -815,
1533 TIM_AF_ENA_DONTFRE_NSET_PERIODIC = -816,
1534 TIM_AF_RING_ALREADY_DISABLED = -817,
1538 TIM_CLK_SRCS_TENNS = 0,
1539 TIM_CLK_SRCS_GPIO = 1,
1540 TIM_CLK_SRCS_GTI = 2,
1541 TIM_CLK_SRCS_PTP = 3,
1542 TIM_CLK_SRSC_INVALID,
1545 enum tim_gpio_edge {
1546 TIM_GPIO_NO_EDGE = 0,
1547 TIM_GPIO_LTOH_TRANS = 1,
1548 TIM_GPIO_HTOL_TRANS = 2,
1549 TIM_GPIO_BOTH_TRANS = 3,
1554 PTP_OP_ADJFINE = 0, /* adjfine(req.scaled_ppm); */
1555 PTP_OP_GET_CLOCK = 1, /* rsp.clk = get_clock() */
1559 struct mbox_msghdr hdr;
1560 uint8_t __otx2_io op;
1561 int64_t __otx2_io scaled_ppm;
1562 uint8_t __otx2_io is_pmu;
1566 struct mbox_msghdr hdr;
1567 uint64_t __otx2_io clk;
1568 uint64_t __otx2_io tsc;
1571 struct get_hw_cap_rsp {
1572 struct mbox_msghdr hdr;
1573 /* Schq mapping fixed or flexible */
1574 uint8_t __otx2_io nix_fixed_txschq_mapping;
1575 uint8_t __otx2_io nix_shaping; /* Is shaping and coloring supported */
1578 struct ndc_sync_op {
1579 struct mbox_msghdr hdr;
1580 uint8_t __otx2_io nix_lf_tx_sync;
1581 uint8_t __otx2_io nix_lf_rx_sync;
1582 uint8_t __otx2_io npa_lf_sync;
1585 struct tim_lf_alloc_req {
1586 struct mbox_msghdr hdr;
1587 uint16_t __otx2_io ring;
1588 uint16_t __otx2_io npa_pf_func;
1589 uint16_t __otx2_io sso_pf_func;
1592 struct tim_ring_req {
1593 struct mbox_msghdr hdr;
1594 uint16_t __otx2_io ring;
1597 struct tim_config_req {
1598 struct mbox_msghdr hdr;
1599 uint16_t __otx2_io ring;
1600 uint8_t __otx2_io bigendian;
1601 uint8_t __otx2_io clocksource;
1602 uint8_t __otx2_io enableperiodic;
1603 uint8_t __otx2_io enabledontfreebuffer;
1604 uint32_t __otx2_io bucketsize;
1605 uint32_t __otx2_io chunksize;
1606 uint32_t __otx2_io interval;
1609 struct tim_lf_alloc_rsp {
1610 struct mbox_msghdr hdr;
1611 uint64_t __otx2_io tenns_clk;
1614 struct tim_enable_rsp {
1615 struct mbox_msghdr hdr;
1616 uint64_t __otx2_io timestarted;
1617 uint32_t __otx2_io currentbucket;
1621 const char *otx2_mbox_id2name(uint16_t id);
1622 int otx2_mbox_id2size(uint16_t id);
1623 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
1624 int otx2_mbox_init(struct otx2_mbox *mbox, uintptr_t hwbase, uintptr_t reg_base,
1625 int direction, int ndevsi, uint64_t intr_offset);
1626 void otx2_mbox_fini(struct otx2_mbox *mbox);
1628 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
1630 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
1631 int otx2_mbox_wait_for_rsp_tmo(struct otx2_mbox *mbox, int devid, uint32_t tmo);
1633 int otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, void **msg);
1635 int otx2_mbox_get_rsp_tmo(struct otx2_mbox *mbox, int devid, void **msg,
1637 int otx2_mbox_get_availmem(struct otx2_mbox *mbox, int devid);
1639 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
1640 int size, int size_rsp);
1642 static inline struct mbox_msghdr *
1643 otx2_mbox_alloc_msg(struct otx2_mbox *mbox, int devid, int size)
1645 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
1649 otx2_mbox_req_init(uint16_t mbox_id, void *msghdr)
1651 struct mbox_msghdr *hdr = msghdr;
1653 hdr->sig = OTX2_MBOX_REQ_SIG;
1654 hdr->ver = OTX2_MBOX_VERSION;
1660 otx2_mbox_rsp_init(uint16_t mbox_id, void *msghdr)
1662 struct mbox_msghdr *hdr = msghdr;
1664 hdr->sig = OTX2_MBOX_RSP_SIG;
1665 hdr->rc = -ETIMEDOUT;
1670 otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid)
1672 struct otx2_mbox_dev *mdev = &mbox->dev[devid];
1675 rte_spinlock_lock(&mdev->mbox_lock);
1676 ret = mdev->num_msgs != 0;
1677 rte_spinlock_unlock(&mdev->mbox_lock);
1683 otx2_mbox_process(struct otx2_mbox *mbox)
1685 otx2_mbox_msg_send(mbox, 0);
1686 return otx2_mbox_get_rsp(mbox, 0, NULL);
1690 otx2_mbox_process_msg(struct otx2_mbox *mbox, void **msg)
1692 otx2_mbox_msg_send(mbox, 0);
1693 return otx2_mbox_get_rsp(mbox, 0, msg);
1697 otx2_mbox_process_tmo(struct otx2_mbox *mbox, uint32_t tmo)
1699 otx2_mbox_msg_send(mbox, 0);
1700 return otx2_mbox_get_rsp_tmo(mbox, 0, NULL, tmo);
1704 otx2_mbox_process_msg_tmo(struct otx2_mbox *mbox, void **msg, uint32_t tmo)
1706 otx2_mbox_msg_send(mbox, 0);
1707 return otx2_mbox_get_rsp_tmo(mbox, 0, msg, tmo);
1710 int otx2_send_ready_msg(struct otx2_mbox *mbox, uint16_t *pf_func /* out */);
1711 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, uint16_t pf_func,
1714 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
1715 static inline struct _req_type \
1716 *otx2_mbox_alloc_msg_ ## _fn_name(struct otx2_mbox *mbox) \
1718 struct _req_type *req; \
1720 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \
1721 mbox, 0, sizeof(struct _req_type), \
1722 sizeof(struct _rsp_type)); \
1726 req->hdr.sig = OTX2_MBOX_REQ_SIG; \
1727 req->hdr.id = _id; \
1728 otx2_mbox_dbg("id=0x%x (%s)", \
1729 req->hdr.id, otx2_mbox_id2name(req->hdr.id)); \
1736 /* This is required for copy operations from device memory which do not work on
1737 * addresses which are unaligned to 16B. This is because of specific
1738 * optimizations to libc memcpy.
1740 static inline volatile void *
1741 otx2_mbox_memcpy(volatile void *d, const volatile void *s, size_t l)
1743 const volatile uint8_t *sb;
1744 volatile uint8_t *db;
1749 db = (volatile uint8_t *)d;
1750 sb = (const volatile uint8_t *)s;
1751 for (i = 0; i < l; i++)
1756 /* This is required for memory operations from device memory which do not
1757 * work on addresses which are unaligned to 16B. This is because of specific
1758 * optimizations to libc memset.
1761 otx2_mbox_memset(volatile void *d, uint8_t val, size_t l)
1763 volatile uint8_t *db;
1768 db = (volatile uint8_t *)d;
1769 for (i = 0; i < l; i++)
1773 #endif /* __OTX2_MBOX_H__ */