1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef __OTX2_MBOX_H__
6 #define __OTX2_MBOX_H__
11 #include <rte_ether.h>
12 #include <rte_spinlock.h>
14 #include <otx2_common.h>
16 #define SZ_64K (64 * 1024)
17 #define SZ_1K (1 * 1024)
18 #define MBOX_SIZE SZ_64K
20 /* AF/PF: PF initiated, PF/VF VF initiated */
21 #define MBOX_DOWN_RX_START 0
22 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
23 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
24 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
25 /* AF/PF: AF initiated, PF/VF PF initiated */
26 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
27 #define MBOX_UP_RX_SIZE SZ_1K
28 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
29 #define MBOX_UP_TX_SIZE SZ_1K
31 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
32 # error "Incorrect mailbox area sizes"
35 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
37 #define MBOX_RSP_TIMEOUT 3000 /* Time to wait for mbox response in ms */
39 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
41 /* Mailbox directions */
42 #define MBOX_DIR_AFPF 0 /* AF replies to PF */
43 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */
44 #define MBOX_DIR_PFVF 2 /* PF replies to VF */
45 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */
46 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */
47 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */
48 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */
49 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */
51 /* Device memory does not support unaligned access, instruct compiler to
52 * not optimize the memory access when working with mailbox memory.
54 #define __otx2_io volatile
56 struct otx2_mbox_dev {
57 void *mbase; /* This dev's mbox region */
58 rte_spinlock_t mbox_lock;
59 uint16_t msg_size; /* Total msg size to be sent */
60 uint16_t rsp_size; /* Total rsp size to be sure the reply is ok */
61 uint16_t num_msgs; /* No of msgs sent or waiting for response */
62 uint16_t msgs_acked; /* No of msgs for which response is received */
66 uintptr_t hwbase; /* Mbox region advertised by HW */
67 uintptr_t reg_base;/* CSR base for this dev */
68 uint64_t trigger; /* Trigger mbox notification */
69 uint16_t tr_shift; /* Mbox trigger shift */
70 uint64_t rx_start; /* Offset of Rx region in mbox memory */
71 uint64_t tx_start; /* Offset of Tx region in mbox memory */
72 uint16_t rx_size; /* Size of Rx region */
73 uint16_t tx_size; /* Size of Tx region */
74 uint16_t ndevs; /* The number of peers */
75 struct otx2_mbox_dev *dev;
78 /* Header which precedes all mbox messages */
80 uint64_t __otx2_io msg_size; /* Total msgs size embedded */
81 uint16_t __otx2_io num_msgs; /* No of msgs embedded */
84 /* Header which precedes every msg and is also part of it */
86 uint16_t __otx2_io pcifunc; /* Who's sending this msg */
87 uint16_t __otx2_io id; /* Mbox message ID */
88 #define OTX2_MBOX_REQ_SIG (0xdead)
89 #define OTX2_MBOX_RSP_SIG (0xbeef)
90 /* Signature, for validating corrupted msgs */
91 uint16_t __otx2_io sig;
92 #define OTX2_MBOX_VERSION (0x0001)
93 /* Version of msg's structure for this ID */
94 uint16_t __otx2_io ver;
95 /* Offset of next msg within mailbox region */
96 uint16_t __otx2_io next_msgoff;
97 int __otx2_io rc; /* Msg processed response code */
100 /* Mailbox message types */
101 #define MBOX_MSG_MASK 0xFFFF
102 #define MBOX_MSG_INVALID 0xFFFE
103 #define MBOX_MSG_MAX 0xFFFF
105 #define MBOX_MESSAGES \
106 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
107 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
108 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach_req, msg_rsp)\
109 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach_req, msg_rsp)\
110 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
111 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
112 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
113 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
114 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
115 M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \
116 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
117 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
118 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
119 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
120 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get,\
121 cgx_mac_addr_set_or_get) \
122 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get,\
123 cgx_mac_addr_set_or_get) \
124 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
125 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
126 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
127 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
128 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg)\
129 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
130 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
131 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
132 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
133 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
135 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
136 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
137 cgx_mac_addr_add_rsp) \
138 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
140 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
141 cgx_max_dmac_entries_get_rsp) \
142 M(CGX_SET_LINK_STATE, 0x214, cgx_set_link_state, \
143 cgx_set_link_state_msg, msg_rsp) \
144 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
145 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, npa_lf_alloc_req, \
147 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
148 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp)\
149 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
150 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
151 M(SSO_LF_ALLOC, 0x600, sso_lf_alloc, sso_lf_alloc_req, \
153 M(SSO_LF_FREE, 0x601, sso_lf_free, sso_lf_free_req, msg_rsp) \
154 M(SSOW_LF_ALLOC, 0x602, ssow_lf_alloc, ssow_lf_alloc_req, msg_rsp)\
155 M(SSOW_LF_FREE, 0x603, ssow_lf_free, ssow_lf_free_req, msg_rsp) \
156 M(SSO_HW_SETCONFIG, 0x604, sso_hw_setconfig, sso_hw_setconfig, \
158 M(SSO_GRP_SET_PRIORITY, 0x605, sso_grp_set_priority, sso_grp_priority, \
160 M(SSO_GRP_GET_PRIORITY, 0x606, sso_grp_get_priority, sso_info_req, \
162 M(SSO_WS_CACHE_INV, 0x607, sso_ws_cache_inv, msg_req, msg_rsp) \
163 M(SSO_GRP_QOS_CONFIG, 0x608, sso_grp_qos_config, sso_grp_qos_cfg, \
165 M(SSO_GRP_GET_STATS, 0x609, sso_grp_get_stats, sso_info_req, \
167 M(SSO_HWS_GET_STATS, 0x610, sso_hws_get_stats, sso_info_req, \
169 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
170 M(TIM_LF_ALLOC, 0x800, tim_lf_alloc, tim_lf_alloc_req, \
172 M(TIM_LF_FREE, 0x801, tim_lf_free, tim_ring_req, msg_rsp) \
173 M(TIM_CONFIG_RING, 0x802, tim_config_ring, tim_config_req, msg_rsp)\
174 M(TIM_ENABLE_RING, 0x803, tim_enable_ring, tim_ring_req, \
176 M(TIM_DISABLE_RING, 0x804, tim_disable_ring, tim_ring_req, msg_rsp) \
177 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
178 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
180 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
181 cpt_inline_ipsec_cfg_msg, msg_rsp) \
182 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
183 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, \
184 npc_mcam_alloc_entry_req, \
185 npc_mcam_alloc_entry_rsp) \
186 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
187 npc_mcam_free_entry_req, msg_rsp) \
188 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
189 npc_mcam_write_entry_req, msg_rsp) \
190 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
191 npc_mcam_ena_dis_entry_req, msg_rsp) \
192 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
193 npc_mcam_ena_dis_entry_req, msg_rsp) \
194 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, \
195 npc_mcam_shift_entry_req, \
196 npc_mcam_shift_entry_rsp) \
197 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
198 npc_mcam_alloc_counter_req, \
199 npc_mcam_alloc_counter_rsp) \
200 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
201 npc_mcam_oper_counter_req, \
203 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
204 npc_mcam_unmap_counter_req, \
206 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
207 npc_mcam_oper_counter_req, \
209 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
210 npc_mcam_oper_counter_req, \
211 npc_mcam_oper_counter_rsp) \
212 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry,\
213 npc_mcam_alloc_and_write_entry_req, \
214 npc_mcam_alloc_and_write_entry_rsp) \
215 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, msg_req, \
216 npc_get_kex_cfg_rsp) \
217 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \
218 npc_install_flow_req, \
219 npc_install_flow_rsp) \
220 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \
221 npc_delete_flow_req, msg_rsp) \
222 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
223 npc_mcam_read_entry_req, \
224 npc_mcam_read_entry_rsp) \
225 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
226 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, nix_lf_alloc_req, \
228 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
229 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, \
231 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, hwctx_disable_req, \
233 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, nix_txsch_alloc_req, \
234 nix_txsch_alloc_rsp) \
235 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, \
237 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
239 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
240 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \
241 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
242 nix_rss_flowkey_cfg, \
243 nix_rss_flowkey_cfg_rsp) \
244 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, \
246 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
247 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
248 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
249 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
250 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
251 nix_mark_format_cfg, \
252 nix_mark_format_cfg_rsp) \
253 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, nix_lso_format_cfg, \
254 nix_lso_format_cfg_rsp) \
255 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, \
257 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, \
259 M(NIX_SET_VLAN_TPID, 0x8015, nix_set_vlan_tpid, nix_set_vlan_tpid, \
261 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
263 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp)\
264 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, \
265 nix_get_mac_addr_rsp) \
266 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \
267 nix_inline_ipsec_cfg, msg_rsp) \
268 M(NIX_INLINE_IPSEC_LF_CFG, \
269 0x801a, nix_inline_ipsec_lf_cfg, \
270 nix_inline_ipsec_lf_cfg, msg_rsp)
272 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
273 #define MBOX_UP_CGX_MESSAGES \
274 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, \
276 M(CGX_PTP_RX_INFO, 0xC01, cgx_ptp_rx_info, cgx_ptp_rx_info_msg, \
280 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
286 /* Mailbox message formats */
288 #define RVU_DEFAULT_PF_FUNC 0xFFFF
290 /* Generic request msg used for those mbox messages which
291 * don't send any data in the request.
294 struct mbox_msghdr hdr;
297 /* Generic response msg used a ack or response for those mbox
298 * messages which doesn't have a specific rsp msg format.
301 struct mbox_msghdr hdr;
304 /* RVU mailbox error codes
308 RVU_INVALID_VF_ID = -256,
311 struct ready_msg_rsp {
312 struct mbox_msghdr hdr;
313 uint16_t __otx2_io sclk_feq; /* SCLK frequency */
316 /* Structure for requesting resource provisioning.
317 * 'modify' flag to be used when either requesting more
318 * or detach partial of a certain resource type.
319 * Rest of the fields specify how many of what type to
322 struct rsrc_attach_req {
323 struct mbox_msghdr hdr;
324 uint8_t __otx2_io modify:1;
325 uint8_t __otx2_io npalf:1;
326 uint8_t __otx2_io nixlf:1;
327 uint16_t __otx2_io sso;
328 uint16_t __otx2_io ssow;
329 uint16_t __otx2_io timlfs;
330 uint16_t __otx2_io cptlfs;
333 /* Structure for relinquishing resources.
334 * 'partial' flag to be used when relinquishing all resources
335 * but only of a certain type. If not set, all resources of all
336 * types provisioned to the RVU function will be detached.
338 struct rsrc_detach_req {
339 struct mbox_msghdr hdr;
340 uint8_t __otx2_io partial:1;
341 uint8_t __otx2_io npalf:1;
342 uint8_t __otx2_io nixlf:1;
343 uint8_t __otx2_io sso:1;
344 uint8_t __otx2_io ssow:1;
345 uint8_t __otx2_io timlfs:1;
346 uint8_t __otx2_io cptlfs:1;
349 /* NIX Transmit schedulers */
350 #define NIX_TXSCH_LVL_SMQ 0x0
351 #define NIX_TXSCH_LVL_MDQ 0x0
352 #define NIX_TXSCH_LVL_TL4 0x1
353 #define NIX_TXSCH_LVL_TL3 0x2
354 #define NIX_TXSCH_LVL_TL2 0x3
355 #define NIX_TXSCH_LVL_TL1 0x4
356 #define NIX_TXSCH_LVL_CNT 0x5
359 * Number of resources available to the caller.
360 * In reply to MBOX_MSG_FREE_RSRC_CNT.
362 struct free_rsrcs_rsp {
363 struct mbox_msghdr hdr;
364 uint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT];
365 uint16_t __otx2_io sso;
366 uint16_t __otx2_io tim;
367 uint16_t __otx2_io ssow;
368 uint16_t __otx2_io cpt;
369 uint8_t __otx2_io npa;
370 uint8_t __otx2_io nix;
373 #define MSIX_VECTOR_INVALID 0xFFFF
374 #define MAX_RVU_BLKLF_CNT 256
376 struct msix_offset_rsp {
377 struct mbox_msghdr hdr;
378 uint16_t __otx2_io npa_msixoff;
379 uint16_t __otx2_io nix_msixoff;
380 uint8_t __otx2_io sso;
381 uint8_t __otx2_io ssow;
382 uint8_t __otx2_io timlfs;
383 uint8_t __otx2_io cptlfs;
384 uint16_t __otx2_io sso_msixoff[MAX_RVU_BLKLF_CNT];
385 uint16_t __otx2_io ssow_msixoff[MAX_RVU_BLKLF_CNT];
386 uint16_t __otx2_io timlf_msixoff[MAX_RVU_BLKLF_CNT];
387 uint16_t __otx2_io cptlf_msixoff[MAX_RVU_BLKLF_CNT];
390 /* CGX mbox message formats */
391 struct cgx_stats_rsp {
392 struct mbox_msghdr hdr;
393 #define CGX_RX_STATS_COUNT 13
394 #define CGX_TX_STATS_COUNT 18
395 uint64_t __otx2_io rx_stats[CGX_RX_STATS_COUNT];
396 uint64_t __otx2_io tx_stats[CGX_TX_STATS_COUNT];
399 /* Structure for requesting the operation for
400 * setting/getting mac address in the CGX interface
402 struct cgx_mac_addr_set_or_get {
403 struct mbox_msghdr hdr;
404 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
407 /* Structure for requesting the operation to
408 * add DMAC filter entry into CGX interface
410 struct cgx_mac_addr_add_req {
411 struct mbox_msghdr hdr;
412 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
415 /* Structure for response against the operation to
416 * add DMAC filter entry into CGX interface
418 struct cgx_mac_addr_add_rsp {
419 struct mbox_msghdr hdr;
420 uint8_t __otx2_io index;
423 /* Structure for requesting the operation to
424 * delete DMAC filter entry from CGX interface
426 struct cgx_mac_addr_del_req {
427 struct mbox_msghdr hdr;
428 uint8_t __otx2_io index;
431 /* Structure for response against the operation to
432 * get maximum supported DMAC filter entries
434 struct cgx_max_dmac_entries_get_rsp {
435 struct mbox_msghdr hdr;
436 uint8_t __otx2_io max_dmac_filters;
439 struct cgx_link_user_info {
440 uint64_t __otx2_io link_up:1;
441 uint64_t __otx2_io full_duplex:1;
442 uint64_t __otx2_io lmac_type_id:4;
443 uint64_t __otx2_io speed:20; /* speed in Mbps */
444 #define LMACTYPE_STR_LEN 16
445 char lmac_type[LMACTYPE_STR_LEN];
448 struct cgx_link_info_msg {
449 struct mbox_msghdr hdr;
450 struct cgx_link_user_info link_info;
453 struct cgx_pause_frm_cfg {
454 struct mbox_msghdr hdr;
455 uint8_t __otx2_io set;
456 /* set = 1 if the request is to config pause frames */
457 /* set = 0 if the request is to fetch pause frames config */
458 uint8_t __otx2_io rx_pause;
459 uint8_t __otx2_io tx_pause;
462 struct cgx_ptp_rx_info_msg {
463 struct mbox_msghdr hdr;
464 uint8_t __otx2_io ptp_en;
465 uint8_t __otx2_io ptp_offset;
468 struct sfp_eeprom_s {
469 #define SFP_EEPROM_SIZE 256
470 uint16_t __otx2_io sff_id;
471 uint8_t __otx2_io buf[SFP_EEPROM_SIZE];
474 struct cgx_lmac_fwdata_s {
475 uint16_t __otx2_io rw_valid;
476 uint64_t __otx2_io supported_fec;
477 uint64_t __otx2_io supported_an;
478 uint64_t __otx2_io supported_link_modes;
479 /* Only applicable if AN is supported */
480 uint64_t __otx2_io advertised_fec;
481 uint64_t __otx2_io advertised_link_modes;
482 /* Only applicable if SFP/QSFP slot is present */
483 struct sfp_eeprom_s sfp_eeprom;
487 struct mbox_msghdr hdr;
488 struct cgx_lmac_fwdata_s fwdata;
491 struct cgx_set_link_state_msg {
492 struct mbox_msghdr hdr;
493 uint8_t __otx2_io enable;
496 /* NPA mbox message formats */
498 /* NPA mailbox error codes
502 NPA_AF_ERR_PARAM = -301,
503 NPA_AF_ERR_AQ_FULL = -302,
504 NPA_AF_ERR_AQ_ENQUEUE = -303,
505 NPA_AF_ERR_AF_LF_INVALID = -304,
506 NPA_AF_ERR_AF_LF_ALLOC = -305,
507 NIX_AF_ERR_X2P_CALIBRATE = -398,
508 NIX_AF_ERR_RAN_OUT_BPID = -399,
511 #define NPA_AURA_SZ_0 0
512 #define NPA_AURA_SZ_128 1
513 #define NPA_AURA_SZ_256 2
514 #define NPA_AURA_SZ_512 3
515 #define NPA_AURA_SZ_1K 4
516 #define NPA_AURA_SZ_2K 5
517 #define NPA_AURA_SZ_4K 6
518 #define NPA_AURA_SZ_8K 7
519 #define NPA_AURA_SZ_16K 8
520 #define NPA_AURA_SZ_32K 9
521 #define NPA_AURA_SZ_64K 10
522 #define NPA_AURA_SZ_128K 11
523 #define NPA_AURA_SZ_256K 12
524 #define NPA_AURA_SZ_512K 13
525 #define NPA_AURA_SZ_1M 14
526 #define NPA_AURA_SZ_MAX 15
528 /* For NPA LF context alloc and init */
529 struct npa_lf_alloc_req {
530 struct mbox_msghdr hdr;
532 int __otx2_io aura_sz; /* No of auras. See NPA_AURA_SZ_* */
533 uint32_t __otx2_io nr_pools; /* No of pools */
534 uint64_t __otx2_io way_mask;
537 struct npa_lf_alloc_rsp {
538 struct mbox_msghdr hdr;
539 uint32_t __otx2_io stack_pg_ptrs; /* No of ptrs per stack page */
540 uint32_t __otx2_io stack_pg_bytes; /* Size of stack page */
541 uint16_t __otx2_io qints; /* NPA_AF_CONST::QINTS */
544 /* NPA AQ enqueue msg */
545 struct npa_aq_enq_req {
546 struct mbox_msghdr hdr;
547 uint32_t __otx2_io aura_id;
548 uint8_t __otx2_io ctype;
549 uint8_t __otx2_io op;
551 /* Valid when op == WRITE/INIT and ctype == AURA.
552 * LF fills the pool_id in aura.pool_addr. AF will translate
553 * the pool_id to pool context pointer.
555 struct npa_aura_s aura;
556 /* Valid when op == WRITE/INIT and ctype == POOL */
557 struct npa_pool_s pool;
559 /* Mask data when op == WRITE (1=write, 0=don't write) */
561 /* Valid when op == WRITE and ctype == AURA */
562 struct npa_aura_s aura_mask;
563 /* Valid when op == WRITE and ctype == POOL */
564 struct npa_pool_s pool_mask;
568 struct npa_aq_enq_rsp {
569 struct mbox_msghdr hdr;
571 /* Valid when op == READ and ctype == AURA */
572 struct npa_aura_s aura;
573 /* Valid when op == READ and ctype == POOL */
574 struct npa_pool_s pool;
578 /* Disable all contexts of type 'ctype' */
579 struct hwctx_disable_req {
580 struct mbox_msghdr hdr;
581 uint8_t __otx2_io ctype;
584 /* NIX mbox message formats */
585 /* NIX mailbox error codes
589 NIX_AF_ERR_PARAM = -401,
590 NIX_AF_ERR_AQ_FULL = -402,
591 NIX_AF_ERR_AQ_ENQUEUE = -403,
592 NIX_AF_ERR_AF_LF_INVALID = -404,
593 NIX_AF_ERR_AF_LF_ALLOC = -405,
594 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
595 NIX_AF_ERR_TLX_INVALID = -407,
596 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
597 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
598 NIX_AF_ERR_FRS_INVALID = -410,
599 NIX_AF_ERR_RX_LINK_INVALID = -411,
600 NIX_AF_INVAL_TXSCHQ_CFG = -412,
601 NIX_AF_SMQ_FLUSH_FAILED = -413,
602 NIX_AF_MACADDR_SET_FAILED = -414,
603 NIX_AF_RX_MODE_SET_FAILED = -415,
604 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
605 NIX_AF_ERR_RSS_NOSPC_FIELD = -417,
606 NIX_AF_ERR_MARK_ALLOC_FAIL = -418,
607 NIX_AF_ERR_LSOFMT_CFG_FAIL = -419,
610 /* For NIX LF context alloc and init */
611 struct nix_lf_alloc_req {
612 struct mbox_msghdr hdr;
614 uint32_t __otx2_io rq_cnt; /* No of receive queues */
615 uint32_t __otx2_io sq_cnt; /* No of send queues */
616 uint32_t __otx2_io cq_cnt; /* No of completion queues */
617 uint8_t __otx2_io xqe_sz;
618 uint16_t __otx2_io rss_sz;
619 uint8_t __otx2_io rss_grps;
620 uint16_t __otx2_io npa_func;
621 /* RVU_DEFAULT_PF_FUNC == default pf_func associated with lf */
622 uint16_t __otx2_io sso_func;
623 uint64_t __otx2_io rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
624 uint64_t __otx2_io way_mask;
627 struct nix_lf_alloc_rsp {
628 struct mbox_msghdr hdr;
629 uint16_t __otx2_io sqb_size;
630 uint16_t __otx2_io rx_chan_base;
631 uint16_t __otx2_io tx_chan_base;
632 uint8_t __otx2_io rx_chan_cnt; /* Total number of RX channels */
633 uint8_t __otx2_io tx_chan_cnt; /* Total number of TX channels */
634 uint8_t __otx2_io lso_tsov4_idx;
635 uint8_t __otx2_io lso_tsov6_idx;
636 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
637 uint8_t __otx2_io lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
638 uint8_t __otx2_io lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
639 uint16_t __otx2_io cints; /* NIX_AF_CONST2::CINTS */
640 uint16_t __otx2_io qints; /* NIX_AF_CONST2::QINTS */
641 uint8_t __otx2_io ptp; /* boolean; true iff PTP block is supported */
644 struct nix_lf_free_req {
645 struct mbox_msghdr hdr;
646 #define NIX_LF_DISABLE_FLOWS 0x1
647 uint64_t __otx2_io flags;
650 /* NIX AQ enqueue msg */
651 struct nix_aq_enq_req {
652 struct mbox_msghdr hdr;
653 uint32_t __otx2_io qidx;
654 uint8_t __otx2_io ctype;
655 uint8_t __otx2_io op;
657 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */
658 struct nix_rq_ctx_s rq;
659 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */
660 struct nix_sq_ctx_s sq;
661 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */
662 struct nix_cq_ctx_s cq;
663 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */
664 struct nix_rsse_s rss;
665 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */
666 struct nix_rx_mce_s mce;
668 /* Mask data when op == WRITE (1=write, 0=don't write) */
670 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */
671 struct nix_rq_ctx_s rq_mask;
672 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */
673 struct nix_sq_ctx_s sq_mask;
674 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */
675 struct nix_cq_ctx_s cq_mask;
676 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */
677 struct nix_rsse_s rss_mask;
678 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */
679 struct nix_rx_mce_s mce_mask;
683 struct nix_aq_enq_rsp {
684 struct mbox_msghdr hdr;
686 struct nix_rq_ctx_s rq;
687 struct nix_sq_ctx_s sq;
688 struct nix_cq_ctx_s cq;
689 struct nix_rsse_s rss;
690 struct nix_rx_mce_s mce;
694 /* Tx scheduler/shaper mailbox messages */
696 #define MAX_TXSCHQ_PER_FUNC 128
698 struct nix_txsch_alloc_req {
699 struct mbox_msghdr hdr;
700 /* Scheduler queue count request at each level */
701 uint16_t __otx2_io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
702 uint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
705 struct nix_txsch_alloc_rsp {
706 struct mbox_msghdr hdr;
707 /* Scheduler queue count allocated at each level */
708 uint16_t __otx2_io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
709 uint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
710 /* Scheduler queue list allocated at each level */
712 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
713 uint16_t __otx2_io schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
714 /* Traffic aggregation scheduler level */
715 uint8_t __otx2_io aggr_level;
716 /* Aggregation lvl's RR_PRIO config */
717 uint8_t __otx2_io aggr_lvl_rr_prio;
718 /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
719 uint8_t __otx2_io link_cfg_lvl;
722 struct nix_txsch_free_req {
723 struct mbox_msghdr hdr;
724 #define TXSCHQ_FREE_ALL BIT_ULL(0)
725 uint16_t __otx2_io flags;
726 /* Scheduler queue level to be freed */
727 uint16_t __otx2_io schq_lvl;
728 /* List of scheduler queues to be freed */
729 uint16_t __otx2_io schq;
732 struct nix_txschq_config {
733 struct mbox_msghdr hdr;
734 uint8_t __otx2_io lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
735 #define TXSCHQ_IDX_SHIFT 16
736 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
737 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
738 uint8_t __otx2_io num_regs;
739 #define MAX_REGS_PER_MBOX_MSG 20
740 uint64_t __otx2_io reg[MAX_REGS_PER_MBOX_MSG];
741 uint64_t __otx2_io regval[MAX_REGS_PER_MBOX_MSG];
744 struct nix_vtag_config {
745 struct mbox_msghdr hdr;
746 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
747 uint8_t __otx2_io vtag_size;
748 /* cfg_type is '0' for tx vlan cfg
749 * cfg_type is '1' for rx vlan cfg
751 uint8_t __otx2_io cfg_type;
753 /* Valid when cfg_type is '0' */
755 uint64_t __otx2_io vtag0;
756 uint64_t __otx2_io vtag1;
758 /* cfg_vtag0 & cfg_vtag1 fields are valid
759 * when free_vtag0 & free_vtag1 are '0's.
761 /* cfg_vtag0 = 1 to configure vtag0 */
762 uint8_t __otx2_io cfg_vtag0 :1;
763 /* cfg_vtag1 = 1 to configure vtag1 */
764 uint8_t __otx2_io cfg_vtag1 :1;
766 /* vtag0_idx & vtag1_idx are only valid when
767 * both cfg_vtag0 & cfg_vtag1 are '0's,
768 * these fields are used along with free_vtag0
769 * & free_vtag1 to free the nix lf's tx_vlan
772 * Denotes the indices of tx_vtag def registers
773 * that needs to be cleared and freed.
775 int __otx2_io vtag0_idx;
776 int __otx2_io vtag1_idx;
778 /* Free_vtag0 & free_vtag1 fields are valid
779 * when cfg_vtag0 & cfg_vtag1 are '0's.
781 /* Free_vtag0 = 1 clears vtag0 configuration
782 * vtag0_idx denotes the index to be cleared.
784 uint8_t __otx2_io free_vtag0 :1;
785 /* Free_vtag1 = 1 clears vtag1 configuration
786 * vtag1_idx denotes the index to be cleared.
788 uint8_t __otx2_io free_vtag1 :1;
791 /* Valid when cfg_type is '1' */
793 /* Rx vtag type index, valid values are in 0..7 range */
794 uint8_t __otx2_io vtag_type;
796 uint8_t __otx2_io strip_vtag :1;
797 /* Rx vtag capture */
798 uint8_t __otx2_io capture_vtag :1;
803 struct nix_vtag_config_rsp {
804 struct mbox_msghdr hdr;
805 /* Indices of tx_vtag def registers used to configure
806 * tx vtag0 & vtag1 headers, these indices are valid
807 * when nix_vtag_config mbox requested for vtag0 and/
808 * or vtag1 configuration.
810 int __otx2_io vtag0_idx;
811 int __otx2_io vtag1_idx;
814 struct nix_rss_flowkey_cfg {
815 struct mbox_msghdr hdr;
816 int __otx2_io mcam_index; /* MCAM entry index to modify */
817 uint32_t __otx2_io flowkey_cfg; /* Flowkey types selected */
818 #define FLOW_KEY_TYPE_PORT BIT(0)
819 #define FLOW_KEY_TYPE_IPV4 BIT(1)
820 #define FLOW_KEY_TYPE_IPV6 BIT(2)
821 #define FLOW_KEY_TYPE_TCP BIT(3)
822 #define FLOW_KEY_TYPE_UDP BIT(4)
823 #define FLOW_KEY_TYPE_SCTP BIT(5)
824 #define FLOW_KEY_TYPE_NVGRE BIT(6)
825 #define FLOW_KEY_TYPE_VXLAN BIT(7)
826 #define FLOW_KEY_TYPE_GENEVE BIT(8)
827 #define FLOW_KEY_TYPE_ETH_DMAC BIT(9)
828 #define FLOW_KEY_TYPE_IPV6_EXT BIT(10)
829 #define FLOW_KEY_TYPE_GTPU BIT(11)
830 #define FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
831 #define FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
832 #define FLOW_KEY_TYPE_INNR_TCP BIT(14)
833 #define FLOW_KEY_TYPE_INNR_UDP BIT(15)
834 #define FLOW_KEY_TYPE_INNR_SCTP BIT(16)
835 #define FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
836 uint8_t group; /* RSS context or group */
839 struct nix_rss_flowkey_cfg_rsp {
840 struct mbox_msghdr hdr;
841 uint8_t __otx2_io alg_idx; /* Selected algo index */
844 struct nix_set_mac_addr {
845 struct mbox_msghdr hdr;
846 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
849 struct nix_get_mac_addr_rsp {
850 struct mbox_msghdr hdr;
851 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
854 struct nix_mark_format_cfg {
855 struct mbox_msghdr hdr;
856 uint8_t __otx2_io offset;
857 uint8_t __otx2_io y_mask;
858 uint8_t __otx2_io y_val;
859 uint8_t __otx2_io r_mask;
860 uint8_t __otx2_io r_val;
863 struct nix_mark_format_cfg_rsp {
864 struct mbox_msghdr hdr;
865 uint8_t __otx2_io mark_format_idx;
868 struct nix_lso_format_cfg {
869 struct mbox_msghdr hdr;
870 uint64_t __otx2_io field_mask;
871 #define NIX_LSO_FIELD_MAX (8)
872 uint64_t __otx2_io fields[NIX_LSO_FIELD_MAX];
875 struct nix_lso_format_cfg_rsp {
876 struct mbox_msghdr hdr;
877 uint8_t __otx2_io lso_format_idx;
881 struct mbox_msghdr hdr;
882 #define NIX_RX_MODE_UCAST BIT(0)
883 #define NIX_RX_MODE_PROMISC BIT(1)
884 #define NIX_RX_MODE_ALLMULTI BIT(2)
885 uint16_t __otx2_io mode;
889 struct mbox_msghdr hdr;
890 uint8_t __otx2_io update_smq; /* Update SMQ's min/max lens */
891 uint8_t __otx2_io update_minlen; /* Set minlen also */
892 uint8_t __otx2_io sdp_link; /* Set SDP RX link */
893 uint16_t __otx2_io maxlen;
894 uint16_t __otx2_io minlen;
897 struct nix_set_vlan_tpid {
898 struct mbox_msghdr hdr;
899 #define NIX_VLAN_TYPE_INNER 0
900 #define NIX_VLAN_TYPE_OUTER 1
901 uint8_t __otx2_io vlan_type;
902 uint16_t __otx2_io tpid;
905 struct nix_bp_cfg_req {
906 struct mbox_msghdr hdr;
907 uint16_t __otx2_io chan_base; /* Starting channel number */
908 uint8_t __otx2_io chan_cnt; /* Number of channels */
909 uint8_t __otx2_io bpid_per_chan;
910 /* bpid_per_chan = 0 assigns single bp id for range of channels */
911 /* bpid_per_chan = 1 assigns separate bp id for each channel */
914 /* Global NIX inline IPSec configuration */
915 struct nix_inline_ipsec_cfg {
916 struct mbox_msghdr hdr;
917 uint32_t __otx2_io cpt_credit;
919 uint8_t __otx2_io egrp;
920 uint8_t __otx2_io opcode;
923 uint16_t __otx2_io cpt_pf_func;
924 uint8_t __otx2_io cpt_slot;
926 uint8_t __otx2_io enable;
929 /* Per NIX LF inline IPSec configuration */
930 struct nix_inline_ipsec_lf_cfg {
931 struct mbox_msghdr hdr;
932 uint64_t __otx2_io sa_base_addr;
934 uint32_t __otx2_io tag_const;
935 uint16_t __otx2_io lenm1_max;
936 uint8_t __otx2_io sa_pow2_size;
937 uint8_t __otx2_io tt;
940 uint32_t __otx2_io sa_idx_max;
941 uint8_t __otx2_io sa_idx_w;
943 uint8_t __otx2_io enable;
946 /* PF can be mapped to either CGX or LBK interface,
947 * so maximum 64 channels are possible.
949 #define NIX_MAX_CHAN 64
950 struct nix_bp_cfg_rsp {
951 struct mbox_msghdr hdr;
952 /* Channel and bpid mapping */
953 uint16_t __otx2_io chan_bpid[NIX_MAX_CHAN];
954 /* Number of channel for which bpids are assigned */
955 uint8_t __otx2_io chan_cnt;
958 /* SSO mailbox error codes
962 SSO_AF_ERR_PARAM = -501,
963 SSO_AF_ERR_LF_INVALID = -502,
964 SSO_AF_ERR_AF_LF_ALLOC = -503,
965 SSO_AF_ERR_GRP_EBUSY = -504,
966 SSO_AF_ERR_AF_LF_INVALID = -599,
969 struct sso_lf_alloc_req {
970 struct mbox_msghdr hdr;
972 uint16_t __otx2_io hwgrps;
975 struct sso_lf_alloc_rsp {
976 struct mbox_msghdr hdr;
977 uint32_t __otx2_io xaq_buf_size;
978 uint32_t __otx2_io xaq_wq_entries;
979 uint32_t __otx2_io in_unit_entries;
980 uint16_t __otx2_io hwgrps;
983 struct sso_lf_free_req {
984 struct mbox_msghdr hdr;
986 uint16_t __otx2_io hwgrps;
989 /* SSOW mailbox error codes
992 enum ssow_af_status {
993 SSOW_AF_ERR_PARAM = -601,
994 SSOW_AF_ERR_LF_INVALID = -602,
995 SSOW_AF_ERR_AF_LF_ALLOC = -603,
998 struct ssow_lf_alloc_req {
999 struct mbox_msghdr hdr;
1001 uint16_t __otx2_io hws;
1004 struct ssow_lf_free_req {
1005 struct mbox_msghdr hdr;
1007 uint16_t __otx2_io hws;
1010 struct sso_hw_setconfig {
1011 struct mbox_msghdr hdr;
1012 uint32_t __otx2_io npa_aura_id;
1013 uint16_t __otx2_io npa_pf_func;
1014 uint16_t __otx2_io hwgrps;
1017 struct sso_info_req {
1018 struct mbox_msghdr hdr;
1020 uint16_t __otx2_io grp;
1021 uint16_t __otx2_io hws;
1025 struct sso_grp_priority {
1026 struct mbox_msghdr hdr;
1027 uint16_t __otx2_io grp;
1028 uint8_t __otx2_io priority;
1029 uint8_t __otx2_io affinity;
1030 uint8_t __otx2_io weight;
1033 struct sso_grp_qos_cfg {
1034 struct mbox_msghdr hdr;
1035 uint16_t __otx2_io grp;
1036 uint32_t __otx2_io xaq_limit;
1037 uint16_t __otx2_io taq_thr;
1038 uint16_t __otx2_io iaq_thr;
1041 struct sso_grp_stats {
1042 struct mbox_msghdr hdr;
1043 uint16_t __otx2_io grp;
1044 uint64_t __otx2_io ws_pc;
1045 uint64_t __otx2_io ext_pc;
1046 uint64_t __otx2_io wa_pc;
1047 uint64_t __otx2_io ts_pc;
1048 uint64_t __otx2_io ds_pc;
1049 uint64_t __otx2_io dq_pc;
1050 uint64_t __otx2_io aw_status;
1051 uint64_t __otx2_io page_cnt;
1054 struct sso_hws_stats {
1055 struct mbox_msghdr hdr;
1056 uint16_t __otx2_io hws;
1057 uint64_t __otx2_io arbitration;
1060 /* CPT mbox message formats */
1062 struct cpt_rd_wr_reg_msg {
1063 struct mbox_msghdr hdr;
1064 uint64_t __otx2_io reg_offset;
1065 uint64_t __otx2_io *ret_val;
1066 uint64_t __otx2_io val;
1067 uint8_t __otx2_io is_write;
1070 #define CPT_INLINE_INBOUND 0
1071 #define CPT_INLINE_OUTBOUND 1
1073 struct cpt_inline_ipsec_cfg_msg {
1074 struct mbox_msghdr hdr;
1075 uint8_t __otx2_io enable;
1076 uint8_t __otx2_io slot;
1077 uint8_t __otx2_io dir;
1078 uint16_t __otx2_io sso_pf_func; /* Inbound path SSO_PF_FUNC */
1079 uint16_t __otx2_io nix_pf_func; /* Outbound path NIX_PF_FUNC */
1082 /* NPC mbox message structs */
1084 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
1085 #define NPC_MCAM_INVALID_MAP 0xFFFF
1087 /* NPC mailbox error codes
1090 enum npc_af_status {
1091 NPC_MCAM_INVALID_REQ = -701,
1092 NPC_MCAM_ALLOC_DENIED = -702,
1093 NPC_MCAM_ALLOC_FAILED = -703,
1094 NPC_MCAM_PERM_DENIED = -704,
1097 struct npc_mcam_alloc_entry_req {
1098 struct mbox_msghdr hdr;
1099 #define NPC_MAX_NONCONTIG_ENTRIES 256
1100 uint8_t __otx2_io contig; /* Contiguous entries ? */
1101 #define NPC_MCAM_ANY_PRIO 0
1102 #define NPC_MCAM_LOWER_PRIO 1
1103 #define NPC_MCAM_HIGHER_PRIO 2
1104 uint8_t __otx2_io priority; /* Lower or higher w.r.t ref_entry */
1105 uint16_t __otx2_io ref_entry;
1106 uint16_t __otx2_io count; /* Number of entries requested */
1109 struct npc_mcam_alloc_entry_rsp {
1110 struct mbox_msghdr hdr;
1111 /* Entry alloc'ed or start index if contiguous.
1112 * Invalid in case of non-contiguous.
1114 uint16_t __otx2_io entry;
1115 uint16_t __otx2_io count; /* Number of entries allocated */
1116 uint16_t __otx2_io free_count; /* Number of entries available */
1117 uint16_t __otx2_io entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1120 struct npc_mcam_free_entry_req {
1121 struct mbox_msghdr hdr;
1122 uint16_t __otx2_io entry; /* Entry index to be freed */
1123 uint8_t __otx2_io all; /* Free all entries alloc'ed to this PFVF */
1127 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max key width */
1128 uint64_t __otx2_io kw[NPC_MAX_KWS_IN_KEY];
1129 uint64_t __otx2_io kw_mask[NPC_MAX_KWS_IN_KEY];
1130 uint64_t __otx2_io action;
1131 uint64_t __otx2_io vtag_action;
1134 struct npc_mcam_write_entry_req {
1135 struct mbox_msghdr hdr;
1136 struct mcam_entry entry_data;
1137 uint16_t __otx2_io entry; /* MCAM entry to write this match key */
1138 uint16_t __otx2_io cntr; /* Counter for this MCAM entry */
1139 uint8_t __otx2_io intf; /* Rx or Tx interface */
1140 uint8_t __otx2_io enable_entry;/* Enable this MCAM entry ? */
1141 uint8_t __otx2_io set_cntr; /* Set counter for this entry ? */
1144 /* Enable/Disable a given entry */
1145 struct npc_mcam_ena_dis_entry_req {
1146 struct mbox_msghdr hdr;
1147 uint16_t __otx2_io entry;
1150 struct npc_mcam_shift_entry_req {
1151 struct mbox_msghdr hdr;
1152 #define NPC_MCAM_MAX_SHIFTS 64
1153 uint16_t __otx2_io curr_entry[NPC_MCAM_MAX_SHIFTS];
1154 uint16_t __otx2_io new_entry[NPC_MCAM_MAX_SHIFTS];
1155 uint16_t __otx2_io shift_count; /* Number of entries to shift */
1158 struct npc_mcam_shift_entry_rsp {
1159 struct mbox_msghdr hdr;
1160 /* Index in 'curr_entry', not entry itself */
1161 uint16_t __otx2_io failed_entry_idx;
1164 struct npc_mcam_alloc_counter_req {
1165 struct mbox_msghdr hdr;
1166 uint8_t __otx2_io contig; /* Contiguous counters ? */
1167 #define NPC_MAX_NONCONTIG_COUNTERS 64
1168 uint16_t __otx2_io count; /* Number of counters requested */
1171 struct npc_mcam_alloc_counter_rsp {
1172 struct mbox_msghdr hdr;
1173 /* Counter alloc'ed or start idx if contiguous.
1174 * Invalid incase of non-contiguous.
1176 uint16_t __otx2_io cntr;
1177 uint16_t __otx2_io count; /* Number of counters allocated */
1178 uint16_t __otx2_io cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1181 struct npc_mcam_oper_counter_req {
1182 struct mbox_msghdr hdr;
1183 uint16_t __otx2_io cntr; /* Free a counter or clear/fetch it's stats */
1186 struct npc_mcam_oper_counter_rsp {
1187 struct mbox_msghdr hdr;
1188 /* valid only while fetching counter's stats */
1189 uint64_t __otx2_io stat;
1192 struct npc_mcam_unmap_counter_req {
1193 struct mbox_msghdr hdr;
1194 uint16_t __otx2_io cntr;
1195 uint16_t __otx2_io entry; /* Entry and counter to be unmapped */
1196 uint8_t __otx2_io all; /* Unmap all entries using this counter ? */
1199 struct npc_mcam_alloc_and_write_entry_req {
1200 struct mbox_msghdr hdr;
1201 struct mcam_entry entry_data;
1202 uint16_t __otx2_io ref_entry;
1203 uint8_t __otx2_io priority; /* Lower or higher w.r.t ref_entry */
1204 uint8_t __otx2_io intf; /* Rx or Tx interface */
1205 uint8_t __otx2_io enable_entry;/* Enable this MCAM entry ? */
1206 uint8_t __otx2_io alloc_cntr; /* Allocate counter and map ? */
1209 struct npc_mcam_alloc_and_write_entry_rsp {
1210 struct mbox_msghdr hdr;
1211 uint16_t __otx2_io entry;
1212 uint16_t __otx2_io cntr;
1215 struct npc_get_kex_cfg_rsp {
1216 struct mbox_msghdr hdr;
1217 uint64_t __otx2_io rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1218 uint64_t __otx2_io tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1219 #define NPC_MAX_INTF 2
1220 #define NPC_MAX_LID 8
1221 #define NPC_MAX_LT 16
1222 #define NPC_MAX_LD 2
1223 #define NPC_MAX_LFL 16
1224 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1225 uint64_t __otx2_io kex_ld_flags[NPC_MAX_LD];
1226 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1228 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
1229 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1231 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1232 #define MKEX_NAME_LEN 128
1233 uint8_t __otx2_io mkex_pfl_name[MKEX_NAME_LEN];
1237 unsigned char __otx2_io dmac[6];
1238 unsigned char __otx2_io smac[6];
1239 uint16_t __otx2_io etype;
1240 uint16_t __otx2_io vlan_etype;
1241 uint16_t __otx2_io vlan_tci;
1243 uint32_t __otx2_io ip4src;
1244 uint32_t __otx2_io ip6src[4];
1247 uint32_t __otx2_io ip4dst;
1248 uint32_t __otx2_io ip6dst[4];
1250 uint8_t __otx2_io tos;
1251 uint8_t __otx2_io ip_ver;
1252 uint8_t __otx2_io ip_proto;
1253 uint8_t __otx2_io tc;
1254 uint16_t __otx2_io sport;
1255 uint16_t __otx2_io dport;
1258 struct npc_install_flow_req {
1259 struct mbox_msghdr hdr;
1260 struct flow_msg packet;
1261 struct flow_msg mask;
1262 uint64_t __otx2_io features;
1263 uint16_t __otx2_io entry;
1264 uint16_t __otx2_io channel;
1265 uint8_t __otx2_io intf;
1266 uint8_t __otx2_io set_cntr;
1267 uint8_t __otx2_io default_rule;
1268 /* Overwrite(0) or append(1) flow to default rule? */
1269 uint8_t __otx2_io append;
1270 uint16_t __otx2_io vf;
1272 uint32_t __otx2_io index;
1273 uint16_t __otx2_io match_id;
1274 uint8_t __otx2_io flow_key_alg;
1275 uint8_t __otx2_io op;
1277 uint8_t __otx2_io vtag0_type;
1278 uint8_t __otx2_io vtag0_valid;
1279 uint8_t __otx2_io vtag1_type;
1280 uint8_t __otx2_io vtag1_valid;
1283 struct npc_install_flow_rsp {
1284 struct mbox_msghdr hdr;
1285 /* Negative if no counter else counter number */
1286 int __otx2_io counter;
1289 struct npc_delete_flow_req {
1290 struct mbox_msghdr hdr;
1291 uint16_t __otx2_io entry;
1293 uint8_t __otx2_io all;
1296 struct npc_mcam_read_entry_req {
1297 struct mbox_msghdr hdr;
1298 /* MCAM entry to read */
1299 uint16_t __otx2_io entry;
1302 struct npc_mcam_read_entry_rsp {
1303 struct mbox_msghdr hdr;
1304 struct mcam_entry entry_data;
1305 uint8_t __otx2_io intf;
1306 uint8_t __otx2_io enable;
1309 /* TIM mailbox error codes
1312 enum tim_af_status {
1313 TIM_AF_NO_RINGS_LEFT = -801,
1314 TIM_AF_INVALID_NPA_PF_FUNC = -802,
1315 TIM_AF_INVALID_SSO_PF_FUNC = -803,
1316 TIM_AF_RING_STILL_RUNNING = -804,
1317 TIM_AF_LF_INVALID = -805,
1318 TIM_AF_CSIZE_NOT_ALIGNED = -806,
1319 TIM_AF_CSIZE_TOO_SMALL = -807,
1320 TIM_AF_CSIZE_TOO_BIG = -808,
1321 TIM_AF_INTERVAL_TOO_SMALL = -809,
1322 TIM_AF_INVALID_BIG_ENDIAN_VALUE = -810,
1323 TIM_AF_INVALID_CLOCK_SOURCE = -811,
1324 TIM_AF_GPIO_CLK_SRC_NOT_ENABLED = -812,
1325 TIM_AF_INVALID_BSIZE = -813,
1326 TIM_AF_INVALID_ENABLE_PERIODIC = -814,
1327 TIM_AF_INVALID_ENABLE_DONTFREE = -815,
1328 TIM_AF_ENA_DONTFRE_NSET_PERIODIC = -816,
1329 TIM_AF_RING_ALREADY_DISABLED = -817,
1333 TIM_CLK_SRCS_TENNS = 0,
1334 TIM_CLK_SRCS_GPIO = 1,
1335 TIM_CLK_SRCS_GTI = 2,
1336 TIM_CLK_SRCS_PTP = 3,
1337 TIM_CLK_SRSC_INVALID,
1340 enum tim_gpio_edge {
1341 TIM_GPIO_NO_EDGE = 0,
1342 TIM_GPIO_LTOH_TRANS = 1,
1343 TIM_GPIO_HTOL_TRANS = 2,
1344 TIM_GPIO_BOTH_TRANS = 3,
1349 PTP_OP_ADJFINE = 0, /* adjfine(req.scaled_ppm); */
1350 PTP_OP_GET_CLOCK = 1, /* rsp.clk = get_clock() */
1354 struct mbox_msghdr hdr;
1355 uint8_t __otx2_io op;
1356 int64_t __otx2_io scaled_ppm;
1360 struct mbox_msghdr hdr;
1361 uint64_t __otx2_io clk;
1364 struct get_hw_cap_rsp {
1365 struct mbox_msghdr hdr;
1366 /* Schq mapping fixed or flexible */
1367 uint8_t __otx2_io nix_fixed_txschq_mapping;
1368 uint8_t __otx2_io nix_express_traffic; /* Are express links supported */
1369 uint8_t __otx2_io nix_shaping; /* Is shaping and coloring supported */
1372 struct ndc_sync_op {
1373 struct mbox_msghdr hdr;
1374 uint8_t __otx2_io nix_lf_tx_sync;
1375 uint8_t __otx2_io nix_lf_rx_sync;
1376 uint8_t __otx2_io npa_lf_sync;
1379 struct tim_lf_alloc_req {
1380 struct mbox_msghdr hdr;
1381 uint16_t __otx2_io ring;
1382 uint16_t __otx2_io npa_pf_func;
1383 uint16_t __otx2_io sso_pf_func;
1386 struct tim_ring_req {
1387 struct mbox_msghdr hdr;
1388 uint16_t __otx2_io ring;
1391 struct tim_config_req {
1392 struct mbox_msghdr hdr;
1393 uint16_t __otx2_io ring;
1394 uint8_t __otx2_io bigendian;
1395 uint8_t __otx2_io clocksource;
1396 uint8_t __otx2_io enableperiodic;
1397 uint8_t __otx2_io enabledontfreebuffer;
1398 uint32_t __otx2_io bucketsize;
1399 uint32_t __otx2_io chunksize;
1400 uint32_t __otx2_io interval;
1403 struct tim_lf_alloc_rsp {
1404 struct mbox_msghdr hdr;
1405 uint64_t __otx2_io tenns_clk;
1408 struct tim_enable_rsp {
1409 struct mbox_msghdr hdr;
1410 uint64_t __otx2_io timestarted;
1411 uint32_t __otx2_io currentbucket;
1414 const char *otx2_mbox_id2name(uint16_t id);
1415 int otx2_mbox_id2size(uint16_t id);
1416 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
1417 int otx2_mbox_init(struct otx2_mbox *mbox, uintptr_t hwbase,
1418 uintptr_t reg_base, int direction, int ndevs);
1419 void otx2_mbox_fini(struct otx2_mbox *mbox);
1420 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
1421 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
1422 int otx2_mbox_wait_for_rsp_tmo(struct otx2_mbox *mbox, int devid, uint32_t tmo);
1423 int otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, void **msg);
1424 int otx2_mbox_get_rsp_tmo(struct otx2_mbox *mbox, int devid, void **msg,
1426 int otx2_mbox_get_availmem(struct otx2_mbox *mbox, int devid);
1427 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
1428 int size, int size_rsp);
1430 static inline struct mbox_msghdr *
1431 otx2_mbox_alloc_msg(struct otx2_mbox *mbox, int devid, int size)
1433 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
1437 otx2_mbox_req_init(uint16_t mbox_id, void *msghdr)
1439 struct mbox_msghdr *hdr = msghdr;
1441 hdr->sig = OTX2_MBOX_REQ_SIG;
1442 hdr->ver = OTX2_MBOX_VERSION;
1448 otx2_mbox_rsp_init(uint16_t mbox_id, void *msghdr)
1450 struct mbox_msghdr *hdr = msghdr;
1452 hdr->sig = OTX2_MBOX_RSP_SIG;
1453 hdr->rc = -ETIMEDOUT;
1458 otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid)
1460 struct otx2_mbox_dev *mdev = &mbox->dev[devid];
1463 rte_spinlock_lock(&mdev->mbox_lock);
1464 ret = mdev->num_msgs != 0;
1465 rte_spinlock_unlock(&mdev->mbox_lock);
1471 otx2_mbox_process(struct otx2_mbox *mbox)
1473 otx2_mbox_msg_send(mbox, 0);
1474 return otx2_mbox_get_rsp(mbox, 0, NULL);
1478 otx2_mbox_process_msg(struct otx2_mbox *mbox, void **msg)
1480 otx2_mbox_msg_send(mbox, 0);
1481 return otx2_mbox_get_rsp(mbox, 0, msg);
1485 otx2_mbox_process_tmo(struct otx2_mbox *mbox, uint32_t tmo)
1487 otx2_mbox_msg_send(mbox, 0);
1488 return otx2_mbox_get_rsp_tmo(mbox, 0, NULL, tmo);
1492 otx2_mbox_process_msg_tmo(struct otx2_mbox *mbox, void **msg, uint32_t tmo)
1494 otx2_mbox_msg_send(mbox, 0);
1495 return otx2_mbox_get_rsp_tmo(mbox, 0, msg, tmo);
1498 int otx2_send_ready_msg(struct otx2_mbox *mbox, uint16_t *pf_func /* out */);
1499 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, uint16_t pf_func,
1502 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
1503 static inline struct _req_type \
1504 *otx2_mbox_alloc_msg_ ## _fn_name(struct otx2_mbox *mbox) \
1506 struct _req_type *req; \
1508 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \
1509 mbox, 0, sizeof(struct _req_type), \
1510 sizeof(struct _rsp_type)); \
1514 req->hdr.sig = OTX2_MBOX_REQ_SIG; \
1515 req->hdr.id = _id; \
1516 otx2_mbox_dbg("id=0x%x (%s)", \
1517 req->hdr.id, otx2_mbox_id2name(req->hdr.id)); \
1524 /* This is required for copy operations from device memory which do not work on
1525 * addresses which are unaligned to 16B. This is because of specific
1526 * optimizations to libc memcpy.
1528 static inline volatile void *
1529 otx2_mbox_memcpy(volatile void *d, const volatile void *s, size_t l)
1531 const volatile uint8_t *sb;
1532 volatile uint8_t *db;
1537 db = (volatile uint8_t *)d;
1538 sb = (const volatile uint8_t *)s;
1539 for (i = 0; i < l; i++)
1544 /* This is required for memory operations from device memory which do not
1545 * work on addresses which are unaligned to 16B. This is because of specific
1546 * optimizations to libc memset.
1549 otx2_mbox_memset(volatile void *d, uint8_t val, size_t l)
1551 volatile uint8_t *db;
1556 db = (volatile uint8_t *)d;
1557 for (i = 0; i < l; i++)
1561 #endif /* __OTX2_MBOX_H__ */