1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2019 Marvell International Ltd.
5 #ifndef __OTX2_MBOX_H__
6 #define __OTX2_MBOX_H__
11 #include <rte_ether.h>
12 #include <rte_spinlock.h>
14 #include <otx2_common.h>
16 #define SZ_64K (64ULL * 1024ULL)
17 #define SZ_1K (1ULL * 1024ULL)
18 #define MBOX_SIZE SZ_64K
20 /* AF/PF: PF initiated, PF/VF VF initiated */
21 #define MBOX_DOWN_RX_START 0
22 #define MBOX_DOWN_RX_SIZE (46 * SZ_1K)
23 #define MBOX_DOWN_TX_START (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
24 #define MBOX_DOWN_TX_SIZE (16 * SZ_1K)
25 /* AF/PF: AF initiated, PF/VF PF initiated */
26 #define MBOX_UP_RX_START (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
27 #define MBOX_UP_RX_SIZE SZ_1K
28 #define MBOX_UP_TX_START (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
29 #define MBOX_UP_TX_SIZE SZ_1K
31 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
32 # error "Incorrect mailbox area sizes"
35 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
37 #define MBOX_RSP_TIMEOUT 3000 /* Time to wait for mbox response in ms */
39 #define MBOX_MSG_ALIGN 16 /* Align mbox msg start to 16bytes */
41 /* Mailbox directions */
42 #define MBOX_DIR_AFPF 0 /* AF replies to PF */
43 #define MBOX_DIR_PFAF 1 /* PF sends messages to AF */
44 #define MBOX_DIR_PFVF 2 /* PF replies to VF */
45 #define MBOX_DIR_VFPF 3 /* VF sends messages to PF */
46 #define MBOX_DIR_AFPF_UP 4 /* AF sends messages to PF */
47 #define MBOX_DIR_PFAF_UP 5 /* PF replies to AF */
48 #define MBOX_DIR_PFVF_UP 6 /* PF sends messages to VF */
49 #define MBOX_DIR_VFPF_UP 7 /* VF replies to PF */
51 /* Device memory does not support unaligned access, instruct compiler to
52 * not optimize the memory access when working with mailbox memory.
54 #define __otx2_io volatile
56 struct otx2_mbox_dev {
57 void *mbase; /* This dev's mbox region */
58 rte_spinlock_t mbox_lock;
59 uint16_t msg_size; /* Total msg size to be sent */
60 uint16_t rsp_size; /* Total rsp size to be sure the reply is ok */
61 uint16_t num_msgs; /* No of msgs sent or waiting for response */
62 uint16_t msgs_acked; /* No of msgs for which response is received */
66 uintptr_t hwbase; /* Mbox region advertised by HW */
67 uintptr_t reg_base;/* CSR base for this dev */
68 uint64_t trigger; /* Trigger mbox notification */
69 uint16_t tr_shift; /* Mbox trigger shift */
70 uint64_t rx_start; /* Offset of Rx region in mbox memory */
71 uint64_t tx_start; /* Offset of Tx region in mbox memory */
72 uint16_t rx_size; /* Size of Rx region */
73 uint16_t tx_size; /* Size of Tx region */
74 uint16_t ndevs; /* The number of peers */
75 struct otx2_mbox_dev *dev;
76 uint64_t intr_offset; /* Offset to interrupt register */
79 /* Header which precedes all mbox messages */
81 uint64_t __otx2_io msg_size; /* Total msgs size embedded */
82 uint16_t __otx2_io num_msgs; /* No of msgs embedded */
85 /* Header which precedes every msg and is also part of it */
87 uint16_t __otx2_io pcifunc; /* Who's sending this msg */
88 uint16_t __otx2_io id; /* Mbox message ID */
89 #define OTX2_MBOX_REQ_SIG (0xdead)
90 #define OTX2_MBOX_RSP_SIG (0xbeef)
91 /* Signature, for validating corrupted msgs */
92 uint16_t __otx2_io sig;
93 #define OTX2_MBOX_VERSION (0x0004)
94 /* Version of msg's structure for this ID */
95 uint16_t __otx2_io ver;
96 /* Offset of next msg within mailbox region */
97 uint16_t __otx2_io next_msgoff;
98 int __otx2_io rc; /* Msg processed response code */
101 /* Mailbox message types */
102 #define MBOX_MSG_MASK 0xFFFF
103 #define MBOX_MSG_INVALID 0xFFFE
104 #define MBOX_MSG_MAX 0xFFFF
106 #define MBOX_MESSAGES \
107 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
108 M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
109 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach_req, msg_rsp)\
110 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach_req, msg_rsp)\
111 M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
112 M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
113 M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
114 M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
115 M(GET_HW_CAP, 0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
116 M(NDC_SYNC_OP, 0x009, ndc_sync_op, ndc_sync_op, msg_rsp) \
117 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
118 M(CGX_START_RXTX, 0x200, cgx_start_rxtx, msg_req, msg_rsp) \
119 M(CGX_STOP_RXTX, 0x201, cgx_stop_rxtx, msg_req, msg_rsp) \
120 M(CGX_STATS, 0x202, cgx_stats, msg_req, cgx_stats_rsp) \
121 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get,\
122 cgx_mac_addr_set_or_get) \
123 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get,\
124 cgx_mac_addr_set_or_get) \
125 M(CGX_PROMISC_ENABLE, 0x205, cgx_promisc_enable, msg_req, msg_rsp) \
126 M(CGX_PROMISC_DISABLE, 0x206, cgx_promisc_disable, msg_req, msg_rsp) \
127 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp) \
128 M(CGX_STOP_LINKEVENTS, 0x208, cgx_stop_linkevents, msg_req, msg_rsp) \
129 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg)\
130 M(CGX_INTLBK_ENABLE, 0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
131 M(CGX_INTLBK_DISABLE, 0x20B, cgx_intlbk_disable, msg_req, msg_rsp) \
132 M(CGX_PTP_RX_ENABLE, 0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
133 M(CGX_PTP_RX_DISABLE, 0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp) \
134 M(CGX_CFG_PAUSE_FRM, 0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg, \
136 M(CGX_FW_DATA_GET, 0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
137 M(CGX_FEC_SET, 0x210, cgx_set_fec_param, fec_mode, fec_mode) \
138 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req, \
139 cgx_mac_addr_add_rsp) \
140 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req, \
142 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req, \
143 cgx_max_dmac_entries_get_rsp) \
144 M(CGX_SET_LINK_STATE, 0x214, cgx_set_link_state, \
145 cgx_set_link_state_msg, msg_rsp) \
146 M(CGX_GET_PHY_MOD_TYPE, 0x215, cgx_get_phy_mod_type, msg_req, \
148 M(CGX_SET_PHY_MOD_TYPE, 0x216, cgx_set_phy_mod_type, cgx_phy_mod_type, \
150 M(CGX_FEC_STATS, 0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
151 M(CGX_SET_LINK_MODE, 0x218, cgx_set_link_mode, cgx_set_link_mode_req,\
152 cgx_set_link_mode_rsp) \
153 /* NPA mbox IDs (range 0x400 - 0x5FF) */ \
154 M(NPA_LF_ALLOC, 0x400, npa_lf_alloc, npa_lf_alloc_req, \
156 M(NPA_LF_FREE, 0x401, npa_lf_free, msg_req, msg_rsp) \
157 M(NPA_AQ_ENQ, 0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp)\
158 M(NPA_HWCTX_DISABLE, 0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
159 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */ \
160 M(SSO_LF_ALLOC, 0x600, sso_lf_alloc, sso_lf_alloc_req, \
162 M(SSO_LF_FREE, 0x601, sso_lf_free, sso_lf_free_req, msg_rsp) \
163 M(SSOW_LF_ALLOC, 0x602, ssow_lf_alloc, ssow_lf_alloc_req, msg_rsp)\
164 M(SSOW_LF_FREE, 0x603, ssow_lf_free, ssow_lf_free_req, msg_rsp) \
165 M(SSO_HW_SETCONFIG, 0x604, sso_hw_setconfig, sso_hw_setconfig, \
167 M(SSO_GRP_SET_PRIORITY, 0x605, sso_grp_set_priority, sso_grp_priority, \
169 M(SSO_GRP_GET_PRIORITY, 0x606, sso_grp_get_priority, sso_info_req, \
171 M(SSO_WS_CACHE_INV, 0x607, sso_ws_cache_inv, msg_req, msg_rsp) \
172 M(SSO_GRP_QOS_CONFIG, 0x608, sso_grp_qos_config, sso_grp_qos_cfg, \
174 M(SSO_GRP_GET_STATS, 0x609, sso_grp_get_stats, sso_info_req, \
176 M(SSO_HWS_GET_STATS, 0x610, sso_hws_get_stats, sso_info_req, \
178 /* TIM mbox IDs (range 0x800 - 0x9FF) */ \
179 M(TIM_LF_ALLOC, 0x800, tim_lf_alloc, tim_lf_alloc_req, \
181 M(TIM_LF_FREE, 0x801, tim_lf_free, tim_ring_req, msg_rsp) \
182 M(TIM_CONFIG_RING, 0x802, tim_config_ring, tim_config_req, msg_rsp)\
183 M(TIM_ENABLE_RING, 0x803, tim_enable_ring, tim_ring_req, \
185 M(TIM_DISABLE_RING, 0x804, tim_disable_ring, tim_ring_req, msg_rsp) \
186 /* CPT mbox IDs (range 0xA00 - 0xBFF) */ \
187 M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \
188 cpt_lf_alloc_rsp_msg) \
189 M(CPT_LF_FREE, 0xA01, cpt_lf_free, msg_req, msg_rsp) \
190 M(CPT_RD_WR_REGISTER, 0xA02, cpt_rd_wr_register, cpt_rd_wr_reg_msg, \
192 M(CPT_SET_CRYPTO_GRP, 0xA03, cpt_set_crypto_grp, \
193 cpt_set_crypto_grp_req_msg, \
195 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg, \
196 cpt_inline_ipsec_cfg_msg, msg_rsp) \
197 M(CPT_RX_INLINE_LF_CFG, 0xBFE, cpt_rx_inline_lf_cfg, \
198 cpt_rx_inline_lf_cfg_msg, msg_rsp) \
199 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */ \
200 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, \
201 npc_mcam_alloc_entry_req, \
202 npc_mcam_alloc_entry_rsp) \
203 M(NPC_MCAM_FREE_ENTRY, 0x6001, npc_mcam_free_entry, \
204 npc_mcam_free_entry_req, msg_rsp) \
205 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry, \
206 npc_mcam_write_entry_req, msg_rsp) \
207 M(NPC_MCAM_ENA_ENTRY, 0x6003, npc_mcam_ena_entry, \
208 npc_mcam_ena_dis_entry_req, msg_rsp) \
209 M(NPC_MCAM_DIS_ENTRY, 0x6004, npc_mcam_dis_entry, \
210 npc_mcam_ena_dis_entry_req, msg_rsp) \
211 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, \
212 npc_mcam_shift_entry_req, \
213 npc_mcam_shift_entry_rsp) \
214 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter, \
215 npc_mcam_alloc_counter_req, \
216 npc_mcam_alloc_counter_rsp) \
217 M(NPC_MCAM_FREE_COUNTER, 0x6007, npc_mcam_free_counter, \
218 npc_mcam_oper_counter_req, \
220 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter, \
221 npc_mcam_unmap_counter_req, \
223 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter, \
224 npc_mcam_oper_counter_req, \
226 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats, \
227 npc_mcam_oper_counter_req, \
228 npc_mcam_oper_counter_rsp) \
229 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry,\
230 npc_mcam_alloc_and_write_entry_req, \
231 npc_mcam_alloc_and_write_entry_rsp) \
232 M(NPC_GET_KEX_CFG, 0x600c, npc_get_kex_cfg, msg_req, \
233 npc_get_kex_cfg_rsp) \
234 M(NPC_INSTALL_FLOW, 0x600d, npc_install_flow, \
235 npc_install_flow_req, \
236 npc_install_flow_rsp) \
237 M(NPC_DELETE_FLOW, 0x600e, npc_delete_flow, \
238 npc_delete_flow_req, msg_rsp) \
239 M(NPC_MCAM_READ_ENTRY, 0x600f, npc_mcam_read_entry, \
240 npc_mcam_read_entry_req, \
241 npc_mcam_read_entry_rsp) \
242 M(NPC_SET_PKIND, 0x6010, npc_set_pkind, \
245 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */ \
246 M(NIX_LF_ALLOC, 0x8000, nix_lf_alloc, nix_lf_alloc_req, \
248 M(NIX_LF_FREE, 0x8001, nix_lf_free, nix_lf_free_req, msg_rsp) \
249 M(NIX_AQ_ENQ, 0x8002, nix_aq_enq, nix_aq_enq_req, \
251 M(NIX_HWCTX_DISABLE, 0x8003, nix_hwctx_disable, hwctx_disable_req, \
253 M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc, nix_txsch_alloc_req, \
254 nix_txsch_alloc_rsp) \
255 M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free, nix_txsch_free_req, \
257 M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_cfg, nix_txschq_config, \
259 M(NIX_STATS_RST, 0x8007, nix_stats_rst, msg_req, msg_rsp) \
260 M(NIX_VTAG_CFG, 0x8008, nix_vtag_cfg, nix_vtag_config, msg_rsp) \
261 M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, \
262 nix_rss_flowkey_cfg, \
263 nix_rss_flowkey_cfg_rsp) \
264 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, \
266 M(NIX_SET_RX_MODE, 0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp) \
267 M(NIX_SET_HW_FRS, 0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp) \
268 M(NIX_LF_START_RX, 0x800d, nix_lf_start_rx, msg_req, msg_rsp) \
269 M(NIX_LF_STOP_RX, 0x800e, nix_lf_stop_rx, msg_req, msg_rsp) \
270 M(NIX_MARK_FORMAT_CFG, 0x800f, nix_mark_format_cfg, \
271 nix_mark_format_cfg, \
272 nix_mark_format_cfg_rsp) \
273 M(NIX_SET_RX_CFG, 0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp) \
274 M(NIX_LSO_FORMAT_CFG, 0x8011, nix_lso_format_cfg, nix_lso_format_cfg, \
275 nix_lso_format_cfg_rsp) \
276 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, \
278 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, \
280 M(NIX_SET_VLAN_TPID, 0x8015, nix_set_vlan_tpid, nix_set_vlan_tpid, \
282 M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \
284 M(NIX_BP_DISABLE, 0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp)\
285 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, \
286 nix_get_mac_addr_rsp) \
287 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg, \
288 nix_inline_ipsec_cfg, msg_rsp) \
289 M(NIX_INLINE_IPSEC_LF_CFG, \
290 0x801a, nix_inline_ipsec_lf_cfg, \
291 nix_inline_ipsec_lf_cfg, msg_rsp)
293 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
294 #define MBOX_UP_CGX_MESSAGES \
295 M(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, \
297 M(CGX_PTP_RX_INFO, 0xC01, cgx_ptp_rx_info, cgx_ptp_rx_info_msg, \
301 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
307 /* Mailbox message formats */
309 #define RVU_DEFAULT_PF_FUNC 0xFFFF
311 /* Generic request msg used for those mbox messages which
312 * don't send any data in the request.
315 struct mbox_msghdr hdr;
318 /* Generic response msg used a ack or response for those mbox
319 * messages which doesn't have a specific rsp msg format.
322 struct mbox_msghdr hdr;
325 /* RVU mailbox error codes
329 RVU_INVALID_VF_ID = -256,
332 struct ready_msg_rsp {
333 struct mbox_msghdr hdr;
334 uint16_t __otx2_io sclk_feq; /* SCLK frequency */
335 uint16_t __otx2_io rclk_freq; /* RCLK frequency */
338 /* Struct to set pkind */
339 struct npc_set_pkind {
340 struct mbox_msghdr hdr;
341 #define OTX2_PRIV_FLAGS_DEFAULT BIT_ULL(0)
342 #define OTX2_PRIV_FLAGS_EDSA BIT_ULL(1)
343 #define OTX2_PRIV_FLAGS_HIGIG BIT_ULL(2)
344 #define OTX2_PRIV_FLAGS_CUSTOM BIT_ULL(63)
345 uint64_t __otx2_io mode;
346 #define PKIND_TX BIT_ULL(0)
347 #define PKIND_RX BIT_ULL(1)
348 uint8_t __otx2_io dir;
349 uint8_t __otx2_io pkind; /* valid only in case custom flag */
352 /* Structure for requesting resource provisioning.
353 * 'modify' flag to be used when either requesting more
354 * or detach partial of a certain resource type.
355 * Rest of the fields specify how many of what type to
358 struct rsrc_attach_req {
359 struct mbox_msghdr hdr;
360 uint8_t __otx2_io modify:1;
361 uint8_t __otx2_io npalf:1;
362 uint8_t __otx2_io nixlf:1;
363 uint16_t __otx2_io sso;
364 uint16_t __otx2_io ssow;
365 uint16_t __otx2_io timlfs;
366 uint16_t __otx2_io cptlfs;
369 /* Structure for relinquishing resources.
370 * 'partial' flag to be used when relinquishing all resources
371 * but only of a certain type. If not set, all resources of all
372 * types provisioned to the RVU function will be detached.
374 struct rsrc_detach_req {
375 struct mbox_msghdr hdr;
376 uint8_t __otx2_io partial:1;
377 uint8_t __otx2_io npalf:1;
378 uint8_t __otx2_io nixlf:1;
379 uint8_t __otx2_io sso:1;
380 uint8_t __otx2_io ssow:1;
381 uint8_t __otx2_io timlfs:1;
382 uint8_t __otx2_io cptlfs:1;
385 /* NIX Transmit schedulers */
386 #define NIX_TXSCH_LVL_SMQ 0x0
387 #define NIX_TXSCH_LVL_MDQ 0x0
388 #define NIX_TXSCH_LVL_TL4 0x1
389 #define NIX_TXSCH_LVL_TL3 0x2
390 #define NIX_TXSCH_LVL_TL2 0x3
391 #define NIX_TXSCH_LVL_TL1 0x4
392 #define NIX_TXSCH_LVL_CNT 0x5
395 * Number of resources available to the caller.
396 * In reply to MBOX_MSG_FREE_RSRC_CNT.
398 struct free_rsrcs_rsp {
399 struct mbox_msghdr hdr;
400 uint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT];
401 uint16_t __otx2_io sso;
402 uint16_t __otx2_io tim;
403 uint16_t __otx2_io ssow;
404 uint16_t __otx2_io cpt;
405 uint8_t __otx2_io npa;
406 uint8_t __otx2_io nix;
409 #define MSIX_VECTOR_INVALID 0xFFFF
410 #define MAX_RVU_BLKLF_CNT 256
412 struct msix_offset_rsp {
413 struct mbox_msghdr hdr;
414 uint16_t __otx2_io npa_msixoff;
415 uint16_t __otx2_io nix_msixoff;
416 uint8_t __otx2_io sso;
417 uint8_t __otx2_io ssow;
418 uint8_t __otx2_io timlfs;
419 uint8_t __otx2_io cptlfs;
420 uint16_t __otx2_io sso_msixoff[MAX_RVU_BLKLF_CNT];
421 uint16_t __otx2_io ssow_msixoff[MAX_RVU_BLKLF_CNT];
422 uint16_t __otx2_io timlf_msixoff[MAX_RVU_BLKLF_CNT];
423 uint16_t __otx2_io cptlf_msixoff[MAX_RVU_BLKLF_CNT];
426 /* CGX mbox message formats */
428 struct cgx_stats_rsp {
429 struct mbox_msghdr hdr;
430 #define CGX_RX_STATS_COUNT 13
431 #define CGX_TX_STATS_COUNT 18
432 uint64_t __otx2_io rx_stats[CGX_RX_STATS_COUNT];
433 uint64_t __otx2_io tx_stats[CGX_TX_STATS_COUNT];
436 struct cgx_fec_stats_rsp {
437 struct mbox_msghdr hdr;
438 uint64_t __otx2_io fec_corr_blks;
439 uint64_t __otx2_io fec_uncorr_blks;
441 /* Structure for requesting the operation for
442 * setting/getting mac address in the CGX interface
444 struct cgx_mac_addr_set_or_get {
445 struct mbox_msghdr hdr;
446 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
449 /* Structure for requesting the operation to
450 * add DMAC filter entry into CGX interface
452 struct cgx_mac_addr_add_req {
453 struct mbox_msghdr hdr;
454 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
457 /* Structure for response against the operation to
458 * add DMAC filter entry into CGX interface
460 struct cgx_mac_addr_add_rsp {
461 struct mbox_msghdr hdr;
462 uint8_t __otx2_io index;
465 /* Structure for requesting the operation to
466 * delete DMAC filter entry from CGX interface
468 struct cgx_mac_addr_del_req {
469 struct mbox_msghdr hdr;
470 uint8_t __otx2_io index;
473 /* Structure for response against the operation to
474 * get maximum supported DMAC filter entries
476 struct cgx_max_dmac_entries_get_rsp {
477 struct mbox_msghdr hdr;
478 uint8_t __otx2_io max_dmac_filters;
481 struct cgx_link_user_info {
482 uint64_t __otx2_io link_up:1;
483 uint64_t __otx2_io full_duplex:1;
484 uint64_t __otx2_io lmac_type_id:4;
485 uint64_t __otx2_io speed:20; /* speed in Mbps */
486 uint64_t __otx2_io an:1; /* AN supported or not */
487 uint64_t __otx2_io fec:2; /* FEC type if enabled else 0 */
488 uint64_t __otx2_io port:8;
489 #define LMACTYPE_STR_LEN 16
490 char lmac_type[LMACTYPE_STR_LEN];
493 struct cgx_link_info_msg {
494 struct mbox_msghdr hdr;
495 struct cgx_link_user_info link_info;
498 struct cgx_ptp_rx_info_msg {
499 struct mbox_msghdr hdr;
500 uint8_t __otx2_io ptp_en;
503 struct cgx_pause_frm_cfg {
504 struct mbox_msghdr hdr;
505 uint8_t __otx2_io set;
506 /* set = 1 if the request is to config pause frames */
507 /* set = 0 if the request is to fetch pause frames config */
508 uint8_t __otx2_io rx_pause;
509 uint8_t __otx2_io tx_pause;
512 struct sfp_eeprom_s {
513 #define SFP_EEPROM_SIZE 256
514 uint16_t __otx2_io sff_id;
515 uint8_t __otx2_io buf[SFP_EEPROM_SIZE];
516 uint64_t __otx2_io reserved;
526 uint64_t __otx2_io can_change_mod_type : 1;
527 uint64_t __otx2_io mod_type : 1;
530 struct cgx_lmac_fwdata_s {
531 uint16_t __otx2_io rw_valid;
532 uint64_t __otx2_io supported_fec;
533 uint64_t __otx2_io supported_an;
534 uint64_t __otx2_io supported_link_modes;
535 /* Only applicable if AN is supported */
536 uint64_t __otx2_io advertised_fec;
537 uint64_t __otx2_io advertised_link_modes;
538 /* Only applicable if SFP/QSFP slot is present */
539 struct sfp_eeprom_s sfp_eeprom;
541 #define LMAC_FWDATA_RESERVED_MEM 1023
542 uint64_t __otx2_io reserved[LMAC_FWDATA_RESERVED_MEM];
546 struct mbox_msghdr hdr;
547 struct cgx_lmac_fwdata_s fwdata;
551 struct mbox_msghdr hdr;
555 struct cgx_set_link_state_msg {
556 struct mbox_msghdr hdr;
557 uint8_t __otx2_io enable;
560 struct cgx_phy_mod_type {
561 struct mbox_msghdr hdr;
565 struct cgx_set_link_mode_args {
566 uint32_t __otx2_io speed;
567 uint8_t __otx2_io duplex;
568 uint8_t __otx2_io an;
569 uint8_t __otx2_io ports;
570 uint64_t __otx2_io mode;
573 struct cgx_set_link_mode_req {
574 struct mbox_msghdr hdr;
575 struct cgx_set_link_mode_args args;
578 struct cgx_set_link_mode_rsp {
579 struct mbox_msghdr hdr;
580 int __otx2_io status;
582 /* NPA mbox message formats */
584 /* NPA mailbox error codes
588 NPA_AF_ERR_PARAM = -301,
589 NPA_AF_ERR_AQ_FULL = -302,
590 NPA_AF_ERR_AQ_ENQUEUE = -303,
591 NPA_AF_ERR_AF_LF_INVALID = -304,
592 NPA_AF_ERR_AF_LF_ALLOC = -305,
593 NPA_AF_ERR_LF_RESET = -306,
596 #define NPA_AURA_SZ_0 0
597 #define NPA_AURA_SZ_128 1
598 #define NPA_AURA_SZ_256 2
599 #define NPA_AURA_SZ_512 3
600 #define NPA_AURA_SZ_1K 4
601 #define NPA_AURA_SZ_2K 5
602 #define NPA_AURA_SZ_4K 6
603 #define NPA_AURA_SZ_8K 7
604 #define NPA_AURA_SZ_16K 8
605 #define NPA_AURA_SZ_32K 9
606 #define NPA_AURA_SZ_64K 10
607 #define NPA_AURA_SZ_128K 11
608 #define NPA_AURA_SZ_256K 12
609 #define NPA_AURA_SZ_512K 13
610 #define NPA_AURA_SZ_1M 14
611 #define NPA_AURA_SZ_MAX 15
613 /* For NPA LF context alloc and init */
614 struct npa_lf_alloc_req {
615 struct mbox_msghdr hdr;
617 int __otx2_io aura_sz; /* No of auras. See NPA_AURA_SZ_* */
618 uint32_t __otx2_io nr_pools; /* No of pools */
619 uint64_t __otx2_io way_mask;
622 struct npa_lf_alloc_rsp {
623 struct mbox_msghdr hdr;
624 uint32_t __otx2_io stack_pg_ptrs; /* No of ptrs per stack page */
625 uint32_t __otx2_io stack_pg_bytes; /* Size of stack page */
626 uint16_t __otx2_io qints; /* NPA_AF_CONST::QINTS */
629 /* NPA AQ enqueue msg */
630 struct npa_aq_enq_req {
631 struct mbox_msghdr hdr;
632 uint32_t __otx2_io aura_id;
633 uint8_t __otx2_io ctype;
634 uint8_t __otx2_io op;
636 /* Valid when op == WRITE/INIT and ctype == AURA.
637 * LF fills the pool_id in aura.pool_addr. AF will translate
638 * the pool_id to pool context pointer.
640 __otx2_io struct npa_aura_s aura;
641 /* Valid when op == WRITE/INIT and ctype == POOL */
642 __otx2_io struct npa_pool_s pool;
644 /* Mask data when op == WRITE (1=write, 0=don't write) */
646 /* Valid when op == WRITE and ctype == AURA */
647 __otx2_io struct npa_aura_s aura_mask;
648 /* Valid when op == WRITE and ctype == POOL */
649 __otx2_io struct npa_pool_s pool_mask;
653 struct npa_aq_enq_rsp {
654 struct mbox_msghdr hdr;
656 /* Valid when op == READ and ctype == AURA */
657 __otx2_io struct npa_aura_s aura;
658 /* Valid when op == READ and ctype == POOL */
659 __otx2_io struct npa_pool_s pool;
663 /* Disable all contexts of type 'ctype' */
664 struct hwctx_disable_req {
665 struct mbox_msghdr hdr;
666 uint8_t __otx2_io ctype;
669 /* NIX mbox message formats */
671 /* NIX mailbox error codes
675 NIX_AF_ERR_PARAM = -401,
676 NIX_AF_ERR_AQ_FULL = -402,
677 NIX_AF_ERR_AQ_ENQUEUE = -403,
678 NIX_AF_ERR_AF_LF_INVALID = -404,
679 NIX_AF_ERR_AF_LF_ALLOC = -405,
680 NIX_AF_ERR_TLX_ALLOC_FAIL = -406,
681 NIX_AF_ERR_TLX_INVALID = -407,
682 NIX_AF_ERR_RSS_SIZE_INVALID = -408,
683 NIX_AF_ERR_RSS_GRPS_INVALID = -409,
684 NIX_AF_ERR_FRS_INVALID = -410,
685 NIX_AF_ERR_RX_LINK_INVALID = -411,
686 NIX_AF_INVAL_TXSCHQ_CFG = -412,
687 NIX_AF_SMQ_FLUSH_FAILED = -413,
688 NIX_AF_ERR_LF_RESET = -414,
689 NIX_AF_ERR_RSS_NOSPC_FIELD = -415,
690 NIX_AF_ERR_RSS_NOSPC_ALGO = -416,
691 NIX_AF_ERR_MARK_CFG_FAIL = -417,
692 NIX_AF_ERR_LSO_CFG_FAIL = -418,
693 NIX_AF_INVAL_NPA_PF_FUNC = -419,
694 NIX_AF_INVAL_SSO_PF_FUNC = -420,
695 NIX_AF_ERR_TX_VTAG_NOSPC = -421,
698 /* For NIX LF context alloc and init */
699 struct nix_lf_alloc_req {
700 struct mbox_msghdr hdr;
702 uint32_t __otx2_io rq_cnt; /* No of receive queues */
703 uint32_t __otx2_io sq_cnt; /* No of send queues */
704 uint32_t __otx2_io cq_cnt; /* No of completion queues */
705 uint8_t __otx2_io xqe_sz;
706 uint16_t __otx2_io rss_sz;
707 uint8_t __otx2_io rss_grps;
708 uint16_t __otx2_io npa_func;
709 /* RVU_DEFAULT_PF_FUNC == default pf_func associated with lf */
710 uint16_t __otx2_io sso_func;
711 uint64_t __otx2_io rx_cfg; /* See NIX_AF_LF(0..127)_RX_CFG */
712 uint64_t __otx2_io way_mask;
713 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
717 struct nix_lf_alloc_rsp {
718 struct mbox_msghdr hdr;
719 uint16_t __otx2_io sqb_size;
720 uint16_t __otx2_io rx_chan_base;
721 uint16_t __otx2_io tx_chan_base;
722 uint8_t __otx2_io rx_chan_cnt; /* Total number of RX channels */
723 uint8_t __otx2_io tx_chan_cnt; /* Total number of TX channels */
724 uint8_t __otx2_io lso_tsov4_idx;
725 uint8_t __otx2_io lso_tsov6_idx;
726 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
727 uint8_t __otx2_io lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
728 uint8_t __otx2_io lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
729 uint16_t __otx2_io cints; /* NIX_AF_CONST2::CINTS */
730 uint16_t __otx2_io qints; /* NIX_AF_CONST2::QINTS */
731 uint8_t __otx2_io hw_rx_tstamp_en; /*set if rx timestamping enabled */
734 struct nix_lf_free_req {
735 struct mbox_msghdr hdr;
736 #define NIX_LF_DISABLE_FLOWS 0x1
737 uint64_t __otx2_io flags;
740 /* NIX AQ enqueue msg */
741 struct nix_aq_enq_req {
742 struct mbox_msghdr hdr;
743 uint32_t __otx2_io qidx;
744 uint8_t __otx2_io ctype;
745 uint8_t __otx2_io op;
747 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RQ */
748 __otx2_io struct nix_rq_ctx_s rq;
749 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_SQ */
750 __otx2_io struct nix_sq_ctx_s sq;
751 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_CQ */
752 __otx2_io struct nix_cq_ctx_s cq;
753 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_RSS */
754 __otx2_io struct nix_rsse_s rss;
755 /* Valid when op == WRITE/INIT and ctype == NIX_AQ_CTYPE_MCE */
756 __otx2_io struct nix_rx_mce_s mce;
758 /* Mask data when op == WRITE (1=write, 0=don't write) */
760 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RQ */
761 __otx2_io struct nix_rq_ctx_s rq_mask;
762 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_SQ */
763 __otx2_io struct nix_sq_ctx_s sq_mask;
764 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_CQ */
765 __otx2_io struct nix_cq_ctx_s cq_mask;
766 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_RSS */
767 __otx2_io struct nix_rsse_s rss_mask;
768 /* Valid when op == WRITE and ctype == NIX_AQ_CTYPE_MCE */
769 __otx2_io struct nix_rx_mce_s mce_mask;
773 struct nix_aq_enq_rsp {
774 struct mbox_msghdr hdr;
776 __otx2_io struct nix_rq_ctx_s rq;
777 __otx2_io struct nix_sq_ctx_s sq;
778 __otx2_io struct nix_cq_ctx_s cq;
779 __otx2_io struct nix_rsse_s rss;
780 __otx2_io struct nix_rx_mce_s mce;
784 /* Tx scheduler/shaper mailbox messages */
786 #define MAX_TXSCHQ_PER_FUNC 128
788 struct nix_txsch_alloc_req {
789 struct mbox_msghdr hdr;
790 /* Scheduler queue count request at each level */
791 uint16_t __otx2_io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
792 uint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
795 struct nix_txsch_alloc_rsp {
796 struct mbox_msghdr hdr;
797 /* Scheduler queue count allocated at each level */
798 uint16_t __otx2_io schq_contig[NIX_TXSCH_LVL_CNT]; /* Contig. queues */
799 uint16_t __otx2_io schq[NIX_TXSCH_LVL_CNT]; /* Non-Contig. queues */
800 /* Scheduler queue list allocated at each level */
802 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
803 uint16_t __otx2_io schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
804 /* Traffic aggregation scheduler level */
805 uint8_t __otx2_io aggr_level;
806 /* Aggregation lvl's RR_PRIO config */
807 uint8_t __otx2_io aggr_lvl_rr_prio;
808 /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
809 uint8_t __otx2_io link_cfg_lvl;
812 struct nix_txsch_free_req {
813 struct mbox_msghdr hdr;
814 #define TXSCHQ_FREE_ALL BIT_ULL(0)
815 uint16_t __otx2_io flags;
816 /* Scheduler queue level to be freed */
817 uint16_t __otx2_io schq_lvl;
818 /* List of scheduler queues to be freed */
819 uint16_t __otx2_io schq;
822 struct nix_txschq_config {
823 struct mbox_msghdr hdr;
824 uint8_t __otx2_io lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
825 #define TXSCHQ_IDX_SHIFT 16
826 #define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1)
827 #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
828 uint8_t __otx2_io num_regs;
829 #define MAX_REGS_PER_MBOX_MSG 20
830 uint64_t __otx2_io reg[MAX_REGS_PER_MBOX_MSG];
831 uint64_t __otx2_io regval[MAX_REGS_PER_MBOX_MSG];
834 struct nix_vtag_config {
835 struct mbox_msghdr hdr;
836 /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
837 uint8_t __otx2_io vtag_size;
838 /* cfg_type is '0' for tx vlan cfg
839 * cfg_type is '1' for rx vlan cfg
841 uint8_t __otx2_io cfg_type;
843 /* Valid when cfg_type is '0' */
845 uint64_t __otx2_io vtag0;
846 uint64_t __otx2_io vtag1;
848 /* cfg_vtag0 & cfg_vtag1 fields are valid
849 * when free_vtag0 & free_vtag1 are '0's.
851 /* cfg_vtag0 = 1 to configure vtag0 */
852 uint8_t __otx2_io cfg_vtag0 :1;
853 /* cfg_vtag1 = 1 to configure vtag1 */
854 uint8_t __otx2_io cfg_vtag1 :1;
856 /* vtag0_idx & vtag1_idx are only valid when
857 * both cfg_vtag0 & cfg_vtag1 are '0's,
858 * these fields are used along with free_vtag0
859 * & free_vtag1 to free the nix lf's tx_vlan
862 * Denotes the indices of tx_vtag def registers
863 * that needs to be cleared and freed.
865 int __otx2_io vtag0_idx;
866 int __otx2_io vtag1_idx;
868 /* Free_vtag0 & free_vtag1 fields are valid
869 * when cfg_vtag0 & cfg_vtag1 are '0's.
871 /* Free_vtag0 = 1 clears vtag0 configuration
872 * vtag0_idx denotes the index to be cleared.
874 uint8_t __otx2_io free_vtag0 :1;
875 /* Free_vtag1 = 1 clears vtag1 configuration
876 * vtag1_idx denotes the index to be cleared.
878 uint8_t __otx2_io free_vtag1 :1;
881 /* Valid when cfg_type is '1' */
883 /* Rx vtag type index, valid values are in 0..7 range */
884 uint8_t __otx2_io vtag_type;
886 uint8_t __otx2_io strip_vtag :1;
887 /* Rx vtag capture */
888 uint8_t __otx2_io capture_vtag :1;
893 struct nix_vtag_config_rsp {
894 struct mbox_msghdr hdr;
895 /* Indices of tx_vtag def registers used to configure
896 * tx vtag0 & vtag1 headers, these indices are valid
897 * when nix_vtag_config mbox requested for vtag0 and/
898 * or vtag1 configuration.
900 int __otx2_io vtag0_idx;
901 int __otx2_io vtag1_idx;
904 struct nix_rss_flowkey_cfg {
905 struct mbox_msghdr hdr;
906 int __otx2_io mcam_index; /* MCAM entry index to modify */
907 uint32_t __otx2_io flowkey_cfg; /* Flowkey types selected */
908 #define FLOW_KEY_TYPE_PORT BIT(0)
909 #define FLOW_KEY_TYPE_IPV4 BIT(1)
910 #define FLOW_KEY_TYPE_IPV6 BIT(2)
911 #define FLOW_KEY_TYPE_TCP BIT(3)
912 #define FLOW_KEY_TYPE_UDP BIT(4)
913 #define FLOW_KEY_TYPE_SCTP BIT(5)
914 #define FLOW_KEY_TYPE_NVGRE BIT(6)
915 #define FLOW_KEY_TYPE_VXLAN BIT(7)
916 #define FLOW_KEY_TYPE_GENEVE BIT(8)
917 #define FLOW_KEY_TYPE_ETH_DMAC BIT(9)
918 #define FLOW_KEY_TYPE_IPV6_EXT BIT(10)
919 #define FLOW_KEY_TYPE_GTPU BIT(11)
920 #define FLOW_KEY_TYPE_INNR_IPV4 BIT(12)
921 #define FLOW_KEY_TYPE_INNR_IPV6 BIT(13)
922 #define FLOW_KEY_TYPE_INNR_TCP BIT(14)
923 #define FLOW_KEY_TYPE_INNR_UDP BIT(15)
924 #define FLOW_KEY_TYPE_INNR_SCTP BIT(16)
925 #define FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
926 #define FLOW_KEY_TYPE_L4_DST BIT(28)
927 #define FLOW_KEY_TYPE_L4_SRC BIT(29)
928 #define FLOW_KEY_TYPE_L3_DST BIT(30)
929 #define FLOW_KEY_TYPE_L3_SRC BIT(31)
930 uint8_t __otx2_io group; /* RSS context or group */
933 struct nix_rss_flowkey_cfg_rsp {
934 struct mbox_msghdr hdr;
935 uint8_t __otx2_io alg_idx; /* Selected algo index */
938 struct nix_set_mac_addr {
939 struct mbox_msghdr hdr;
940 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
943 struct nix_get_mac_addr_rsp {
944 struct mbox_msghdr hdr;
945 uint8_t __otx2_io mac_addr[RTE_ETHER_ADDR_LEN];
948 struct nix_mark_format_cfg {
949 struct mbox_msghdr hdr;
950 uint8_t __otx2_io offset;
951 uint8_t __otx2_io y_mask;
952 uint8_t __otx2_io y_val;
953 uint8_t __otx2_io r_mask;
954 uint8_t __otx2_io r_val;
957 struct nix_mark_format_cfg_rsp {
958 struct mbox_msghdr hdr;
959 uint8_t __otx2_io mark_format_idx;
962 struct nix_lso_format_cfg {
963 struct mbox_msghdr hdr;
964 uint64_t __otx2_io field_mask;
965 uint64_t __otx2_io fields[NIX_LSO_FIELD_MAX];
968 struct nix_lso_format_cfg_rsp {
969 struct mbox_msghdr hdr;
970 uint8_t __otx2_io lso_format_idx;
974 struct mbox_msghdr hdr;
975 #define NIX_RX_MODE_UCAST BIT(0)
976 #define NIX_RX_MODE_PROMISC BIT(1)
977 #define NIX_RX_MODE_ALLMULTI BIT(2)
978 uint16_t __otx2_io mode;
982 struct mbox_msghdr hdr;
983 #define NIX_RX_OL3_VERIFY BIT(0)
984 #define NIX_RX_OL4_VERIFY BIT(1)
985 uint8_t __otx2_io len_verify; /* Outer L3/L4 len check */
986 #define NIX_RX_CSUM_OL4_VERIFY BIT(0)
987 uint8_t __otx2_io csum_verify; /* Outer L4 checksum verification */
991 struct mbox_msghdr hdr;
992 uint8_t __otx2_io update_smq; /* Update SMQ's min/max lens */
993 uint8_t __otx2_io update_minlen; /* Set minlen also */
994 uint8_t __otx2_io sdp_link; /* Set SDP RX link */
995 uint16_t __otx2_io maxlen;
996 uint16_t __otx2_io minlen;
999 struct nix_set_vlan_tpid {
1000 struct mbox_msghdr hdr;
1001 #define NIX_VLAN_TYPE_INNER 0
1002 #define NIX_VLAN_TYPE_OUTER 1
1003 uint8_t __otx2_io vlan_type;
1004 uint16_t __otx2_io tpid;
1007 struct nix_bp_cfg_req {
1008 struct mbox_msghdr hdr;
1009 uint16_t __otx2_io chan_base; /* Starting channel number */
1010 uint8_t __otx2_io chan_cnt; /* Number of channels */
1011 uint8_t __otx2_io bpid_per_chan;
1012 /* bpid_per_chan = 0 assigns single bp id for range of channels */
1013 /* bpid_per_chan = 1 assigns separate bp id for each channel */
1016 /* PF can be mapped to either CGX or LBK interface,
1017 * so maximum 64 channels are possible.
1019 #define NIX_MAX_CHAN 64
1020 struct nix_bp_cfg_rsp {
1021 struct mbox_msghdr hdr;
1022 /* Channel and bpid mapping */
1023 uint16_t __otx2_io chan_bpid[NIX_MAX_CHAN];
1024 /* Number of channel for which bpids are assigned */
1025 uint8_t __otx2_io chan_cnt;
1028 /* Global NIX inline IPSec configuration */
1029 struct nix_inline_ipsec_cfg {
1030 struct mbox_msghdr hdr;
1031 uint32_t __otx2_io cpt_credit;
1033 uint8_t __otx2_io egrp;
1034 uint8_t __otx2_io opcode;
1037 uint16_t __otx2_io cpt_pf_func;
1038 uint8_t __otx2_io cpt_slot;
1040 uint8_t __otx2_io enable;
1043 /* Per NIX LF inline IPSec configuration */
1044 struct nix_inline_ipsec_lf_cfg {
1045 struct mbox_msghdr hdr;
1046 uint64_t __otx2_io sa_base_addr;
1048 uint32_t __otx2_io tag_const;
1049 uint16_t __otx2_io lenm1_max;
1050 uint8_t __otx2_io sa_pow2_size;
1051 uint8_t __otx2_io tt;
1054 uint32_t __otx2_io sa_idx_max;
1055 uint8_t __otx2_io sa_idx_w;
1057 uint8_t __otx2_io enable;
1060 /* SSO mailbox error codes
1063 enum sso_af_status {
1064 SSO_AF_ERR_PARAM = -501,
1065 SSO_AF_ERR_LF_INVALID = -502,
1066 SSO_AF_ERR_AF_LF_ALLOC = -503,
1067 SSO_AF_ERR_GRP_EBUSY = -504,
1068 SSO_AF_INVAL_NPA_PF_FUNC = -505,
1071 struct sso_lf_alloc_req {
1072 struct mbox_msghdr hdr;
1074 uint16_t __otx2_io hwgrps;
1077 struct sso_lf_alloc_rsp {
1078 struct mbox_msghdr hdr;
1079 uint32_t __otx2_io xaq_buf_size;
1080 uint32_t __otx2_io xaq_wq_entries;
1081 uint32_t __otx2_io in_unit_entries;
1082 uint16_t __otx2_io hwgrps;
1085 struct sso_lf_free_req {
1086 struct mbox_msghdr hdr;
1088 uint16_t __otx2_io hwgrps;
1091 /* SSOW mailbox error codes
1094 enum ssow_af_status {
1095 SSOW_AF_ERR_PARAM = -601,
1096 SSOW_AF_ERR_LF_INVALID = -602,
1097 SSOW_AF_ERR_AF_LF_ALLOC = -603,
1100 struct ssow_lf_alloc_req {
1101 struct mbox_msghdr hdr;
1103 uint16_t __otx2_io hws;
1106 struct ssow_lf_free_req {
1107 struct mbox_msghdr hdr;
1109 uint16_t __otx2_io hws;
1112 struct sso_hw_setconfig {
1113 struct mbox_msghdr hdr;
1114 uint32_t __otx2_io npa_aura_id;
1115 uint16_t __otx2_io npa_pf_func;
1116 uint16_t __otx2_io hwgrps;
1119 struct sso_info_req {
1120 struct mbox_msghdr hdr;
1122 uint16_t __otx2_io grp;
1123 uint16_t __otx2_io hws;
1127 struct sso_grp_priority {
1128 struct mbox_msghdr hdr;
1129 uint16_t __otx2_io grp;
1130 uint8_t __otx2_io priority;
1131 uint8_t __otx2_io affinity;
1132 uint8_t __otx2_io weight;
1135 struct sso_grp_qos_cfg {
1136 struct mbox_msghdr hdr;
1137 uint16_t __otx2_io grp;
1138 uint32_t __otx2_io xaq_limit;
1139 uint16_t __otx2_io taq_thr;
1140 uint16_t __otx2_io iaq_thr;
1143 struct sso_grp_stats {
1144 struct mbox_msghdr hdr;
1145 uint16_t __otx2_io grp;
1146 uint64_t __otx2_io ws_pc;
1147 uint64_t __otx2_io ext_pc;
1148 uint64_t __otx2_io wa_pc;
1149 uint64_t __otx2_io ts_pc;
1150 uint64_t __otx2_io ds_pc;
1151 uint64_t __otx2_io dq_pc;
1152 uint64_t __otx2_io aw_status;
1153 uint64_t __otx2_io page_cnt;
1156 struct sso_hws_stats {
1157 struct mbox_msghdr hdr;
1158 uint16_t __otx2_io hws;
1159 uint64_t __otx2_io arbitration;
1162 /* CPT mailbox error codes
1165 enum cpt_af_status {
1166 CPT_AF_ERR_PARAM = -901,
1167 CPT_AF_ERR_GRP_INVALID = -902,
1168 CPT_AF_ERR_LF_INVALID = -903,
1169 CPT_AF_ERR_ACCESS_DENIED = -904,
1170 CPT_AF_ERR_SSO_PF_FUNC_INVALID = -905,
1171 CPT_AF_ERR_NIX_PF_FUNC_INVALID = -906,
1172 CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907,
1173 CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908
1176 /* CPT mbox message formats */
1178 struct cpt_rd_wr_reg_msg {
1179 struct mbox_msghdr hdr;
1180 uint64_t __otx2_io reg_offset;
1181 uint64_t __otx2_io *ret_val;
1182 uint64_t __otx2_io val;
1183 uint8_t __otx2_io is_write;
1186 struct cpt_set_crypto_grp_req_msg {
1187 struct mbox_msghdr hdr;
1188 uint8_t __otx2_io crypto_eng_grp;
1191 struct cpt_lf_alloc_req_msg {
1192 struct mbox_msghdr hdr;
1193 uint16_t __otx2_io nix_pf_func;
1194 uint16_t __otx2_io sso_pf_func;
1197 struct cpt_lf_alloc_rsp_msg {
1198 struct mbox_msghdr hdr;
1199 uint8_t __otx2_io crypto_eng_grp;
1202 #define CPT_INLINE_INBOUND 0
1203 #define CPT_INLINE_OUTBOUND 1
1205 struct cpt_inline_ipsec_cfg_msg {
1206 struct mbox_msghdr hdr;
1207 uint8_t __otx2_io enable;
1208 uint8_t __otx2_io slot;
1209 uint8_t __otx2_io dir;
1210 uint16_t __otx2_io sso_pf_func; /* Inbound path SSO_PF_FUNC */
1211 uint16_t __otx2_io nix_pf_func; /* Outbound path NIX_PF_FUNC */
1214 struct cpt_rx_inline_lf_cfg_msg {
1215 struct mbox_msghdr hdr;
1216 uint16_t __otx2_io sso_pf_func;
1219 /* NPC mbox message structs */
1221 #define NPC_MCAM_ENTRY_INVALID 0xFFFF
1222 #define NPC_MCAM_INVALID_MAP 0xFFFF
1224 /* NPC mailbox error codes
1227 enum npc_af_status {
1228 NPC_MCAM_INVALID_REQ = -701,
1229 NPC_MCAM_ALLOC_DENIED = -702,
1230 NPC_MCAM_ALLOC_FAILED = -703,
1231 NPC_MCAM_PERM_DENIED = -704,
1234 struct npc_mcam_alloc_entry_req {
1235 struct mbox_msghdr hdr;
1236 #define NPC_MAX_NONCONTIG_ENTRIES 256
1237 uint8_t __otx2_io contig; /* Contiguous entries ? */
1238 #define NPC_MCAM_ANY_PRIO 0
1239 #define NPC_MCAM_LOWER_PRIO 1
1240 #define NPC_MCAM_HIGHER_PRIO 2
1241 uint8_t __otx2_io priority; /* Lower or higher w.r.t ref_entry */
1242 uint16_t __otx2_io ref_entry;
1243 uint16_t __otx2_io count; /* Number of entries requested */
1246 struct npc_mcam_alloc_entry_rsp {
1247 struct mbox_msghdr hdr;
1248 /* Entry alloc'ed or start index if contiguous.
1249 * Invalid in case of non-contiguous.
1251 uint16_t __otx2_io entry;
1252 uint16_t __otx2_io count; /* Number of entries allocated */
1253 uint16_t __otx2_io free_count; /* Number of entries available */
1254 uint16_t __otx2_io entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1257 struct npc_mcam_free_entry_req {
1258 struct mbox_msghdr hdr;
1259 uint16_t __otx2_io entry; /* Entry index to be freed */
1260 uint8_t __otx2_io all; /* Free all entries alloc'ed to this PFVF */
1264 #define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max key width */
1265 uint64_t __otx2_io kw[NPC_MAX_KWS_IN_KEY];
1266 uint64_t __otx2_io kw_mask[NPC_MAX_KWS_IN_KEY];
1267 uint64_t __otx2_io action;
1268 uint64_t __otx2_io vtag_action;
1271 struct npc_mcam_write_entry_req {
1272 struct mbox_msghdr hdr;
1273 struct mcam_entry entry_data;
1274 uint16_t __otx2_io entry; /* MCAM entry to write this match key */
1275 uint16_t __otx2_io cntr; /* Counter for this MCAM entry */
1276 uint8_t __otx2_io intf; /* Rx or Tx interface */
1277 uint8_t __otx2_io enable_entry;/* Enable this MCAM entry ? */
1278 uint8_t __otx2_io set_cntr; /* Set counter for this entry ? */
1281 /* Enable/Disable a given entry */
1282 struct npc_mcam_ena_dis_entry_req {
1283 struct mbox_msghdr hdr;
1284 uint16_t __otx2_io entry;
1287 struct npc_mcam_shift_entry_req {
1288 struct mbox_msghdr hdr;
1289 #define NPC_MCAM_MAX_SHIFTS 64
1290 uint16_t __otx2_io curr_entry[NPC_MCAM_MAX_SHIFTS];
1291 uint16_t __otx2_io new_entry[NPC_MCAM_MAX_SHIFTS];
1292 uint16_t __otx2_io shift_count; /* Number of entries to shift */
1295 struct npc_mcam_shift_entry_rsp {
1296 struct mbox_msghdr hdr;
1297 /* Index in 'curr_entry', not entry itself */
1298 uint16_t __otx2_io failed_entry_idx;
1301 struct npc_mcam_alloc_counter_req {
1302 struct mbox_msghdr hdr;
1303 uint8_t __otx2_io contig; /* Contiguous counters ? */
1304 #define NPC_MAX_NONCONTIG_COUNTERS 64
1305 uint16_t __otx2_io count; /* Number of counters requested */
1308 struct npc_mcam_alloc_counter_rsp {
1309 struct mbox_msghdr hdr;
1310 /* Counter alloc'ed or start idx if contiguous.
1311 * Invalid incase of non-contiguous.
1313 uint16_t __otx2_io cntr;
1314 uint16_t __otx2_io count; /* Number of counters allocated */
1315 uint16_t __otx2_io cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1318 struct npc_mcam_oper_counter_req {
1319 struct mbox_msghdr hdr;
1320 uint16_t __otx2_io cntr; /* Free a counter or clear/fetch it's stats */
1323 struct npc_mcam_oper_counter_rsp {
1324 struct mbox_msghdr hdr;
1325 /* valid only while fetching counter's stats */
1326 uint64_t __otx2_io stat;
1329 struct npc_mcam_unmap_counter_req {
1330 struct mbox_msghdr hdr;
1331 uint16_t __otx2_io cntr;
1332 uint16_t __otx2_io entry; /* Entry and counter to be unmapped */
1333 uint8_t __otx2_io all; /* Unmap all entries using this counter ? */
1336 struct npc_mcam_alloc_and_write_entry_req {
1337 struct mbox_msghdr hdr;
1338 struct mcam_entry entry_data;
1339 uint16_t __otx2_io ref_entry;
1340 uint8_t __otx2_io priority; /* Lower or higher w.r.t ref_entry */
1341 uint8_t __otx2_io intf; /* Rx or Tx interface */
1342 uint8_t __otx2_io enable_entry;/* Enable this MCAM entry ? */
1343 uint8_t __otx2_io alloc_cntr; /* Allocate counter and map ? */
1346 struct npc_mcam_alloc_and_write_entry_rsp {
1347 struct mbox_msghdr hdr;
1348 uint16_t __otx2_io entry;
1349 uint16_t __otx2_io cntr;
1352 struct npc_get_kex_cfg_rsp {
1353 struct mbox_msghdr hdr;
1354 uint64_t __otx2_io rx_keyx_cfg; /* NPC_AF_INTF(0)_KEX_CFG */
1355 uint64_t __otx2_io tx_keyx_cfg; /* NPC_AF_INTF(1)_KEX_CFG */
1356 #define NPC_MAX_INTF 2
1357 #define NPC_MAX_LID 8
1358 #define NPC_MAX_LT 16
1359 #define NPC_MAX_LD 2
1360 #define NPC_MAX_LFL 16
1361 /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1362 uint64_t __otx2_io kex_ld_flags[NPC_MAX_LD];
1363 /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1365 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
1366 /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1368 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1369 #define MKEX_NAME_LEN 128
1370 uint8_t __otx2_io mkex_pfl_name[MKEX_NAME_LEN];
1373 enum header_fields {
1387 NPC_HEADER_FIELDS_MAX,
1391 unsigned char __otx2_io dmac[6];
1392 unsigned char __otx2_io smac[6];
1393 uint16_t __otx2_io etype;
1394 uint16_t __otx2_io vlan_etype;
1395 uint16_t __otx2_io vlan_tci;
1397 uint32_t __otx2_io ip4src;
1398 uint32_t __otx2_io ip6src[4];
1401 uint32_t __otx2_io ip4dst;
1402 uint32_t __otx2_io ip6dst[4];
1404 uint8_t __otx2_io tos;
1405 uint8_t __otx2_io ip_ver;
1406 uint8_t __otx2_io ip_proto;
1407 uint8_t __otx2_io tc;
1408 uint16_t __otx2_io sport;
1409 uint16_t __otx2_io dport;
1412 struct npc_install_flow_req {
1413 struct mbox_msghdr hdr;
1414 struct flow_msg packet;
1415 struct flow_msg mask;
1416 uint64_t __otx2_io features;
1417 uint16_t __otx2_io entry;
1418 uint16_t __otx2_io channel;
1419 uint8_t __otx2_io intf;
1420 uint8_t __otx2_io set_cntr;
1421 uint8_t __otx2_io default_rule;
1422 /* Overwrite(0) or append(1) flow to default rule? */
1423 uint8_t __otx2_io append;
1424 uint16_t __otx2_io vf;
1426 uint32_t __otx2_io index;
1427 uint16_t __otx2_io match_id;
1428 uint8_t __otx2_io flow_key_alg;
1429 uint8_t __otx2_io op;
1431 uint8_t __otx2_io vtag0_type;
1432 uint8_t __otx2_io vtag0_valid;
1433 uint8_t __otx2_io vtag1_type;
1434 uint8_t __otx2_io vtag1_valid;
1436 /* vtag tx action */
1437 uint16_t __otx2_io vtag0_def;
1438 uint8_t __otx2_io vtag0_op;
1439 uint16_t __otx2_io vtag1_def;
1440 uint8_t __otx2_io vtag1_op;
1443 struct npc_install_flow_rsp {
1444 struct mbox_msghdr hdr;
1445 /* Negative if no counter else counter number */
1446 int __otx2_io counter;
1449 struct npc_delete_flow_req {
1450 struct mbox_msghdr hdr;
1451 uint16_t __otx2_io entry;
1452 uint16_t __otx2_io start;/*Disable range of entries */
1453 uint16_t __otx2_io end;
1454 uint8_t __otx2_io all; /* PF + VFs */
1457 struct npc_mcam_read_entry_req {
1458 struct mbox_msghdr hdr;
1459 /* MCAM entry to read */
1460 uint16_t __otx2_io entry;
1463 struct npc_mcam_read_entry_rsp {
1464 struct mbox_msghdr hdr;
1465 struct mcam_entry entry_data;
1466 uint8_t __otx2_io intf;
1467 uint8_t __otx2_io enable;
1470 /* TIM mailbox error codes
1473 enum tim_af_status {
1474 TIM_AF_NO_RINGS_LEFT = -801,
1475 TIM_AF_INVALID_NPA_PF_FUNC = -802,
1476 TIM_AF_INVALID_SSO_PF_FUNC = -803,
1477 TIM_AF_RING_STILL_RUNNING = -804,
1478 TIM_AF_LF_INVALID = -805,
1479 TIM_AF_CSIZE_NOT_ALIGNED = -806,
1480 TIM_AF_CSIZE_TOO_SMALL = -807,
1481 TIM_AF_CSIZE_TOO_BIG = -808,
1482 TIM_AF_INTERVAL_TOO_SMALL = -809,
1483 TIM_AF_INVALID_BIG_ENDIAN_VALUE = -810,
1484 TIM_AF_INVALID_CLOCK_SOURCE = -811,
1485 TIM_AF_GPIO_CLK_SRC_NOT_ENABLED = -812,
1486 TIM_AF_INVALID_BSIZE = -813,
1487 TIM_AF_INVALID_ENABLE_PERIODIC = -814,
1488 TIM_AF_INVALID_ENABLE_DONTFREE = -815,
1489 TIM_AF_ENA_DONTFRE_NSET_PERIODIC = -816,
1490 TIM_AF_RING_ALREADY_DISABLED = -817,
1494 TIM_CLK_SRCS_TENNS = 0,
1495 TIM_CLK_SRCS_GPIO = 1,
1496 TIM_CLK_SRCS_GTI = 2,
1497 TIM_CLK_SRCS_PTP = 3,
1498 TIM_CLK_SRSC_INVALID,
1501 enum tim_gpio_edge {
1502 TIM_GPIO_NO_EDGE = 0,
1503 TIM_GPIO_LTOH_TRANS = 1,
1504 TIM_GPIO_HTOL_TRANS = 2,
1505 TIM_GPIO_BOTH_TRANS = 3,
1510 PTP_OP_ADJFINE = 0, /* adjfine(req.scaled_ppm); */
1511 PTP_OP_GET_CLOCK = 1, /* rsp.clk = get_clock() */
1515 struct mbox_msghdr hdr;
1516 uint8_t __otx2_io op;
1517 int64_t __otx2_io scaled_ppm;
1518 uint8_t __otx2_io is_pmu;
1522 struct mbox_msghdr hdr;
1523 uint64_t __otx2_io clk;
1524 uint64_t __otx2_io tsc;
1527 struct get_hw_cap_rsp {
1528 struct mbox_msghdr hdr;
1529 /* Schq mapping fixed or flexible */
1530 uint8_t __otx2_io nix_fixed_txschq_mapping;
1531 uint8_t __otx2_io nix_shaping; /* Is shaping and coloring supported */
1534 struct ndc_sync_op {
1535 struct mbox_msghdr hdr;
1536 uint8_t __otx2_io nix_lf_tx_sync;
1537 uint8_t __otx2_io nix_lf_rx_sync;
1538 uint8_t __otx2_io npa_lf_sync;
1541 struct tim_lf_alloc_req {
1542 struct mbox_msghdr hdr;
1543 uint16_t __otx2_io ring;
1544 uint16_t __otx2_io npa_pf_func;
1545 uint16_t __otx2_io sso_pf_func;
1548 struct tim_ring_req {
1549 struct mbox_msghdr hdr;
1550 uint16_t __otx2_io ring;
1553 struct tim_config_req {
1554 struct mbox_msghdr hdr;
1555 uint16_t __otx2_io ring;
1556 uint8_t __otx2_io bigendian;
1557 uint8_t __otx2_io clocksource;
1558 uint8_t __otx2_io enableperiodic;
1559 uint8_t __otx2_io enabledontfreebuffer;
1560 uint32_t __otx2_io bucketsize;
1561 uint32_t __otx2_io chunksize;
1562 uint32_t __otx2_io interval;
1565 struct tim_lf_alloc_rsp {
1566 struct mbox_msghdr hdr;
1567 uint64_t __otx2_io tenns_clk;
1570 struct tim_enable_rsp {
1571 struct mbox_msghdr hdr;
1572 uint64_t __otx2_io timestarted;
1573 uint32_t __otx2_io currentbucket;
1576 const char *otx2_mbox_id2name(uint16_t id);
1577 int otx2_mbox_id2size(uint16_t id);
1578 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
1579 int otx2_mbox_init(struct otx2_mbox *mbox, uintptr_t hwbase, uintptr_t reg_base,
1580 int direction, int ndevsi, uint64_t intr_offset);
1581 void otx2_mbox_fini(struct otx2_mbox *mbox);
1582 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
1583 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
1584 int otx2_mbox_wait_for_rsp_tmo(struct otx2_mbox *mbox, int devid, uint32_t tmo);
1585 int otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid, void **msg);
1586 int otx2_mbox_get_rsp_tmo(struct otx2_mbox *mbox, int devid, void **msg,
1588 int otx2_mbox_get_availmem(struct otx2_mbox *mbox, int devid);
1589 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
1590 int size, int size_rsp);
1592 static inline struct mbox_msghdr *
1593 otx2_mbox_alloc_msg(struct otx2_mbox *mbox, int devid, int size)
1595 return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
1599 otx2_mbox_req_init(uint16_t mbox_id, void *msghdr)
1601 struct mbox_msghdr *hdr = msghdr;
1603 hdr->sig = OTX2_MBOX_REQ_SIG;
1604 hdr->ver = OTX2_MBOX_VERSION;
1610 otx2_mbox_rsp_init(uint16_t mbox_id, void *msghdr)
1612 struct mbox_msghdr *hdr = msghdr;
1614 hdr->sig = OTX2_MBOX_RSP_SIG;
1615 hdr->rc = -ETIMEDOUT;
1620 otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid)
1622 struct otx2_mbox_dev *mdev = &mbox->dev[devid];
1625 rte_spinlock_lock(&mdev->mbox_lock);
1626 ret = mdev->num_msgs != 0;
1627 rte_spinlock_unlock(&mdev->mbox_lock);
1633 otx2_mbox_process(struct otx2_mbox *mbox)
1635 otx2_mbox_msg_send(mbox, 0);
1636 return otx2_mbox_get_rsp(mbox, 0, NULL);
1640 otx2_mbox_process_msg(struct otx2_mbox *mbox, void **msg)
1642 otx2_mbox_msg_send(mbox, 0);
1643 return otx2_mbox_get_rsp(mbox, 0, msg);
1647 otx2_mbox_process_tmo(struct otx2_mbox *mbox, uint32_t tmo)
1649 otx2_mbox_msg_send(mbox, 0);
1650 return otx2_mbox_get_rsp_tmo(mbox, 0, NULL, tmo);
1654 otx2_mbox_process_msg_tmo(struct otx2_mbox *mbox, void **msg, uint32_t tmo)
1656 otx2_mbox_msg_send(mbox, 0);
1657 return otx2_mbox_get_rsp_tmo(mbox, 0, msg, tmo);
1660 int otx2_send_ready_msg(struct otx2_mbox *mbox, uint16_t *pf_func /* out */);
1661 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, uint16_t pf_func,
1664 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \
1665 static inline struct _req_type \
1666 *otx2_mbox_alloc_msg_ ## _fn_name(struct otx2_mbox *mbox) \
1668 struct _req_type *req; \
1670 req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \
1671 mbox, 0, sizeof(struct _req_type), \
1672 sizeof(struct _rsp_type)); \
1676 req->hdr.sig = OTX2_MBOX_REQ_SIG; \
1677 req->hdr.id = _id; \
1678 otx2_mbox_dbg("id=0x%x (%s)", \
1679 req->hdr.id, otx2_mbox_id2name(req->hdr.id)); \
1686 /* This is required for copy operations from device memory which do not work on
1687 * addresses which are unaligned to 16B. This is because of specific
1688 * optimizations to libc memcpy.
1690 static inline volatile void *
1691 otx2_mbox_memcpy(volatile void *d, const volatile void *s, size_t l)
1693 const volatile uint8_t *sb;
1694 volatile uint8_t *db;
1699 db = (volatile uint8_t *)d;
1700 sb = (const volatile uint8_t *)s;
1701 for (i = 0; i < l; i++)
1706 /* This is required for memory operations from device memory which do not
1707 * work on addresses which are unaligned to 16B. This is because of specific
1708 * optimizations to libc memset.
1711 otx2_mbox_memset(volatile void *d, uint8_t val, size_t l)
1713 volatile uint8_t *db;
1718 db = (volatile uint8_t *)d;
1719 for (i = 0; i < l; i++)
1723 #endif /* __OTX2_MBOX_H__ */