1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2021 Intel Corporation
5 #include "qat_device.h"
7 #include "adf_transport_access_macros.h"
8 #include "qat_dev_gens.h"
13 const struct qat_qp_hw_data qat_gen3_qps[QAT_MAX_SERVICES]
14 [ADF_MAX_QPS_ON_ANY_SERVICE] = {
15 /* queue pairs which provide an asymmetric crypto service */
16 [QAT_SERVICE_ASYMMETRIC] = {
18 .service_type = QAT_SERVICE_ASYMMETRIC,
26 /* queue pairs which provide a symmetric crypto service */
27 [QAT_SERVICE_SYMMETRIC] = {
29 .service_type = QAT_SERVICE_SYMMETRIC,
37 /* queue pairs which provide a compression service */
38 [QAT_SERVICE_COMPRESSION] = {
40 .service_type = QAT_SERVICE_COMPRESSION,
51 static const struct qat_qp_hw_data *
52 qat_qp_get_hw_data_gen3(struct qat_pci_device *dev __rte_unused,
53 enum qat_service_type service_type, uint16_t qp_id)
55 return qat_gen3_qps[service_type] + qp_id;
58 static struct qat_qp_hw_spec_funcs qat_qp_hw_spec_gen3 = {
59 .qat_qp_rings_per_service = qat_qp_rings_per_service_gen1,
60 .qat_qp_build_ring_base = qat_qp_csr_build_ring_base_gen1,
61 .qat_qp_adf_arb_enable = qat_qp_adf_arb_enable_gen1,
62 .qat_qp_adf_arb_disable = qat_qp_adf_arb_disable_gen1,
63 .qat_qp_adf_configure_queues = qat_qp_adf_configure_queues_gen1,
64 .qat_qp_csr_write_tail = qat_qp_csr_write_tail_gen1,
65 .qat_qp_csr_write_head = qat_qp_csr_write_head_gen1,
66 .qat_qp_csr_setup = qat_qp_csr_setup_gen1,
67 .qat_qp_get_hw_data = qat_qp_get_hw_data_gen3
70 static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen3 = {
71 .qat_dev_reset_ring_pairs = qat_reset_ring_pairs_gen1,
72 .qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen1,
73 .qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen1,
74 .qat_dev_read_config = qat_dev_read_config_gen1,
75 .qat_dev_get_extra_size = qat_dev_get_extra_size_gen1,
78 RTE_INIT(qat_dev_gen_gen3_init)
80 qat_qp_hw_spec[QAT_GEN3] = &qat_qp_hw_spec_gen3;
81 qat_dev_hw_spec[QAT_GEN3] = &qat_dev_hw_spec_gen3;
82 qat_gen_config[QAT_GEN3].dev_gen = QAT_GEN3;