1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2021 Intel Corporation
5 #ifndef ADF_TRANSPORT_ACCESS_MACROS_GEN4_H
6 #define ADF_TRANSPORT_ACCESS_MACROS_GEN4_H
8 #include "adf_transport_access_macros.h"
10 #define ADF_RINGS_PER_INT_SRCSEL_GEN4 2
11 #define ADF_BANK_INT_SRC_SEL_MASK_GEN4 0x44UL
12 #define ADF_BANK_INT_FLAG_CLEAR_MASK_GEN4 0x3
13 #define ADF_RING_BUNDLE_SIZE_GEN4 0x2000
14 #define ADF_RING_CSR_ADDR_OFFSET_GEN4 0x100000
15 #define ADF_RING_CSR_RING_CONFIG_GEN4 0x1000
16 #define ADF_RING_CSR_RING_LBASE_GEN4 0x1040
17 #define ADF_RING_CSR_RING_UBASE_GEN4 0x1080
19 #define BUILD_RING_BASE_ADDR_GEN4(addr, size) \
20 ((((addr) >> 6) & (0xFFFFFFFFFFFFFFFFULL << (size))) << 6)
22 #define WRITE_CSR_RING_BASE_GEN4(csr_base_addr, bank, ring, value) \
24 uint32_t l_base = 0, u_base = 0; \
25 l_base = (uint32_t)(value & 0xFFFFFFFF); \
26 u_base = (uint32_t)((value & 0xFFFFFFFF00000000ULL) >> 32); \
27 ADF_CSR_WR(csr_base_addr + ADF_RING_CSR_ADDR_OFFSET_GEN4, \
28 (ADF_RING_BUNDLE_SIZE_GEN4 * bank) + \
29 ADF_RING_CSR_RING_LBASE_GEN4 + (ring << 2), \
31 ADF_CSR_WR(csr_base_addr + ADF_RING_CSR_ADDR_OFFSET_GEN4, \
32 (ADF_RING_BUNDLE_SIZE_GEN4 * bank) + \
33 ADF_RING_CSR_RING_UBASE_GEN4 + (ring << 2), \
37 #define WRITE_CSR_RING_CONFIG_GEN4(csr_base_addr, bank, ring, value) \
38 ADF_CSR_WR(csr_base_addr + ADF_RING_CSR_ADDR_OFFSET_GEN4, \
39 (ADF_RING_BUNDLE_SIZE_GEN4 * bank) + \
40 ADF_RING_CSR_RING_CONFIG_GEN4 + (ring << 2), value)
42 #define WRITE_CSR_RING_TAIL_GEN4(csr_base_addr, bank, ring, value) \
43 ADF_CSR_WR((u8 *)(csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_GEN4, \
44 (ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
45 ADF_RING_CSR_RING_TAIL + ((ring) << 2), value)
47 #define WRITE_CSR_RING_HEAD_GEN4(csr_base_addr, bank, ring, value) \
48 ADF_CSR_WR((u8 *)(csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_GEN4, \
49 (ADF_RING_BUNDLE_SIZE_GEN4 * (bank)) + \
50 ADF_RING_CSR_RING_HEAD + ((ring) << 2), value)