1265c2a1380eddf0b89c7d0f2a8ca8055f88ac80
[dpdk.git] / drivers / common / qat / qat_adf / icp_qat_fw.h
1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2  * Copyright(c) 2015-2018 Intel Corporation
3  */
4 #ifndef _ICP_QAT_FW_H_
5 #define _ICP_QAT_FW_H_
6 #include <sys/types.h>
7 #include "icp_qat_hw.h"
8
9 #define QAT_FIELD_SET(flags, val, bitpos, mask) \
10 { (flags) = (((flags) & (~((mask) << (bitpos)))) | \
11                 (((val) & (mask)) << (bitpos))) ; }
12
13 #define QAT_FIELD_GET(flags, bitpos, mask) \
14         (((flags) >> (bitpos)) & (mask))
15
16 #define ICP_QAT_FW_REQ_DEFAULT_SZ 128
17 #define ICP_QAT_FW_RESP_DEFAULT_SZ 32
18 #define ICP_QAT_FW_COMN_ONE_BYTE_SHIFT 8
19 #define ICP_QAT_FW_COMN_SINGLE_BYTE_MASK 0xFF
20 #define ICP_QAT_FW_NUM_LONGWORDS_1 1
21 #define ICP_QAT_FW_NUM_LONGWORDS_2 2
22 #define ICP_QAT_FW_NUM_LONGWORDS_3 3
23 #define ICP_QAT_FW_NUM_LONGWORDS_4 4
24 #define ICP_QAT_FW_NUM_LONGWORDS_5 5
25 #define ICP_QAT_FW_NUM_LONGWORDS_6 6
26 #define ICP_QAT_FW_NUM_LONGWORDS_7 7
27 #define ICP_QAT_FW_NUM_LONGWORDS_10 10
28 #define ICP_QAT_FW_NUM_LONGWORDS_13 13
29 #define ICP_QAT_FW_NULL_REQ_SERV_ID 1
30
31 enum icp_qat_fw_comn_resp_serv_id {
32         ICP_QAT_FW_COMN_RESP_SERV_NULL,
33         ICP_QAT_FW_COMN_RESP_SERV_CPM_FW,
34         ICP_QAT_FW_COMN_RESP_SERV_DELIMITER
35 };
36
37 enum icp_qat_fw_comn_request_id {
38         ICP_QAT_FW_COMN_REQ_NULL = 0,
39         ICP_QAT_FW_COMN_REQ_CPM_FW_PKE = 3,
40         ICP_QAT_FW_COMN_REQ_CPM_FW_LA = 4,
41         ICP_QAT_FW_COMN_REQ_CPM_FW_DMA = 7,
42         ICP_QAT_FW_COMN_REQ_CPM_FW_COMP = 9,
43         ICP_QAT_FW_COMN_REQ_DELIMITER
44 };
45
46 struct icp_qat_fw_comn_req_hdr_cd_pars {
47         union {
48                 struct {
49                         uint64_t content_desc_addr;
50                         uint16_t content_desc_resrvd1;
51                         uint8_t content_desc_params_sz;
52                         uint8_t content_desc_hdr_resrvd2;
53                         uint32_t content_desc_resrvd3;
54                 } s;
55                 struct {
56                         uint32_t serv_specif_fields[4];
57                 } s1;
58         } u;
59 };
60
61 struct icp_qat_fw_comn_req_mid {
62         uint64_t opaque_data;
63         uint64_t src_data_addr;
64         uint64_t dest_data_addr;
65         uint32_t src_length;
66         uint32_t dst_length;
67 };
68
69 struct icp_qat_fw_comn_req_cd_ctrl {
70         uint32_t content_desc_ctrl_lw[ICP_QAT_FW_NUM_LONGWORDS_5];
71 };
72
73 struct icp_qat_fw_comn_req_hdr {
74         uint8_t resrvd1;
75         uint8_t service_cmd_id;
76         uint8_t service_type;
77         uint8_t hdr_flags;
78         uint16_t serv_specif_flags;
79         uint16_t comn_req_flags;
80 };
81
82 struct icp_qat_fw_comn_req_rqpars {
83         uint32_t serv_specif_rqpars_lw[ICP_QAT_FW_NUM_LONGWORDS_13];
84 };
85
86 struct icp_qat_fw_comn_req {
87         struct icp_qat_fw_comn_req_hdr comn_hdr;
88         struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars;
89         struct icp_qat_fw_comn_req_mid comn_mid;
90         struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars;
91         struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl;
92 };
93
94 struct icp_qat_fw_comn_error {
95         uint8_t xlat_err_code;
96         uint8_t cmp_err_code;
97 };
98
99 struct icp_qat_fw_comn_resp_hdr {
100         uint8_t resrvd1;
101         uint8_t service_id;
102         uint8_t response_type;
103         uint8_t hdr_flags;
104         struct icp_qat_fw_comn_error comn_error;
105         uint8_t comn_status;
106         uint8_t cmd_id;
107 };
108
109 struct icp_qat_fw_comn_resp {
110         struct icp_qat_fw_comn_resp_hdr comn_hdr;
111         uint64_t opaque_data;
112         uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];
113 };
114
115 #define ICP_QAT_FW_COMN_REQ_FLAG_SET 1
116 #define ICP_QAT_FW_COMN_REQ_FLAG_CLR 0
117 #define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7
118 #define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1
119 #define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F
120 #define ICP_QAT_FW_COMN_CNV_FLAG_BITPOS 6
121 #define ICP_QAT_FW_COMN_CNV_FLAG_MASK 0x1
122 #define ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS 5
123 #define ICP_QAT_FW_COMN_CNVNR_FLAG_MASK 0x1
124
125 #define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
126         icp_qat_fw_comn_req_hdr_t.service_type
127
128 #define ICP_QAT_FW_COMN_OV_SRV_TYPE_SET(icp_qat_fw_comn_req_hdr_t, val) \
129         icp_qat_fw_comn_req_hdr_t.service_type = val
130
131 #define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_GET(icp_qat_fw_comn_req_hdr_t) \
132         icp_qat_fw_comn_req_hdr_t.service_cmd_id
133
134 #define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_SET(icp_qat_fw_comn_req_hdr_t, val) \
135         icp_qat_fw_comn_req_hdr_t.service_cmd_id = val
136
137 #define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \
138         ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags)
139
140 #define ICP_QAT_FW_COMN_HDR_CNVNR_FLAG_GET(hdr_flags) \
141         QAT_FIELD_GET(hdr_flags, \
142                 ICP_QAT_FW_COMN_CNVNR_FLAG_BITPOS, \
143                 ICP_QAT_FW_COMN_CNVNR_FLAG_MASK)
144
145 #define ICP_QAT_FW_COMN_HDR_CNV_FLAG_GET(hdr_flags) \
146         QAT_FIELD_GET(hdr_flags, \
147                 ICP_QAT_FW_COMN_CNV_FLAG_BITPOS, \
148                 ICP_QAT_FW_COMN_CNV_FLAG_MASK)
149
150 #define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \
151         ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val)
152
153 #define ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_flags) \
154         QAT_FIELD_GET(hdr_flags, \
155         ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \
156         ICP_QAT_FW_COMN_VALID_FLAG_MASK)
157
158 #define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_GET(hdr_flags) \
159         (hdr_flags & ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK)
160
161 #define ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) \
162         QAT_FIELD_SET((hdr_t.hdr_flags), (val), \
163         ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \
164         ICP_QAT_FW_COMN_VALID_FLAG_MASK)
165
166 #define ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(valid) \
167         (((valid) & ICP_QAT_FW_COMN_VALID_FLAG_MASK) << \
168          ICP_QAT_FW_COMN_VALID_FLAG_BITPOS)
169
170 #define QAT_COMN_PTR_TYPE_BITPOS 0
171 #define QAT_COMN_PTR_TYPE_MASK 0x1
172 #define QAT_COMN_CD_FLD_TYPE_BITPOS 1
173 #define QAT_COMN_CD_FLD_TYPE_MASK 0x1
174 #define QAT_COMN_PTR_TYPE_FLAT 0x0
175 #define QAT_COMN_PTR_TYPE_SGL 0x1
176 #define QAT_COMN_CD_FLD_TYPE_64BIT_ADR 0x0
177 #define QAT_COMN_CD_FLD_TYPE_16BYTE_DATA 0x1
178 #define QAT_COMN_EXT_FLAGS_BITPOS 8
179 #define QAT_COMN_EXT_FLAGS_MASK 0x1
180 #define QAT_COMN_EXT_FLAGS_USED 0x1
181
182 #define ICP_QAT_FW_COMN_FLAGS_BUILD(cdt, ptr) \
183         ((((cdt) & QAT_COMN_CD_FLD_TYPE_MASK) << QAT_COMN_CD_FLD_TYPE_BITPOS) \
184          | (((ptr) & QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS))
185
186 #define ICP_QAT_FW_COMN_PTR_TYPE_GET(flags) \
187         QAT_FIELD_GET(flags, QAT_COMN_PTR_TYPE_BITPOS, QAT_COMN_PTR_TYPE_MASK)
188
189 #define ICP_QAT_FW_COMN_CD_FLD_TYPE_GET(flags) \
190         QAT_FIELD_GET(flags, QAT_COMN_CD_FLD_TYPE_BITPOS, \
191                         QAT_COMN_CD_FLD_TYPE_MASK)
192
193 #define ICP_QAT_FW_COMN_PTR_TYPE_SET(flags, val) \
194         QAT_FIELD_SET(flags, val, QAT_COMN_PTR_TYPE_BITPOS, \
195                         QAT_COMN_PTR_TYPE_MASK)
196
197 #define ICP_QAT_FW_COMN_CD_FLD_TYPE_SET(flags, val) \
198         QAT_FIELD_SET(flags, val, QAT_COMN_CD_FLD_TYPE_BITPOS, \
199                         QAT_COMN_CD_FLD_TYPE_MASK)
200
201 #define ICP_QAT_FW_COMN_NEXT_ID_BITPOS 4
202 #define ICP_QAT_FW_COMN_NEXT_ID_MASK 0xF0
203 #define ICP_QAT_FW_COMN_CURR_ID_BITPOS 0
204 #define ICP_QAT_FW_COMN_CURR_ID_MASK 0x0F
205
206 #define ICP_QAT_FW_COMN_NEXT_ID_GET(cd_ctrl_hdr_t) \
207         ((((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \
208         >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))
209
210 #define ICP_QAT_FW_COMN_NEXT_ID_SET(cd_ctrl_hdr_t, val) \
211         { ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \
212         & ICP_QAT_FW_COMN_CURR_ID_MASK) | \
213         ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
214          & ICP_QAT_FW_COMN_NEXT_ID_MASK)); }
215
216 #define ICP_QAT_FW_COMN_CURR_ID_GET(cd_ctrl_hdr_t) \
217         (((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK)
218
219 #define ICP_QAT_FW_COMN_CURR_ID_SET(cd_ctrl_hdr_t, val) \
220         { ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \
221         & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
222         ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)); }
223
224 #define ICP_QAT_FW_COMN_NEXT_ID_SET_2(next_curr_id, val)                       \
225         do {                                                                   \
226                 (next_curr_id) =                                               \
227                     (((next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK) |         \
228                      (((val) << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) &              \
229                       ICP_QAT_FW_COMN_NEXT_ID_MASK))                           \
230         } while (0)
231
232 #define ICP_QAT_FW_COMN_CURR_ID_SET_2(next_curr_id, val)                       \
233         do {                                                                   \
234                 (next_curr_id) =                                               \
235                     (((next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) |         \
236                      ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK))                   \
237         } while (0)
238
239 #define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7
240 #define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1
241 #define QAT_COMN_RESP_PKE_STATUS_BITPOS 6
242 #define QAT_COMN_RESP_PKE_STATUS_MASK 0x1
243 #define QAT_COMN_RESP_CMP_STATUS_BITPOS 5
244 #define QAT_COMN_RESP_CMP_STATUS_MASK 0x1
245 #define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4
246 #define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1
247 #define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3
248 #define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1
249 #define QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS 2
250 #define QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK 0x1
251 #define QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS 0
252 #define QAT_COMN_RESP_XLT_WA_APPLIED_MASK 0x1
253
254 #define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \
255         QAT_FIELD_GET(status, QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \
256         QAT_COMN_RESP_CRYPTO_STATUS_MASK)
257
258 #define ICP_QAT_FW_COMN_RESP_PKE_STAT_GET(status) \
259         QAT_FIELD_GET(status, QAT_COMN_RESP_PKE_STATUS_BITPOS, \
260         QAT_COMN_RESP_PKE_STATUS_MASK)
261
262 #define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \
263         QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_STATUS_BITPOS, \
264         QAT_COMN_RESP_CMP_STATUS_MASK)
265
266 #define ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(status) \
267         QAT_FIELD_GET(status, QAT_COMN_RESP_XLAT_STATUS_BITPOS, \
268         QAT_COMN_RESP_XLAT_STATUS_MASK)
269
270 #define ICP_QAT_FW_COMN_RESP_XLT_WA_APPLIED_GET(status) \
271         QAT_FIELD_GET(status, QAT_COMN_RESP_XLT_WA_APPLIED_BITPOS, \
272         QAT_COMN_RESP_XLT_WA_APPLIED_MASK)
273
274 #define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \
275         QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \
276         QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK)
277
278 #define ICP_QAT_FW_COMN_RESP_UNSUPPORTED_REQUEST_STAT_GET(status) \
279         QAT_FIELD_GET(status, QAT_COMN_RESP_UNSUPPORTED_REQUEST_BITPOS, \
280         QAT_COMN_RESP_UNSUPPORTED_REQUEST_MASK)
281
282 #define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0
283 #define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1
284 #define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0
285 #define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_SET 1
286 #define ERR_CODE_NO_ERROR 0
287 #define ERR_CODE_INVALID_BLOCK_TYPE -1
288 #define ERR_CODE_NO_MATCH_ONES_COMP -2
289 #define ERR_CODE_TOO_MANY_LEN_OR_DIS -3
290 #define ERR_CODE_INCOMPLETE_LEN -4
291 #define ERR_CODE_RPT_LEN_NO_FIRST_LEN -5
292 #define ERR_CODE_RPT_GT_SPEC_LEN -6
293 #define ERR_CODE_INV_LIT_LEN_CODE_LEN -7
294 #define ERR_CODE_INV_DIS_CODE_LEN -8
295 #define ERR_CODE_INV_LIT_LEN_DIS_IN_BLK -9
296 #define ERR_CODE_DIS_TOO_FAR_BACK -10
297 #define ERR_CODE_OVERFLOW_ERROR -11
298 #define ERR_CODE_SOFT_ERROR -12
299 #define ERR_CODE_FATAL_ERROR -13
300 #define ERR_CODE_COMP_OUTPUT_CORRUPTION -14
301 #define ERR_CODE_HW_INCOMPLETE_FILE -15
302 #define ERR_CODE_SSM_ERROR -16
303 #define ERR_CODE_ENDPOINT_ERROR -17
304 #define ERR_CODE_CNV_ERROR -18
305 #define ERR_CODE_EMPTY_DYM_BLOCK -19
306 #define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_HANDLE -20
307 #define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_HMAC_FAILED -21
308 #define ERR_CODE_KPT_CRYPTO_SERVICE_FAIL_INVALID_WRAPPING_ALGO -22
309 #define ERR_CODE_KPT_DRNG_SEED_NOT_LOAD -23
310
311 enum icp_qat_fw_slice {
312         ICP_QAT_FW_SLICE_NULL = 0,
313         ICP_QAT_FW_SLICE_CIPHER = 1,
314         ICP_QAT_FW_SLICE_AUTH = 2,
315         ICP_QAT_FW_SLICE_DRAM_RD = 3,
316         ICP_QAT_FW_SLICE_DRAM_WR = 4,
317         ICP_QAT_FW_SLICE_COMP = 5,
318         ICP_QAT_FW_SLICE_XLAT = 6,
319         ICP_QAT_FW_SLICE_DELIMITER
320 };
321 #endif