1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2015-2018 Intel Corporation
7 #include "icp_qat_hw.h"
9 #define QAT_FIELD_SET(flags, val, bitpos, mask) \
10 { (flags) = (((flags) & (~((mask) << (bitpos)))) | \
11 (((val) & (mask)) << (bitpos))) ; }
13 #define QAT_FIELD_GET(flags, bitpos, mask) \
14 (((flags) >> (bitpos)) & (mask))
16 #define ICP_QAT_FW_REQ_DEFAULT_SZ 128
17 #define ICP_QAT_FW_RESP_DEFAULT_SZ 32
18 #define ICP_QAT_FW_COMN_ONE_BYTE_SHIFT 8
19 #define ICP_QAT_FW_COMN_SINGLE_BYTE_MASK 0xFF
20 #define ICP_QAT_FW_NUM_LONGWORDS_1 1
21 #define ICP_QAT_FW_NUM_LONGWORDS_2 2
22 #define ICP_QAT_FW_NUM_LONGWORDS_3 3
23 #define ICP_QAT_FW_NUM_LONGWORDS_4 4
24 #define ICP_QAT_FW_NUM_LONGWORDS_5 5
25 #define ICP_QAT_FW_NUM_LONGWORDS_6 6
26 #define ICP_QAT_FW_NUM_LONGWORDS_7 7
27 #define ICP_QAT_FW_NUM_LONGWORDS_10 10
28 #define ICP_QAT_FW_NUM_LONGWORDS_13 13
29 #define ICP_QAT_FW_NULL_REQ_SERV_ID 1
31 enum icp_qat_fw_comn_resp_serv_id {
32 ICP_QAT_FW_COMN_RESP_SERV_NULL,
33 ICP_QAT_FW_COMN_RESP_SERV_CPM_FW,
34 ICP_QAT_FW_COMN_RESP_SERV_DELIMITER
37 enum icp_qat_fw_comn_request_id {
38 ICP_QAT_FW_COMN_REQ_NULL = 0,
39 ICP_QAT_FW_COMN_REQ_CPM_FW_PKE = 3,
40 ICP_QAT_FW_COMN_REQ_CPM_FW_LA = 4,
41 ICP_QAT_FW_COMN_REQ_CPM_FW_DMA = 7,
42 ICP_QAT_FW_COMN_REQ_CPM_FW_COMP = 9,
43 ICP_QAT_FW_COMN_REQ_DELIMITER
46 struct icp_qat_fw_comn_req_hdr_cd_pars {
49 uint64_t content_desc_addr;
50 uint16_t content_desc_resrvd1;
51 uint8_t content_desc_params_sz;
52 uint8_t content_desc_hdr_resrvd2;
53 uint32_t content_desc_resrvd3;
56 uint32_t serv_specif_fields[4];
61 struct icp_qat_fw_comn_req_mid {
63 uint64_t src_data_addr;
64 uint64_t dest_data_addr;
69 struct icp_qat_fw_comn_req_cd_ctrl {
70 uint32_t content_desc_ctrl_lw[ICP_QAT_FW_NUM_LONGWORDS_5];
73 struct icp_qat_fw_comn_req_hdr {
75 uint8_t service_cmd_id;
78 uint16_t serv_specif_flags;
79 uint16_t comn_req_flags;
82 struct icp_qat_fw_comn_req_rqpars {
83 uint32_t serv_specif_rqpars_lw[ICP_QAT_FW_NUM_LONGWORDS_13];
86 struct icp_qat_fw_comn_req {
87 struct icp_qat_fw_comn_req_hdr comn_hdr;
88 struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars;
89 struct icp_qat_fw_comn_req_mid comn_mid;
90 struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars;
91 struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl;
94 struct icp_qat_fw_comn_error {
95 uint8_t xlat_err_code;
99 struct icp_qat_fw_comn_resp_hdr {
102 uint8_t response_type;
104 struct icp_qat_fw_comn_error comn_error;
109 struct icp_qat_fw_comn_resp {
110 struct icp_qat_fw_comn_resp_hdr comn_hdr;
111 uint64_t opaque_data;
112 uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];
115 #define ICP_QAT_FW_COMN_REQ_FLAG_SET 1
116 #define ICP_QAT_FW_COMN_REQ_FLAG_CLR 0
117 #define ICP_QAT_FW_COMN_VALID_FLAG_BITPOS 7
118 #define ICP_QAT_FW_COMN_VALID_FLAG_MASK 0x1
119 #define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK 0x7F
121 #define ICP_QAT_FW_COMN_OV_SRV_TYPE_GET(icp_qat_fw_comn_req_hdr_t) \
122 icp_qat_fw_comn_req_hdr_t.service_type
124 #define ICP_QAT_FW_COMN_OV_SRV_TYPE_SET(icp_qat_fw_comn_req_hdr_t, val) \
125 icp_qat_fw_comn_req_hdr_t.service_type = val
127 #define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_GET(icp_qat_fw_comn_req_hdr_t) \
128 icp_qat_fw_comn_req_hdr_t.service_cmd_id
130 #define ICP_QAT_FW_COMN_OV_SRV_CMD_ID_SET(icp_qat_fw_comn_req_hdr_t, val) \
131 icp_qat_fw_comn_req_hdr_t.service_cmd_id = val
133 #define ICP_QAT_FW_COMN_HDR_VALID_FLAG_GET(hdr_t) \
134 ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_t.hdr_flags)
136 #define ICP_QAT_FW_COMN_HDR_VALID_FLAG_SET(hdr_t, val) \
137 ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val)
139 #define ICP_QAT_FW_COMN_VALID_FLAG_GET(hdr_flags) \
140 QAT_FIELD_GET(hdr_flags, \
141 ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \
142 ICP_QAT_FW_COMN_VALID_FLAG_MASK)
144 #define ICP_QAT_FW_COMN_HDR_RESRVD_FLD_GET(hdr_flags) \
145 (hdr_flags & ICP_QAT_FW_COMN_HDR_RESRVD_FLD_MASK)
147 #define ICP_QAT_FW_COMN_VALID_FLAG_SET(hdr_t, val) \
148 QAT_FIELD_SET((hdr_t.hdr_flags), (val), \
149 ICP_QAT_FW_COMN_VALID_FLAG_BITPOS, \
150 ICP_QAT_FW_COMN_VALID_FLAG_MASK)
152 #define ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(valid) \
153 (((valid) & ICP_QAT_FW_COMN_VALID_FLAG_MASK) << \
154 ICP_QAT_FW_COMN_VALID_FLAG_BITPOS)
156 #define QAT_COMN_PTR_TYPE_BITPOS 0
157 #define QAT_COMN_PTR_TYPE_MASK 0x1
158 #define QAT_COMN_CD_FLD_TYPE_BITPOS 1
159 #define QAT_COMN_CD_FLD_TYPE_MASK 0x1
160 #define QAT_COMN_PTR_TYPE_FLAT 0x0
161 #define QAT_COMN_PTR_TYPE_SGL 0x1
162 #define QAT_COMN_CD_FLD_TYPE_64BIT_ADR 0x0
163 #define QAT_COMN_CD_FLD_TYPE_16BYTE_DATA 0x1
165 #define ICP_QAT_FW_COMN_FLAGS_BUILD(cdt, ptr) \
166 ((((cdt) & QAT_COMN_CD_FLD_TYPE_MASK) << QAT_COMN_CD_FLD_TYPE_BITPOS) \
167 | (((ptr) & QAT_COMN_PTR_TYPE_MASK) << QAT_COMN_PTR_TYPE_BITPOS))
169 #define ICP_QAT_FW_COMN_PTR_TYPE_GET(flags) \
170 QAT_FIELD_GET(flags, QAT_COMN_PTR_TYPE_BITPOS, QAT_COMN_PTR_TYPE_MASK)
172 #define ICP_QAT_FW_COMN_CD_FLD_TYPE_GET(flags) \
173 QAT_FIELD_GET(flags, QAT_COMN_CD_FLD_TYPE_BITPOS, \
174 QAT_COMN_CD_FLD_TYPE_MASK)
176 #define ICP_QAT_FW_COMN_PTR_TYPE_SET(flags, val) \
177 QAT_FIELD_SET(flags, val, QAT_COMN_PTR_TYPE_BITPOS, \
178 QAT_COMN_PTR_TYPE_MASK)
180 #define ICP_QAT_FW_COMN_CD_FLD_TYPE_SET(flags, val) \
181 QAT_FIELD_SET(flags, val, QAT_COMN_CD_FLD_TYPE_BITPOS, \
182 QAT_COMN_CD_FLD_TYPE_MASK)
184 #define ICP_QAT_FW_COMN_NEXT_ID_BITPOS 4
185 #define ICP_QAT_FW_COMN_NEXT_ID_MASK 0xF0
186 #define ICP_QAT_FW_COMN_CURR_ID_BITPOS 0
187 #define ICP_QAT_FW_COMN_CURR_ID_MASK 0x0F
189 #define ICP_QAT_FW_COMN_NEXT_ID_GET(cd_ctrl_hdr_t) \
190 ((((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \
191 >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))
193 #define ICP_QAT_FW_COMN_NEXT_ID_SET(cd_ctrl_hdr_t, val) \
194 { ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \
195 & ICP_QAT_FW_COMN_CURR_ID_MASK) | \
196 ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
197 & ICP_QAT_FW_COMN_NEXT_ID_MASK)); }
199 #define ICP_QAT_FW_COMN_CURR_ID_GET(cd_ctrl_hdr_t) \
200 (((cd_ctrl_hdr_t)->next_curr_id) & ICP_QAT_FW_COMN_CURR_ID_MASK)
202 #define ICP_QAT_FW_COMN_CURR_ID_SET(cd_ctrl_hdr_t, val) \
203 { ((cd_ctrl_hdr_t)->next_curr_id) = ((((cd_ctrl_hdr_t)->next_curr_id) \
204 & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
205 ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)); }
207 #define QAT_COMN_RESP_CRYPTO_STATUS_BITPOS 7
208 #define QAT_COMN_RESP_CRYPTO_STATUS_MASK 0x1
209 #define QAT_COMN_RESP_CMP_STATUS_BITPOS 5
210 #define QAT_COMN_RESP_CMP_STATUS_MASK 0x1
211 #define QAT_COMN_RESP_XLAT_STATUS_BITPOS 4
212 #define QAT_COMN_RESP_XLAT_STATUS_MASK 0x1
213 #define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS 3
214 #define QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK 0x1
216 #define ICP_QAT_FW_COMN_RESP_STATUS_BUILD(crypto, comp, xlat, eolb) \
217 ((((crypto) & QAT_COMN_RESP_CRYPTO_STATUS_MASK) << \
218 QAT_COMN_RESP_CRYPTO_STATUS_BITPOS) | \
219 (((comp) & QAT_COMN_RESP_CMP_STATUS_MASK) << \
220 QAT_COMN_RESP_CMP_STATUS_BITPOS) | \
221 (((xlat) & QAT_COMN_RESP_XLAT_STATUS_MASK) << \
222 QAT_COMN_RESP_XLAT_STATUS_BITPOS) | \
223 (((eolb) & QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK) << \
224 QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS))
226 #define ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(status) \
227 QAT_FIELD_GET(status, QAT_COMN_RESP_CRYPTO_STATUS_BITPOS, \
228 QAT_COMN_RESP_CRYPTO_STATUS_MASK)
230 #define ICP_QAT_FW_COMN_RESP_CMP_STAT_GET(status) \
231 QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_STATUS_BITPOS, \
232 QAT_COMN_RESP_CMP_STATUS_MASK)
234 #define ICP_QAT_FW_COMN_RESP_XLAT_STAT_GET(status) \
235 QAT_FIELD_GET(status, QAT_COMN_RESP_XLAT_STATUS_BITPOS, \
236 QAT_COMN_RESP_XLAT_STATUS_MASK)
238 #define ICP_QAT_FW_COMN_RESP_CMP_END_OF_LAST_BLK_FLAG_GET(status) \
239 QAT_FIELD_GET(status, QAT_COMN_RESP_CMP_END_OF_LAST_BLK_BITPOS, \
240 QAT_COMN_RESP_CMP_END_OF_LAST_BLK_MASK)
242 #define ICP_QAT_FW_COMN_STATUS_FLAG_OK 0
243 #define ICP_QAT_FW_COMN_STATUS_FLAG_ERROR 1
244 #define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_CLR 0
245 #define ICP_QAT_FW_COMN_STATUS_CMP_END_OF_LAST_BLK_FLAG_SET 1
246 #define ERR_CODE_NO_ERROR 0
247 #define ERR_CODE_INVALID_BLOCK_TYPE -1
248 #define ERR_CODE_NO_MATCH_ONES_COMP -2
249 #define ERR_CODE_TOO_MANY_LEN_OR_DIS -3
250 #define ERR_CODE_INCOMPLETE_LEN -4
251 #define ERR_CODE_RPT_LEN_NO_FIRST_LEN -5
252 #define ERR_CODE_RPT_GT_SPEC_LEN -6
253 #define ERR_CODE_INV_LIT_LEN_CODE_LEN -7
254 #define ERR_CODE_INV_DIS_CODE_LEN -8
255 #define ERR_CODE_INV_LIT_LEN_DIS_IN_BLK -9
256 #define ERR_CODE_DIS_TOO_FAR_BACK -10
257 #define ERR_CODE_OVERFLOW_ERROR -11
258 #define ERR_CODE_SOFT_ERROR -12
259 #define ERR_CODE_FATAL_ERROR -13
260 #define ERR_CODE_SSM_ERROR -14
261 #define ERR_CODE_ENDPOINT_ERROR -15
263 enum icp_qat_fw_slice {
264 ICP_QAT_FW_SLICE_NULL = 0,
265 ICP_QAT_FW_SLICE_CIPHER = 1,
266 ICP_QAT_FW_SLICE_AUTH = 2,
267 ICP_QAT_FW_SLICE_DRAM_RD = 3,
268 ICP_QAT_FW_SLICE_DRAM_WR = 4,
269 ICP_QAT_FW_SLICE_COMP = 5,
270 ICP_QAT_FW_SLICE_XLAT = 6,
271 ICP_QAT_FW_SLICE_DELIMITER