1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2015-2018 Intel Corporation
4 #ifndef _ICP_QAT_FW_COMP_H_
5 #define _ICP_QAT_FW_COMP_H_
7 #include "icp_qat_fw.h"
9 enum icp_qat_fw_comp_cmd_id {
10 ICP_QAT_FW_COMP_CMD_STATIC = 0,
11 /*!< Static Compress Request */
13 ICP_QAT_FW_COMP_CMD_DYNAMIC = 1,
14 /*!< Dynamic Compress Request */
16 ICP_QAT_FW_COMP_CMD_DECOMPRESS = 2,
17 /*!< Decompress Request */
19 ICP_QAT_FW_COMP_CMD_DELIMITER
20 /**< Delimiter type */
25 #define ICP_QAT_FW_COMP_STATELESS_SESSION 0
26 /**< @ingroup icp_qat_fw_comp
27 * Flag representing that session is stateless
30 #define ICP_QAT_FW_COMP_STATEFUL_SESSION 1
31 /**< @ingroup icp_qat_fw_comp
32 * Flag representing that session is stateful
35 #define ICP_QAT_FW_COMP_NOT_AUTO_SELECT_BEST 0
36 /**< @ingroup icp_qat_fw_comp
37 * Flag representing that autoselectbest is NOT used
40 #define ICP_QAT_FW_COMP_AUTO_SELECT_BEST 1
41 /**< @ingroup icp_qat_fw_comp
42 * Flag representing that autoselectbest is used
45 #define ICP_QAT_FW_COMP_NOT_ENH_AUTO_SELECT_BEST 0
46 /**< @ingroup icp_qat_fw_comp
47 * Flag representing that enhanced autoselectbest is NOT used
50 #define ICP_QAT_FW_COMP_ENH_AUTO_SELECT_BEST 1
51 /**< @ingroup icp_qat_fw_comp
52 * Flag representing that enhanced autoselectbest is used
55 #define ICP_QAT_FW_COMP_NOT_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 0
56 /**< @ingroup icp_qat_fw_comp
57 * Flag representing that enhanced autoselectbest is NOT used
60 #define ICP_QAT_FW_COMP_DISABLE_TYPE0_ENH_AUTO_SELECT_BEST 1
61 /**< @ingroup icp_qat_fw_comp
62 * Flag representing that enhanced autoselectbest is used
65 #define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_USED_AS_INTMD_BUF 1
66 /**< @ingroup icp_qat_fw_comp
67 * Flag representing secure RAM from being used as
68 * an intermediate buffer is DISABLED.
71 #define ICP_QAT_FW_COMP_ENABLE_SECURE_RAM_USED_AS_INTMD_BUF 0
72 /**< @ingroup icp_qat_fw_comp
73 * Flag representing secure RAM from being used as
74 * an intermediate buffer is ENABLED.
77 /**< Flag mask & bit position */
79 #define ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS 2
80 /**< @ingroup icp_qat_fw_comp
81 * Starting bit position for the session type
84 #define ICP_QAT_FW_COMP_SESSION_TYPE_MASK 0x1
85 /**< @ingroup icp_qat_fw_comp
86 * One bit mask used to determine the session type
89 #define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS 3
90 /**< @ingroup icp_qat_fw_comp
91 * Starting bit position for auto select best
94 #define ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK 0x1
95 /**< @ingroup icp_qat_fw_comp
96 * One bit mask for auto select best
99 #define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS 4
100 /**< @ingroup icp_qat_fw_comp
101 * Starting bit position for enhanced auto select best
104 #define ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK 0x1
105 /**< @ingroup icp_qat_fw_comp
106 * One bit mask for enhanced auto select best
109 #define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS 5
110 /**< @ingroup icp_qat_fw_comp
111 * Starting bit position for disabling type zero header write back
112 * when Enhanced autoselect best is enabled. If set firmware does
113 * not return type0 store block header, only copies src to dest.
114 * (if best output is Type0)
117 #define ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK 0x1
118 /**< @ingroup icp_qat_fw_comp
119 * One bit mask for auto select best
122 #define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS 7
123 /**< @ingroup icp_qat_fw_comp
124 * Starting bit position for flag used to disable secure ram from
125 * being used as an intermediate buffer.
128 #define ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK 0x1
129 /**< @ingroup icp_qat_fw_comp
130 * One bit mask for disable secure ram for use as an intermediate
134 #define ICP_QAT_FW_COMP_FLAGS_BUILD(sesstype, autoselect, enhanced_asb, \
135 ret_uncomp, secure_ram) \
136 ((((sesstype)&ICP_QAT_FW_COMP_SESSION_TYPE_MASK) \
137 << ICP_QAT_FW_COMP_SESSION_TYPE_BITPOS) | \
138 (((autoselect)&ICP_QAT_FW_COMP_AUTO_SELECT_BEST_MASK) \
139 << ICP_QAT_FW_COMP_AUTO_SELECT_BEST_BITPOS) | \
140 (((enhanced_asb)&ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_MASK) \
141 << ICP_QAT_FW_COMP_ENHANCED_AUTO_SELECT_BEST_BITPOS) | \
142 (((ret_uncomp)&ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_MASK) \
143 << ICP_QAT_FW_COMP_RET_DISABLE_TYPE0_HEADER_DATA_BITPOS) | \
144 (((secure_ram)&ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_MASK) \
145 << ICP_QAT_FW_COMP_DISABLE_SECURE_RAM_AS_INTMD_BUF_BITPOS))
147 union icp_qat_fw_comp_req_hdr_cd_pars {
150 uint64_t content_desc_addr;
151 /**< Address of the content descriptor */
153 uint16_t content_desc_resrvd1;
154 /**< Content descriptor reserved field */
156 uint8_t content_desc_params_sz;
157 /**< Size of the content descriptor parameters in quad words.
158 * These parameters describe the session setup configuration
159 * info for the slices that this request relies upon i.e.
160 * the configuration word and cipher key needed by the cipher
161 * slice if there is a request for cipher processing.
164 uint8_t content_desc_hdr_resrvd2;
165 /**< Content descriptor reserved field */
167 uint32_t content_desc_resrvd3;
168 /**< Content descriptor reserved field */
172 uint32_t comp_slice_cfg_word[ICP_QAT_FW_NUM_LONGWORDS_2];
173 /* Compression Slice Config Word */
175 uint32_t content_desc_resrvd4;
176 /**< Content descriptor reserved field */
182 struct icp_qat_fw_comp_req_params {
185 /**< Size of input to process in bytes Note: Only EOP requests can be
186 * odd for decompression. IA must set LSB to zero for odd sized
187 * intermediate inputs
191 uint32_t out_buffer_sz;
192 /**< Size of output buffer in bytes */
195 uint32_t initial_crc32;
196 /**< CRC of previously processed bytes */
199 uint32_t initial_adler;
200 /**< Adler of previously processed bytes */
203 uint32_t req_par_flags;
209 #define ICP_QAT_FW_COMP_REQ_PARAM_FLAGS_BUILD(sop, eop, bfinal, cnv, cnvnr) \
210 ((((sop)&ICP_QAT_FW_COMP_SOP_MASK) << ICP_QAT_FW_COMP_SOP_BITPOS) | \
211 (((eop)&ICP_QAT_FW_COMP_EOP_MASK) << ICP_QAT_FW_COMP_EOP_BITPOS) | \
212 (((bfinal)&ICP_QAT_FW_COMP_BFINAL_MASK) \
213 << ICP_QAT_FW_COMP_BFINAL_BITPOS) | \
214 ((cnv & ICP_QAT_FW_COMP_CNV_MASK) << ICP_QAT_FW_COMP_CNV_BITPOS) | \
215 ((cnvnr & ICP_QAT_FW_COMP_CNV_RECOVERY_MASK) \
216 << ICP_QAT_FW_COMP_CNV_RECOVERY_BITPOS))
218 #define ICP_QAT_FW_COMP_NOT_SOP 0
219 /**< @ingroup icp_qat_fw_comp
220 * Flag representing that a request is NOT Start of Packet
223 #define ICP_QAT_FW_COMP_SOP 1
224 /**< @ingroup icp_qat_fw_comp
225 * Flag representing that a request IS Start of Packet
228 #define ICP_QAT_FW_COMP_NOT_EOP 0
229 /**< @ingroup icp_qat_fw_comp
230 * Flag representing that a request is NOT Start of Packet
233 #define ICP_QAT_FW_COMP_EOP 1
234 /**< @ingroup icp_qat_fw_comp
235 * Flag representing that a request IS End of Packet
238 #define ICP_QAT_FW_COMP_NOT_BFINAL 0
239 /**< @ingroup icp_qat_fw_comp
240 * Flag representing to indicate firmware this is not the last block
243 #define ICP_QAT_FW_COMP_BFINAL 1
244 /**< @ingroup icp_qat_fw_comp
245 * Flag representing to indicate firmware this is the last block
248 #define ICP_QAT_FW_COMP_NO_CNV 0
249 /**< @ingroup icp_qat_fw_comp
250 * Flag indicating that NO cnv check is to be performed on the request
253 #define ICP_QAT_FW_COMP_CNV 1
254 /**< @ingroup icp_qat_fw_comp
255 * Flag indicating that a cnv check IS to be performed on the request
258 #define ICP_QAT_FW_COMP_NO_CNV_RECOVERY 0
259 /**< @ingroup icp_qat_fw_comp
260 * Flag indicating that NO cnv recovery is to be performed on the request
263 #define ICP_QAT_FW_COMP_CNV_RECOVERY 1
264 /**< @ingroup icp_qat_fw_comp
265 * Flag indicating that a cnv recovery is to be performed on the request
268 #define ICP_QAT_FW_COMP_SOP_BITPOS 0
269 /**< @ingroup icp_qat_fw_comp
270 * Starting bit position for SOP
273 #define ICP_QAT_FW_COMP_SOP_MASK 0x1
274 /**< @ingroup icp_qat_fw_comp
275 * One bit mask used to determine SOP
278 #define ICP_QAT_FW_COMP_EOP_BITPOS 1
279 /**< @ingroup icp_qat_fw_comp
280 * Starting bit position for EOP
283 #define ICP_QAT_FW_COMP_EOP_MASK 0x1
284 /**< @ingroup icp_qat_fw_comp
285 * One bit mask used to determine EOP
288 #define ICP_QAT_FW_COMP_BFINAL_MASK 0x1
289 /**< @ingroup icp_qat_fw_comp
290 * One bit mask for the bfinal bit
293 #define ICP_QAT_FW_COMP_BFINAL_BITPOS 6
294 /**< @ingroup icp_qat_fw_comp
295 * Starting bit position for the bfinal bit
298 #define ICP_QAT_FW_COMP_CNV_MASK 0x1
299 /**< @ingroup icp_qat_fw_comp
300 * One bit mask for the CNV bit
303 #define ICP_QAT_FW_COMP_CNV_BITPOS 16
304 /**< @ingroup icp_qat_fw_comp
305 * Starting bit position for the CNV bit
308 #define ICP_QAT_FW_COMP_CNV_RECOVERY_MASK 0x1
309 /**< @ingroup icp_qat_fw_comp
310 * One bit mask for the CNV Recovery bit
313 #define ICP_QAT_FW_COMP_CNV_RECOVERY_BITPOS 17
314 /**< @ingroup icp_qat_fw_comp
315 * Starting bit position for the CNV Recovery bit
318 struct icp_qat_fw_xlt_req_params {
320 uint64_t inter_buff_ptr;
321 /**< This field specifies the physical address of an intermediate
322 * buffer SGL array. The array contains a pair of 64-bit
323 * intermediate buffer pointers to SGL buffer descriptors, one pair
324 * per CPM. Please refer to the CPM1.6 Firmware Interface HLD
325 * specification for more details.
330 struct icp_qat_fw_comp_cd_hdr {
332 uint16_t ram_bank_flags;
333 /**< Flags to show which ram banks to access */
335 uint8_t comp_cfg_offset;
336 /**< Quad word offset from the content descriptor parameters address
337 * to the parameters for the compression processing
340 uint8_t next_curr_id;
341 /**< This field combines the next and current id (each four bits) -
342 * the next id is the most significant nibble.
343 * Next Id: Set to the next slice to pass the compressed data through.
344 * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
345 * anymore slices after compression
346 * Current Id: Initialised with the compression slice type
353 uint64_t comp_state_addr;
354 /**< Pointer to compression state */
357 uint64_t ram_banks_addr;
358 /**< Pointer to banks */
363 struct icp_qat_fw_xlt_cd_hdr {
366 /**< Reserved field and assumed set to 0 */
369 /**< Reserved field and assumed set to 0 */
371 uint8_t next_curr_id;
372 /**< This field combines the next and current id (each four bits) -
373 * the next id is the most significant nibble.
374 * Next Id: Set to the next slice to pass the translated data through.
375 * Set to ICP_QAT_FW_SLICE_DRAM_WR if the data is not to go through
376 * any more slices after compression
377 * Current Id: Initialised with the translation slice type
382 /**< Reserved and should be set to zero, needed for quadword
387 struct icp_qat_fw_comp_req {
389 struct icp_qat_fw_comn_req_hdr comn_hdr;
390 /**< Common request header - for Service Command Id,
391 * use service-specific Compression Command Id.
392 * Service Specific Flags - use Compression Command Flags
396 union icp_qat_fw_comp_req_hdr_cd_pars cd_pars;
397 /**< Compression service-specific content descriptor field which points
398 * either to a content descriptor parameter block or contains the
399 * compression slice config word.
403 struct icp_qat_fw_comn_req_mid comn_mid;
404 /**< Common request middle section */
407 struct icp_qat_fw_comp_req_params comp_pars;
408 /**< Compression request Parameters block */
412 struct icp_qat_fw_xlt_req_params xlt_pars;
413 /**< Translation request Parameters block */
414 uint32_t resrvd1[ICP_QAT_FW_NUM_LONGWORDS_2];
415 /**< Reserved if not used for translation */
421 uint32_t resrvd2[ICP_QAT_FW_NUM_LONGWORDS_2];
422 /**< Reserved - not used if Batch and Pack is disabled.*/
424 uint64_t bnp_res_table_addr;
425 /**< A generic pointer to the unbounded list of
426 * icp_qat_fw_resp_comp_pars members. This pointer is only
427 * used when the Batch and Pack is enabled.
432 struct icp_qat_fw_comp_cd_hdr comp_cd_ctrl;
433 /**< Compression request content descriptor control block header */
437 struct icp_qat_fw_xlt_cd_hdr xlt_cd_ctrl;
438 /**< Translation request content descriptor
439 * control block header
442 uint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_2];
443 /**< Reserved if not used for translation */
447 struct icp_qat_fw_resp_comp_pars {
449 uint32_t input_byte_counter;
450 /**< Input byte counter */
453 uint32_t output_byte_counter;
454 /**< Output byte counter */
458 uint64_t curr_chksum;
463 uint32_t curr_adler_32;
468 struct icp_qat_fw_comp_resp {
470 struct icp_qat_fw_comn_resp_hdr comn_resp;
471 /**< Common interface response format see icp_qat_fw.h */
474 uint64_t opaque_data;
475 /**< Opaque data passed from the request to the response message */
478 struct icp_qat_fw_resp_comp_pars comp_resp_pars;
479 /**< Common response params (checksums and byte counts) */