1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2015-2019 Intel Corporation
4 #ifndef _ICP_QAT_FW_LA_H_
5 #define _ICP_QAT_FW_LA_H_
6 #include "icp_qat_fw.h"
8 enum icp_qat_fw_la_cmd_id {
9 ICP_QAT_FW_LA_CMD_CIPHER = 0,
10 ICP_QAT_FW_LA_CMD_AUTH = 1,
11 ICP_QAT_FW_LA_CMD_CIPHER_HASH = 2,
12 ICP_QAT_FW_LA_CMD_HASH_CIPHER = 3,
13 ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM = 4,
14 ICP_QAT_FW_LA_CMD_TRNG_TEST = 5,
15 ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE = 6,
16 ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE = 7,
17 ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE = 8,
18 ICP_QAT_FW_LA_CMD_MGF1 = 9,
19 ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP = 10,
20 ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP = 11,
21 ICP_QAT_FW_LA_CMD_DELIMITER = 12
24 #define ICP_QAT_FW_LA_ICV_VER_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK
25 #define ICP_QAT_FW_LA_ICV_VER_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR
26 #define ICP_QAT_FW_LA_TRNG_STATUS_PASS ICP_QAT_FW_COMN_STATUS_FLAG_OK
27 #define ICP_QAT_FW_LA_TRNG_STATUS_FAIL ICP_QAT_FW_COMN_STATUS_FLAG_ERROR
29 struct icp_qat_fw_la_bulk_req {
30 struct icp_qat_fw_comn_req_hdr comn_hdr;
31 struct icp_qat_fw_comn_req_hdr_cd_pars cd_pars;
32 struct icp_qat_fw_comn_req_mid comn_mid;
33 struct icp_qat_fw_comn_req_rqpars serv_specif_rqpars;
34 struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl;
37 #define QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_BITPOS 13
38 #define ICP_QAT_FW_LA_SINGLE_PASS_PROTO 1
39 #define QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_MASK 0x1
40 #define ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS 1
41 #define ICP_QAT_FW_LA_GCM_IV_LEN_NOT_12_OCTETS 0
42 #define QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS 12
43 #define ICP_QAT_FW_LA_ZUC_3G_PROTO 1
44 #define QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK 0x1
45 #define QAT_LA_GCM_IV_LEN_FLAG_BITPOS 11
46 #define QAT_LA_GCM_IV_LEN_FLAG_MASK 0x1
47 #define ICP_QAT_FW_LA_DIGEST_IN_BUFFER 1
48 #define ICP_QAT_FW_LA_NO_DIGEST_IN_BUFFER 0
49 #define QAT_LA_DIGEST_IN_BUFFER_BITPOS 10
50 #define QAT_LA_DIGEST_IN_BUFFER_MASK 0x1
51 #define ICP_QAT_FW_LA_SNOW_3G_PROTO 4
52 #define ICP_QAT_FW_LA_GCM_PROTO 2
53 #define ICP_QAT_FW_LA_CCM_PROTO 1
54 #define ICP_QAT_FW_LA_NO_PROTO 0
55 #define QAT_LA_PROTO_BITPOS 7
56 #define QAT_LA_PROTO_MASK 0x7
57 #define ICP_QAT_FW_LA_CMP_AUTH_RES 1
58 #define ICP_QAT_FW_LA_NO_CMP_AUTH_RES 0
59 #define QAT_LA_CMP_AUTH_RES_BITPOS 6
60 #define QAT_LA_CMP_AUTH_RES_MASK 0x1
61 #define ICP_QAT_FW_LA_RET_AUTH_RES 1
62 #define ICP_QAT_FW_LA_NO_RET_AUTH_RES 0
63 #define QAT_LA_RET_AUTH_RES_BITPOS 5
64 #define QAT_LA_RET_AUTH_RES_MASK 0x1
65 #define ICP_QAT_FW_LA_UPDATE_STATE 1
66 #define ICP_QAT_FW_LA_NO_UPDATE_STATE 0
67 #define QAT_LA_UPDATE_STATE_BITPOS 4
68 #define QAT_LA_UPDATE_STATE_MASK 0x1
69 #define ICP_QAT_FW_CIPH_AUTH_CFG_OFFSET_IN_CD_SETUP 0
70 #define ICP_QAT_FW_CIPH_AUTH_CFG_OFFSET_IN_SHRAM_CP 1
71 #define QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS 3
72 #define QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK 0x1
73 #define ICP_QAT_FW_CIPH_IV_64BIT_PTR 0
74 #define ICP_QAT_FW_CIPH_IV_16BYTE_DATA 1
75 #define QAT_LA_CIPH_IV_FLD_BITPOS 2
76 #define QAT_LA_CIPH_IV_FLD_MASK 0x1
77 #define ICP_QAT_FW_LA_PARTIAL_NONE 0
78 #define ICP_QAT_FW_LA_PARTIAL_START 1
79 #define ICP_QAT_FW_LA_PARTIAL_MID 3
80 #define ICP_QAT_FW_LA_PARTIAL_END 2
81 #define QAT_LA_PARTIAL_BITPOS 0
82 #define QAT_LA_PARTIAL_MASK 0x3
83 #define ICP_QAT_FW_LA_FLAGS_BUILD(zuc_proto, gcm_iv_len, auth_rslt, proto, \
84 cmp_auth, ret_auth, update_state, \
85 ciph_iv, ciphcfg, partial) \
86 (((zuc_proto & QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK) << \
87 QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS) | \
88 ((gcm_iv_len & QAT_LA_GCM_IV_LEN_FLAG_MASK) << \
89 QAT_LA_GCM_IV_LEN_FLAG_BITPOS) | \
90 ((auth_rslt & QAT_LA_DIGEST_IN_BUFFER_MASK) << \
91 QAT_LA_DIGEST_IN_BUFFER_BITPOS) | \
92 ((proto & QAT_LA_PROTO_MASK) << \
93 QAT_LA_PROTO_BITPOS) | \
94 ((cmp_auth & QAT_LA_CMP_AUTH_RES_MASK) << \
95 QAT_LA_CMP_AUTH_RES_BITPOS) | \
96 ((ret_auth & QAT_LA_RET_AUTH_RES_MASK) << \
97 QAT_LA_RET_AUTH_RES_BITPOS) | \
98 ((update_state & QAT_LA_UPDATE_STATE_MASK) << \
99 QAT_LA_UPDATE_STATE_BITPOS) | \
100 ((ciph_iv & QAT_LA_CIPH_IV_FLD_MASK) << \
101 QAT_LA_CIPH_IV_FLD_BITPOS) | \
102 ((ciphcfg & QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK) << \
103 QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS) | \
104 ((partial & QAT_LA_PARTIAL_MASK) << \
105 QAT_LA_PARTIAL_BITPOS))
107 #define ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_GET(flags) \
108 QAT_FIELD_GET(flags, QAT_LA_CIPH_IV_FLD_BITPOS, \
109 QAT_LA_CIPH_IV_FLD_MASK)
111 #define ICP_QAT_FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_GET(flags) \
112 QAT_FIELD_GET(flags, QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS, \
113 QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK)
115 #define ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_GET(flags) \
116 QAT_FIELD_GET(flags, QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS, \
117 QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK)
119 #define ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_GET(flags) \
120 QAT_FIELD_GET(flags, QAT_LA_GCM_IV_LEN_FLAG_BITPOS, \
121 QAT_LA_GCM_IV_LEN_FLAG_MASK)
123 #define ICP_QAT_FW_LA_PROTO_GET(flags) \
124 QAT_FIELD_GET(flags, QAT_LA_PROTO_BITPOS, QAT_LA_PROTO_MASK)
126 #define ICP_QAT_FW_LA_CMP_AUTH_GET(flags) \
127 QAT_FIELD_GET(flags, QAT_LA_CMP_AUTH_RES_BITPOS, \
128 QAT_LA_CMP_AUTH_RES_MASK)
130 #define ICP_QAT_FW_LA_RET_AUTH_GET(flags) \
131 QAT_FIELD_GET(flags, QAT_LA_RET_AUTH_RES_BITPOS, \
132 QAT_LA_RET_AUTH_RES_MASK)
134 #define ICP_QAT_FW_LA_DIGEST_IN_BUFFER_GET(flags) \
135 QAT_FIELD_GET(flags, QAT_LA_DIGEST_IN_BUFFER_BITPOS, \
136 QAT_LA_DIGEST_IN_BUFFER_MASK)
138 #define ICP_QAT_FW_LA_UPDATE_STATE_GET(flags) \
139 QAT_FIELD_GET(flags, QAT_LA_UPDATE_STATE_BITPOS, \
140 QAT_LA_UPDATE_STATE_MASK)
142 #define ICP_QAT_FW_LA_PARTIAL_GET(flags) \
143 QAT_FIELD_GET(flags, QAT_LA_PARTIAL_BITPOS, \
146 #define ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(flags, val) \
147 QAT_FIELD_SET(flags, val, QAT_LA_CIPH_IV_FLD_BITPOS, \
148 QAT_LA_CIPH_IV_FLD_MASK)
150 #define ICP_QAT_FW_LA_CIPH_AUTH_CFG_OFFSET_FLAG_SET(flags, val) \
151 QAT_FIELD_SET(flags, val, QAT_LA_CIPH_AUTH_CFG_OFFSET_BITPOS, \
152 QAT_LA_CIPH_AUTH_CFG_OFFSET_MASK)
154 #define ICP_QAT_FW_LA_ZUC_3G_PROTO_FLAG_SET(flags, val) \
155 QAT_FIELD_SET(flags, val, QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS, \
156 QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK)
158 #define ICP_QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_SET(flags, val) \
159 QAT_FIELD_SET(flags, val, QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_BITPOS, \
160 QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_MASK)
162 #define ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(flags, val) \
163 QAT_FIELD_SET(flags, val, QAT_LA_GCM_IV_LEN_FLAG_BITPOS, \
164 QAT_LA_GCM_IV_LEN_FLAG_MASK)
166 #define ICP_QAT_FW_LA_PROTO_SET(flags, val) \
167 QAT_FIELD_SET(flags, val, QAT_LA_PROTO_BITPOS, \
170 #define ICP_QAT_FW_LA_CMP_AUTH_SET(flags, val) \
171 QAT_FIELD_SET(flags, val, QAT_LA_CMP_AUTH_RES_BITPOS, \
172 QAT_LA_CMP_AUTH_RES_MASK)
174 #define ICP_QAT_FW_LA_RET_AUTH_SET(flags, val) \
175 QAT_FIELD_SET(flags, val, QAT_LA_RET_AUTH_RES_BITPOS, \
176 QAT_LA_RET_AUTH_RES_MASK)
178 #define ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(flags, val) \
179 QAT_FIELD_SET(flags, val, QAT_LA_DIGEST_IN_BUFFER_BITPOS, \
180 QAT_LA_DIGEST_IN_BUFFER_MASK)
182 #define ICP_QAT_FW_LA_UPDATE_STATE_SET(flags, val) \
183 QAT_FIELD_SET(flags, val, QAT_LA_UPDATE_STATE_BITPOS, \
184 QAT_LA_UPDATE_STATE_MASK)
186 #define ICP_QAT_FW_LA_PARTIAL_SET(flags, val) \
187 QAT_FIELD_SET(flags, val, QAT_LA_PARTIAL_BITPOS, \
190 struct icp_qat_fw_cipher_req_hdr_cd_pars {
193 uint64_t content_desc_addr;
194 uint16_t content_desc_resrvd1;
195 uint8_t content_desc_params_sz;
196 uint8_t content_desc_hdr_resrvd2;
197 uint32_t content_desc_resrvd3;
200 uint32_t cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];
205 struct icp_qat_fw_cipher_auth_req_hdr_cd_pars {
208 uint64_t content_desc_addr;
209 uint16_t content_desc_resrvd1;
210 uint8_t content_desc_params_sz;
211 uint8_t content_desc_hdr_resrvd2;
212 uint32_t content_desc_resrvd3;
215 uint32_t cipher_key_array[ICP_QAT_FW_NUM_LONGWORDS_4];
220 struct icp_qat_fw_cipher_cd_ctrl_hdr {
221 uint8_t cipher_state_sz;
222 uint8_t cipher_key_sz;
223 uint8_t cipher_cfg_offset;
224 uint8_t next_curr_id;
225 uint8_t cipher_padding_sz;
228 uint32_t resrvd3[ICP_QAT_FW_NUM_LONGWORDS_3];
231 struct icp_qat_fw_auth_cd_ctrl_hdr {
235 uint8_t hash_cfg_offset;
236 uint8_t next_curr_id;
238 uint8_t outer_prefix_sz;
240 uint8_t inner_res_sz;
242 uint8_t inner_state1_sz;
243 uint8_t inner_state2_offset;
244 uint8_t inner_state2_sz;
245 uint8_t outer_config_offset;
246 uint8_t outer_state1_sz;
247 uint8_t outer_res_sz;
248 uint8_t outer_prefix_offset;
251 struct icp_qat_fw_cipher_auth_cd_ctrl_hdr {
252 uint8_t cipher_state_sz;
253 uint8_t cipher_key_sz;
254 uint8_t cipher_cfg_offset;
255 uint8_t next_curr_id_cipher;
256 uint8_t cipher_padding_sz;
258 uint8_t hash_cfg_offset;
259 uint8_t next_curr_id_auth;
261 uint8_t outer_prefix_sz;
263 uint8_t inner_res_sz;
265 uint8_t inner_state1_sz;
266 uint8_t inner_state2_offset;
267 uint8_t inner_state2_sz;
268 uint8_t outer_config_offset;
269 uint8_t outer_state1_sz;
270 uint8_t outer_res_sz;
271 uint8_t outer_prefix_offset;
274 #define ICP_QAT_FW_AUTH_HDR_FLAG_DO_NESTED 1
275 #define ICP_QAT_FW_AUTH_HDR_FLAG_NO_NESTED 0
276 #define ICP_QAT_FW_AUTH_HDR_FLAG_SNOW3G_UIA2_BITPOS 3
277 #define ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS 4
278 #define ICP_QAT_FW_CCM_GCM_AAD_SZ_MAX 240
279 #define ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET 24
280 #define ICP_QAT_FW_CIPHER_REQUEST_PARAMETERS_OFFSET (0)
282 struct icp_qat_fw_la_cipher_req_params {
283 uint32_t cipher_offset;
284 uint32_t cipher_length;
286 uint32_t cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4];
288 uint64_t cipher_IV_ptr;
292 uint64_t spc_aad_addr;
293 uint64_t spc_auth_res_addr;
296 uint8_t spc_auth_res_sz;
299 struct icp_qat_fw_la_auth_req_params {
303 uint64_t auth_partial_st_prefix;
306 uint64_t auth_res_addr;
308 uint8_t inner_prefix_sz;
312 uint8_t hash_state_sz;
316 struct icp_qat_fw_la_auth_req_params_resrvd_flds {
317 uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_6];
319 uint8_t inner_prefix_sz;
326 struct icp_qat_fw_la_resp {
327 struct icp_qat_fw_comn_resp_hdr comn_resp;
328 uint64_t opaque_data;
329 uint32_t resrvd[ICP_QAT_FW_NUM_LONGWORDS_4];
332 #define ICP_QAT_FW_CIPHER_NEXT_ID_GET(cd_ctrl_hdr_t) \
333 ((((cd_ctrl_hdr_t)->next_curr_id_cipher) & \
334 ICP_QAT_FW_COMN_NEXT_ID_MASK) >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))
336 #define ICP_QAT_FW_CIPHER_NEXT_ID_SET(cd_ctrl_hdr_t, val) \
337 { (cd_ctrl_hdr_t)->next_curr_id_cipher = \
338 ((((cd_ctrl_hdr_t)->next_curr_id_cipher) \
339 & ICP_QAT_FW_COMN_CURR_ID_MASK) | \
340 ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
341 & ICP_QAT_FW_COMN_NEXT_ID_MASK)) }
343 #define ICP_QAT_FW_CIPHER_CURR_ID_GET(cd_ctrl_hdr_t) \
344 (((cd_ctrl_hdr_t)->next_curr_id_cipher) \
345 & ICP_QAT_FW_COMN_CURR_ID_MASK)
347 #define ICP_QAT_FW_CIPHER_CURR_ID_SET(cd_ctrl_hdr_t, val) \
348 { (cd_ctrl_hdr_t)->next_curr_id_cipher = \
349 ((((cd_ctrl_hdr_t)->next_curr_id_cipher) \
350 & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
351 ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) }
353 #define ICP_QAT_FW_AUTH_NEXT_ID_GET(cd_ctrl_hdr_t) \
354 ((((cd_ctrl_hdr_t)->next_curr_id_auth) & ICP_QAT_FW_COMN_NEXT_ID_MASK) \
355 >> (ICP_QAT_FW_COMN_NEXT_ID_BITPOS))
357 #define ICP_QAT_FW_AUTH_NEXT_ID_SET(cd_ctrl_hdr_t, val) \
358 { (cd_ctrl_hdr_t)->next_curr_id_auth = \
359 ((((cd_ctrl_hdr_t)->next_curr_id_auth) \
360 & ICP_QAT_FW_COMN_CURR_ID_MASK) | \
361 ((val << ICP_QAT_FW_COMN_NEXT_ID_BITPOS) \
362 & ICP_QAT_FW_COMN_NEXT_ID_MASK)) }
364 #define ICP_QAT_FW_AUTH_CURR_ID_GET(cd_ctrl_hdr_t) \
365 (((cd_ctrl_hdr_t)->next_curr_id_auth) \
366 & ICP_QAT_FW_COMN_CURR_ID_MASK)
368 #define ICP_QAT_FW_AUTH_CURR_ID_SET(cd_ctrl_hdr_t, val) \
369 { (cd_ctrl_hdr_t)->next_curr_id_auth = \
370 ((((cd_ctrl_hdr_t)->next_curr_id_auth) \
371 & ICP_QAT_FW_COMN_NEXT_ID_MASK) | \
372 ((val) & ICP_QAT_FW_COMN_CURR_ID_MASK)) }