1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2015-2018 Intel Corporation
7 enum icp_qat_hw_ae_id {
18 ICP_QAT_HW_AE_10 = 10,
19 ICP_QAT_HW_AE_11 = 11,
20 ICP_QAT_HW_AE_DELIMITER = 12
23 enum icp_qat_hw_qat_id {
30 ICP_QAT_HW_QAT_DELIMITER = 6
33 enum icp_qat_hw_auth_algo {
34 ICP_QAT_HW_AUTH_ALGO_NULL = 0,
35 ICP_QAT_HW_AUTH_ALGO_SHA1 = 1,
36 ICP_QAT_HW_AUTH_ALGO_MD5 = 2,
37 ICP_QAT_HW_AUTH_ALGO_SHA224 = 3,
38 ICP_QAT_HW_AUTH_ALGO_SHA256 = 4,
39 ICP_QAT_HW_AUTH_ALGO_SHA384 = 5,
40 ICP_QAT_HW_AUTH_ALGO_SHA512 = 6,
41 ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC = 7,
42 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC = 8,
43 ICP_QAT_HW_AUTH_ALGO_AES_F9 = 9,
44 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 = 10,
45 ICP_QAT_HW_AUTH_ALGO_GALOIS_64 = 11,
46 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12,
47 ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13,
48 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14,
49 ICP_QAT_HW_AUTH_RESERVED_1 = 15,
50 ICP_QAT_HW_AUTH_RESERVED_2 = 16,
51 ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17,
52 ICP_QAT_HW_AUTH_RESERVED_3 = 18,
53 ICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19,
54 ICP_QAT_HW_AUTH_ALGO_DELIMITER = 20
57 enum icp_qat_hw_auth_mode {
58 ICP_QAT_HW_AUTH_MODE0 = 0,
59 ICP_QAT_HW_AUTH_MODE1 = 1,
60 ICP_QAT_HW_AUTH_MODE2 = 2,
61 ICP_QAT_HW_AUTH_MODE_DELIMITER = 3
64 struct icp_qat_hw_auth_config {
69 #define QAT_AUTH_MODE_BITPOS 4
70 #define QAT_AUTH_MODE_MASK 0xF
71 #define QAT_AUTH_ALGO_BITPOS 0
72 #define QAT_AUTH_ALGO_MASK 0xF
73 #define QAT_AUTH_CMP_BITPOS 8
74 #define QAT_AUTH_CMP_MASK 0x7F
75 #define QAT_AUTH_SHA3_PADDING_BITPOS 16
76 #define QAT_AUTH_SHA3_PADDING_MASK 0x1
77 #define QAT_AUTH_ALGO_SHA3_BITPOS 22
78 #define QAT_AUTH_ALGO_SHA3_MASK 0x3
79 #define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
80 (((mode & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
81 ((algo & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
82 (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) << \
83 QAT_AUTH_ALGO_SHA3_BITPOS) | \
84 (((((algo == ICP_QAT_HW_AUTH_ALGO_SHA3_256) || \
85 (algo == ICP_QAT_HW_AUTH_ALGO_SHA3_512)) ? 1 : 0) \
86 & QAT_AUTH_SHA3_PADDING_MASK) << QAT_AUTH_SHA3_PADDING_BITPOS) | \
87 ((cmp_len & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
89 struct icp_qat_hw_auth_counter {
94 #define QAT_AUTH_COUNT_MASK 0xFFFFFFFF
95 #define QAT_AUTH_COUNT_BITPOS 0
96 #define ICP_QAT_HW_AUTH_COUNT_BUILD(val) \
97 (((val) & QAT_AUTH_COUNT_MASK) << QAT_AUTH_COUNT_BITPOS)
99 struct icp_qat_hw_auth_setup {
100 struct icp_qat_hw_auth_config auth_config;
101 struct icp_qat_hw_auth_counter auth_counter;
104 #define QAT_HW_DEFAULT_ALIGNMENT 8
105 #define QAT_HW_ROUND_UP(val, n) (((val) + ((n) - 1)) & (~(n - 1)))
106 #define ICP_QAT_HW_NULL_STATE1_SZ 32
107 #define ICP_QAT_HW_MD5_STATE1_SZ 16
108 #define ICP_QAT_HW_SHA1_STATE1_SZ 20
109 #define ICP_QAT_HW_SHA224_STATE1_SZ 32
110 #define ICP_QAT_HW_SHA256_STATE1_SZ 32
111 #define ICP_QAT_HW_SHA3_256_STATE1_SZ 32
112 #define ICP_QAT_HW_SHA384_STATE1_SZ 64
113 #define ICP_QAT_HW_SHA512_STATE1_SZ 64
114 #define ICP_QAT_HW_SHA3_512_STATE1_SZ 64
115 #define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
116 #define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
117 #define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16
118 #define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16
119 #define ICP_QAT_HW_AES_F9_STATE1_SZ 32
120 #define ICP_QAT_HW_KASUMI_F9_STATE1_SZ 16
121 #define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16
122 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8
123 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8
124 #define ICP_QAT_HW_NULL_STATE2_SZ 32
125 #define ICP_QAT_HW_MD5_STATE2_SZ 16
126 #define ICP_QAT_HW_SHA1_STATE2_SZ 20
127 #define ICP_QAT_HW_SHA224_STATE2_SZ 32
128 #define ICP_QAT_HW_SHA256_STATE2_SZ 32
129 #define ICP_QAT_HW_SHA3_256_STATE2_SZ 0
130 #define ICP_QAT_HW_SHA384_STATE2_SZ 64
131 #define ICP_QAT_HW_SHA512_STATE2_SZ 64
132 #define ICP_QAT_HW_SHA3_512_STATE2_SZ 0
133 #define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
134 #define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
135 #define ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ 48
136 #define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16
137 #define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16
138 #define ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ 16
139 #define ICP_QAT_HW_F9_IK_SZ 16
140 #define ICP_QAT_HW_F9_FK_SZ 16
141 #define ICP_QAT_HW_KASUMI_F9_STATE2_SZ (ICP_QAT_HW_F9_IK_SZ + \
143 #define ICP_QAT_HW_AES_F9_STATE2_SZ ICP_QAT_HW_KASUMI_F9_STATE2_SZ
144 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ 24
145 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ 32
146 #define ICP_QAT_HW_GALOIS_H_SZ 16
147 #define ICP_QAT_HW_GALOIS_LEN_A_SZ 8
148 #define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16
150 struct icp_qat_hw_auth_sha512 {
151 struct icp_qat_hw_auth_setup inner_setup;
152 uint8_t state1[ICP_QAT_HW_SHA512_STATE1_SZ];
153 struct icp_qat_hw_auth_setup outer_setup;
154 uint8_t state2[ICP_QAT_HW_SHA512_STATE2_SZ];
157 struct icp_qat_hw_auth_algo_blk {
158 struct icp_qat_hw_auth_sha512 sha;
161 #define ICP_QAT_HW_GALOIS_LEN_A_BITPOS 0
162 #define ICP_QAT_HW_GALOIS_LEN_A_MASK 0xFFFFFFFF
164 enum icp_qat_hw_cipher_algo {
165 ICP_QAT_HW_CIPHER_ALGO_NULL = 0,
166 ICP_QAT_HW_CIPHER_ALGO_DES = 1,
167 ICP_QAT_HW_CIPHER_ALGO_3DES = 2,
168 ICP_QAT_HW_CIPHER_ALGO_AES128 = 3,
169 ICP_QAT_HW_CIPHER_ALGO_AES192 = 4,
170 ICP_QAT_HW_CIPHER_ALGO_AES256 = 5,
171 ICP_QAT_HW_CIPHER_ALGO_ARC4 = 6,
172 ICP_QAT_HW_CIPHER_ALGO_KASUMI = 7,
173 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8,
174 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9,
175 ICP_QAT_HW_CIPHER_DELIMITER = 10
178 enum icp_qat_hw_cipher_mode {
179 ICP_QAT_HW_CIPHER_ECB_MODE = 0,
180 ICP_QAT_HW_CIPHER_CBC_MODE = 1,
181 ICP_QAT_HW_CIPHER_CTR_MODE = 2,
182 ICP_QAT_HW_CIPHER_F8_MODE = 3,
183 ICP_QAT_HW_CIPHER_XTS_MODE = 6,
184 ICP_QAT_HW_CIPHER_MODE_DELIMITER = 7
187 struct icp_qat_hw_cipher_config {
192 enum icp_qat_hw_cipher_dir {
193 ICP_QAT_HW_CIPHER_ENCRYPT = 0,
194 ICP_QAT_HW_CIPHER_DECRYPT = 1,
197 enum icp_qat_hw_auth_op {
198 ICP_QAT_HW_AUTH_VERIFY = 0,
199 ICP_QAT_HW_AUTH_GENERATE = 1,
202 enum icp_qat_hw_cipher_convert {
203 ICP_QAT_HW_CIPHER_NO_CONVERT = 0,
204 ICP_QAT_HW_CIPHER_KEY_CONVERT = 1,
207 #define QAT_CIPHER_MODE_BITPOS 4
208 #define QAT_CIPHER_MODE_MASK 0xF
209 #define QAT_CIPHER_ALGO_BITPOS 0
210 #define QAT_CIPHER_ALGO_MASK 0xF
211 #define QAT_CIPHER_CONVERT_BITPOS 9
212 #define QAT_CIPHER_CONVERT_MASK 0x1
213 #define QAT_CIPHER_DIR_BITPOS 8
214 #define QAT_CIPHER_DIR_MASK 0x1
215 #define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2
216 #define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2
217 #define ICP_QAT_HW_CIPHER_CONFIG_BUILD(mode, algo, convert, dir) \
218 (((mode & QAT_CIPHER_MODE_MASK) << QAT_CIPHER_MODE_BITPOS) | \
219 ((algo & QAT_CIPHER_ALGO_MASK) << QAT_CIPHER_ALGO_BITPOS) | \
220 ((convert & QAT_CIPHER_CONVERT_MASK) << QAT_CIPHER_CONVERT_BITPOS) | \
221 ((dir & QAT_CIPHER_DIR_MASK) << QAT_CIPHER_DIR_BITPOS))
222 #define ICP_QAT_HW_DES_BLK_SZ 8
223 #define ICP_QAT_HW_3DES_BLK_SZ 8
224 #define ICP_QAT_HW_NULL_BLK_SZ 8
225 #define ICP_QAT_HW_AES_BLK_SZ 16
226 #define ICP_QAT_HW_KASUMI_BLK_SZ 8
227 #define ICP_QAT_HW_SNOW_3G_BLK_SZ 8
228 #define ICP_QAT_HW_ZUC_3G_BLK_SZ 8
229 #define ICP_QAT_HW_NULL_KEY_SZ 256
230 #define ICP_QAT_HW_DES_KEY_SZ 8
231 #define ICP_QAT_HW_3DES_KEY_SZ 24
232 #define ICP_QAT_HW_AES_128_KEY_SZ 16
233 #define ICP_QAT_HW_AES_192_KEY_SZ 24
234 #define ICP_QAT_HW_AES_256_KEY_SZ 32
235 #define ICP_QAT_HW_AES_128_F8_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
236 QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
237 #define ICP_QAT_HW_AES_192_F8_KEY_SZ (ICP_QAT_HW_AES_192_KEY_SZ * \
238 QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
239 #define ICP_QAT_HW_AES_256_F8_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
240 QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
241 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
242 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
243 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
244 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
245 #define ICP_QAT_HW_KASUMI_KEY_SZ 16
246 #define ICP_QAT_HW_KASUMI_F8_KEY_SZ (ICP_QAT_HW_KASUMI_KEY_SZ * \
247 QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
248 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
249 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
250 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
251 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
252 #define ICP_QAT_HW_ARC4_KEY_SZ 256
253 #define ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ 16
254 #define ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ 16
255 #define ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ 16
256 #define ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ 16
257 #define ICP_QAT_HW_MODE_F8_NUM_REG_TO_CLEAR 2
259 #define ICP_QAT_HW_CIPHER_MAX_KEY_SZ ICP_QAT_HW_AES_256_F8_KEY_SZ
261 /* These defines describe position of the bit-fields
262 * in the flags byte in B0
264 #define ICP_QAT_HW_CCM_B0_FLAGS_ADATA_SHIFT 6
265 #define ICP_QAT_HW_CCM_B0_FLAGS_T_SHIFT 3
267 #define ICP_QAT_HW_CCM_BUILD_B0_FLAGS(Adata, t, q) \
268 ((((Adata) > 0 ? 1 : 0) << ICP_QAT_HW_CCM_B0_FLAGS_ADATA_SHIFT) \
269 | ((((t) - 2) >> 1) << ICP_QAT_HW_CCM_B0_FLAGS_T_SHIFT) \
272 #define ICP_QAT_HW_CCM_NQ_CONST 15
273 #define ICP_QAT_HW_CCM_AAD_B0_LEN 16
274 #define ICP_QAT_HW_CCM_AAD_LEN_INFO 2
275 #define ICP_QAT_HW_CCM_AAD_DATA_OFFSET (ICP_QAT_HW_CCM_AAD_B0_LEN + \
276 ICP_QAT_HW_CCM_AAD_LEN_INFO)
277 #define ICP_QAT_HW_CCM_AAD_ALIGNMENT 16
278 #define ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE 4
279 #define ICP_QAT_HW_CCM_NONCE_OFFSET 1
281 struct icp_qat_hw_cipher_algo_blk {
282 struct icp_qat_hw_cipher_config cipher_config;
283 uint8_t key[ICP_QAT_HW_CIPHER_MAX_KEY_SZ];
284 } __rte_cache_aligned;