drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp.h

   1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
   2  * Copyright(c) 2021 Intel Corporation
   3  */
   4
   5 #ifndef _ICP_QAT_HW_GEN4_COMP_H_
   6 #define _ICP_QAT_HW_GEN4_COMP_H_
   7
   8 #include "icp_qat_fw.h"
   9 #include "icp_qat_hw_gen4_comp_defs.h"
  10
  11 struct icp_qat_hw_comp_20_config_csr_lower {
  12         icp_qat_hw_comp_20_extended_delay_match_mode_t edmm;
  13         icp_qat_hw_comp_20_hw_comp_format_t algo;
  14         icp_qat_hw_comp_20_search_depth_t sd;
  15         icp_qat_hw_comp_20_hbs_control_t hbs;
  16         icp_qat_hw_comp_20_abd_t abd;
  17         icp_qat_hw_comp_20_lllbd_ctrl_t lllbd;
  18         icp_qat_hw_comp_20_min_match_control_t mmctrl;
  19         icp_qat_hw_comp_20_skip_hash_collision_t hash_col;
  20         icp_qat_hw_comp_20_skip_hash_update_t hash_update;
  21         icp_qat_hw_comp_20_byte_skip_t skip_ctrl;
  22 };
  23
  24 static inline uint32_t ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(
  25                 struct icp_qat_hw_comp_20_config_csr_lower csr)
  26 {
  27         uint32_t val32 = 0;
  28
  29         QAT_FIELD_SET(val32, csr.algo,
  30                 ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_BITPOS,
  31                 ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_MASK);
  32
  33         QAT_FIELD_SET(val32, csr.sd,
  34                 ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_BITPOS,
  35                 ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_MASK);
  36
  37         QAT_FIELD_SET(val32, csr.edmm,
  38                 ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_BITPOS,
  39                 ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_MASK);
  40
  41         QAT_FIELD_SET(val32, csr.hbs,
  42                 ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS,
  43                 ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_MASK);
  44
  45         QAT_FIELD_SET(val32, csr.lllbd,
  46                 ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS,
  47                 ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK);
  48
  49         QAT_FIELD_SET(val32, csr.mmctrl,
  50                 ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS,
  51                 ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK);
  52
  53         QAT_FIELD_SET(val32, csr.hash_col,
  54                 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS,
  55                 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_MASK);
  56
  57         QAT_FIELD_SET(val32, csr.hash_update,
  58                 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS,
  59                 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_MASK);
  60
  61         QAT_FIELD_SET(val32, csr.skip_ctrl,
  62                 ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_BITPOS,
  63                 ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_MASK);
  64
  65         QAT_FIELD_SET(val32, csr.abd,
  66                 ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_BITPOS,
  67                 ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_MASK);
  68
  69         QAT_FIELD_SET(val32, csr.lllbd,
  70                 ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS,
  71                 ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK);
  72
  73         return rte_bswap32(val32);
  74 }
  75
  76 struct icp_qat_hw_comp_20_config_csr_upper {
  77         icp_qat_hw_comp_20_scb_control_t scb_ctrl;
  78         icp_qat_hw_comp_20_rmb_control_t rmb_ctrl;
  79         icp_qat_hw_comp_20_som_control_t som_ctrl;
  80         icp_qat_hw_comp_20_skip_hash_rd_control_t skip_hash_ctrl;
  81         icp_qat_hw_comp_20_scb_unload_control_t scb_unload_ctrl;
  82         icp_qat_hw_comp_20_disable_token_fusion_control_t
  83                         disable_token_fusion_ctrl;
  84         icp_qat_hw_comp_20_lbms_t lbms;
  85         icp_qat_hw_comp_20_scb_mode_reset_mask_t scb_mode_reset;
  86         uint16_t lazy;
  87         uint16_t nice;
  88 };
  89
  90 static inline uint32_t ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(
  91                 struct icp_qat_hw_comp_20_config_csr_upper csr)
  92 {
  93         uint32_t val32 = 0;
  94
  95         QAT_FIELD_SET(val32, csr.scb_ctrl,
  96                 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_BITPOS,
  97                 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_MASK);
  98
  99         QAT_FIELD_SET(val32, csr.rmb_ctrl,
 100                 ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_BITPOS,
 101                 ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_MASK);
 102
 103         QAT_FIELD_SET(val32, csr.som_ctrl,
 104                 ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_BITPOS,
 105                 ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_MASK);
 106
 107         QAT_FIELD_SET(val32, csr.skip_hash_ctrl,
 108                 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_BITPOS,
 109                 ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK);
 110
 111         QAT_FIELD_SET(val32, csr.scb_unload_ctrl,
 112                 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_BITPOS,
 113                 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_MASK);
 114
 115         QAT_FIELD_SET(val32, csr.disable_token_fusion_ctrl,
 116         ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_BITPOS,
 117         ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_MASK);
 118
 119         QAT_FIELD_SET(val32, csr.lbms,
 120                 ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_BITPOS,
 121                 ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_MASK);
 122
 123         QAT_FIELD_SET(val32, csr.scb_mode_reset,
 124                 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS,
 125                 ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK);
 126
 127         QAT_FIELD_SET(val32, csr.lazy,
 128                 ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_BITPOS,
 129                 ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_MASK);
 130
 131         QAT_FIELD_SET(val32, csr.nice,
 132                 ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_BITPOS,
 133                 ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_MASK);
 134
 135         return rte_bswap32(val32);
 136 }
 137
 138 struct icp_qat_hw_decomp_20_config_csr_lower {
 139         icp_qat_hw_decomp_20_hbs_control_t hbs;
 140         icp_qat_hw_decomp_20_lbms_t lbms;
 141         icp_qat_hw_decomp_20_hw_comp_format_t algo;
 142         icp_qat_hw_decomp_20_min_match_control_t mmctrl;
 143         icp_qat_hw_decomp_20_lz4_block_checksum_present_t lbc;
 144 };
 145
 146 static inline uint32_t ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER(
 147                 struct icp_qat_hw_decomp_20_config_csr_lower csr)
 148 {
 149         uint32_t val32 = 0;
 150
 151         QAT_FIELD_SET(val32, csr.hbs,
 152                 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS,
 153                 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_MASK);
 154
 155         QAT_FIELD_SET(val32, csr.lbms,
 156                 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_BITPOS,
 157                 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_MASK);
 158
 159         QAT_FIELD_SET(val32, csr.algo,
 160                 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_BITPOS,
 161                 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_MASK);
 162
 163         QAT_FIELD_SET(val32, csr.mmctrl,
 164                 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS,
 165                 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK);
 166
 167         QAT_FIELD_SET(val32, csr.lbc,
 168         ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_BITPOS,
 169         ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_MASK);
 170
 171         return rte_bswap32(val32);
 172 }
 173
 174 struct icp_qat_hw_decomp_20_config_csr_upper {
 175         icp_qat_hw_decomp_20_speculative_decoder_control_t sdc;
 176         icp_qat_hw_decomp_20_mini_cam_control_t mcc;
 177 };
 178
 179 static inline uint32_t ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_UPPER(
 180                 struct icp_qat_hw_decomp_20_config_csr_upper csr)
 181 {
 182         uint32_t val32 = 0;
 183
 184         QAT_FIELD_SET(val32, csr.sdc,
 185         ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_BITPOS,
 186         ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_MASK);
 187
 188         QAT_FIELD_SET(val32, csr.mcc,
 189                 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_BITPOS,
 190                 ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_MASK);
 191
 192         return rte_bswap32(val32);
 193 }
 194
 195 #endif /* _ICP_QAT_HW_GEN4_COMP_H_ */