drivers/common/qat/qat_adf/icp_qat_hw_gen4_comp_defs.h

   1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
   2  * Copyright(c) 2021 Intel Corporation
   3  */
   4
   5 #ifndef _ICP_QAT_HW_GEN4_COMP_DEFS_H
   6 #define _ICP_QAT_HW_GEN4_COMP_DEFS_H
   7
   8 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_BITPOS        31
   9 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_MASK          0x1
  10
  11 typedef enum {
  12         ICP_QAT_HW_COMP_20_SCB_CONTROL_ENABLE = 0x0,
  13         ICP_QAT_HW_COMP_20_SCB_CONTROL_DISABLE = 0x1,
  14 } icp_qat_hw_comp_20_scb_control_t;
  15
  16 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_DEFAULT_VAL   \
  17                 ICP_QAT_HW_COMP_20_SCB_CONTROL_DISABLE
  18
  19 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_BITPOS        30
  20 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_MASK          0x1
  21
  22 typedef enum {
  23         ICP_QAT_HW_COMP_20_RMB_CONTROL_RESET_ALL = 0x0,
  24         ICP_QAT_HW_COMP_20_RMB_CONTROL_RESET_FC_ONLY = 0x1,
  25 } icp_qat_hw_comp_20_rmb_control_t;
  26
  27 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_DEFAULT_VAL   \
  28                 ICP_QAT_HW_COMP_20_RMB_CONTROL_RESET_ALL
  29
  30 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_BITPOS        28
  31 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_MASK          0x3
  32
  33 typedef enum {
  34         ICP_QAT_HW_COMP_20_SOM_CONTROL_NORMAL_MODE = 0x0,
  35         ICP_QAT_HW_COMP_20_SOM_CONTROL_REPLAY_MODE = 0x1,
  36         ICP_QAT_HW_COMP_20_SOM_CONTROL_INPUT_CRC = 0x2,
  37         ICP_QAT_HW_COMP_20_SOM_CONTROL_RESERVED_MODE = 0x3,
  38 } icp_qat_hw_comp_20_som_control_t;
  39
  40 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_DEFAULT_VAL   \
  41                 ICP_QAT_HW_COMP_20_SOM_CONTROL_NORMAL_MODE
  42
  43 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_BITPOS       27
  44 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK         0x1
  45
  46 typedef enum {
  47         ICP_QAT_HW_COMP_20_SKIP_HASH_RD_CONTROL_NO_SKIP = 0x0,
  48         ICP_QAT_HW_COMP_20_SKIP_HASH_RD_CONTROL_SKIP_HASH_READS = 0x1,
  49 } icp_qat_hw_comp_20_skip_hash_rd_control_t;
  50
  51 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_DEFAULT_VAL  \
  52                 ICP_QAT_HW_COMP_20_SKIP_HASH_RD_CONTROL_NO_SKIP
  53
  54 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_BITPOS 26
  55 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_MASK   0x1
  56
  57 typedef enum {
  58         ICP_QAT_HW_COMP_20_SCB_UNLOAD_CONTROL_UNLOAD = 0x0,
  59         ICP_QAT_HW_COMP_20_SCB_UNLOAD_CONTROL_NO_UNLOAD = 0x1,
  60 } icp_qat_hw_comp_20_scb_unload_control_t;
  61
  62 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_DEFAULT_VAL    \
  63                 ICP_QAT_HW_COMP_20_SCB_UNLOAD_CONTROL_UNLOAD
  64
  65 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_BITPOS 21
  66 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_MASK   0x1
  67
  68 typedef enum {
  69         ICP_QAT_HW_COMP_20_DISABLE_TOKEN_FUSION_CONTROL_ENABLE = 0x0,
  70         ICP_QAT_HW_COMP_20_DISABLE_TOKEN_FUSION_CONTROL_DISABLE = 0x1,
  71 } icp_qat_hw_comp_20_disable_token_fusion_control_t;
  72
  73 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_DEFAULT_VAL \
  74                 ICP_QAT_HW_COMP_20_DISABLE_TOKEN_FUSION_CONTROL_ENABLE
  75
  76 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_BITPOS       19
  77 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_MASK         0x3
  78
  79 typedef enum {
  80         ICP_QAT_HW_COMP_20_LBMS_LBMS_64KB = 0x0,
  81         ICP_QAT_HW_COMP_20_LBMS_LBMS_256KB = 0x1,
  82         ICP_QAT_HW_COMP_20_LBMS_LBMS_1MB = 0x2,
  83         ICP_QAT_HW_COMP_20_LBMS_LBMS_4MB = 0x3,
  84 } icp_qat_hw_comp_20_lbms_t;
  85
  86 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_DEFAULT_VAL  \
  87                 ICP_QAT_HW_COMP_20_LBMS_LBMS_64KB
  88
  89 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS        18
  90 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK          0x1
  91
  92 typedef enum {
  93         ICP_QAT_HW_COMP_20_SCB_MODE_RESET_MASK_RESET_COUNTERS = 0x0,
  94         ICP_QAT_HW_COMP_20_SCB_MODE_RESET_MASK_RESET_COUNTERS_AND_HISTORY = 0x1,
  95 } icp_qat_hw_comp_20_scb_mode_reset_mask_t;
  96
  97 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_DEFAULT_VAL   \
  98                 ICP_QAT_HW_COMP_20_SCB_MODE_RESET_MASK_RESET_COUNTERS
  99
 100 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_BITPOS 9
 101 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_MASK   0x1ff
 102 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_DEFAULT_VAL 258
 103
 104 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_BITPOS 0
 105 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_MASK   0x1ff
 106 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_DEFAULT_VAL 259
 107
 108 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS        14
 109 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_MASK          0x7
 110
 111 typedef enum {
 112         ICP_QAT_HW_COMP_20_HBS_CONTROL_HBS_IS_32KB = 0x0,
 113 } icp_qat_hw_comp_20_hbs_control_t;
 114
 115 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_DEFAULT_VAL   \
 116                 ICP_QAT_HW_COMP_20_HBS_CONTROL_HBS_IS_32KB
 117
 118 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_BITPOS        13
 119 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_MASK          0x1
 120
 121 typedef enum {
 122         ICP_QAT_HW_COMP_20_ABD_ABD_ENABLED = 0x0,
 123         ICP_QAT_HW_COMP_20_ABD_ABD_DISABLED = 0x1,
 124 } icp_qat_hw_comp_20_abd_t;
 125
 126 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_DEFAULT_VAL   \
 127                 ICP_QAT_HW_COMP_20_ABD_ABD_ENABLED
 128
 129 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS 12
 130 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK   0x1
 131
 132 typedef enum {
 133         ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_ENABLED = 0x0,
 134         ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_DISABLED = 0x1,
 135 } icp_qat_hw_comp_20_lllbd_ctrl_t;
 136
 137 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_DEFAULT_VAL    \
 138                 ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_ENABLED
 139
 140 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_BITPOS       8
 141 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_MASK         0xf
 142
 143 typedef enum {
 144         ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_1 = 0x1,
 145         ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_6 = 0x3,
 146         ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_9 = 0x4,
 147 } icp_qat_hw_comp_20_search_depth_t;
 148
 149 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_DEFAULT_VAL  \
 150                 ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_1
 151
 152 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_BITPOS     5
 153 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_MASK       0x7
 154
 155 typedef enum {
 156         ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_ILZ77 = 0x0,
 157         ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_DEFLATE = 0x1,
 158         ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_LZ4 = 0x2,
 159         ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_LZ4S = 0x3,
 160 } icp_qat_hw_comp_20_hw_comp_format_t;
 161
 162 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_DEFAULT_VAL        \
 163                 ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_DEFLATE
 164
 165 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS  4
 166 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK    0x1
 167
 168 typedef enum {
 169         ICP_QAT_HW_COMP_20_MIN_MATCH_CONTROL_MATCH_3B = 0x0,
 170         ICP_QAT_HW_COMP_20_MIN_MATCH_CONTROL_MATCH_4B = 0x1,
 171 } icp_qat_hw_comp_20_min_match_control_t;
 172
 173 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_DEFAULT_VAL     \
 174                 ICP_QAT_HW_COMP_20_MIN_MATCH_CONTROL_MATCH_3B
 175
 176 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS        3
 177 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_MASK          0x1
 178
 179 typedef enum {
 180         ICP_QAT_HW_COMP_20_SKIP_HASH_COLLISION_ALLOW = 0x0,
 181         ICP_QAT_HW_COMP_20_SKIP_HASH_COLLISION_DONT_ALLOW = 0x1,
 182 } icp_qat_hw_comp_20_skip_hash_collision_t;
 183
 184 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_DEFAULT_VAL   \
 185                 ICP_QAT_HW_COMP_20_SKIP_HASH_COLLISION_ALLOW
 186
 187 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS   2
 188 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_MASK     0x1
 189
 190 typedef enum {
 191         ICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_ALLOW = 0x0,
 192         ICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_DONT_ALLOW = 0x1,
 193 } icp_qat_hw_comp_20_skip_hash_update_t;
 194
 195 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_DEFAULT_VAL      \
 196                 ICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_ALLOW
 197
 198 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_BITPOS  1
 199 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_MASK    0x1
 200
 201 typedef enum {
 202         ICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_TOKEN = 0x0,
 203         ICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_LITERAL = 0x1,
 204 } icp_qat_hw_comp_20_byte_skip_t;
 205
 206 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_DEFAULT_VAL     \
 207                 ICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_TOKEN
 208
 209 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_BITPOS  0
 210 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_MASK    0x1
 211
 212 typedef enum {
 213         ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_DISABLED = 0x0,
 214         ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_ENABLED = 0x1,
 215 } icp_qat_hw_comp_20_extended_delay_match_mode_t;
 216
 217 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_DEFAULT_VAL \
 218                 ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_DISABLED
 219
 220 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_BITPOS 31
 221 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_MASK   0x1
 222
 223 typedef enum {
 224         ICP_QAT_HW_DECOMP_20_SPECULATIVE_DECODER_CONTROL_ENABLE = 0x0,
 225         ICP_QAT_HW_DECOMP_20_SPECULATIVE_DECODER_CONTROL_DISABLE = 0x1,
 226 } icp_qat_hw_decomp_20_speculative_decoder_control_t;
 227
 228 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_DEFAULT_VAL\
 229                 ICP_QAT_HW_DECOMP_20_SPECULATIVE_DECODER_CONTROL_ENABLE
 230
 231 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_BITPOS 30
 232 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_MASK   0x1
 233
 234 typedef enum {
 235         ICP_QAT_HW_DECOMP_20_MINI_CAM_CONTROL_ENABLE = 0x0,
 236         ICP_QAT_HW_DECOMP_20_MINI_CAM_CONTROL_DISABLE = 0x1,
 237 } icp_qat_hw_decomp_20_mini_cam_control_t;
 238
 239 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MINI_CAM_CONTROL_DEFAULT_VAL    \
 240                 ICP_QAT_HW_DECOMP_20_MINI_CAM_CONTROL_ENABLE
 241
 242 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS      14
 243 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_MASK        0x7
 244
 245 typedef enum {
 246         ICP_QAT_HW_DECOMP_20_HBS_CONTROL_HBS_IS_32KB = 0x0,
 247 } icp_qat_hw_decomp_20_hbs_control_t;
 248
 249 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_DEFAULT_VAL \
 250                 ICP_QAT_HW_DECOMP_20_HBS_CONTROL_HBS_IS_32KB
 251
 252 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_BITPOS     8
 253 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_MASK       0x3
 254
 255 typedef enum {
 256         ICP_QAT_HW_DECOMP_20_LBMS_LBMS_64KB = 0x0,
 257         ICP_QAT_HW_DECOMP_20_LBMS_LBMS_256KB = 0x1,
 258         ICP_QAT_HW_DECOMP_20_LBMS_LBMS_1MB = 0x2,
 259         ICP_QAT_HW_DECOMP_20_LBMS_LBMS_4MB = 0x3,
 260 } icp_qat_hw_decomp_20_lbms_t;
 261
 262 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_DEFAULT_VAL        \
 263                 ICP_QAT_HW_DECOMP_20_LBMS_LBMS_64KB
 264
 265 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_BITPOS 5
 266 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_MASK   0x7
 267
 268 typedef enum {
 269         ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_DEFLATE = 0x1,
 270         ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_LZ4 = 0x2,
 271         ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_LZ4S = 0x3,
 272 } icp_qat_hw_decomp_20_hw_comp_format_t;
 273
 274 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_DEFAULT_VAL    \
 275                 ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_DEFLATE
 276
 277 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS        4
 278 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK          0x1
 279
 280 typedef enum {
 281         ICP_QAT_HW_DECOMP_20_MIN_MATCH_CONTROL_MATCH_3B = 0x0,
 282         ICP_QAT_HW_DECOMP_20_MIN_MATCH_CONTROL_MATCH_4B = 0x1,
 283 } icp_qat_hw_decomp_20_min_match_control_t;
 284
 285 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_DEFAULT_VAL   \
 286                 ICP_QAT_HW_DECOMP_20_MIN_MATCH_CONTROL_MATCH_3B
 287
 288 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_BITPOS 3
 289 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_MASK   0x1
 290
 291 typedef enum {
 292         ICP_QAT_HW_DECOMP_20_LZ4_BLOCK_CHKSUM_ABSENT  =  0x0,
 293         ICP_QAT_HW_DECOMP_20_LZ4_BLOCK_CHKSUM_PRESENT  =  0x1,
 294 } icp_qat_hw_decomp_20_lz4_block_checksum_present_t;
 295
 296 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_DEFAULT_VAL \
 297         ICP_QAT_HW_DECOMP_20_LZ4_BLOCK_CHKSUM_ABSENT
 298
 299 #endif /* _ICP_QAT_HW_GEN4_COMP_DEFS_H */